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SPARC64-III User's Guide

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SPARC64-III User's Guide SPARC64-III User’s Guide HAL Computer Systems, Inc. Campbell, California May 1998 Copyright © 1998 HAL Computer Systems, Inc. All rights reserved. This product and related documentation are protected by copyright and distributed under licenses restricting their use, copying, distribution, and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of HAL Computer Systems, Inc., and its licensors, if any. Portions of this product may be derived from the UNIX and Berkeley 4.3 BSD Systems, licensed from UNIX System Laboratories, Inc., a wholly owned subsidiary of Novell, Inc., and the University of California, respectively. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii), FAR 52.227-19, and NASA FAR Supplement. The product described in this book may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS HAL, the HAL logo, HyperScalar, and OLIAS are registered trademarks and HAL Computer Systems, Inc. HALstation 300, and Ishmail are trademarks of HAL Computer Systems, Inc. SPARC64 and SPARC64/OS are trademarks of SPARC International, Inc., licensed by SPARC International, Inc., to HAL Computer Systems, Inc. Fujitsu and the Fujitsu logo are trademarks of Fujitsu Limited. All SPARC trademarks, including the SCD Compliant Logo, are trademarks or registered trademarks of SPARC International, Inc. SPARCstation, SPARCserver, SPARCengine, SPARCstorage, SPARCware, SPARCcenter, SPARCclassic, SPARCcluster, SPARCdesign, SPARC811 SPARCprinter, UltraSPARC, microSPARC, SPARCworks, and SPARCompiler are licensed exclusively to Sun Microsystems, Inc. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark of Novell, Inc., in the United States and other countries, licensed exclusively through the X/OPEN Company, Ltd. All other product names mentioned herein are the trademarks of their respective owners. THIS PUBLICATION IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT. THIS PUBLICATION COULD INCLUDE TECHNICAL INACCURACIES OR TYPOGRAPHICAL ERRORS. CHANGES ARE PERIODICALLY ADDED TO THE INFORMATION HEREIN; THESE CHANGES WILL BE INCORPORATED IN NEW EDITIONS OF THE PUBLICATION. HAL COMPUTER SYSTEMS, INC. MAY MAKE IMPROVEMENTS AND/OR CHANGES IN THE PRODUCT(S) AND/OR THE PROGRAM(S) DESCRIBED IN THIS PUBLICATION AT ANY TIME. SPARC64-III User’s Guide Internal part number 620-00205-A Reorder document number 620-00205-A May 1998 HAL Computer Systems, Inc. A Fujitsu Company 1315 Dell Avenue Campbell, CA 95008 http://www.hal.com Contents 1 Overview .......................................................................................................................... 11 1.1 Notes About This Book ........................................................................................... 11 1.2 SPARC64-III Architecture ...................................................................................... 17 2 Definitions ........................................................................................................................ 21 SPARC-V9 Terms ................................................................................................... 21 SPARC64-III Implementation-Specific Terms ....................................................... 26 3 Architectural Overview .................................................................................................. 31 3.1 SPARC-V9 Processor Architecture ........................................................................ 31 3.2 Instructions .............................................................................................................. 33 3.3 Traps ........................................................................................................................37 3.4 SPARC64-III Processor Architecture ..................................................................... 38 4 Data Formats ................................................................................................................... 51 4.1 Signed Integer Byte ................................................................................................. 52 4.2 Signed Integer Halfword ......................................................................................... 52 4.3 Signed Integer Word ............................................................................................... 52 4.4 Signed Integer Double ............................................................................................. 52 4.5 Signed Extended Integer ......................................................................................... 53 4.6 Unsigned Integer Byte ............................................................................................. 53 4.7 Unsigned Integer Halfword ..................................................................................... 53 4.8 Unsigned Integer Word ........................................................................................... 53 4.9 Unsigned Integer Double ........................................................................................ 54 4.10 Unsigned Extended Integer ..................................................................................... 54 4.11 Tagged Word ........................................................................................................... 54 4.12 Floating-point Single Precision ............................................................................... 54 4.13 Floating-point Double Precision ............................................................................. 55 4.14 Floating-point Quad-precision ................................................................................ 55 5 Registers ........................................................................................................................... 59 5.1 Nonprivileged Registers .......................................................................................... 60 5.2 Privileged Registers ................................................................................................. 82 4 Contents 6 Instructions ...................................................................................................................... 107 6.1 Instruction Execution .............................................................................................. 107 6.2 Instruction Formats .................................................................................................. 111 6.3 Instruction Categories .............................................................................................. 116 6.4 Register Window Management ............................................................................... 133 7 Traps ................................................................................................................................. 137 7.1 Overview ................................................................................................................. 137 7.2 Processor States, Normal and Special Traps ........................................................... 137 7.3 Trap Categories ....................................................................................................... 142 7.4 Trap Control ............................................................................................................ 146 7.5 Trap-table Entry Addresses ..................................................................................... 147 7.6 Trap Processing ....................................................................................................... 153 7.7 Exception and Interrupt Descriptions ...................................................................... 161 8 Memory Models ............................................................................................................... 169 8.1 Introduction ............................................................................................................. 169 8.2 Memory, Real Memory, and I/O Locations ............................................................ 173 8.3 Addressing and Alternate Address Spaces .............................................................. 174 8.4 SPARC-V9 Memory Model .................................................................................... 176 9 Guidelines for Instruction Scheduling .......................................................................... 185 9.1 Introduction ............................................................................................................. 185 9.2 Instruction Fetch ...................................................................................................... 187 9.3 Branches and Branch Prediction ............................................................................. 190 9.4 Instruction Issue ...................................................................................................... 194 9.5 Instruction Dispatch, and the DFM Queue .............................................................. 195 9.6 Data Flow Unit ........................................................................................................ 198
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