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Common Source Stage Miller Approximation ZVTC Analysis Backgate Effect Claudio Talarico Gonzaga University Sources: most of the figures were provided by B. Murmann CS with Resistive Load Vout VDD RD Bias Point (Q) vout Idi D = ID + id + VOUT v = V + v VoutOU=T OUT out Signal vin V in - Bias VIN vin Vin VIN + + gmvin 2I D 2I D vin ro RD vout Av = − RD || ro ≅ − RD - - VOV VOV gm often but not always !!! R EE 303 – Common Source Stage 2 Does ro matter ? § ro can be neglected in the gain calculation as long as the desired gain |Av| is much less than the intrinsic gain gmro 1 1 1 | AV |= gm (RD || ro ) = + | AV | gm RD gmro | A | g R = V ≅| A | m D | A | V 1− V gmro for | AV |<<gmro NOTE: IB The small signal 2ID 1 2 v VOoutUT gmro ≅ ⋅ = parameters (that is V V λI λV in vIN OV D OV gm and ro) are determined by the DC bias point Intrinsic Gain EE 303 – Common Source Stage 3 Upper Bound on Gain § In the basic common source stage RD performs two “conflicting” tasks – it translates the device’s drain current id into the output voltage vout. – it sets the drain bias voltage (VDS) of the MOSFET § This creates an upper bound on the achievable small signal voltage gain V 2ID RD | AV |≅ RD = 2 VOV VOV VRDmax VDD −VOV min VDD | AV max |=2 = 2 ≅ 2 VOUT VOV min VOV min VOV min VDD A NOTE: VIN – VT only a limited range B of the VTC is useful for amplification VDD ⋅ RON C For VIN large: VOUT ≅ (resistivedivider) RD + RON D VIN VT VDD cutoff saturation triode EE 303 – Common Source Stage 4 Voltage Gain and Drain Biasing Considerations (1) VIN ID VDS=VDD−RDID For a given ID if RD ( VDS ) the bias point Q moves toward triode region ID VIN5 Small RD Intercepts D VIN4 at VDD/RD VIN3 C Load line Large R D ID = (VDD-VOUT)/RD VIN2 B VIN1 A VDS = VOUT VDD EE 303 – Common Source Stage 5 Voltage Gain and Drain Biasing Considerations (2) Id For a given ID if RD the voltage gain Small RD Intercepts Q = (VDS,ID) at VDD/RD Large RD Id =gmvin Q Q1 2 ID Vout VDD vout EE 303 – Common Source Stage 6 Importance of choosing the “right” bias point § Deciding the location of the bias point Q affects: – gain (the values of gm and ro depend on the DC bias) – allowable signal swing at the output Vout Vout vout Q vout Q Vin Vin vin vin EE 303 – Common Source Stage 7 Can we overcome the upper bound on gain ? § The upper bound comes from the fact that both gain and bias point depend on RD V | A | 2 DD – Want large R for large gain V max ≅ D VOV min – Want small RD to prevent device from entering triode region § We can overcome the upper bound, if we can find a way to set VOUT independently of RD Small Id Large RD RD Q ID Vout VOUT EE 303 – Common Source Stage 8 CS stage with improved drain biasing scheme VB −Vout at the point V =V we have I =I I = I + out B d B d B regardless the value of R RD D Id IB RD VB vVOUT IidD out Q IB vin VIN Vout VB We wish to set IB=ID and VB=VOUT EE 303 – Common Source Stage 9 Plot for IB=ID Small Id Large RD RD I Q D gmid vout Vout VOUT § We can increase RD (and gain) without changing operating point EE 303 – Common Source Stage 10 Infinite gain? § It is tempting to think we can make RD nearly “infinitely” large and get close to “infinite” gain § This is not possible in practice for two reasons – Finite dId/dVds of the transistor I B 2I 1 2 V D vOUoutT A = g r ≅ ⋅ = V m o V λI λV Vin vIN OV D OV – Sensitivity to mismatch between ID and IB will render the circuit impractical EE 303 – Common Source Stage 11 Bias point shift due to mismatch in IB and ID § For large values of RD, it becomes harder to absorb differences between ID and IB and still maintain an operating point that is close to the desired value Id 1/RD IB ΔI ID Q ΔV= ΔI RD Vout VB VOUT EE 303 – Common Source Stage 12 Solutions to bias point shift issue § Limit RD to values such that expected mismatch in bias currents causes acceptable bias point variations § Feedback – Somehow sense VOUT and adjust IB (or ID) such that the outputs sits at a proper operating point regardless of mismatch between ID and IB – More later … § In a realistic circuit implementation, the auxiliary current source IB can be built, for example, using a pMOS that operates in saturation – More later … (CS stage with current source load) EE 303 – Common Source Stage 13 How fast can the CS stage go ? § There are two perspectives on “how fast” a circuit can go – Which one of the two matters more is dependent on the application § Time domain – Apply a transient at the input (e.g. a voltage step), measure how fast the output settles § Frequency domain – Apply a sinusoid at the input, measure the gain and phase of the circuit transfer function across frequency § Knowing the time domain response, we can estimate the frequency domain response, and vice versa EE 303 – Common Source Stage 14 Common Source Stage revisited VB IB R RD V “Transducer” o Ri vi VI Ri models finite resistance in the driving circuit EE 303 – Common Source Stage 15 Matlab Design Script % % C. Talarico % filename: csdesign.m % Design of CS amplifier using gm/Id methodology % clc; clear all; close all; addpath('~/gm_ID_starter_kit_2014'); load 180n.mat; % specs. av0 = 10; Id = 400e-6; Ri = 10e3; RD = 2e3; Vdd = 1.8; VB = Vdd/2; % design choice Ln = 0.18e-6 % calculations gm = av0/RD gm_id = gm/Id wT = lookup(nch, 'GM_CGG', 'GM_ID', gm_id, 'L', Ln); fT = wT/2/pi cgd_cgg = lookup(nch, 'CGD_CGG', 'GM_ID', gm_id, 'L', Ln); cdd_cgg = lookup(nch, 'CDD_CGG', 'GM_ID', gm_id, 'L', Ln); cgg = gm/wT; cgd = cgd_cgg*cgg cdd = cdd_cgg*cgg; cdb = cdd - cgd cgs = cgg - cgd gmro = lookup(nch, 'GM_GDS','GM_ID', gm_id, 'L', Ln) ro = gmro/gm % finding input bias VI = lookupVGS(nch, 'GM_ID', gm_id, 'L', Ln) % device sizing id_w = lookup(nch, 'ID_W', 'GM_ID', gm_id, 'L', Ln) W = Id/id_w % neglecting ro is not a very accurate assumption R = (1/RD + 1/ro)^-1 Av0 = gm*R Av0db = 20*log10(gm*R) % pole calculations (dominant pole assumption) b1 = Ri*(cgs + cgd*(1+Av0))+R*(cdb+cgd); b2 = Ri*R*(cgs*cdb + cgs*cgd + cdb*cgd); fp1 = 1/2/pi/b1 fp2 = 1/2/pi*b1/b2 % zero calculation fz = 1/2/pi/cgd*gm ! EE 303 – Common Source Stage 16 What is the speed of the CS ? VB VDD = 1.8 V IB R RD VB = VDD/2 = 0.9 V V R = 10K “Transducer” o i Ω RD = 2 KΩ Ri VI = 0.627 V vi IB = 400 µA VI W/L = 21.34 µm/0.18µm Cgd Ri + RD + Cgd≈10.28 fF g v vi vgs Cgs m gs ro R Cdb vo Cgs≈ 33.26 fF - - Cdb≈ 15.72 fF R ro≅ 7.63KΩ R = RD||ro ≅ 1.58KΩ EE 303 – Common Source Stage 17 CS Frequency Response AC Response 20 0 −20 |H(f)| [dB] −40 4 5 6 7 8 9 10 11 10 10 10 10 10 10 10 10 f [Hz] 200 150 100 50 phase[H(f)] [deg] 0 4 5 6 7 8 9 10 11 10 10 10 10 10 10 10 10 f [Hz] § There seems to be two poles. Let’s analyze the situation in detail. EE 303 – Common Source Stage 18 Exact Analytical Analysis 1 Cgd 2 + + Ri g v vi/Ri vgs Cgs m gs ro R Cdb vo - - Applying KCL at nodes 1 and 2, and solving for vo/vi yields ⎛ C ⎞ g R 1 s gd − m ⎜ − ⎟ vo( s ) ⎝ gm ⎠ = 2 vi ( s ) 1+ s[(Cdb + Cgd )R + (Cgs + Cgd )Ri + gm Ri RCgd ]+ s Ri R(CgsCdb + CgdCdb + CgsCgd ) High “entropy” expression. Difficult to get any insight !!! EE 303 – Common Source Stage 19 Issue § We could in principle use this expression to plot the frequency response of the circuit and compute the 3-dB bandwidth – The result would match the Spice simulation result exactly § There are two issues with going in this direction for hand analysis – The procedure is quite tedious… • Imagine how complex the equations would get for a multi- transistor circuit – The derived expression is useless for reasoning about the circuit from an intuitive design perspective • By looking at this equation we cannot easily tell what exactly limits the bandwidth, or how we can improve it EE 303 – Common Source Stage 20 Simulation Result § Want to have a method that § Non-dominant, high-frequency let’s us estimate the dominant poles and zeros may or may pole quickly using intuitive not be important methods – If they are, it may be OK to do a – Without running into high entropy little more work expressions that tell us things we are not interested in… AC Response 20 0 Dominant pole −20 −40 Non-dominant |H(f)| [dB] pole(s) and zero(s) −60 −80 4 5 6 7 8 9 10 11 12 10 10 10 10 10 10 10 10 10 f [Hz] EE 303 – Common Source Stage 21 The Culprit § The main reason for the high complexity in the derived expression is that Cgd “couples” nodes 1 and 2 § For Cgd=0, the circuit becomes 1 2 + + Ri g v vi/Ri vgs Cgs m gs R Cdb vo - - τ1 τ2 vo (s) vgs (s) vo (s) 1 −gm R 1 = ⋅ = ⋅ = −gm R vi (s) vi (s) vgs (s) (1+ sRiCgs ) (1+ sRCdb ) (1+ sτ1)(1+ sτ 2 ) EE 303 – Common Source Stage 22 A Promising Trick: Miller Theorem Z 1 2 + General + Linear V V1 Network 2 - - V K ≡ 2 V1 1 2 General + + Z Linear K V Z V2 1 1− K Network K −1 - - EE 303 – Common Source Stage 23 Finding K(s) for Our Circuit 1 Cgd 2 + + g v vgs m gs R Cdb vo - - Applying KCL at node 2, and solving for vo/vgs yields: " Cgd % $ 1− s ' v (s) g K(s) = o = −g R$ m ' v (s) m $1+ sR(C +C )' gs $ gd db ' # & EE 303 – Common Source Stage 24 Circuit After Applying Miller Theorem 1 2 + gmvgs + Ri vi/Ri vgs Cgs R Cdb vo - Cgd[1-K(s)] Cgd[1-1/K(s)] - g ⎛ C ⎞ z = + m ⎜ 1− s gd ⎟ C v ( s ) g gd K( s ) o g R⎜ m ⎟ = = − m ⎜ ⎟ vgs( s ) 1+ sR( Cgd + Cdb ) 1 ⎜ ⎟ p = − ⎝ ⎠ R(Cgd +Cdb ) Intuitively, the zero is caused because at high frequency Cgd shorts the gate and drain of the device together, providing a direct path from the amplifier’s input to output.
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    EECS 105 Fall 2003, Lecture 17 Lecture 17: Common Source/Gate/Drain Amplifiers Prof. Niknejad Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 17 Prof. A. Niknejad Lecture Outline MOS Common Source Amp Current Source Active Load Common Gate Amp Common Drain Amp Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 17 Prof. A. Niknejad Common-Source Amplifier Isolate DC level Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 17 Prof. A. Niknejad Load-Line Analysis to find Q V −V I = DD out RD RD Q 1 5V slope = I = 10k D 10k 0V I = D 10k Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 17 Prof. A. Niknejad Small-Signal Analysis =∞ Rin Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 17 Prof. A. Niknejad Two-Port Parameters: Generic Transconductance Amp Rs + vs Rin Gmvin RL vin Rout − Find Rin, Rout, Gm =∞ Rin = = Gm gm RrRout o|| D Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 17 Prof. A. Niknejad Two-Port CS Model Reattach source and load one-ports: Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 17 Prof. A. Niknejad Maximize Gain of CS Amp =− AgRrv mD|| o Increase the gm (more current) Increase RD (free? Don’t need to dissipate extra power) Limit: Must keep the device in saturation =− > VVIRVDS DD D D DS, sat For a fixed current, the load resistor can only be chosen so large To have good swing we’d also like to avoid getting to close to saturation Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 17 Prof.
  • A Comparison Between Common-Source and Cascode Topologies for 60Ghz Amplifier Design in 65Nm CMOS Qinghong Bu, Ning Li, Kenichi Okada and Akira Matsuzawa

    A Comparison Between Common-Source and Cascode Topologies for 60Ghz Amplifier Design in 65Nm CMOS Qinghong Bu, Ning Li, Kenichi Okada and Akira Matsuzawa

    A Comparison between Common-source and Cascode Topologies for 60GHz Amplifier Design in 65nm CMOS Qinghong Bu, Ning Li, Kenichi Okada and Akira Matsuzawa Department of Physical Electronics, Tokyo Institute of Technology 2-12-1-S3-27 Ookayama, Meguro-ku, Tokyo, 152-8552, Japan. Tel & Fax: +81-3-5734-3764, E-mail: [email protected] voltage Vdd are the 1.2 V. Fig. 2 (a) shows that the maxi- 1. Introduction mum gain of the cascode topology decreased faster than the Although RF front-end amplifiers are implemented at CS topology as the frequency increases. The same maxi- low noise amplifiers and power amplifiers with different mum gain can be obtained around 60 GHz. The gain-boost specifications due to the different functions they perform, cascode topology achieves a 3-dB higher maximum gain sufficient gain and low power consumption are the general than the CS and the common cascode topologies. Both the requirements. For the design consideration, the active de- cascode topology and the gain-boost cascode topology have vice structure and models should be optimized at 60 GHz. about -30dB reverse isolation at 60GHz while the reverse Both common-source (CS) and cascode topologies are isolation of CS topology is only -13dB at 60GHz as shown utilized in millimeter-wave (MMW) circuit design. CS to- in Fig. 2(b). The stability factor is shown in Fig. 2(c). pology, which has reasonable power gain and small noise Common cascode topology and the gain-boost cascode figure, is widely used in MMW amplifier designs. The topology have much better stability factor than the CS to- good isolation between input and output of cascode topol- pology at 60GHz.