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Intel from 8086 to Nehalem

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Intel 8086 1 10 13 Intel 80386 17 24 Intel 80486 29 37 () 45 (microarchitecture) 52 Nehalem (microarchitecture) 55 References Article Sources and Contributors 60 Image Sources, Licenses and Contributors 62 Article Licenses License 64 1 Intel 8086

Intel 8086

Produced From 1978 to

Common manufacturer(s) • Intel, AMD, NEC, , Harris (Intersil), OKI, AG, , Mitsubishi.

Max. CPU 5 MHz to 10 MHz

Min. feature size 3μm

Instruction set -16

Predecessor (8080)

Successor 80186

Package(s) • 40 pin DIP

Variant 8088

The 8086[1] (also called iAPX86) is a 16-bit chip designed by Intel between early 1976 and mid-1978, when it was released. The 8086 gave rise to the x86 architecture of Intel's future processors. The Intel 8088, released in 1979, was a slightly modified chip with an external 8-bit data (allowing the use of cheaper and fewer supporting logic chips[2]), and is notable as the processor used in the original IBM PC.

History

Background In 1972, Intel launched the 8008, the first 8-bit microprocessor.[3] It implemented an instruction set designed by Datapoint corporation with programmable CRT terminals in mind, that also proved to be fairly general purpose. The device needed several additional ICs to produce a functional , in part due to its small 18-pin "memory-package", which ruled out the use of a separate address bus (Intel was primarily a DRAM manufacturer at the time). Two years later, in 1974, Intel launched the 8080,[4] employing the new 40-pin DIL packages originally developed for calculator ICs to enable a separate address bus. It had an extended instruction set that was source- (not binary-) compatible with the 8008 and also included some 16-bit instructions to make programming easier. The 8080 device, often described as the first truly useful microprocessor, was eventually replaced by the depletion-load based 8085 (1977) which could cope with a single 5V power supply instead of the three different operating voltages of earlier chips.[5] Other well known 8-bit that emerged during these years were Motorola 6800 (1974), General Instrument PIC16X (1975), MOS Technology 6502 (1975), Zilog Z80 (1976), and Motorola 6809 (1978). Intel 8086 2

The first x86 design The 8086 project started in May 1976 and was originally intended as a temporary substitute for the ambitious and delayed iAPX 432 project. It was an attempt to draw attention from the less-delayed 16 and 32-bit processors of other manufacturers (such as Motorola, Zilog, and ) and at the same time to counter the threat from the Zilog Z80 (designed by former Intel employees), which became very successful. Both the architecture and the physical chip were therefore developed rather quickly by a small group of people, and using the same basic microarchitecture elements and physical implementation techniques as employed for the slightly older 8085 (and for which the 8086 also would function as a continuation). Marketed as source compatible, the 8086 was designed so that assembly language for the 8008, 8080, or 8085 could be automatically converted into equivalent (sub-optimal) 8086 source code, with little or no hand-editing. The programming model and instruction set was (loosely) based on the 8080 in order to make this possible. However, the 8086 design was expanded to support full 16-bit processing, instead of the fairly basic 16-bit capabilities of the 8080/8085. New kinds of instructions were added as well; full support for signed integers, base+offset addressing, and self-repeating operations were akin to the Z80 design[6] but were all made slightly more general in the 8086. Instructions directly supporting nested ALGOL-family languages such as Pascal and PL/M were also added. According to principal architect Stephen P. Morse, this was a result of a more software centric approach than in the design of earlier Intel processors (the designers had experience working with compiler implementations). Other enhancements included microcoded multiply and divide instructions and a bus-structure better adapted to future co-processors (such as 8087 and 8089) and multiprocessor systems. The first revision of the instruction set and high level architecture was ready after about three months,[7] and as almost no CAD-tools were used, four engineers and 12 layout people were simultaneously working on the chip.[8] The 8086 took a little more than two years from idea to working product, which was considered rather fast for a complex design in 1976–1978. The 8086 was sequenced[9] using a mixture of random logic[10] and and was implemented using depletion-load nMOS circuitry with approximately 20,000 active (29,000 counting all ROM and PLA sites). It was soon moved to a new refined nMOS manufacturing process called HMOS (for High performance MOS) that Intel originally developed for manufacturing of fast static RAM products.[11] This was followed by HMOS-II, HMOS-III versions, and, eventually, a fully static CMOS version for battery-powered devices, manufactured using Intel's CHMOS processes.[12] The original chip measured 33 mm² and minimum feature size was 3.2 μm. The architecture was defined by Stephen P. Morse with some help and assistance by Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team[13] and William Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the Intel 286 and the Intel 386, all of which eventually became known as the x86 family. (Another reference is that the PCI Vendor ID for Intel devices is 8086 .) h Intel 8086 3

Details

The 8086 pin-assignments in min and max mode. Intel 8086 4

Main registers

AH AL AX (primary )

BH BL BX (base, accumulator)

CH CL CX (counter, accumulator)

DH DL DX (accumulator, other functions)

Index registers

SI Source Index

DI Destination Index

BP Base Pointer

SP Stack Pointer

Status register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (bit position)

- - - - O D I T S Z - A - P - C Flags

Segment register

CS Code Segment

DS Data Segment

ES ExtraSegment

SS Stack Segment

Instruction pointer

IP Instruction Pointer

The 8086 registers

Buses and operation All internal registers, as well as internal and external data buses, were 16 bits wide, firmly establishing the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus gave a 1 MB physical address space (220 = 1,048,576). This address space was addressed by means of internal 'segmentation'. The data bus was multiplexed with the address bus in order to fit a standard 40-pin dual in-line package. 16-bit I/O addresses meant 64 KB of separate I/O space (216 = 65,536). The maximum linear address space was limited to 64 KB, simply because internal registers were only 16 bits wide. Programming over 64 KB boundaries involved adjusting segment registers (see below) and was therefore fairly awkward (and remained so until the 80386). Some of the control pins, which carry essential signals for all external operations, had more than one function depending upon whether the device was operated in min or max mode. The former was intended for small single processor systems whilst the latter was for medium or large systems, using more than one processor. Intel 8086 5

Registers and instructions The 8086 had eight (more or less general) 16-bit registers including the stack pointer, but excluding the instruction pointer, flag register and segment registers. Four of them, AX, BX, CX, DX, could also be accessed as twice as many 8-bit registers (see figure) while the other four, BP, SI, DI, SP, were 16-bit only. Due to a compact encoding inspired by 8-bit processors, most instructions were one-address or two-address operations which means that the result were stored in one of the operands. At most one of the operands could be in memory, but this memory operand could also be the destination, while the other operand, the source, could be either register or immediate. A single memory location could also often be used as both source and destination which, among other factors, further contributed to a code density comparable to (and often better than) most eight bit machines. Although the degree of generality of most registers were much greater than in the 8080 or 8085, it was still fairly low compared to the typical contemporary minicomputer, and registers were also sometimes used implicitly by instructions. While perfectly sensible for the assembly programmer, this complicated register allocation for compilers compared to more regular 16- and 32-bit processors such as the PDP-11, VAX, 68000, etc.; on the other hand, compared to semi-contemporary simple (but popular and ubiquitous) 8-bit microprocessors such as the 6502, 6809, or 8085, it was significantly easier to generate code for the 8086 design. The 8086 also featured 64 KB of 8-bit (or alternatively 32 K-word of 16-bit) I/O space. A 64 KB (one segment) stack growing towards lower addresses is supported by computer hardware; 2-byte words are pushed to the stack and the stack top (bottom) is pointed out by SS:SP. There are 256 interrupts, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return addresses. The processor had some new instructions (not present in the 8080 and 8085) to better support stack based high level programming languages such as Pascal and PL/M; some of the more useful ones were push mem-op, and ret size, supporting the "pascal calling convention" directly. (Several others, such as push immed and enter, would be added in the subsequent 80186, 80286, and 80386 designs.) It also had a stack-marker mechanism. There are three control flags IF(Intrrupt Flag)TF()DF().

Flags 8086 has a 16-bit flag register. Out of these, 9 are active, and indicate the current state of the processor. These are — , , Auxiliary flag, , Sign flag, Trap flag, , Direction flag and .

Segmentation There were also four 16-bit segment registers (see figure) that allowed the 8086 CPU to access one megabyte of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeded their register size, the 8086 shifted the 16-bit segment only four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, each external address could be referred to by 212 = 4096 different segment:offset pairs. The 16-byte separation between segment bases (due to the 4-bit shift) was called a paragraph. Although considered complicated and cumbersome by many programmers, this scheme also had advantages; a small program (less than 64 KB) could be loaded starting at a fixed offset (such as 0) in its own segment, avoiding the need for relocation, with at most 15 bytes of alignment waste. Compilers for the 8086-family commonly supported two types of pointer, near and far. Near pointers were 16-bit offsets implicitly associated with the program's code and/or data segment and so could be used only within parts of a program small enough to fit in one segment. Far pointers were 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also supported huge pointers, which were like far pointers except that pointer Intel 8086 6

arithmetic on a huge pointer treated it as a linear 20-bit pointer, while pointer arithmetic on a far pointer wrapped around within its 16-bit offset without touching the segment part of the address. To avoid the need to specify near and far on numerous pointers, data structures, and functions, compilers also supported "memory models" which specified default pointer sizes. The tiny (max 64K), small (max 128K), compact (data > 64K), medium (code > 64K), large (code,data > 64K), and huge (individual arrays > 64K) models covered practical combinations of near, far, and huge pointers for code and data. The tiny model meant that code and data was shared in a single segment, just as in most 8-bit based processors, and could be used to build .com-files for instance. Precompiled libraries often came in several versions compiled for different memory models. According to Morse et al., the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low-cost 40-pin package.[14] In principle, the address space of the x86 series could have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the and did not make assumptions about the equivalence of different segment:offset pairs.[15] In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way (see below).

Porting older software Small programs could ignore the segmentation and just use plain 16-bit addressing. This allowed 8-bit software to be quite easily ported to the 8086. The authors of MS-DOS took advantage of this by providing an Application Programming Interface very similar to CP/M as well as including the simple .com executable file format, identical to CP/M. This was important when the 8086 and MS-DOS was new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform.

Performance Although partly shadowed by other design choices in this particular chip, the multiplexed bus limited performance slightly; transfers of 16-bit or 8-bit quantities were done in a four-clock memory access cycle (which was faster on 16-bit, although slower on 8-bit quantities, compared to typical contemporary "8-bit" CPUs). As instructions varied from one to six bytes, fetch and execution were made concurrent (as it remains in today's x86 processors): The bus interface unit fed the instruction stream to the execution unit through a 6-byte prefetch queue (a form of loosely coupled pipelining), speeding up operations on registers and immediates, while memory operations unfortunately became slower; four years later, this performance problem was fixed with the 80186 and 80286). However, the full (instead of partial) 16-bit architecture with a full width ALU meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via carry), speeding up such instructions considerably. Combined with orthogonalizations of operations versus operand-types and addressing modes, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below). Intel 8086 7

Execution times for typical instructions (in clock cycles)[16]

instruction register-register register immediate register-memory memory-register memory-immediate

mov 2 4 8+EA 9+EA 10+EA

ALU 3 4 9+EA, 16+EA, 17+EA

jump register => 11 ; label => 15 ; condition,label => 16

integer multiply 70~160 (depending on operand data as well as size) plus EA

signed integer divide 80~190 (depending on operand data as well as size) plus EA

• EA = time to compute effective address, ranging from 5 to 12 cycles. • Timings are best case, depending on prefetch status, instruction alignment, and other factors. As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple 8080 and 8085, and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold:

• Loosely-coupled fetch and execution units are efficient for instruction prefetch, but not for jumps and random data access (without special measures). • No dedicated address calculation Simplified block diagram over Intel 8088 (a variant of 8086); 1=main registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction adder was afforded; the microcode queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; routines had to use the main ALU 10/11/12=external address/data/control bus. for this (although there was a dedicated segment + offset adder). • The address and data buses were multiplexed, forcing a slightly longer (33~50%) bus cycle than in typical contemporary 8-bit processors. However, memory access performance was drastically enhanced with Intel's generation chips. The 80186 and 80286 both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses.

Floating point The 8086/8088 could be connected to a mathematical to add hardware/microcode-based floating point performance. The was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers like (8087-compatible) and (non 8087-compatible) eventually came up with high performance floating point co-processors that competed with the 8087 as well as with the subsequent, higher performing Intel 80387. Intel 8086 8

Chip versions The clock frequency was originally limited to 5 MHz (IBM PC used 4.77 MHz, 4/3 the standard NTSC color burst frequency), but the last versions in HMOS were specified for 10 MHz. HMOS-III and CMOS versions were manufactured for a long time (at least a while into the 1990s) for embedded systems, although its successor, the 80186/80188 (which includes some on-chip peripherals), has been more popular for embedded use.

Derivatives and clones

Compatible—and, in many cases, enhanced—versions were manufactured by Fujitsu, Harris/Intersil, OKI, Siemens AG, Texas Instruments, NEC, Mitsubishi, and AMD. For example, the NEC V20 and NEC V30 pair were hardware compatible with the 8088 and 8086, respectively, but incorporated the instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed Soviet clone KP1810BM86. without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems.

The electronics industry of the Soviet Union was able to replicate the 8086 through both industrial espionage and reverse engineering. The resulting chip, K1810BM86, was binary and pin-compatible with the 8086, but was not mechanically compatible because it used metric measurements. The 8088 and 8086 were the respective cores of the Soviet-made PC-compatible ES1840 and ES1841 desktops. However, these

computers had significant hardware differences from their authentic OKI M80C86A QFP-56. prototypes, and the data/address bus circuitry was designed independently of Intel products. ES1841 was the first PC compatible computer with dynamic bus sizing (US Pat. No 4,831,514). Later some of the ES1841 principles were adopted in PS/2 (US Pat. No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June. 28, 1989).

Microcomputers using the 8086 • One of the most influential microcomputers of all, the IBM PC, used the Intel 8088, a version of the 8086 with an eight-bit data bus (as mentioned above). • The first commercial microcomputer built on the basis of the 8086 was the Mycron 2000. • The IBM Displaywriter word processing machine and the Wang Professional Computer, manufactured by , also used the 8086. Also, this chip could be found in the AT&T 6300 PC (built by Olivetti). • The NEC PC-9801. • The first Deskpro used an 8086 running at 7.14 MHz, but was capable of running add-in cards designed for the 4.77 MHz IBM PC XT. • The IBM PS/2 models 25 and 30 were built with an 8 MHz 8086. • The Tandy 1000 SL-series machines used 8086 CPUs. • The PC1512, PC1640, PC2086, PC3086 and PC5086 all used 8086 CPUs at 8 MHz. • NASA used original 8086 CPUs on equipment for ground-based maintenance of the Space Shuttle Discovery until the end of the space shuttle program in 2011. This decision was made to prevent software regression that might result from upgrading or from switching to imperfect clones.[17] Intel 8086 9

Notes and references

[1] "Microprocessor Hall of Fame" (http:/ / web. archive. org/ web/ 20070706032836/ http:/ / www. intel. com/ museum/ online/ hist_micro/ hof/

). Intel. Archived from the original (http:/ / www. intel. com/ museum/ online/ hist_micro/ hof/ ) on 2007-07-06. . Retrieved 2007-08-11. [2] It also permitted cheap 8080-family chips to be used (such as the 8254 CTC, 8255 PIO, and 8259 PIC which were used in the IBM PC design). In , it made PCB layout simpler and boards cheaper, as well as demanding fewer (1- or 4-bit wide) DRAM chips. [3] using enhancement load PMOS logic (demanding 14V, achieving TTL-compatibility by having V at +5V and V at -9V) CC DD [4] using non-saturated enhancement load NMOS logic (demanding a higher gate voltage for the load -gates) [5] made possible with depletion load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086) [6] Birth of a Standard: The Intel 8086 Microprocessor. Thirty years ago, Intel released the 8086 processor, introducing the x86 architecture that

underlies every PC-Windows, Mac, or -produced today (http:/ / www. pcworld. com/ article/ 146957/

birth_of_a_standard_the_intel_8086_microprocessor. html), PC World, June 17, 2008 [7] Rev.0 of the instruction set and architecture was ready in about three months, according to Morse. [8] Using rubylith, light boards, rulers, electric erasers, and a digitizer (according to Jenny Hernandez, member of the 8086 design team, in a statement made on Intel's web-page for its 25th birthday). [9] 8086 used less microcode than many competitors designs, such as the MC68000 and others [10] Randall L. Geiger, Phillip E. Allen, Noel R. Strader VLSI design techniques for analog and digital circuits, McGraw-Hill Book Co., 1990, ISBN 0070232539, page 779 "Random Logic vs. Structured Logic Forms", illustration of use of "random" describing CPU control logic [11] Fast static RAMs in MOS technology (as fast as bipolar RAMs) was an important product for Intel during this period. [12] CHMOS is name for CMOS circuits manufactured using processing steps very similar to HMOS. [13] Other members of the design team were Peter A.Stoll and Jenny Hernandez. [14] to 8086 by Stephen P. Morse et al. [15] Some 80186 clones did change the shift value, but were never commonly used in desktop computers. [16] Macro Assembler 5.0 Reference Manual. Microsoft Corporation. 1987. "Timings and encodings in this manual are used with permission of Intel and come from the following publications: Intel Corporation. iAPX 86, 88, 186 and 188 User's Manual, Programmer's Reference, Santa Clara, Calif. 1986." (Similarly for iAPX 286, 80386, 80387.)

[17] For Old Parts, NASA Boldly Goes ... on eBay (http:/ / www. nytimes. com/ 2002/ 05/ 12/ technology/ ebusiness/ 12NASA. html?pagewanted=2), May 12, 2002

External links

• Intel datasheets (http:/ / datasheets. chipdb. org/ Intel/ x86/ 808x/ datashts/ 8086)

• List of 8086 CPUs and their clones at CPUworld.com (http:/ / www. cpu-world. com/ CPUs/ 8086/ )

• 8086 Pinouts (http:/ / www. cpu-world. com/ info/ Pinouts/ 8086. html) Intel 8088 10 Intel 8088

Intel 8088

An Intel 8088 microprocessor Produced From 1979 to 1990s

Designed by Intel

Common manufacturer(s) • Intel • AMD • NEC • Fujitsu • Harris (Intersil)

Max. CPU clock rate 5 MHz to 10 MHz

FSB speeds 5 MHz to 10 MHz

Min. feature size 3μm

Instruction set x86 (IA-16)

Microarchitecture 8088

Cores 1

L1 dependent

L2 cache none

Application Desktop, Embedded

Predecessor (8080)

Successor 80188

Package(s) • 40-pin DIP • 44-pin PLCC

Variant 8086

The Intel 8088 microprocessor was a variant of the Intel 8086 and was introduced on July 1, 1979. It had an 8-bit external data bus instead of the 16-bit bus of the 8086. The 16-bit registers and the one megabyte address range were unchanged, however. The original IBM PC was based on the 8088. Intel 8088 11

History and description

The 8088 was targeted at economical systems by allowing the use of an 8-bit data path and 8-bit support and peripheral chips; complex circuit boards were still fairly cumbersome and expensive when it was released. The prefetch queue of the 8088 was shortened to four bytes, from the 8086's six bytes, and the prefetch algorithm was slightly modified to adapt to the narrower bus. These modifications of the basic 8086 design were one of the first jobs assigned to Intel's then new design office and laboratory in Haifa, Israel.

Variants of the 8088 with more than 5 MHz maximum clock frequency include the 8088-2, which was fabricated using Intel's new enhanced nMOS process called HMOS and specified for a maximum frequency The Intel 80C88. of 8 MHz. Later followed the 80C88, a fully static CHMOS design, which could operate from DC to 8 MHz. There were also several other, more or less similar, variants from other manufacturers. For instance, the NEC V20 was a pin compatible and slightly faster (at the same clock frequency) variant of the 8088, designed and manufactured by NEC. Successive NEC 8088 compatible processors would run at up to 16 MHz.

When announced the list price on the 8088 was US $124.80.[1]

Performance Depending on the clock frequency, the number of memory wait states, as well as on the characteristics of the particular application program, the average performance for the Intel 8088 ranged from approximately 0.33–1 million .[2] Meanwhile, the mov reg,reg and ALU[3] reg,reg instructions taking two and three cycles respectively yielded an absolute peak performance of between 1/3 and 1/2 MIPS per MHz, that is, somewhere in the range 3–5 MIPS at 10 MHz.

Selection for use in the IBM PC The original IBM PC was the most influential microcomputer to use the 8088. It used a clock frequency of 4.77 MHz (4/3 the NTSC colorburst frequency). Some of IBM's engineers and other employees wanted to use the IBM 801 processor, some would prefer the new Motorola 68000,[4] while others argued for a small and simple microprocessor similar to that which had been used in earlier personal computers (such as the TRS-80 or Apple II). However, IBM already had a history of using Intel chips in its products and had also acquired the rights to manufacture the 8086 family.[5] Another factor was that the 8088 allowed the computer to be based on a modified 8085 design, as it could easily interface with most nMOS chips with 8-bit databuses, i.e. existing and mature, and therefore economical, components. This included ICs originally intended for support and peripheral functions around the 8085 and similar processors (not exclusively Intels) which were already well known by many engineers, further reducing cost.[6] The descendants of the 8088 include the 80188, 80186, 80286, 80386, and later software compatible processors, which are in use today. See below for a more complete list. Intel 8088 12

Notes and references

[1] "Intel Brings Out 8-Bit MPU featuring 16-Bit Architecture" (http:/ / books. google. ca/ books?id=ouiYCe_Xw20C& pg=PA71& dq=Intel+

8088+ + architecture& hl=en& ei=uSHMTuujM4rIhAfulK3bDQ& sa=X& oi=book_result& ct=result& redir_esc=y#v=onepage& q=Intel

8088 architecture& f=false). Computerworld. 14 May 1979. p. 71. . Retrieved 21 November 2011.

[2] http:/ / www. olympusmicro. com/ micd/ galleries/ chips/ intel8088a. html [3] ALU stands for one of the instructions add, adc, sub, sbc, cmp, and, or, xor. [4] Later used for the IBM Instruments Laboratory Computer [5] In exchange for giving Intel the rights to its bubble memory designs. However, due to fierce competition from Japanese manufacturers who were able to undercut by cost, Intel soon left this market and changed focus to microprocessors. [6] 68000 components were not widely available at the time, though it could use Motorola 6800 components to an extent.

External links

• Intel Datasheet (http:/ / datasheets. chipdb. org/ Intel/ x86/ 808x/ datashts/ 8088) Intel 80286 13 Intel 80286

Intel 80286

An 8MHz Intel 80286 Microprocessor Produced From 1982 to early 1990s

Common manufacturer(s) • Intel, IBM, AMD, Harris (Intersil), Siemens AG, Fujitsu

Max. CPU clock rate 6 MHz (4 MHz for a short time) to 25 MHz

Min. feature size 1.5µm

Instruction set x86-16 (with MMU)

Predecessor

Successor Intel 80386

Package(s) • PGA, CLCC and PLCC 68-pin

The Intel 80286[1] (also called iAPX 286), introduced on 1 February 1982, was a 16-bit x86 microprocessor with 134,000 transistors. Like its contemporary simpler cousin, the 80186, it could correctly execute most software written for the earlier Intel 8086 and 8088.[2] It was employed for the IBM PC/AT, introduced in 1984, and then widely used in most PC/AT compatible computers until the early 1990s.The 80286 is the first member of the family of advanced microprocessors with and wide protection abilities.

History

After the 6 and 8 MHz initial releases, it was subsequently scaled up to 12.5 MHz. (AMD and Harris later pushed the architecture to speeds as high as 20 MHz and 25 MHz (Harris), respectively.) On average, the 80286 had a speed of about 0.21 instructions per clock.[3] The 6 MHz model operated at 0.9 MIPS, the 10 MHz model at 1.5 MIPS, and the 12 MHz model at 1.8 MIPS.[4]

AMD 80286 (16 MHz version) Intel 80286 14

Design

The 80286's performance per clock cycle was more than twice that of its predecessors, the Intel 8086 and Intel 8088. In fact, the performance increase per clock cycle of the 80286 over its immediate predecessor may be the largest among the generations of x86 processors. Calculation of the more complex addressing modes (such as base+index) had less clock penalty because it was performed by a special circuit in the 286; the 8086, its predecessor, had to perform effective address calculation in the general ALU, taking many cycles. Also, complex mathematical operations (such as 80286 microarchitecture. MUL/DIV) took fewer clock cycles compared to the 8086.

It is a 68-pin microprocessor.It is available in PLCC(Plastic Leaded ), LCC(Lead Less Chip Carrier) and PGA().[5] Having a 24-bit address bus, the 286 was able to address up to 16 MB of RAM, in contrast to 1 MB that the 8086 could directly access. While DOS could utilize this additional RAM () via BIOS call (INT 15h, AH=87h), or as RAM disk, or emulation of , cost and initial rarity of software utilizing extended memory meant that 286 computers were rarely equipped with more than a megabyte of RAM. Additionally, there was a performance penalty involved in accessing extended memory from , as noted below. The 286 was designed to run multitasking applications, including communications (such as automated PBXs), real-time process control, and multi-user systems. The later E-stepping level of the 80286 was a very clean CPU, free of the several significant errata that caused problems for programmers and operating system writers in the earlier B-step and C-step CPUs (common in the AT and AT clones).

Features

An interesting feature of this processor is that it was the first x86 processor with . Protected mode enabled up to 16 MB of memory to be addressed by the on-chip linear (MMU) with 1 GB logical address space. The MMU also provided protection from (crashed or ill-behaved) applications writing outside their allocated memory zones. The MMU and protection mechanisms are enabled only in case of protected mode keeping them disabled in real mode of operation. The use of additional instructions which are helpful for multitasking operating systems are allowed Siemens 80286 (10 MHz version) in protected mode of 80286. Another important feature of 80286 is Prevention of Unauthorised Access. This is achieved by:

• Forming different segments for data,code,stack and preventing their overlapping • Assigning Privilege levels to each segment.Segment with lower privilege level cannot access the segment with higher privilege level. Intel 80286 15

The 80286 provided built in memory protection mechanisms which was then almost exclusive to mainframes and minicomputers (CPUs like the NS320xx and M68000 needed additional components in order to implement MMU functions) and the large performance enhancements represented by the 80286 and many of its successors would pave the way for the x86 and the IBM PC architecture to extend from low performance personal computers all the way to high-end and servers and even drive the market for other architectures.

In 80286, arithmetic operations can be performed on following different types of numbers:

IBM 80286 (8 MHz version)

• unsigned packed decimal, • unsigned binary, • unsigned unpacked decimal, • signed binary, and • floating point numbers. By design, the 286 could not revert from protected mode to the basic 8086-compatible "real mode" without a hardware-initiated reset. In the PC/AT introduced in 1984, IBM added external circuitry as well as specialized code in the ROM BIOS to enable special series of program instructions to cause the reset, allowing real-mode reentry (while retaining active memory and control). Though it worked correctly, the method imposed a huge performance penalty. In theory, real-mode applications could be directly executed in 16-bit protected mode if certain rules were followed; however, as many DOS programs broke those rules, protected mode was not widely used until the appearance of its successor, the 32-bit Intel 80386, which was designed to go back and forth between modes easily. When Intel designed the 286, it was not designed to be able to multitask real-mode applications; real mode was intended to be a simple way for a bootstrap loader to prepare the system and then switch to protected mode. In January 1985, previewed Concurrent DOS 286 in cooperation with Intel. The product would function strictly as an 80286 native mode operating system, allowing users to take full advantage of the protected mode to perform multi-user, multitasking operations while running 8086 emulation.[6] This worked on the B-1 prototype step of the chip, but Digital Research discovered problems with the emulation on the production level C-1 step in May, which would not allow Concurrent DOS 286 to run 8086 software in protected mode. The release of Concurrent DOS 286 was delayed until Intel would develop a new version of the chip.[6] In August, after extensive testing E-1 step samples of the 80286, Digital Research acknowledged that Intel corrected all documented 286 errata, but said there were still undocumented chip performance problems with the prerelease version of Concurrent DOS 286 running on the E-1 step. Intel said the approach Digital Research wished to take in emulating 8086 software in protected mode differed from the original specifications. Nevertheless, they implemented minor changes in the microcode that would allow Digital Research to run emulation mode much faster, incorporated into the E-2 step.[7] Named IBM 4680 OS, IBM originally chose DR Concurrent DOS 286 as the basis of their IBM 4680 computer for IBM Plant System products and Point-of-Sale terminals in 1986.[8] The same limitations affected Digital Research's FlexOS 286 version 1.0, a derivation of Concurrent DOS 286, developed in 1986, introduced in January 1987, and later adopted by IBM for their IBM 4690 OS. The problems led to famously referring to the 80286 as a "brain dead chip",[9] since it was clear that the new environment would not be able to run multiple MS-DOS applications with the 286. It was arguably responsible for the split between Microsoft and IBM, since IBM insisted that OS/2, originally a joint Intel 80286 16

venture between IBM and Microsoft, would run on a 286 (and in text mode).

References

[1] "Microprocessor Hall of Fame" (http:/ / web. archive. org/ web/ 20070706032836/ http:/ / www. intel. com/ museum/ online/ hist_micro/ hof/

). Intel. Archived from the original (http:/ / www. intel. com/ museum/ online/ hist_micro/ hof/ ) on 2007-07-06. . Retrieved 2007-08-11.

[2] " - Microprocessor Hall of Fame" (http:/ / www. intel. com/ museum/ online/ hist_micro/ hof/ index. htm). Intel.com. 2009-05-14. . Retrieved 2009-06-20.

[3] "Intel Architecure [sic] Programming and Information" (http:/ / www. intel80386. com). Intel80386.com. 2004-01-13. . Retrieved 2009-04-28.

[4] "80286 Microprocessor Package, 1982" (http:/ / content. cdlib. org/ ark:/ 13030/ kt7h4nc9c2/ ?layout=metadata& brand=calisphere). Content.cdlib.org. . Retrieved 2009-04-28.

[5] "cpu-world" (http:/ / www. cpu-world. com/ CPUs/ 80286/ ). . [6] Edward Foster. Super DOS awaits new 80286 - Concurrent DOS 286 - delayed until Intel upgrades chip - offers 's power and IBM PC

compatibility. InfoWorld Media Group, InfoWorld, Volume 7, No. 19, 1985-05-13, ISSN 0199-6649, pages 17-18, ( (http:/ / books. google.

com/ books?id=2y4EAAAAMBAJ& lpg=PA57& vq=concurrent pc& hl=en& pg=PA17#v=snippet& q=concurrent pc& f=false)). [7] Edward Foster. Intel shows new 80286 chip - Future of DRI's Concurrent DOS 286 still unclear after processor fixed. InfoWorld Media

Group, InfoWorld, Volume 7, No. 34, 1985-08-26, ISSN 0199-6649, page 21 ( (http:/ / books. google. com/ books?id=_y4EAAAAMBAJ&

lpg=PA21& vq=Concurrent DOS& hl=en& pg=PA21#v=snippet& q=Concurrent DOS& f=false)).

[8] Melissa Calvo and Jim Forbes (1986-02-10). InfoWorld. ed. IBM to use a DRI operating system (http:/ / books. google. com. br/

books?id=oi8EAAAAMBAJ& pg=PA12& dq=InfoWorld+ Concurrent+ DOS& as_pt=MAGAZINES& cd=9#v=onepage& q=InfoWorld

Concurrent DOS& f=false). . Retrieved 2011-09-06. [9] Microprocessors: A Programmer's View, Robert B. K. Dewar and Matthew Smosna, New York: McGraw-Hill, 1990, ISBN 0-07-016638-2

External links

• Intel Datasheets (http:/ / datasheets. chipdb. org/ Intel/ x86/ 286/ datashts)

• Intel 80286 Programmer's Reference Manual 1987(txt) (http:/ / www. ragestorm. net/ downloads/ 286intel. txt). Hint: use e.g. Hebrew (IBM-862) encoding.

• Linux on 286 and notebooks (http:/ / tuxmobil. org/ 286_mobile. html)

• Intel 80286 images and descriptions at cpu-collection.de (http:/ / www. cpu-collection. de/ ?tn=1& l0=cl& l1=80286)

• CPU-INFO: 80286, in-depth processor history (http:/ / www. cpu-info. com/ index2. php?mainid=286)

• Overview of all 286 compatible chips (http:/ / www. cpu-info. com/ index2. php?mainid=Collection&

ID=80286& type=cpu) Intel 80386 17 Intel 80386

Intel 386

Intel 80386 DX rated at 16 MHz Produced From 1985 to September 2007

Common manufacturer(s) • Intel • AMD • IBM

Max. CPU clock rate 12 MHz to 40 MHz

Min. feature size 1.5µm to 1µm

Instruction set x86 (IA-32)

Predecessor Intel 80286

Successor Intel 80486

Package(s) • 132-pin PGA, 132-pin PQFP; SX variant: 88-pin PGA, 100-pin PQFP

The Intel 80386, also known as the , or just 386, was a 32-bit microprocessor introduced by Intel in 1985. The first versions had 275,000 transistors and were used as the (CPU) of many workstations and high-end personal computers of the time. As the original implementation of the 32-bit extension of the 8086 architecture, the 80386 instruction set, programming model, and binary encodings are still the common denominator for all 32-bit x86 processors, this is termed x86, IA-32, or i386-architecture, depending on context. The 80386 could correctly execute most code intended for earlier 16-bit x86 processors such as the 8088 and 80286 that were ubiquitous in early PCs. Following the same tradition, modern 64-bit x86 processors are able to run most programs written for older chips, all the way back to the original 16-bit 8086 of 1978. Over the years, successively newer implementations of the same architecture have become several hundreds of times faster than the original 80386 (and thousands of times faster than the 8086).[1] A 33 MHz 80386 was reportedly measured to operate at about 11.4 MIPS.[2] The 80386 was launched in October 1985, but full-function chips were first delivered in the third quarter of 1986.[3][4] Mainboards for 80386-based computer systems were cumbersome and expensive at first, but manufacturing was rationalized upon the 80386's mainstream adoption. The first to make use of the 80386 was designed and manufactured by Compaq[5] and marked the first time a fundamental component in the IBM PC compatible de facto-standard was updated by a company other than IBM. In May 2006, Intel announced that 80386 production would stop at the end of September 2007.[6] Although it had long been obsolete as a personal computer CPU, Intel and others had continued making the chip for embedded systems. Such systems using an 80386 or one of many derivatives are common in aerospace technology, among others. Some mobile phones also used the 80386 processor, such as BlackBerry 950[7] and Nokia 9000 Intel 80386 18

Communicator.

Architecture

The processor was a significant evolution in the x86 architecture, and extended a long line of processors that stretched back to the Intel 8008. The predecessor of the 80386 was the Intel 80286, a 16-bit processor with a segment-based memory management and protection system. The 80386 added a 32-bit architecture and a paging translation unit, which made it much easier to implement operating systems that used . It also had support for hardware debugging.

The 80386 featured three operating modes: real mode, protected mode and virtual mode. The protected mode which debuted in the Block diagram of the i386 microarchitecture. 286 was extended to allow the 386 to address up to 4 GB of memory. The all new (or VM86) made it possible to run one or more real mode programs in a protected environment, although some programs were not compatible.

The 32-bit of the 386 would arguably be the most important feature change for the x86 processor family until AMD released x86-64 in 2003. Chief architect in the development of the 80386 was John H. Crawford.[8] He was responsible for extending the 80286 architecture and instruction set to 32-bit, and then led the microprogram development for the 80386 chip. The 80486 and P5 Pentium line of processors were descendants of the 80386 design.

Datatypes of 80386 The 80386 supports the following 17 data types,[9] each of which is discussed here in brief. 1. Bit. 2. Bit field-A group of at most 32 bits i.e., 4 bytes. 3. Bit string- A string of continuous bits of maximum 4Gbytes length. 4. Signed Byte- Signed byte data. Sign of the operand depends upon its most significant bit. If it is 0, then the number is positive. else it is negative. Range is from -128 to 127. 5. Unsigned Byte-Unsigned byte data.Range from 0 to 255. 6. Integer word- Signed 16-bit data. Range from -32,768 to 32,767. 7. Long Integer-32-bit signed data that is represented in 2's complement form. Range is from -2.147*109 to 2.1479. 8. Unsigned Integer Word- Unsigned 16-bit data.Range from 0 to 65,535. 9. Unsigned Long Integer-Unsigned 32 bit data. Range from 0 to 4,294,967,295. 10. Signed quad word- A signed 64-bit or four word data. 11. Unsigned Quad Word-An unsigned 64-bit data. 12. Offset-A 16 or 32- bit displacement that references a memory location using any of the addressing modes. 13. Pointer-16-bit selector and 16 or 32 bit offset. 14. Character-An ASCII equavelent to any of the alphanumeric or control characters . 15. Strings-These are the sequences of bytes, words or double words . A string may contain up to maximum 4 Gbytes. Intel 80386 19

16. BCD- Decimal digits from 0-9 represented by unpacked bytes. 17. Packed BCD- This represents two packed BCD digits using a byte from 00 to99.

The i386SX variant

In 1988, Intel introduced the i386SX, a low cost version of the 80386 with a 16-bit data bus. The CPU remained fully 32-bit internally, but the 16-bit bus was intended to simplify circuit board layout and reduce total cost.[10] The 16-bit bus simplified designs but hampered performance. Only 24 pins were connected to the address bus, therefore limiting addressing to 16 MB,[11] but this was not a critical constraint at the time. Performance differences were due not only to differing databus-widths, but also to performance-enhancing cache memories often employed on boards using the original chip. The Intel 80386SX processor of a Compaq Deskpro The original 80386 was subsequently renamed i386DX to avoid computer. confusion. However, Intel subsequently used the 'DX' suffix to refer to the floating-point capability of the i486DX. The i387SX was an i387 part that was compatible with the i386SX (i.e. with a 16-bit databus). The 386SX was packaged in a surface-mount QFP, and sometimes offered in a socket to allow for an upgrade.

The i386SL variant The i386SL was introduced as a power efficient version for computers. The processor offered several power management options (e.g. SMM), as well as different "sleep" modes to conserve battery power. It also contained support for an external cache of 16 to 64 kB. The extra functions and circuit implementation techniques caused this variant to have over 3 times as many transistors as the i386DX. The i386SL was first available at 20 MHz clock speed,[12] with the 25 MHz model later added.[13]

Business importance The first company to design and manufacture a PC based on the Intel 80386 was Compaq. By extending the 16/24-bit IBM PC/AT standard into a natively 32-bit computing environment, Compaq became the first third party to implement a major technical hardware advance on the PC platform. IBM was offered use of the 80386, but had manufacturing rights for the earlier 80286. IBM therefore chose to rely on that processor for a couple of more years. The early success of the Compaq 386 PC played an important role in legitimizing the PC "clone" industry, and in de-emphasizing IBM's role within it. Prior to the 386, the difficulty of manufacturing microchips and the uncertainty of reliable supply made it desirable that any mass-market semiconductor be multi-sourced, that is, made by two or more manufacturers, the second and subsequent companies manufacturing under license from the originating company. The 386 was for a time only available from Intel, since Andy Grove, Intel's CEO at the time, made the decision not to encourage other manufacturers to produce the processor as second sources. This decision was ultimately crucial to Intel's success in the market. The 386 was the first significant microprocessor to be single-sourced. Single-sourcing the 386 allowed Intel greater control over its development and substantially greater profits in later years. AMD introduced its compatible processor in March 1991 after overcoming legal obstacles, thus ending Intel's monopoly on 386-compatible processors. IBM also later manufactured 386 chips under license. Intel 80386 20

Compatibles

• The AMD Am386SX and Am386DX were almost exact clones of the 80386SX and 80386DX. Legal disputes caused production delays for several years, but AMD's 40 MHz part eventually became very popular with computer enthusiasts as a low cost and low power alternative to the 25 MHz 486SX. The power draw was further reduced in the "notebook models" (Am386 DXL/SXL/DXLV/SXLV) which could operate with 3.3V and were implemented in fully static CMOS circuitry.

• Super386 38600SX and 38600DX were developed using reverse engineering. They sold poorly, due to some technical errors and incompatibilities, as well as their late Intel i386 packaged by IBM. appearance on the market. They were therefore short-lived products. • Cyrix Cx486SLC/Cx486DLC could be (simplistically) described as a kind of 386/486 hybrid chip that included a small amount of on-chip cache. It was popular among computer enthusiasts but did poorly with OEMs. The Cyrix Cx486SLC and Cyrix Cx486DLC processors were pin-compatible with 80386SX and 80386DX respectively. These processors were also manufactured and sold by Texas Instruments. • IBM 386SLC and 486SLC/DLC were variants of Intel's design which contained a large amount of on-chip cache (8 kB, and later 16 kB). The agreement with Intel limited their use to IBM's own line of computers and upgrade boards only, so they were not available on the open market.

Early problems

Intel originally intended for the 80386 to debut at 16 MHz. However, due to poor yields, it was instead introduced at 12 MHz. Early in production, Intel discovered a bug that could cause a system to unexpectedly halt when running 32-bit software. Not all of the processors already manufactured were affected, so Intel tested its inventory. Processors that were found to be bug-free were marked with a double-sigma (ΣΣ), and affected processors were marked "16 BIT S/W ONLY". These latter processors were sold as good parts, since at the time 32 bit capability was not relevant for most users. Such chips are now extremely rare.

The i387 math coprocessor was not ready in time for the introduction An Intel 80386 marked "16 BIT S/W ONLY". of the 80386, and so many of the early 80386 instead provided a socket and hardware logic to make use of an 80287. In this configuration the FPU would operate asynchronously to the CPU, usually with a clock rate of 10 MHz. The original Compaq Deskpro 386 is an example of such design. However, this was an annoyance to those who depended on floating point performance, as the performance of the 287 was nowhere near that of the 387. Intel 80386 21

Pin-compatible upgrades

Intel later offered a modified version of its 80486DX in 80386 packaging, branded as the Intel RapidCAD. This provided an upgrade path for users with 80386-compatible hardware. The upgrade was a pair of chips that replaced both the 80386 and 80387. Since the 80486DX design contained an FPU, the chip that replaced the 80386 contained the floating point functionality, and the chip that replaced the 80387 served very little purpose. However, the latter chip was necessary in order to provide the FERR signal to the mainboard and appear to function as a normal floating point unit. The CAD branding referred to the ease of upgrading existing OEM designs from 386 to 486 CPUs with rapid turn-around in the CAD room.

Third parties offered a wide range of upgrades, for both SX and DX systems. The most popular ones were based on the Cyrix 486DLC/SLC core, which typically offered a substantial speed improvement due to its more efficient instruction and internal L1 SRAM cache. The cache was usually 1 kB, or sometimes 8 kB in the TI variant. Some of these upgrade chips (such as the 486DRx2/SRx2) were marketed by Cyrix themselves, but they were more commonly found in kits offered by upgrade specialists such as Kingston, Evergreen and Improve-It Technologies. Some of the fastest CPU Typical 386 Upgrade CPUs from Cyrix upgrade modules featured the IBM SLC/DLC family (notable for its 16 kB and Texas Instruments. L1 cache), or even the Intel 486 itself. Many 386 upgrade kits were advertised as being simple drop-in replacements, but often required complicated software to control the cache and/or clock doubling. Part of the problem was that on most 386 motherboards, the was controlled entirely by the motherboard with the CPU being unaware, which caused problems on CPUs with internal caches.

Overall it was very difficult to configure upgrades to produce the results advertised on the packaging, and upgrades were often less than 100% stable and/or less than 100% compatible.

Models and variants

Early 5V models

i386DX

Original version, released in October 1985. • Capable of working with 16- or 32-bit external busses • Cache: depends on mainboard • Package: PGA-132 or PQFP-132 • Process: First types CHMOS III, 1.5 µm, later CHMOS IV, 1 µm • Die size: 104 mm² (ca. 10 mm x 10 mm) in CHMOS III and 39 mm² (6 mm x 6.5 mm) in CHMOS IV. • : 275 000 • Specified max clock: 12 MHz (early models), later 16, 20, 25 and 33 MHz

Intel i386DX, 25 MHz. Intel 80386 22

RapidCAD

A specially packaged Intel 486DX and a dummy floating point unit (FPU) designed as pin-compatible replacements for an Intel 80386 processor and 80387 FPU.

Versions for embedded systems

i376

This was an embedded version of the i386SX which did not support real mode and paging in the MMU.

i386SX 16 MHz.

i386EX, i386EXTB and i386EXTC

System and power management and built in peripheral and support functions: Two 82C59A interrupt controllers; Timer, Counter (3 channels); Asynchronous SIO (2 channels); Synchronous SIO (1 channel); Watchdog timer (Hardware/Software); PIO. Usable with i387SX or i387SL FPUs. • Data/address bus: 16 / 26 bits • Package: PQFP-132, SQFP-144 and PGA-168 • Process: CHMOS V, 0.8 µm • Specified max clock: • i386EX: 16 MHz @2.7~3.3 volt or 20 MHz @3.0~3.6 volt or 25 MHz @4.5~5.5 volt • i386EXTB: 20 MHz @2.7~3.6 volt or 25 MHz @3.0~3.6 volt Intel i386EXTC, 25 MHz. • i386EXTC: 25 MHz @4.5~5.5 volt or 33 MHz @4.5~5.5 volt

i386CXSA and i386SXSA (or i386SXTA)

Transparent power management mode, integrated MMU and TTL compatible inputs (only 386SXSA). Usable with i387SX or i387SL FPUs. • Data/address bus: 16 / 26 bits (24 bits for i386SXSA) • Package: PQFP-100 • Voltage: 4.5~5.5 volt (25 and 33 MHz); 4.75~5.25 volt (40 MHz) • Process: CHMOS V, 0.8 µm • Specified max clock: 25, 33, 40 MHz

i386CXSB

Transparent power management mode and integrated MMU. Usable with i387SX or i387SL FPUs. Intel i386CXSA, 25 MHz. • Data/address bus: 16 / 26 bits Intel 80386 23

• Package: PQFP-100 • Voltage: 3.0 volt (16 MHz) or 3.3 volt (25 MHz) • Process: CHMOS V, 0.8 µm • Specified max clock: 16, 25 MHz

Notes and references [1] Not counting the advances in the performance of corresponding x87 implementations. These are measured in tens of thousands of times, compared to the original 8087, or hundreds of thousands of times compared to software implementations of floating point on the 8086.

[2] Intel 80386 (http:/ / intel80386. com)

[3] Forbes, Jim (January 27, 1986). "Development of 386 Accelerating" (http:/ / books. google. com/ books?id=my8EAAAAMBAJ& pg=PA5). InfoWorld (InfoWorld Media Group) 8 (4): p. 5. ISSN 0199-6649. .Introduced October 1985, production chip in June 1986

[4] Ranney, Elizabeth (September 1, 1986). "ALR Hopes to Beat Completion With Fall Release of 386 Line" (http:/ / books. google. com/

books?id=cS8EAAAAMBAJ& pg=PA5). InfoWorld (InfoWorld Media Group) 8 (35): p. 5. ISSN 0199-6649. .First 80386 computers released around October 1986

[5] http:/ / web. archive. org/ web/ 20090627055110/ http:/ / www. crn. com/ crn/ special/ supplement/ 816/ 816p65_hof. jhtml

[6] "Intel cashes in ancient chips" (http:/ / www. reghardware. co. uk/ 2006/ 05/ 18/ intel_cans_386_486_960_cpus/ ). .

[7] http:/ / the-gadgeteer. com/ 2001/ 02/ 26/ rim_blackberry_950_review/

[8] "Intel Fellow - John H. Crawford" (http:/ / www. intel. com/ pressroom/ kits/ / crawford. htm). Intel.com. 2010-08-16. . Retrieved 2010-09-17. [9] A K Ray, K M Bhurchandi, “Advanced microprocessors and peripherals” [10] This was a similar approach to that used by Intel with the 8088 that was used in the original IBM PC. [11] The 16 MB limit was similar to that of the 68000, a comparable processor.

[12] "Chronology of Microprocessors (1990-1992)" (http:/ / www. islandnet. com/ ~kpolsson/ micropro/ proc1990. htm). Islandnet.com. . Retrieved 2010-09-17.

[13] Mueller, Scott. "Microprocessor Types and Specifications > P3 (386) Third-Generation Processors" (http:/ / www. informit. com/ articles/

article. aspx?p=130978& seqNum=27). InformIT. . Retrieved 2010-09-17.

External links

• Intel 80386 Programmer's Reference Manual 1986 (PDF) (http:/ / www. microsym. com/ content/ index.

php?pid=4& id=25)

• Intel 80386 processor family (http:/ / www. cpu-world. com/ CPUs/ 80386/ ) x87 24 x87

x87 is a floating point-related subset of the x86 architecture instruction set. It originated as an extension of the 8086 instruction set in the form of optional floating point that worked in tandem with corresponding x86 CPUs. These microchips had names ending in "87". Like other extensions to the basic instruction set, x87-instructions are not strictly needed to construct working programs, but provide hardware and microcode implementations of common numerical tasks, allowing these tasks to be performed much faster than corresponding machine code routines can. The x87 instruction set includes instructions for basic floating point operations such as addition, subtraction and comparison, but also for more complex numerical operations, such as the computation of the tangent function and its inverse, for example. Most x86 processors since the Intel 80486 have had these x87 instructions implemented in the main CPU but the term is sometimes still used to refer to that part of the instruction set. Before x87 instructions were standard in PCs, compilers or programmers had to use rather slow library calls to perform floating-point operations, a method that is still common in (low-cost) embedded systems.

Description The x87 registers form an 8-level deep non-strict stack structure ranging from ST(0) to ST(7) with registers that can be directly accessed by either operand, using an offset relative to the top, as well as pushed and popped. (This scheme may be compared to how a stack frame may be both pushed, popped and indexed.) There are instructions to push, calculate, and pop values on top of this stack; monadic operations (FSQRT, FPTAN etc.) then implicitly address the topmost ST(0) while dyadic operations (FADD, FMUL, FCOM, etc.) implicitly address ST(0) and ST(1). The non-strict stack-model also allows dyadic operations to use ST(0) together with a direct memory operand or with an explicitly specified stack-register, ST(x), in a role similar to a traditional accumulator (a combined destination and left operand). This can also be reversed on an instruction-by-instruction basis with ST(0) as the unmodified operand and ST(x) as the destination. Furthermore, the contents in ST(0) can be exchanged with another stack register using an instruction called FXCH ST(x). These properties makes the x87 stack usable as seven freely addressable registers plus a dedicated accumulator (or as seven independent accumulators). This is especially applicable on superscalar x86 processors (such as the Pentium of 1993 and later) where these exchange instructions (codes D9C8..D9CF ) are optimized down to a zero clock h penalty by using one of the integer paths for FXCH ST(x) in parallel with the FPU instruction. Despite being natural and convenient for human assembly language programmers, some compiler writers have found it complicated to construct automatic code generators that schedule x87 code effectively. The x87 provides single precision, double precision and 80-bit double- binary floating-point arithmetic as per the IEEE 754-1985 standard. By default, the x87 processors all use 80-bit double-extended precision internally (to allow for sustained precision over many calculations). A given sequence of arithmetic operations may thus behave slightly differently compared to a strict single-precision or double-precision IEEE 754 FPU.[1] This may sometimes be problematic for some semi-numerical calculations relying on knowledge of exact FPU precision for correct operation. To avoid such problems, the x87 can be configured via a special configuration/status register to automatically round to single or double precision after each operation. Since the introduction of SSE2, the x87 instructions are not as essential as they once were, except for high-precision calculations demanding the 64-bit mantissa precision available in the 80-bit format. x87 25

Performance Clock cycle counts for examples of typical x87 FPU instructions (only register-register versions shown here).[2] The A~B notation (minimum to maximum) covers timing variations dependent on transient pipeline status as well as the arithmetic precision chosen (32, 64 or 80 bits); it also includes variations due to numerical cases (such as the number of set bits, zero, etc.). The L→H notation depicts values corresponding to the lowest (L) and the highest (H) maximum clock frequencies that were available.

x87 FADD FMUL FDIV FXCH FCOM FSQRT FPTAN FPATAN Max Clock Peak Relative implementation FMUL/sec 5 MHz 8087§ FMUL

8087 70~100 90~145 193~203 10~15 40~50 180~186 30~540 250~800 5→10 MHz 34~55K → 1.0 → 2.0 100~111K times as fast

80287 (original) 70~100 90~145 193~203 10~15 40~50 180~186 30~540 250~800 6→12 MHz 41~66K → 1.2 → 2.4 83~133K times as fast

80387 (and later 23~34 29~57 88~91 18 24 122~129 191~497 314~487 16→33 MHz 280~552K → approx 10 287 models) 579~1100K → 20 × as fast

80486 (or 80487) 8~20 16 73 4 4 83~87 200~273 218~303 16→50 MHz 1.0M → 3.1M approx 18 → 56 × as fast

Cyrix 6x86, Cyrix 4~7 4~6 24~34 2 4 59~60 117~129 97~161 66→300 MHz 11~16M → approx MII 50~75M 320 → 1400 ×

AMD K6 2 2 todo 2 todo todo todo todo 166→550 MHz 83M → 275M approx (including K6 1500 → II/III) 5000 ×

Pentium / 1~3 1~3 39 1 (0*) 1~4 70 17~173 19~134 60→300 MHz 20~60M → approx Pentium MMX 100~300M 1100 → 5400 ×

Pentium Pro 1~3 2~5 16~56 1 (0*) 1 28~68 todo todo 150→200 MHz 30~75M → approx 40~100M 1400 → 1800 ×

Pentium II / III 1~3 2~5 17~38 1 (0*) 1 27~50 todo todo 233→1400 MHz 47~116M → approx 280~700M 2100 → 13000 ×

Athlon (K7) 1~4 1~4 13~24 1 (0*) 1~2 16~35 todo todo 500→2330 MHz 125~500M → approx 0.580~2.33G 9000 → 42000 ×

Pentium 4 1~5 2~7 20~43 1 (0*) todo 20~43 todo todo 1.3→3.8 GHz 186~650M → approx 0.543~1.90G 11000 → 34000 ×

Athlon 64 (K8) 1~4 1~4 13~24 1 (0*) 1~2 16~35 todo todo 1.0→3.2 GHz 250~1000M approx → 18000 → 0.800~3.2G 58000 ×

* An effective zero clock delay is often possible, via superscalar execution. x87 26

§ The 5 MHz 8087 was the original x87 processor. Compared to typical software-implemented floating point routines on an 8086 (without an 8087), the factors would be even larger, perhaps by another factor of 10 (i.e., a correct floating point addition in assembly language may well consume over 1000 cycles).

Manufacturers Companies that have designed and/or manufactured floating point units compatible with the Intel 8087 or later models include AMD (287, 387, 486DX, 5x86, K5, K6, K7, K8), Chips and Technologies (the Super MATH coprocessors), Cyrix (the FasMath, Cx87SLC, Cx87DLC, etc., 6x86, Cyrix MII), Fujitsu (early Pentium Mobile etc.), Harris Semiconductor (manufactured 80387 and 486DX processors), IBM (various 387 and 486 designs), IDT (the WinChip, C3, C7, Nano, etc.), IIT (the 2C87, 3C87, etc.), LC Technology (the Green MATH coprocessors), National Semiconductor (the GX1, Geode GXm, etc.), NexGen (the Nx587), Rise Technology (the mP6), ST Microelectronics (manufactured 486DX, 5x86, etc.), Texas Instruments (manufactured 486DX processors etc.), Transmeta (the TM5600 and TM5800), ULSI (the Math·Co coprocessors), VIA (the C3, C7, and Nano, etc.), and Xtend (the 83S87SX-25 and other coprocessors).

Architectural generations

8087 The 8087 was the first math coprocessor for 16-bit processors designed by Intel (the I8231 was older but designed for the 8-bit ); it was built to be paired with the Intel 8088 or 8086 microprocessors.

80287

The 80287 (i287) was the math coprocessor for the Intel 80286 series of microprocessors. Intel (and its competitors) later introduced an 80287XL, which was actually an 80387SX with a 287 pinout. The 80287XL contained an internal 3/2 multiplier so that motherboards which ran the coprocessor at 2/3 CPU speed could instead run the FPU at the same speed of the CPU. Other 287 models with 387-like performance were the Intel 80C287, built using CHMOS III, and the AMD 80EC287 manufactured in AMD's CMOS 6 MHz version of the Intel 80287 process, using only fully static gates.

The 80287 and 80287XL also worked with the 80386 microprocessor, and were initially the only coprocessors available for the 80386 until the introduction of the 80387 in 1987. Finally, they were also able to work with the Cyrix Cx486SLC. However, for both of these chips the 80387 was strongly preferred for its higher performance and the greater capability of its instruction set. Intel 80287XL.

Intel's models included i80287 variants with specified upper frequency limits ranging from 6 up to 12 MHz. Later followed the i80287XL with 387 microarchitecture and the i80287XLT, a special version intended for laptops, as well as other variants. x87 27

80387

The 80387 (387 or i387) was the first Intel coprocessor to be fully compliant with the IEEE 754 standard. Released in 1987, a full two years after the 386 chip, the i387 included much improved speed over Intel's previous 8087/80287 coprocessors, and improved the characteristics of trigonometric functions. (The 80287 limited the argument range to plus or minus 45 degrees.)

Without a coprocessor, the 386 normally performed floating-point arithmetic through (slow) software routines, implemented at runtime through a software Intel 80287XLT. exception-handler. When a math coprocessor is paired with the 386, the coprocessor performs the floating point arithmetic in hardware, returning results much faster than an (emulating) software library call. The i387 was compatible only with the standard i386 chip, which had a 32-bit processor bus. The later cost-reduced i386SX, which had a narrower 16-bit data bus, could not interface with the i387's 32-bit bus. The i386SX required its own coprocessor, the 80387SX, which was compatible with the SX's narrower 16-bit data bus.

16 MHz version of the Intel 80187

i387 i387SX i387DX i387 microarchitecture with 16-bit Barrel shifter and CORDIC unit x87 28

80187

The 80187 (80C187)[3] was the math coprocessor for Intel 80186 CPU. It is incapable of operating with the 80188, as the 80188 has a 8 bit data bus; the 80188 can only use the 8087. The 80187 did not appear at the same time as the 80186 and 80188, but was in fact launched after the 80287 and the 80387. Although the interface to the main processor was the same as the 8087, its core was that of the 80387, and was thus fully IEEE 754 compliant as well as capable of executing all the 80387's extra instructions.[4]

i487SX

80487 The i487SX was marketed as a floating point unit coprocessor for Intel i486SX machines. It actually contained a full-blown i486DX implementation. When installed into an i486SX system, the i487 disabled the main CPU and took over all CPU operations. The i487 took measures to detect the presence of an i486SX and would not function without the original CPU in place.[5]

80587 The Nx587 was the last FPU for x86 to be manufactured separately from the CPU, in this case NexGen's Nx586.

References

[1] David Monniaux, The pitfalls of verifying floating-point computations (http:/ / hal. archives-ouvertes. fr/ hal-00128124/ en), to appear in ACM TOPLAS [2] Numbers are taken from respective processors' data sheets, programming manuals, and/or optimization manuals.

[3] CPU Collection - Model 80187 (http:/ / www. cpu-info. com/ index2. php?mainid=Overview& showm=8)

[4] http:/ / www. datasheetcatalog. org/ datasheet/ Intel/ mXryvuw. pdf

[5] Dictionary.com, ed. "Intel 487SX" (http:/ / dictionary. reference. com/ browse/ Intel+ 487SX). . Retrieved 2010-10-17. • Intel Corp., IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture, order number 253665-017

External links

• Coprocessor.info : x86 Coprocessor development & history knowledge (http:/ / www. coprocessor. info)

• Everything you always wanted to know about math coprocessors (http:/ / wiretap. area. com/ Gopher/ Library/

Techdoc/ Cpu/ coproc. txt) Intel 80486 29 Intel 80486

Intel 486

The exposed die of an Intel 80486DX2 microprocessor. Produced From 1989 to 2007

Common manufacturer(s) • Intel, IBM, AMD, Texas Instruments, Harris Semiconductor, UMC, SGS Thomson

Max. CPU clock rate 16 MHz to 100 MHz

FSB speeds 16 MHz to 50 MHz

Min. feature size 1µm to 0.6µm

Instruction set x86 (IA-32) including x87 for DX models

Predecessor Intel 80386

Successor Pentium (P5)

Package(s) • PGA (, 2, 3), 196-pin PQFP

The Intel 80486 microprocessor (alias or Intel486) was a higher performance follow up on the Intel 80386. Introduced in 1989, it was the first tightly[1] pipelined x86 design as well as the first x86 chip to use more than a million transistors, due to a large on-chip cache and an integrated floating point unit. It represents a fourth generation of binary compatible CPUs since the original 8086 of 1978. A 50 MHz 80486 executed around 40 million instructions per second on average and was able to reach 50 MIPS peak. The i486 was without the usual 80-prefix because of a court ruling that prohibited trademarking numbers (such as 80486). Later, with the introduction of the Pentium brand, Intel began branding its chips with words rather than numbers.

Background The 80486 was announced at Spring Comdex in April 1989. At the announcement, Intel stated that samples would be available in the third quarter of 1989 and production quantities would ship in the fourth quarter of 1989.[2] The first 80486-based PCs were announced in late 1989, but some advised that people wait until 1990 to purchase an 80486 PC because there were early reports of bugs and software incompatibilities.[3]

Improvements The instruction set of the i486 is very similar to its predecessor, the Intel 80386, with the addition of only a few extra instructions, such as CMPXCHG which executes the compare-and-swap atomic operation and the XADD which executes the fetch-and-add atomic operation returning the original value, unlike the ADD instruction that only returned some flags. Intel 80486 30

From a performance point of view, the architecture of the i486 is a vast improvement over the 80386. It has an on-chip unified instruction and data cache, an on-chip floating-point unit (FPU), except in the SX and SL models, and an enhanced bus interface unit. Simple instructions (such as ALU reg, reg) execute in one clock cycle. These improvements yield a rough doubling in ALU performance over the 386 at the same clock rate. A 16-MHz 486 therefore has a performance similar to a 33-MHz 386, and the older design has to reach 50 MHz to be comparable with a 25-MHz 486 part.[4]

Differences between i386 and i486

• An 8 KB on-chip SRAM cache stores the most recently used instructions and data (16 KB and/or write-back on some later models). The 386 had no such internal cache but supported a slower off-chip cache. • Tightly coupled pipelining allows the 486 to complete a simple instruction like ALU reg,reg or ALU reg,im every clock cycle. The 386 needed two clock cycles for this. • Integrated FPU (disabled or absent in SX models) with a dedicated local bus; The 486DX2 architecture. together with faster algorithms on more extensive hardware than in the i387, this gives faster floating point calculations compared to the i386+i387 combination. • Improved MMU performance. The 486 has a 32-bit data bus and a 32-bit address bus. This required either four matched 30-pin (8-bit) or one 72-pin (32-bit) SIMM on a typical PC motherboard. Just like the 80386, the 32-bit address bus of the 80486 enabled up to 4 gigabytes of memory to be directly addressed using a flat memory model with 32-bit linear addresses in protected mode. Just as with the 80386, the ability to use memory directly without segmentation helped performance in compliant operating systems and applications.

Models There are several suffixes and variants including: • i486DX: The original chip (without any clock doubling). • i486DX-S: SL Enhanced 486DX • Intel RapidCAD: a specially packaged Intel 486DX and a dummy floating point unit (FPU) designed as pin-compatible replacements for an Intel 80386 processor and 80387 FPU. • i486SX: an i486DX with the FPU part disabled or missing. Early variants were parts with disabled (defective) FPUs, later versions had the FPU removed from the die to reduce area and hence cost. • i486SX-S: SL Enhanced 486SX • i486DX2: the internal processor clock runs at twice the clock rate of the external bus clock. • i486SX2: i486DX2 with the FPU disabled. • i486SL: low power version of the i486DX, reduced VCore, SMM (), stop clock, and power saving features - mainly for use in portable computers. • i486SL-NM: i486SL based on i486SX Intel 80486 31

• i487SX: i486DX with a slightly different pinout sold as an FPU upgrade to i486SX systems; it was widely documented that an i487SX when installed completely disabled the existing i486SX on the motherboard, replacing it. • i486 OverDrive: i486SX, i486SX2, i486DX2 or i486DX4. Marked as upgrade processors, some models had different pinouts or voltage handling abilities from 'standard' chips of the same speed stepping. Fitted to a coprocessor or "OverDrive" socket on the motherboard, worked the same as the i487SX. • i486DX4: designed to run at triple clock rate (not quadruple as often believed; the DX3, which was meant to run at 2.5x the clock speed, was never released). DX4 models that featured write-back cache were identified by an "&EW" laser etched into their top surface, while the write-through models were identified by "&E". • i486GX: Embedded Ultra-Low power CPU with all features of the i486SX and 16 Bit external data bus. This CPU is for embedded battery-operated and hand-held applications. The specified maximum internal clock frequency (on Intel's versions) ranged from 16 to 100 MHz. The 16 MHz i486SX model was used by Computers. One of the few 486 models specified for a 50 MHz bus (486DX-50) initially had overheating problems and was moved to the 0.8 micrometre fabrication process. However, problems continued when the 486DX-50 was installed in local bus systems due to the high bus speed, making it rather unpopular with mainstream consumers as local bus video was considered a requirement at the time, though it remained popular with users of EISA systems. The 486DX-50 was soon eclipsed by the clock-doubled i486DX2 which instead ran the CPU logic at twice the external bus speed. More powerful 486 iterations such as the OverDrive and DX4 were less popular (the latter available as an OEM part only), as they came out after Intel had released the next generation P5 Pentium processor family. Certain steppings of the DX4 also officially supported 50 MHz bus operation but was a seldom used feature.

Model Specified max clock Voltage L1-Cache Introduced

i486DX (P4) 20,25,33 MHz; 50 MHz 5V 8 KB WT April 1989; April 1989; May 1990; June 1991

i486SL 20,25,33 MHz 5V or 8 KB WT Nov 1992 3.3V

i486SX (P23) 16,20,25 MHz (33 MHz) 5V 8 KB WT September 1991 (September 1992)

i486DX2 (P24) 40/20, 50/25 MHz 5V 8 KB WT March 1992 (August 1992) (66/33 MHz) Intel 80486 32

i486DX-S (P4S) 33 MHz; 50 MHz 5V or 8 KB WT June 1993 3.3V

i486DX2-S (P24S) 40/20, 50/25 MHz 5V or 8 KB WT June 1993 (66/33 MHz) 3.3V

i486SX-S (P23S) 25,33 MHz 5V or 8 KB WT June 1993 3.3V

i486SX2 50/25, 66/33 MHz 5V 8 KB WT March 1994

IntelDX4 (P24C) 75/25, 100/33 MHz 3.3V 16 KB March 1994 WT

IntelDX4WB 100/33 MHz 3.3V 16 KB October 1994 WB

i486DX2WB 50/25, 66/33 MHz 5V 8 KB WB October 1994 (P24D)

i486DX2 (P24LM) 90/30 MHz; 100/33 MHz 2.5-2.9V 8 KB WT 1994

i486GX up to 33 MHz 3.3V 8 KB WT

WT = Write-Through cache strategy, WB = Write-Back cache strategy Intel 80486 33

Other makers of 486-like CPUs

486 compatible processors have been produced by other companies such as IBM, Texas Instruments, AMD, Cyrix, UMC, and SGS Thompson. Some were clones (identical at the microarchitectural level), others were clean-room implementations of the Intel instruction-set. (IBM's multiple source requirement is one of the reasons behind its x86-manufacturing since the 80286.) The 486 was, however, covered by many of Intel's patents covering new R&D as well as that of the prior 80386. Intel and IBM have broad cross-licenses of these patents, and AMD was granted rights to the relevant patents in the 1995 settlement of a lawsuit between the companies.[5]

AMD produced several clones of the 486 using a 40 MHz bus (486DX-40, STMicroelectronics It's ST 486DX/2-80, and 486DX/4-120) which had no equivalent available from ST486DX2-40. Intel, as well as a part specified for 90 MHz, using a 30 MHz external clock, that was sold only to OEMs. The fastest running 486 CPU, the , ran at 133 MHz and was released by AMD in 1995. 150 MHz and 160 MHz parts were planned but never officially released.

Cyrix made a variety of 486-compatible processors, positioned at the cost-sensitive desktop and low-power (laptop) markets. Unlike AMD's 486 clones, the Cyrix processors were the result of clean-room reverse-engineering. Cyrix's early offerings included the 486DLC and 486SLC, two hybrid chips which plugged into 386DX or SX sockets respectively, and offered 1 KB of cache (versus 8 KB for the then-current Intel/AMD parts). Cyrix also made "real" 486 processors, which plugged into

the i486's socket and offered 2 or 8 KB of cache. Clock-for-clock, the UMC Green CPU U5SX. Cyrix-made chips were generally slower than their Intel/AMD equivalents, though later products with 8 KB caches were more competitive, if late to market. The (best known for its use in the Quadra series), while not compatible with the 486, was often positioned as the 486's equivalent in features and performance.[6] While the 68040 outperformed the 486 significantly on a clock for clock basis[7], the 486 had the ability to be clocked significantly faster without suffering from overheating problems. For a time Apple attempted to compete with Intel's clock doubling 486DX2 systems by publicizing doubled clock rates for its '040-based Macintosh Performa systems, despite the lack of any clock doubling. Intel 80486 34

Motherboards and buses

Early 486 machines were equipped with several ISA slots (using an emulated PC/AT-bus) and sometimes one or two 8-bit-only slots (compatible with the PC/XT-bus).[8] Many motherboards enabled of these up from the default 6 or 8 MHz to perhaps 16.5 or 20 MHz (half the i486 bus clock) in a number of steps, often from within the BIOS setup. Especially older peripheral cards normally worked well at such speeds as they often used standard MSI chips instead of slower (at the time) custom VLSI designs. This could give significant performance gains (such as for old video cards moved from a 386 or 286 computer, for example). However, operation beyond 8 or 10 MHz could sometimes lead to stability problems, at least in systems equipped with SCSI or sound cards.

Some motherboards came equipped with a 32-bit bus called EISA that was backward compatible with the ISA-standard. EISA offered a number of attractive features such as increased bandwidth, extended addressing, IRQ sharing, and card configuration through software (rather than through jumpers, DIP The first 486 system from Britain on the cover of switches, etc.) However, EISA cards were expensive and therefore BYTE, September 1989 mostly employed in servers and workstations. Consumer desktops often used the simpler but faster VESA Local Bus (VLB), unfortunately somewhat prone to electrical and timing-based instability; typical consumer desktops had ISA slots combined with a single VLB slot for a video card. VLB was gradually replaced by PCI during the final years of the 80486 period. Few Pentium class motherboards had VLB support as VLB was based directly on the i486 bus; it was no trivial matter adapting it to the quite different P5 Pentium-bus. ISA persisted through the P5 Pentium generation and was not completely displaced by PCI until the Pentium III era.

Late 486 boards were normally equipped with both PCI- and ISA-slots, and sometimes a single VLB slot as well. In this configuration VLB or PCI throughput suffered depending on how buses were bridged. The VLB slot in these systems was usually only fully compatible with video cards (quite fitting as "VESA" stands for Video Electronics Standards Association); VLB-IDE, multi I/O, or SCSI cards could have problems on motherboards with PCI slots. The VL-Bus operated at the same clock speed as the i486-bus (basically being a local 486-bus) while the PCI bus also usually depended on the i486 clock but sometimes had a divider setting available via the BIOS. This could be set to 1/1 or 1/2, sometimes even 2/3 (for 50 MHz CPU clocks). Some motherboards limited the PCI clock to the specified maximum of 33 MHz and certain network cards depended on this frequency for correct bit-rates. The ISA clock was typically generated by a divider of the CPU/VLB/PCI clock (as implied above). One of the earliest complete systems to use the 80486 chip was the Apricot VX FT, produced by United Kingdom hardware manufacturer Apricot Computers. Even overseas in the United States it drew attention as "The World's First 486" in a popular September 1989 issue of Byte magazine (shown right). Later 486 boards also supported Plug-And-Play, a specification designed by Microsoft to make component installation easier for consumers that began as a part of . Intel 80486 35

Gaming The 486DX2 66 MHz processor was popular with many players of video games during the early to mid 1990s, toward the end of the MS-DOS gaming era. It was often coupled with a VESA Local Bus video card. The introduction of 3D computer graphics spelled the end of the 486's reign, because 3D graphics make heavy use of floating point calculations, need faster CPU cache and more memory bandwidth. Developers began to target the P5 Pentium processor family almost exclusively with optimizations (e.g., Quake) which led to the usage of terms like "Pentium compatible processor" for software requirements. Many of these games required the speed of the P5 Pentium processor family's double-pipelined architecture.

Obsolescence The AMD Am5x86, up to 150 MHz, and Cyrix Cx5x86, up to 120 MHz, were the last 486 processors that were often used in late generation 486 motherboards with PCI slots and 72-pin SIMMs that are designed to be able to run Windows 95, and also often used as upgrades for older 486 motherboards. While the Cyrix Cx5x86 faded quite quickly when the took over, the AMD Am5x86 was important during the time when the AMD K5 was delayed. In the general purpose desktop computer role, the 486s were used as budget machines for people who could not afford the latest computers, until around 2001, when Windows 95 support ended and , ME, 2000, and XP required much more powerful computers to perform well. Although the 486 became obsolete for personal computer applications by the mid-1990s, Intel had continued production for use in embedded systems. In May 2006 Intel announced that production of the 80486 would stop at the end of September 2007.[9]

Notes and references [1] The 386, 286, and even the 8086 was already somewhat pipelined, i.e. they all had somewhat overlapping fetch, decode, execution (calculation), and write back; however, "tightly pipelined" (or "risc like") usually means that the pipeline stages overlaps 100% for important instructions, i.e. that all stages are bound to perform their respective duties within the same length time slot. In contrast "loosely pipelined" usually implies that some kind of buffering is used to decouple the units and allow them to work a little more independently. Both the original 8086 and the high performance x86-chips of today are, although very different, "loosely pipelined" in this sense. [2] 80486 32-bit CPU breaks new ground in chip density and operating performance. (Intel Corp.) (product announcement) EDN | May 11, 1989 | Pryce, Dave

[3] Lewis, Peter H. (October 22, 1989). "THE EXECUTIVE COMPUTER; The Race to Market a 486 Machine" (http:/ / www. nytimes. com/

1989/ 10/ 22/ business/ the-executive-computer-the-race-to-market-a-486-machine. html?pagewanted=1). The New York Times. . Retrieved May 5, 2010. [4] The "low-end" 16 and 25 MHz 486 parts did not use a clock multiplier and are therefore comparable to a 386/286 clock by clock.

[5] amd.com (http:/ / www. amd. com/ us-en/ assets/ content_type/ DownloadableAssets/ AMD_-_Intel_Litigation_History. pdf)

[6] (http:/ / www. bbs. ingedigit. com. ve/ TechInfo/ 68040. Microprocessor. html)

[7] (http:/ / www. stevenmatarazzo. com/ oldmac/ AppleGuides/ Macintosh_CPUs_and_Expansion_Cards/ 68040_Microprocessor. pdf) [8] In general, 8-bit ISA slots in these systems were implemented just by leaving off the shorter "C"/"D" connector of the slot, though the copper traces for a 16-bit slot were still there on the motherboard; the computer could tell no difference between an 8-bit ISA adapter in such a slot and the same adapter in a 16-bit slot, and there were still enough 8-bit adapters in circulation that vendors figured they could save money on a few connectors this way. Also, leaving off the 16-bit extension to the ISA connector allowed use of some early 8-bit ISA cards that otherwise could not be used due to the PCB "skirt" hanging down into that 16-bit extension space. IBM was the first to do this in the IBM AT.

[9] reghardware.co.uk (http:/ / www. reghardware. co. uk/ 2006/ 05/ 18/ intel_cans_386_486_960_cpus/ ) This article was originally based on material from the Free On-line Dictionary of Computing, which is licensed under the GFDL. Intel 80486 36

External links

• Intel486 datasheets (http:/ / datasheets. chipdb. org/ Intel/ x86/ 486/ datashts)

• Intel 80486 images and descriptions at cpu-collection.de (http:/ / www. cpu-collection. de/ ?l0=co& l1=Intel& l2=i486 DX) Pentium 37 Pentium

Pentium

Produced From 1993 to current

Common manufacturer(s) • Intel

Max. CPU clock rate 60 MHz to 3.8 GHz

FSB speeds 60 MHz to 1333 MT/s

Min. feature size 0.8 µm to 32 nm

Instruction set x86, x86-64

Microarchitecture P5 P6 NetBurst Core Nehalem

Cores 1-2

Predecessor Intel 80486

Socket(s) • Various

Core name(s) • Various

Pentium is a brand used for a series of x86-compatible microprocessors produced by Intel. In its most current form, a Pentium processor is a consumer-level product with a two-star rating[1], above the low-end and products but below the faster Core i3, i5 and i7 lines as well as the high-end processors. The name Pentium is originally derived from the Greek word pente (πέντε), meaning 'five' (as the series was Intel's 5th generation microarchitecture, the P5), and the Latin ending -ium. The current Pentium processors only share the name but are in fact based on the same processor chips that are used in the but are typically used with a lower clock frequency, a partially disabled L3 cache and some of the advanced features such as Hyper-threading and Virtualization disabled.

Overview During development Intel generally identifies processors with codenames, such as Prescott, Willamette, Coppermine, Katmai, Klamath or Deschutes. These usually become widely known,[2] even after the processors are given official names on launch. Pentium 38

Brand Microarchitecture Desktop Laptop Server

Pentium P5 P5 (0.8 µm) Pentium OverDrive P54C (0.6 µm) P54CS (0.35 µm)

Pentium MMX P55C (0.35 µm) Pentium OverDrive MMX Tillamook (0.25 µm)

Pentium Pro P6 P6 (0.5 µm) P6 (0.35 µm)

Pentium II Klamath (0.35 µm) Tonga (0.25 µm) Drake (0.25 µm) Pentium II Xeon Deschutes (0.25 µm) Dixon (0.25 µm) Pentium II OverDrive Mobile Pentium II

Pentium III Katmai (0.25 µm) Coppermine Tanner (0.25 µm) Pentium III Xeon Coppermine (180 nm) (180 nm) Cascades (180 nm) Mobile Pentium III Tualatin (130 nm) Tualatin(130 nm) Pentium III M

Pentium 4 NetBurst Willamette (180 nm) Northwood (130 nm) Rebranded as Xeon Pentium 4 Extreme Edition Northwood (130 nm) Prescott (90 nm) Gallatin (130 nm) Prescott-2M (90 nm) Prescott (90 nm) Cedar Mill (65 nm)

Pentium D Smithfield (90 nm) Pentium Extreme Edition Presler (65 nm)

Pentium M P6 based Banias (90 nm) Dothan (65 nm)

Pentium Dual-Core (65 nm)

Core Allendale (65 nm) -2M (65 nm) Wolfdale-3M (45 nm)

Pentium Wolfdale-3M (45 nm) -3M (45 nm)

Nehalem Clarkdale (32 nm) " (32 nm)

Sandy Bridge Sandy Bridge (32 nm)

History The original Pentium branded CPUs were expected to be named 586 or i586, to follow the naming convention of previous generations (286, i386, i486). However, as the company wanted to prevent their competitors from branding their processors with similar names, as AMD had done with their , Intel attempted to file a trademark on the name in the United States, only to be denied because a series of numbers was not considered distinct. Following Intel's previous series of 8086, 80186, 80286, 80386, and 80486 microprocessors, the company's first P5-based processor was released as the original Intel Pentium on March 22, 1993. Due to its success, the Pentium brand would continue through several generations of high-end processors beyond the original. In 2006, the Pentium brand briefly disappeared from Intel's roadmaps,[3][4] only to re-emerge in 2007.[5] In 1998, Intel introduced the Celeron[6] brand for low-priced microprocessors. With the 2006 introduction of the Intel Core brand as the company's new flagship line of processors, the Pentium series was to be discontinued. However, due to a demand for mid-range dual-core processors, the Pentium brand was re-purposed to be Intel's mid-range processor series, in between the Celeron and Core series, continuing with the Pentium Dual-Core line.[7] Pentium 39

[8][9]

In 2009, the "Dual-Core" suffix was dropped, and new x86 microprocessors started carrying the plain Pentium name again.

Pentium-branded processors

P5 microarchitecture based The original Pentium and Pentium MMX processors were the superscalar follow-on to the 80486 processor and were marketed from 1993 to 1999. Some versions of these were available as Pentium OverDrive that would fit into older CPU sockets.

Pentium

Core Process Frequency L1 Cache FSB Socket Release date

P5 0.8 µm 60–66 MHz 16 KB 60–66 MHz March 1993

P54C 0.6 µm 75–120 MHz 16 KB 50–66 MHz October 1994

P54CS 0.35 µm 133–200 MHz 16 KB 60–66 MHz June 1995

P55C 0.35 µm 120–233 MHz 32 KB 60–66 MHz Socket 7 March 1995

Tillamook 0.25 µm 166–300 MHz 32 KB 66 MHz Socket 7 August 1997

P6 microarchitecture based In parallel with the P5 microarchitecture, Intel developed the P6 microarchitecture and started marketing it as the Pentium Pro for the high-end market in 1995. It introduced out-of-order execution and an integrated second level cache on dual-chip processor package. The second P6 generation replaced the original P5 with the Pentium II and rebranded the high-end version as Pentium II Xeon. It was followed by a third version called the Pentium III and Pentium III Xeon, respectively. The Pentium II line added the MMX instructions that were also present in the Pentium MMX. Versions of these processors for the Laptop market were initially called Mobile Pentium II and Mobile Pentium III, later versions were called Pentium III-M. Starting with the Pentium II, the Celeron brand was used for low-end versions of most Pentium processors with a reduced feature set such as a smaller cache or missing power management features.

Pentium Pro

Core Process Frequency L2 Cache FSB Socket Release date

P6 0.5 µm 150 MHz 256 KB 60–66 MHz Socket 8 November 1995

P6 0.35 µm 166–200 MHz 256–1024 KB 60–66 MHz Socket 8

Pentium II Pentium 40

Core Process Frequency L2 Cache FSB Socket Release date

Klamath 0.35 µm 233–300 MHz 512 KB 66 MHz May 1996

Deschutes 0.25 µm 266–450 MHz 512 KB 66–100 MHz Slot 1 January 1998

Tonga 0.25 µm 233–300 MHz 512 KB 66 MHz MMC-2 April 1998

Dixon 0.25 µm 266–366 MHz 256 KB 66 MHz MMC-2

Pentium III

Core Process Frequency L2 Cache FSB Socket Release date

Katmai 0.25 µm 450–600 MHz 512 KB 100–133 MHz Slot 1 February 1999

Coppermine 0.18 µm 400–1130 MHz 256 KB 100–133 MHz Slot 1, Socket 370, BGA2, µPGA2 October 1999

Tualatin 0.13 µm 700–1400 MHz 512 KB 100–133 MHz Socket 370, BGA2, µPGA2

Netburst microarchitecture based In 2000, Intel introduced a new microarchitecture called NetBurst, with a much longer pipeline enabling higher clock frequencies than the P6 based processors. Initially, these were called Pentium 4 and the high-end versions have since been called just Xeon. As with Pentium III, there are both Mobile Pentium 4 and Pentium 4 M processors for the laptop market, with Pentium 4 M denoting the more power-efficient versions. Enthusiasts version of the Pentium 4 with the highest clock frequency were called Pentium 4 Extreme Edition. The was the first multi-core Pentium, integrating two Pentium 4 chips in one package and was also available as the enthusiast Pentium Extreme Edition.

Pentium 4

Core Process Clock Speeds L2 Cache FSB Speeds Socket Release Date

Willamette 180 nm 1.3–2.0 GHz 256 KB 400 MT/s Socket 423, Socket 478 November 2000

Northwood 130 nm 1.6–3.4 GHz 512 KB 400–800 MT/s Socket 478 January 2002

Gallatin 130 nm 3.2–3.46 GHz 512 KB + 2 MB L3 800–1066 MT/s Socket 478, LGA 775 November 2003

Prescott 90 nm 2.4–3.8 GHz 1 MB 533–800 MT/s Socket 478, LGA 775 February 2004

Prescott-2M 90 nm 2.8–3.8 GHz 2 MB 800–1066 MT/s LGA 775 February 2005

Cedar Mill 65 nm 3.0–3.6 GHz 2 MB 800 MT/s LGA 775 January 2006

Pentium D Pentium 41

Core Process Clock Speeds L2 Cache FSB Speeds Socket Release Date

Smithfield 90 nm 2.66–3.2 GHz 2 MB 533–800 MT/s Socket T May, 2005

Smithfield XE 90 nm 3.2 GHz 2 MB 800 MT/s Socket T May, 2005

Presler 65 nm 2.8–3.6 GHz 4 MB 800 MT/s Socket T January, 2006

Presler XE 65 nm 3.46–3.73 GHz 4 MB 1066 MT/s Socket T January, 2006

Pentium M microarchitecture based In 2003, Intel introduced a new processor based on the P6 microarchitecture called Pentium M, which was much more power efficient than the Mobile Pentium 4, Pentium 4 M and Pentium III M. Dual-core version of the Pentium M was developed under the code name Yonah and sold under the marketing names Core Duo and Pentium Dual-Core. Unlike Pentium D, it integrated both cores on a single chip. From this point, the Intel Core brand name was used for the mainstream Intel processors and the Pentium brand became a low-end version between Celeron and Core. All Pentium M based designs including Yonah are for the mobile market.

Pentium M

Core Process Frequency L1 Cache L2 Cache FSB Socket Release date

Banias 130 nm 900–1700 MHz 64 KB 1 MB 400 MT/s Socket 479 March 2003

Dothan 90 nm 1.00–2.26 GHz 64 KB 2 MB 400–533 MT/s FC-uBGA June 2004

Pentium Dual-Core

Core Process Clock Speeds L1 Cache L2 Cache FSB Speeds Socket Release date

Yonah 65 nm 1.6–1.86 GHz 64 KB 1 MB 533 MT/s Socket M January 2007

Core microarchitecture based The Pentium Dual-Core name continued to be used when the Yonah design was extended with 64 bit support, now called the Core microarchitecture. This microarchitecture eventually replaced all NetBurst based processors across the four brands, Celeron, Pentium, Core and Xeon. Pentium Dual-Core processors based on the Core microarchitecture use the Allendale and Wolfdale-3M designs for desktop processors and Merom-2M for mobile processors.

Pentium Dual-Core Pentium 42

Core Process Clock Speeds L1 Cache L2 Cache FSB Speeds Socket Release date

Merom-2M 65 nm 1.46–2.16 GHz 64 KB 1 MB 533–667 MT/s Socket P Q4 2007

Allendale 65 nm 1.6–2.4 GHz 64 KB 1 MB 800 MT/s Socket 775 June 2007

Wolfdale-3M 45 nm 2.2–2.7 GHz 64 KB 2 MB 800 MT/s Socket 775 August 2008

Pentium (2009)

Core Process Clock Speeds L1 Cache L2 Cache FSB Speeds Socket Release date

Wolfdale-3M 45 nm 2.8–3.2 GHz 64 KB 2 MB 1066 MT/s Socket 775 May 2009

Penryn-3M 45 nm 2.0–2.3 GHz 64 KB 1 MB 800 MT/s Socket P January 2009

Penryn-3M ULV 45 nm 1.3–1.5 GHz 64 KB 2 MB 800 MT/s BGA 956 September 2009

Penryn-L ULV 1 45 nm 1.3–1.4 GHz 64 KB 2 MB 800 MT/s BGA 956 May 2009

Codename Brand Name Model (list) Cores L2 Cache Socket TDP

Allendale Pentium Dual-Core E2xxx 2 1 MB LGA 775 65 W

Merom-2M Mobile Pentium Dual-Core T2xxx 2 1 MB Socket P 35 W T3xxx

Wolfdale-3M Pentium Dual-Core E2xxx 2 1 MB LGA 775 65 W

E5xxx 2 MB

Pentium E6xxx

Penryn-3M Mobile Pentium T4xxx 2 1 MB Socket P 35 W

SU4xxx 2 MB µFC-BGA 956 10 W

Penryn-L SU2xxx 1 5.5 W

In 2009, Intel changed the naming system for Pentium processors, renaming the Wolfdale-3M based processors to Pentium, without the Dual-Core name and introduced new single- and dual-core processors based on Penryn under the Pentium name. The Penryn core is the successor to the Merom core and Intel's 45 nm version of their mobile series of Pentium microprocessors. The FSB is increased from 667 MHz to 800 MHz and the voltage is lowered. Intel released the first Penryn Core, the Pentium T4200, in December, 2008. In June 2009, Intel released the first single-core processor to use the Pentium name, a Consumer Ultra-Low Voltage (CULV) Penryn core called the Pentium SU2700. In September 2009, Intel introduced the Pentium SU4000 series together with the Celeron SU2000 and Core 2 Duo SU7000 series, which are dual-core CULV processors based on Penryn-3M and using 800 MHz FSB. The Pentium SU4000 series has 2 MB L2 cache but is otherwise basically identical to the other two lines. Pentium 43

Nehalem microarchitecture based The Nehalem microarchitecture was introduced in late 2008 as a successor to the Core microarchitecture, and in early 2010, a new Pentium G6950 processor based on the Clarkdale design was introduced based on the Westmere refresh of Nehalem, which were followed by the mobile P6xxx based on Arrandale a few months later.

Core Process Clock Speeds L2 Cache L3 Cache I/O Bus Socket Release date

Clarkdale 32 nm 2.8 GHz 512 KB 3 MB DMI Socket 1156 January 2010

Arrandale 32 nm 1.2-1.86 GHz 512 KB 3 MB DMI Socket 988 Q2 2010 BGA

Codename Brand name L3 Cache Socket TDP Features

Clarkdale Pentium G6xxx 3 MB LGA 1156 73 W Integrated GPU

Arrandale Pentium P6xxx 3 MB LGA 1156 35 W Integrated GPU

Pentium U5xxx BGA 18 W

On January 7, 2010, Intel launched a new Pentium model using the Clarkdale chip in parallel with other desktop and mobile CPUs based on their new Westmere microarchitecture. The first model in this series is the Pentium G6950. The Clarkdale chip is also used in the Core i3-5xx and Core i5-6xx series and features a 32 nm process (as it is based on the Westmere microarchitecture), integrated memory controller and 45 nm graphics controller and a third-level cache. In the Pentium series, some features of Clarkdale are disabled. Compared to Core i3, it lacks Hyper-Threading and the graphics controller in the Pentium runs at 533 MHz, while in the Core i3 i3-5xx series they run at 733 MHz. Dual Video Decode that enables Blu-ray picture-in picture hardware acceleration is disabled as well as Deep Color and xvYCC support. The memory controller in the Pentium supports DDR3-1066 max and the Core i3 i3-5xx series supports DDR3-1333 max. The L3 cache is also 1 MB less than in the Core i3-5xx series.

Sandy Bridge microarchitecture based The Sandy Bridge microarchitecture was released in the Pentium line on May 22, 2011. • aAll models share the following details: 2 cores, 2 logical processors (4 on Pentium 3xx with Hyper-threading), CPUID signature 206A7, family 6 (06h), model 42 (02Ah), stepping 7 (07h) • bTLB / cache 64-byte Prefetching; Data TLB0 2-MB or 4-MB pages, 4-way associative, 32 entries; Data TLB 4-KB Pages, 4-way set associative, 64 entries; Instruction TLB 4-KB Pages, 4-way set associative, 128 entries, L2 TLB 1-MB, 4-way set associative, 64-byte line size; Shared 2nd-level TLB 4 KB pages, 4-way set associative, 512 entries. • cAll models feature: On-chip Floating Point Unit, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Smart Cache. • dAll models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 • eHD Graphics (Sandy Bridge) contain 6 EUs as well as HD Graphics 2000, but does not support the following technologies: , InTru 3D, Clear Video HD, Wireless Display, and it doesn't support 3D Video or 3D graphics acceleration. Pentium 44

Codename Brand namea L3 Cacheb Socket TDP Featuresc,d

Sandy Bridge Pentium 3xx 3 MB LGA 1155 15 W Hyper-threading, ECC

Pentium B9xx 2 MB rPGA988B 35 W Integrated GPU

[10] Pentium G6xxT 3 MB 8-way set associative Line size 64 bytes LGA 1155 35 W Integrated GPUe

[11] Pentium G6xx 65 W

[12] [13] Pentium G8xx 3 MB 12-way set associative Line size 64 bytes

Pentium compatible Intel processors Due to its prominence, the term "Pentium compatible" is often used to describe any x86 processor that supports the IA-32 instruction set and architecture. Even though they do not use the Pentium name, Intel also manufacturers other processors based on the Pentium series for other markets. Most of these processors share the core design with one of the Pentium processor lines, usually differing in the amount of CPU cache, power efficiency or other features. The notable exception is the Atom line, which is an independent design. • Celeron, a low-end version • Core, the mainstream version including Core 2 and Core i7, now placed above Pentium • Xeon, a high-end version used in servers and workstations • A100 (discontinued), an ultra-mobile version of Pentium M • EP80579, A system-on-a-chip based on Pentium M • Atom, current ultra-mobile processors

References

[1] "Intel Processor Rating" (http:/ / www. intel. com/ en_uk/ consumer/ products/ processors/ ratings. htm). . Retrieved 2011-11-21.

[2] Names of processors (http:/ / www. ece. iastate. edu/ ~morris/ cs570/ name. html)

[3] "Intel "-L" Details Unveiled" (http:/ / www. dailytech. com/ article. aspx?newsid=4252). DailyTech. . Retrieved 2007-08-16.

[4] The multicore era is upon us - CNET Asia (http:/ / asia. cnet. com/ reviews/ pcperipherals/ 0,39051168,61998152-8,00. htm)

[5] "Intel to unify product naming scheme" (http:/ / www. tgdaily. com/ content/ view/ 33234/ 122/ ). TG Daily. . Retrieved 2007-08-12.

[6] "Microprocessor Hall of Fame" (http:/ / web. archive. org/ web/ 20070706032836/ http:/ / www. intel. com/ museum/ online/ hist_micro/ hof/

). Intel. Archived from the original (http:/ / www. intel. com/ museum/ online/ hist_micro/ hof/ ) on 2007-07-06. . Retrieved 2007-08-11.

[7] Brown, Rich; Michelle Thatcher (23 April 2008). "The multicore era is upon us: How we got here – Where we stand today" (http:/ / asia.

cnet. com/ reviews/ pcperipherals/ 0,39051168,61998152-5,00. htm). CNET Asia. . Retrieved 2009-04-18.

[8] Shilov, Anton. "Intel Readies Pentium E2000-Series Processors" (http:/ / www. xbitlabs. com/ news/ cpu/ display/ 20061115223825. html). X-bit labs. . Retrieved 2007-08-15.

[9] "Intel to unify product naming scheme" (http:/ / www. tgdaily. com/ content/ view/ 33234/ 122/ ). TG Daily. . Retrieved 2007-08-15.

[10] "CPU ID: SR05T Intel Pentium Dual-Core G620T" (http:/ / www. cpu-world. com/ sspec/ SR/ SR05T. html). cpu-world.com. . Retrieved 5 August 2011.

[11] "SR05R Intel Pentium Dual-Core G620" (http:/ / www. cpu-world. com/ sspec/ SR/ SR05R. html). cpu-world.com. . Retrieved 6 August 2011.

[12] "SR05P Intel Pentium Dual-Core G840" (http:/ / www. cpu-world. com/ sspec/ SR/ SR05P. html). cpu-world.com. . Retrieved 6 August 2011.

[13] "SR05Q (Intel Pentium Dual-Core G850)" (http:/ / www. cpu-world. com/ sspec/ SR/ SR05Q. html). cpu-world.com. . Retrieved 6 August 2011. P5 (microarchitecture) 45 P5 (microarchitecture)

The Intel P5 Pentium family Produced From 1993 to 1999

Common manufacturer(s) • Intel

Max. CPU clock rate 60 MHz to 300 MHz

FSB speeds 50 MHz to 66 MHz

Min. feature size 0.8µm to 0.25µm

Instruction set x86

Socket(s) • Socket 4, Socket 5, Socket 7

Core name(s) • P5. P54C, P54CS, P55C, Tillamook

The original Pentium microprocessor was introduced on March 22, 1993.[1][2] Its microarchitecture, deemed P5, was Intel's fifth-generation and first superscalar x86 microarchitecture. As a direct extension of the 80486 architecture, it included dual integer pipelines, a faster FPU, wider data bus, separate code and data caches and features for further reduced address calculation latency. In 1996, the Pentium with MMX Technology (often simply referred to as Pentium MMX) was introduced with the same basic microarchitecture complemented with an MMX instruction set, larger caches, and some other enhancements. The P5 Pentium competitors included the and the PowerPC 601 as well as the SPARC, MIPS, and Alpha microprocessor families, most of which also used a superscalar in-order dual instruction pipeline configuration at some time. Intel's Larrabee multicore architecture project uses a processor core derived from a P5 core (P54C), augmented by multithreading, 64-bit instructions, and a 16-wide vector processing unit.[3] Intel's low-powered Bonnell microarchitecture employed in Atom processor cores also uses an in-order dual pipeline similar to P5.[4]

Development The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486.[5] Design work started in 1989;[6] the team decided to use a superscalar architecture, with on-chip cache, floating-point, and branch prediction. The preliminary design was first successfully simulated in 1990, followed by the laying-out of the design. By this time the team had several dozen engineers. The design was taped out, or transferred to silicon, in April 1992, at which point beta-testing began.[7] By mid-1992, the P5 team had 200 engineers.[8] Intel at first planned to demonstrate the P5 in June 1992 at the trade show PC Expo, and to formally announce the processor in September 1992,[9] but design problems forced the demo to be cancelled, and the official introduction of the chip was delayed until the spring of 1993.[10][11] John H. Crawford, chief architect of the original 386, co-managed the design of the P5,[12] along with Donald Alpert, who managed the architectural team. Dror Avnon managed the design of the FPU.[13] Vinod K. Dham was general manager of the P5 group.[14] P5 (microarchitecture) 46

Major improvements over i486 microarchitecture • Performance: • Superscalar architecture — The Pentium has two datapaths (pipelines) that allow it to complete two instructions per clock cycle in many cases. The main pipe (U) can handle any instruction, while the other (V) can handle the most common simple instructions. Some RISC proponents had argued that the "complicated" x86 instruction set would probably never be implemented by a tightly pipelined microarchitecture, much less by a dual pipeline design. The 486 and the Pentium demonstrated that this was indeed possible and feasible. • 64-bit external databus doubles the amount of information possible to read or write on each memory access and therefore allows the Pentium to load its code cache faster than the 80486; it also allows faster access and storage of 64-bit and 80-bit x87 FPU data. • Separation of code and data caches lessens the fetch and operand read/write conflicts compared to the 486. To reduce access time and implementation cost, both of them are 2-way associative, instead of the single 4-way cache of the 486. A related enhancement in the Pentium is the ability to read a contiguous block from the code cache even when it is split between two cache lines (at least 17 bytes in worst case). • Much faster floating point unit. Some instructions showed an enormous improvement, most notably FMUL, with up to 15 times higher throughput than in the 80486 FPU. The Pentium is also able to execute a FXCH ST(x) instruction in parallel with an ordinary (arithmetical or load/store) FPU instruction. • Four-input address-adders enables the Pentium to further reduce the address calculation latency compared to the 80486. The Pentium can calculate full addressing modes with segment-base + base-register + scaled register + immediate offset in a single cycle; the 486 has a three-input address-adder only, and must therefore divide such calculations between two cycles. • The microcode can employ both pipelines to enable auto-repeating instructions such as rep movsw perform one iteration every clock cycle, while the 80486 needed three clocks per iteration (and the earliest x86-chips significantly more than the 486). Also, optimization of the access to the first microcode words during the decode stages helps in making several frequent instructions execute significantly more quickly, especially in their most common forms, and in typical cases. Some examples are (486→Pentium, in clock cycles): CALL (3→1), RET (5→2), shifts/rotates (2~3→1), etc. • A faster, fully hardware-based multiplier makes instructions such as MUL and IMUL several times as fast (and more predictable) than in the 80486; the execution time is reduced from 13~42 clock cycles down to 10~11 for 32-bit operands. • Virtualized interrupt to speed up virtual 8086 mode. • Other features: • Enhanced debug features with the introduction of the Processor-based debug port (See Pentium Processor Debugging in the Developers Manual, Vol 1). • Enhanced self test features like the L1 cache parity check (see Cache Structure in the Developers Manual, Vol 1). • The later Pentium MMX also added the MMX instruction set, a basic integer SIMD instruction set extension marketed for use in multimedia applications. MMX could not be used simultaneously with the x87 FPU instructions because the registers were reused (to allow for fast context switches). More important enhancements were the doubling of the instruction and data cache sizes and a few microarchitectural changes for better performance. The Pentium was designed to execute over 100 million instructions per second (MIPS),[15] and the 75 MHz model was able to reach 126.5 MIPS in certain benchmarks.[16] The Pentium architecture typically offered just under twice the performance of a 486 processor per clock cycle in common benchmarks. The fastest 80486 parts (with slightly improved microarchitecture and 100 MHz operation) were almost as powerful as the first-generation , and the AMD Am5x86 was roughly equal to the Pentium 75 regarding pure ALU performance. P5 (microarchitecture) 47

Bugs and problems The early versions of 60-100 MHz P5 Pentiums had a problem in the floating point unit that resulted in incorrect (but predictable) results from some operations. This bug, discovered in 1994 by professor Thomas Nicely at Lynchburg College, Virginia, became known as the Pentium FDIV bug and caused embarrassment for Intel, which created an exchange program to replace the faulty processors. Soon afterwards, a bug was discovered which could allow a malicious program to crash a system without any special privileges (the "f00f" bug); fortunately, operating systems were able to implement workarounds to prevent crashes. The 60 and 66 MHz 0.8 µm versions of the P5 Pentium processors also had (for the time) high heat production due to their 5V operation, and were often known colloquially as "coffee warmers" or some similar nickname. The P54C used 3.3V and had significantly lower power draw (a quadratic relationship). P5 Pentiums used Socket 4, while P54C started out on Socket 5 before moving to Socket 7 in later revisions. All desktop Pentiums from P54CS onwards used Socket 7.

Cores and steppings The Pentium was Intel's primary microprocessor for personal computers during the mid-1990s. The original design was reimplemented in newer processes and new features were added to maintain its competitiveness as well as to address specific markets such as portable computers. As a result, there were several variants of the P5 microarchitecture.

P5

The first Pentium microprocessor core was code-named "P5". Its product code was 80501 (80500 for the earliest steppings). There were two versions, specified to operate at 60 MHz and 66 MHz respectively. This first implementation of the Pentium used a traditional 5 Volt power supply (descended from the usual TTL logic compatibility requirements). It contained 3.1 million transistors and measured 16.7 mm by 17.6 mm for an area of 293.92 mm2.[17] It was fabricated in a 0.8 µm BiCMOS process. The 5 volt design resulted in relatively high energy consumption for its operating Intel Pentium microarchitecture. frequency compared to the later models.

P54C The P5 was followed by the P54C (80502); there were versions specified to operate at 75, 90, or 100 MHz using a 3.3 volt power supply. This was the first Pentium processor to operate at a 3.3 volts, reducing energy consumption. It employed an internal clock multiplier to let the internal circuitry work at a higher frequency than the external address and data buses, as it is more complicated and cumbersome to increase the external frequency, due to physical constraints. It also allowed two-way multiprocessing and had new power management features as well as an on chip 8259-compatible interrupt controller. It contained 3.3 million transistors and measured 163 mm2.[18] It was fabricated in a BiCMOS process which has been described as both 0.5 µm and 0.6 µm due to differing definitions.[18] P5 (microarchitecture) 48

P54CQS The P54C was followed by the P54CQS which operated at 120 MHz. It was fabricated in a 0.35 µm BiCMOS process and was the first commercial microprocessor to be fabricated in a 0.35 µm process.[18] Its transistor count is identical to the P54C and, despite the newer process, it had an identical die area as well. The chip was connected to the package using wire bonding, which only allows connections along the edges of the chip. A smaller chip would have required a redesign of the package, as there is a limit on the length of the wires and the edges of the chip would be further away from the pads on the package. The solution was to keep the chip the same size, retain the existing pad-ring, and only reduce the size of the Pentium's logic circuitry to enable it to achieve higher clock frequencies.[18]

P54CS The P54CQS was followed by the P54CS, which operated at 133, 150, 166 and 200 MHz. It contained 3.3 million transistors, measured 90 mm2 and was fabricated in a 0.35 µm BiCMOS process with four levels of interconnect.

P24T Further information: Pentium OverDrive The P24T Pentium OverDrive for 486-systems were released in 1995, which were based on 3.3V 0.6 µm versions using a 63 or 83 MHz clock. Since these used /3, some modifications had to be made to compensate for the 32-bit data bus and slower on-board L2 cache of 486-motherboards. They were therefore equipped with a 32KB L1 cache (double that of pre-P55C Pentium CPUs).

P55C

The P55C (or 80503) was developed by Intel's Research & Development Center in Haifa, Israel. It was sold as Pentium with MMX Technology (usually just called Pentium MMX); although it was based on the P5 core, it featured a new set of 57 "MMX" instructions intended to improve performance on multimedia tasks, such as encoding and decoding digital media data. The Pentium MMX line was introduced on 22 October 1996.[19]

The new instructions work on new data types: 64-bit packed vectors of either Intel Pentium MMX microarchitecture. eight 8-bit integers, four 16-bit integers, two 32-bit integers, or one 64-bit integer. So, for example, the PADDUSB (Packed ADD Unsigned Saturated Byte) instruction adds two vectors, each containing eight 8-bit unsigned integers together, pairwise; each addition that would overflow saturates, yielding 255, the maximum unsigned value that can be represented in a byte. These rather specialized instructions generally require special coding by the programmer for them to be used. The performance of the P55C was improved over previous versions by a doubling of the Level 1 CPU cache from 16 KB to 32 KB.

It contained 4.5 million transistors and had an area of 140 mm2. It was fabricated in a 0.28 µm CMOS process with the same metal pitches as the Pentium MMX 166 MHz without cover previous 0.35 µm BiCMOS process, so Intel described it as "0.35 µm" because of its similar transistor density.[20] The process has four levels of interconnect.[20] While the P55C is compatible with the common Socket 7 motherboard configuration, the voltage requirements for powering the chip differ from the standard Socket 7 specifications. Most motherboards manufactured for Socket 7 prior to the establishment of the P55C standard are not compliant with the dual intensity required for proper P5 (microarchitecture) 49

operation of this chip. Intel temporarily manufactured an upgrade kit called the OverDrive that was designed to correct this lack of planning on the motherboard makers part.

Tillamook Pentium MMX notebook CPUs used a "mobile module" that held the CPU. This module was a PCB with the CPU directly attached to it in a smaller form factor. The module snapped to the notebook motherboard and typically a heat spreader was installed and made contact with the module. However, with the 0.25 µm Tillamook Mobile Pentium MMX (named after a city in Oregon), the module also held the 430TX along with the system's 512 KB SRAM cache memory.

Models and variants

Pentium and Pentium with MMX Technology

Code P5 P54C P54CS P55C Tillamook name

Product 80500/ 80502 80503 code 80501

Process 0.80 0.60 or 0.35* 0.35 0.35 (later 0.28) 0.25 size (µm)

Socket Socket 4 Socket 5/7 Socket 7

Package CPGA CPGA/TCP* CPGA/PPGA/TCP* CPGA/PPGA/TCP* TCP/TCP on MMC-1

Clock 60 66 75 90 100 120 133 150 166 200 120* 133* 150* 166 200 233 200 233 266 300 speed (MHz)

Bus speed 60 66 50 60 66 60 66 60 66 60 66 60 66 (MHz)

Voltage 5.0 5.0 3.3 2,9* 3.3 3.3 3.3 3.1* 3.3 3.1* 3.3 3.3 3.3 2.8 2.45 2.45 2.8 2.8 2.8 1.8 1.8 2.0 2.0 2.9* 3.1* 2.9* 2.9* 3.1* 2.9* 2.9*

Introduced 1993-03-22 1994-10-10 1994-03-07 1995-03-27 1995-06-12 1996-01-04 1996-06-10 1997-10-20 1997-05-19 1997-01-08 1997-06-02 1997-08 1998-01 1999-01

An asterisk indicates that these were only available as Mobile Pentium or Mobile Pentium MMX chips for laptops. P5 (microarchitecture) 50

Pentium OverDrive with MMX Technology

Code name P54CTB

Product code PODPMT60X150 PODPMT66X166 PODPMT60X180 PODPMT66X200

Process size (µm) 0.35

Socket Socket 5/7

Package CPGA with heatsink, fan and voltage regulator

Clock speed (MHz) 125 150 166 150 180 200

Bus speed (MHz) 50 60 66 50 60 66

Upgrade for Pentium 75 Pentium 90 Pentium 100 and 133 Pentium 75 Pentium 90, 120 and 150 Pentium 100, 133 and 166

TDP (max. W) 15.6 15.6 15.6 18

Voltage 3.3 3.3 3.3 3.3

Embedded versions of Pentium with MMX Technology

Code P55C Tillamook name

Product FV8050366200 FV8050366233 FV80503CSM66166 GC80503CSM66166 GC80503CS166EXT FV80503CSM66266 GC80503CSM66266 code

Process 0.35 0.25 size (µm)

Clock 200 233 166 166 166 266 266 speed (MHz)

Bus 66 66 66 66 66 66 66 speed (MHz)

Package PPGA PPGA PPGA BGA BGA PPGA BGA

TDP 15.7 17 4.5 4.1 4.1 7.6 7.6 (max. W)

Voltage 2.8 2.8 1.9 1.8 1.8 1.9 2.0 P5 (microarchitecture) 51

References

[1] View Processors Chronologically by Date of Introduction: (http:/ / www. intel. com/ pressroom/ kits/ quickrefyr. htm#1993), Intel, , retrieved 2007-08-14

[2] Intel Pentium Processor Family (http:/ / www. intel. com/ pressroom/ kits/ quickreffam. htm#pentium), Intel, , retrieved 2007-08-14 [3] §3 of Seiler, L.; Carmean, D.; Sprangle, E.; Forsyth, T.; Abrash, M.; Dubey, P.; Junkins, S.; Lake, A. et al (August 2008). "Larrabee: A

Many-Core x86 Architecture for Visual Computing" (http:/ / softwarecommunity. intel. com/ UserFiles/ en-us/ File/ larrabee_manycore. pdf) (PDF). ACM Transactions on Graphics. Proceedings of ACM SIGGRAPH 2008 27 (3): 18:11–18:11. doi:10.1145/1360612.1360617. ISSN 0730-0301. . Retrieved 2008-08-06.

[4] Anand Lal Shimpi (January 27, 2010), Why Pine Trail Isn't Much Faster Than the First Atom (http:/ / www. anandtech. com/ show/ 2925), , retrieved 2010-08-04 [5] p. 1, The Pentium Chronicles: The People, Passion, and Politics Behind Intel's Landmark Chips, Robert P. Colwell, Wiley, 2006, ISBN 978-0-471-73617-2. [6] p. 88, "Inside Intel", Business Week, #3268, June 1, 1992.

[7] "The hot new star of microchips" (http:/ / www. iptegrity. com/ index. php?option=com_content& task=view& id=34& Itemid=42), Monica Horten, New Scientist, #1871, pp. 31 ff., May 1, 1993. Accessed on line June 9, 2009. [8] p. 89, "Inside Intel", Business Week, #3268, June 1, 1992. [9] p. 8, "Intel to offer a peek at its `586' chip", Tom Quinlan, InfoWorld, March 16, 1992. [10] p. 1, "Design woes force Intel to cancel 586 chip demo", Tom Quinlan and Cate Corcoran, InfoWorld 14, #24, June 15, 1992. [11] pp. 1, 103, "P5 chip delay won't alter rivals' plans", Tom Quinlan, InfoWorld 14, #30, July 27, 1992. [12] p. 54, "Intel Turns 35: Now What?", David L. Margulius, InfoWorld, July 21, 2003, ISSN 0199-6649.

[13] p. 21, " Architecture of the Pentium microprocessor (http:/ / ieeexplore. ieee. org/ xpls/ abs_all. jsp?arnumber=216745)", D. Alpert and D. Avnon, IEEE Micro, 13, #3 (June 1993), pp. 11–21, doi:10.1109/40.216745. [14] p. 90, "Inside Intel", Business Week, #3268, June 1, 1992.

[15] http:/ / dede. essortment. com/ pcusersguides_rjje. htm

[16] http:/ / www. islandnet. com/ ~kpolsson/ micropro/ proc1994. htm [17] Case, Brian (29 March 1993). "Intel Reveals Pentium Implementation Details". Microprocessor Report. [18] Gwennap, Linley (27 March 1995). "Pentium is First CPU to Reach 0.35 Micron". Microprocessor Report.

[19] New Chip Begs New Questions (http:/ / news. cnet. com/ New-chip-begs-new-questions/ 2100-1001_3-240247. html?tag=mncol), CNet, , retrieved 2009-02-06 [20] Slater, Michael (5 March 1996). "Intel's Long-Awaited P55C Disclosed". Microprocessor Report.

External links

• CPU-Collection.de (http:/ / www. cpu-collection. de/ ?tn=0& l0=co& l1=Intel& l2=Pentium P54) - Intel Pentium images and descriptions

• Plasma Online Intel CPU Identification (http:/ / www. plasma-online. de/ english/ identify/ picture/ intel_cpu. html)

• Pictures of all known Pentium chips at chipdb.org (http:/ / www. chipdb. org/ cat-pentium-417. htm)

• The Pentium Timeline Project (http:/ / www. chipdb. org/ index. php?template=timeline) The Pentium Timeline Project maps oldest and youngest chip known of every s-spec made. Data are shown in a interactive timeline.

Intel Datasheets

• Pentium (P5) (http:/ / datasheets. chipdb. org/ Intel/ x86/ Pentium/ 24159502. pdf)

• Pentium (P54) (http:/ / datasheets. chipdb. org/ Intel/ x86/ Pentium/ 24199710. PDF)

• Pentium MMX (P55C) (http:/ / datasheets. chipdb. org/ Intel/ x86/ Pentium MMX/ 24318504. PDF)

• Mobile Pentium MMX (P55C) (http:/ / datasheets. chipdb. org/ Intel/ x86/ Pentium MMX/ 24329204. PDF)

• Mobile Pentium MMX (Tillamook) (http:/ / datasheets. chipdb. org/ Intel/ x86/ Pentium MMX/ 24346802. PDF) P5 (microarchitecture) 52

Intel Manuals These Manuals do provide a overview of the Pentium Processor and its features:

• Pentium Processor Family Developer’s Manual Pentium Processor (Volume 1) (http:/ / download. intel. com/

design/ intarch/ manuals/ 24142805. pdf) (Intel Order Number 241428)

• Pentium Processor Family Developer’s Manual Volume 2: Instruction Set Reference (ftp:/ / download. intel. com/

design/ pentium/ manuals/ 24319101. PDF) (Intel Order Number 243191)

• Pentium Processor Family Developer’s Manual Volume 3: Architecture and Programming Manual (ftp:/ /

download. intel. com/ design/ pentium/ manuals/ 24143004. pdf) (Intel Order Number 241430)

P6 (microarchitecture)

The P6 microarchitecture is the sixth generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is sometimes referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture.

From Pentium Pro to Pentium III The P6 core was the sixth generation Intel microprocessor in the x86 space. The first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design (P5). Some techniques first used in the x86 space in the P6 core include: • Speculative execution and out-of-order completion (called "dynamic execution" by Intel), which required new retire units in the execution core. This lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs. • Superpipelining, which increased from Pentium's 5-stage pipeline to 14 of the Pentium Pro, and eventually morphed into the 10-stage pipeline of the Pentium III, and the 12- to 14-stage pipeline of the Pentium M. • PAE and wider 36-bit address bus to support 64 GB of physical memory (the linear address space of a process was still limited to 4 GB). • Register renaming, which enabled more efficient execution of multiple instructions in the pipeline. • CMOV instructions heavily used in compiler optimization. The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high (IPC). When the new NetBurst (P68) architecture was conceived, initially in the Willamette core, which had relatively low IPC and less efficient overall design both in terms of power consumption and throughput efficiency, the P6 line of processing cores were largely thought to be abandoned.

Revived microarchitecture in Pentium M (Banias and Dothan) Upon release of the Pentium 4-M and Mobile Pentium 4, it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing. The Netburst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran much hotter than Pentium III-M processors and didn't offer significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life. Realizing their new microarchitecture wasn't the best choice for the mobile space, Intel went back to the drawing board for a design that would be optimally suited for this market segment. The result was a hybrid, and at the time, modernized P6 design called the Pentium M: P6 (microarchitecture) 53

Design Overview[1] • Quad-pumped Front Side Bus. With the initial Banias core, Intel adopted the 400 MHz FSB first used in the Pentium 4. The Dothan core moved to the 533 MHz FSB, following the Pentium 4's evolution. • Larger L2 cache. Initially 1 MB in the Banias core, then 2 MB in the Dothan core. Dynamic cache activation by quadrant selector from sleep states. • SSE2 Streaming SIMD (Single Instruction, Multiple Data) Extensions 2 support. • A 12-14-stage instruction pipeline to achieve higher clock speeds than the Pentium III-M. • Dedicated register stack management. • Addition of global history to branch prediction table. • Micro-ops Fusion of certain sub-instructions mediated by decoding units. x86 commands can be combined into fewer RISC micro operations. The Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth.[1] A 1.7GHz Dothan could easily outperform a 2.4GHz Pentium 4, visibly doubling performance in real world applications and games over its faster clocked alternative. For the first time in PC history, desktop motherboards were built for a mobile processor, as the fastest clocked Dothan processors outperformed the fastest clocked Pentium 4 processors of the time.

Intel Core (Yonah) The Yonah CPU was launched in January 2006 under the Core brand. Single and dual-core mobile version were sold under the Core Solo, Core Duo, and Pentium Dual-Core brands, and a server version was released as Xeon LV. These processors provided partial solutions to some of the foregoing Pentium M's shortcomings, by adding to its P6 microarchitecture: • SSE3 Support • Single- and dual-core technology with 2 MB of shared L2 cache (restructuring processor organization) • Increased FSB speed, with the FSB running at 533 MHz or 667 MHz. • A 12-stage instruction pipeline. This resulted in the interim microarchitecture for low-voltage only CPUs, part way between P6 and the following Core microarchitecture.

Successor

Intel CPU core roadmaps from NetBurst and P6 to Skylake

On July 27, 2006, the Core microarchitecture, a distant relative of P6, was launched in form of the Core 2 processor. Subsequently, more processors were released with the Core microarchitecture under Core 2, Xeon, Pentium and Celeron brand names. The Core microarchitecture is Intel's final mainstream processor line to use FSB, with all later Intel processors based on Nehalem and following Intel microarchitectures exclusively using the QPI or DMI bus. P6 (microarchitecture) 54

Improvements from the Intel Core processors were: • A 14-stage instruction pipeline to achieve significantly higher clock speeds than the Core processsors. • SSSE3 support for all models and SSE4.1 support for all Core 2 models manufactured at a 45 nm lithography. • An x86-64 (64-bit) instruction set is added, allowing all Core 2 processors to run 64-bit applications. • Increased FSB speed, with the FSB running from 533 MHz to 1600 MHz. • Increased L2 cache size, with the L2 cache size ranging from 1 MB to 12 MB (Core 2 Duo processors use a shared L2 cache with Core 2 Quad processors having half of the total cache allocated to each die). • Some mobile Core 2 Duo processors support Dynamic Front Side Bus Throttling, with the FSB running at half of its full speed in Super Low Frequency Mode, therefore reducing the core speed to half of its full speed as well. This technique allows the processors to consume less power, increasing battery life. • Some mobile Core 2 Duo processors have Dynamic Acceleration Technology, while mobile Core 2 Quad processors support Dual Dynamic Acceleration Technology. For a mobile Core 2 Duo, this feature allows the CPU to overclock one processor core while turning off the other one. As for a mobile Core 2 Quad, two cores can be overclocked. The processor does this if an application only uses a single core or two as a minimum requirement to function effectively and the clock multiplier is only increased by 1.

P6 based chips • Celeron (Covington/Mendocino/Coppermine/Tualatin variants) • Pentium Pro • Pentium II Overdrive (a Pentium II chip in the 387 pin Socket 8) • Pentium II • Pentium II Xeon • Pentium III • Pentium III Xeon

Banias/Dothan variant • Celeron M (Banias/Shelton/Dothan variants) • Pentium M • A100/A110 • EP80579

Yonah variant • Celeron M 400 series • Core Solo/Duo • Pentium Dual-Core T2060/T2080/T2130 • Xeon LV/ULV (Sossaman) While all these chips are technically derivatives of the Pentium Pro the architecture has gone through several radical changes since its inception.[2] Page 1 of 9

Nehalem (microarchitecture) From Wikipedia, the free encyclopedia

Nehalem (pronounced /nəˈheɪləm/ [1]) is the codename for an Intel processor microarchitecture, successor to the Core microarchitecture.[2] Nehalem processors use the 45 nm process. A preview system with two Nehalem processors was shown at in 2007. The first processor released with the Nehalem architecture was the desktop Core i7,[3] which was released in November 2008.

Nehalem, a recycled codename, refers to a completely different architecture from Netburst, although Nehalem still has some things in common with NetBurst. Nehalem-based microprocessors utilize higher clock speeds and are more energy-efficient than Penryn microprocessors. Hyper- threading is reintroduced along with an L3 Cache missing from most Core-based microprocessors. Nehalem was replaced with the Sandy Bridge microarchitecture, released in January 2011.

Contents

■ 1 Technology ■ 2 Performance and power improvements ■ 3 Westmere ■ 4 Variants Overview ■ 4.1 Nehalem ■ 4.1.1 Server / Desktop Processors ■ 4.1.2 Mobile Processors ■ 4.2 Westmere ■ 4.2.1 Server / Desktop Processors ■ 4.2.2 Mobile Processors ■ 5 Successor ■ 6 References ■ 7 Further reading ■ 8 External links

Technology

■ Hyper-threading reintroduced. ■ 4–12 MB L3 cache ■ Second-level and translation lookaside buffer ■ Native (all processor cores on a single die) quad- and octo-core processors ■ Intel QuickPath Interconnect in high-end models replacing the legacy front side bus ■ 64 KB L1 cache/core (32 KB L1 Data + 32 KB L1 Instruction) and 256 KB L2 cache/core.

■ Integration of PCI Express and DMI into the processor in mid-range models, replacing the northbridge ■ Integrated memory controller supporting two or three memory channels of DDR3 SDRAM or four FB- DIMM2 channels ■ 2nd generation Intel Virtualization Technology which introduced Extended Page Table support, virtual processor identifiers (VPIDs), and non-maskable interrupt-window exiting [4]

Microarchitecture of the Performance and power improvements quad-core implementation

It has been reported that Nehalem has a focus on performance, thus the increased core size. [5] Compared to Penryn, Nehalem has:

■ 10-25% more single-threaded performance / 20-100% more multithreaded performance at the same power level ■ 30% lower power usage for the same performance ■ Nehalem provides a 15–20% clock-for-clock increase in performance per core(average)

Overclocking is possible with Bloomfield processors and the X58 chipset. Lynnfield processors use a PCH removing the need for a northbridge chipset. [6]

Nehalem processors incorporate SSE 4.2 SIMD instructions, adding 7 new instructions to the SSE 4.1 set in the Core 2 series. The Nehalem architecture reduces atomic operation latency by 50% in an attempt to eliminate atomic overhead . [7] Westmere

Westmere (formerly Nehalem -C) is the name given to the 32 nm die shrink of Nehalem . The first Westmere -based processors were launched on January 7, 2010.

Westmere's feature improvements from Nehalem as reported:

■ Native six -core ( ) and ten -core ( Westmere -EX ) processors. [8] ■ A new set of instructions that gives over 3x the encryption and decryption rate of Advanced Encryption Standard (AES) processes compared to before. [9] ■ Delivers seven new instructions (AES instruction set or AES-NI) that will be used by the AES algorithm. Also an instruction called PCLMULQDQ (see CLMUL instruction set ) that will perform carry -less for use in cryptography. [10] Page 2 of 9

These instructions will allow the processor to perform hardware-accelerated encryption, not only resulting in faster execution but also protecting against software targeted attacks. ■ Integrated graphics, added into the processor package (dual core Arrandale and Clarkdale only). ■ Improved virtualization latency. [11] ■ New virtualization capability: "VMX Unrestricted mode support," which allows 16-bit guests to run (real mode and big real mode). ■ Support for "Huge Pages" of 1 GB in size. Variants Overview

Processing Cores Desktop, UP Process Die Size CPUID Model Stepping Mobile DP Server MP Server (interface) Server Eight-Core (Quad- Beckton 45 nm 684 mm² 206E6 46 D0 Channel) (80604) Quad-Core (Triple- 106A4 C0 Bloomfield Gainestown 45 nm 263 mm² 26 Channel) 106A5 D0 (80601) (80602) Quad-Core (Dual- 106E4 B0 Clarksfield Lynnfield Jasper Forest 45 nm 296 mm² 30 Channel, PCIe) 106E5 B1 (80607) (80605) (80612) Dual-Core (Dual- Auburndale Havendale Channel, PCIe, 45 nm (canceled) (canceled) Graphics Core)

Ten-Core (Quad- Westmere-EX 32 nm 513 mm² 206F2 47 A2 channel) [12] (80615) Six-Core (Triple- Gulftown Westmere-EP 32 nm 248 mm² 206C2 44 B1 Channel) (80613) (80614) Dual-Core (Dual- 32 nm 20652 C2 Arrandale Clarkdale Channel, PCIe, 81+114 mm² 37 45 nm 20655 K0 (80617) (80616) Graphics Core)

Nehalem

■ Lynnfield processors feature integrated PCIe 1 x16 or 2 x8. ■ 1 6500 series scalable up to 2 sockets, 7500 series scalable up to 4/8 sockets. [13] Page 3 of 9

Server / Desktop Processors Page 4 of 9

Processor CPU Price Cores / Interfaces L3 Release Codename Market Socket Branding & Clock Turbo TDP for Threads cache Date Model rate Chipset Memory 1k Unit 24 X7560 2.26 GHz $3692 130 4× QPI 6.4 MB X7550 W GT /s 18 $2837 8 (16) 2.0 GHz X6550 MB $2461 4× QPI 5.86 24 L7555 1.86 GHz 95 W $3157 GT/s MB Yes DDR3-800 / 18 E7540 4× QPI 6.4 $1980 2.0 GHz 1066 MB 1 MP Server / LGA [14] GT/s 2010-03-30 Beckton Xeon 105 (Up to 4x with [15] DP Server 6 (12) 1567 E6540 12 $1712 W SMB-Ready E7530 Motherboard) MB $1391 1.86 GHz L7545 4× QPI 5.86 $2087 130 GT/s 18 6 (6) X7542 2.66 GHz $1980 W MB E7520 1.86 GHz $856 105 4× QPI 4.8 4 (8) No 12 E6510 1.73 GHz W GT/s $744 MB W5590 3.33 GHz 130 2009 -08 -09 $1600 W5580 3.2 GHz W $1500 2× QPI 6.4 3× DDR3- X5570 2.93 GHz $1286 GT/s 1333 1 X5560 2.8 GHz 95 W $1072 2009-03-29 X5550 2.66 GHz [18] $858 4 (8) E5540 2.53 GHz Yes 8 MB $744 E5530 2.4 GHz 80 W $530 E5520 2.26 GHz 3× DDR3- $373 2× 5.86 GT/s 1 DP Server L5530 2.4 GHz 1066 2009 -08 -09 $744 Gainestown Xeon [17] [16] L5520 2.26 GHz 60 W $530 2009 -03 -30 L5518 2.13 GHz $ E5507 2.26 GHz 2010 -03 -16 80 W $266 E5506 2.13 GHz 4 (4) No 2× 4.8 GT/s 3× DDR3 -800 1 4 MB L5506 2.13 GHz 60 W $423 LGA 2009 -03 -29 1366 E5504 2.0 GHz 80 W $224 2 (4) L5508 2.0 GHz Yes 38 W 2× 5.86 GT/s 3× DDR3 -1066 8 MB $ E5503 2.0 GHz 2010 -03 -16 $224 2 (2) No 80 W 2× 4.8 GT/s 3× DDR3 -800 4 MB E5502 1.86 GHz 2009 -03 -29 $188 W3580 3.33 GHz 2009 -08 -09 1× QPI 6.4 3× DDR3 -1333 $999 GT/s 2009-03-29 W3570 3.2 GHz [20] W3565 3.2 GHz 2009 -11 -01 4 (8) W3550 3.06 GHz Yes 8 MB 2009 -08 -09 130 $562 Bloomfield 2009-03-29 W3540 2.93 GHz W [20] 1× QPI 4.8 3× DDR3 -1066 W3530 2.8 GHz GT/s 2010 -03 -16 $294 W3520 2.66 GHz $284 UP Server [20 ] 2009-03-29 [19] Xeon W3505 2.53 GHz $ 2(2) No 4 MB [20] W3503 2.4 GHz $ X3480 3.06 GHz 2010 -05 -30 $612 X3470 2.93 GHz $589 X3460 2.8 GHz 95 W $316 4 (8) LGA Lynnfield X3450 2.66 GHz Yes DMI 2× DDR3 -1333 $241 1156 2009 -09 -08 X3440 2.53 GHz $215 L3426 1.86 GHz 45 W $284 4 (4) X3430 2.4 GHz 95 W $189 Core i7 975 [22 ] 3.33 GHz 1× QPI 6.4 2009 -05 -31 8 MB $999 Extreme 965 3.2 GHz GT/s 2008 -11 -17 960 [23 ] 3.2 GHz 2009 -10 -20 Enthusiast LGA 130 Bloomfield [22] Yes 3× DDR3 -1066 $562 Desktop [21] 1366 950 3.06 GHz W 2009 -05 -31 4 (8) 1× QPI 4.8 940 2.93 GHz GT/s 2008 -11 -17 Core i7 930 2.8 GHz 2010 -02 -28 $294 920 2.66 GHz 2008 -11 -17 $284 Performance LGA 880 3.06 GHz $583 Lynnfield Yes 95 W DMI 2× DDR3 -1333 2010 -05 -30 Desktop 1156 875K 2.93 GHz $342 Page 5 of 9

870 [24] 2009-09-08 $562 870S 2.66 GHz 82 W 2010-07-19 $351 860 2.8 GHz 95 W 2009-09-08 $284 860S 2.53 GHz 82 W 2010-01-07 $337 760 2.8 GHz 95 W 2010-07-17 $209 4 (4) Core i5 750 [25] 2.66 GHz 95 W 2009-09-08 $196 750S 2.4 GHz 82 W 2010-01-07 $259

■ Intel states the Gainestown processors have six memory channels. Gainestown processors have dual QPI links and have a separate set of memory registers for each link in effect, a multiplexed six -channel system. [26][27]

Mobile Processors

Cores / Processor Core L3 Price for Codename Market Socket Turbo TDP Interface Release Date Threads Branding & Model Clock rate cache 1k Unit Core i7 940XM 2.13 GHz 2010-06-21 $1096 55 W Extreme 920XM 2.0 GHz 2009-09-23 $1054 Extreme / 8 MB * DMI µPGA 840QM 1.86 GHz 2010-06-21 $568 Clarksfield Performance 4 (8) Yes * 2x DDR3-1333 988 820QM 2009-09-23 $546 Mobile Core i7 1.73 GHz 45 W * PCIe 1 x16 / 2 x8 740QM 2010-06-21 $378 6 MB 720QM 1.6 GHz 2009-09-23 $364

Westmere

■ TDP includes the integrated GPU, if present. ■ Clarkdale processors feature an integrated PCIe 1 x16. ■ Clarkdale and Arrandale contain the 32 nm dual core processor Hillel and the 45 nm integrated graphics device Ironlake , and support switchable graphics. [28][29] Page 6 of 9

Server / Desktop Processors

Processor Cores / Clock rate Interfaces L3 Release Codename Market Socket Branding & Turbo TDP Price Threads cache Date model Core GPU Chipset Memory E7- 30 2.4 GHz $4394 4870 MB 2011-04- Westmere- LGA E7- 130 2× QPI 6.4 MP Server 10 (20) Xeon 2.26 GHz N/A Yes 05 $3838 EX 1567 4860 W GT/s 24 [30] E7- MB 2 GHz $2837 4850 2011-02- X5690 3.46 GHz 130 13 $1663 W 2010-03- X5680 3.33 GHz 16 2× QPI 6.4 2011-02- X5675 3.06 GHz $1440 GT /s 05 6 (12) X5670 2.93 GHz 95 W $1440 X5660 2.8 GHz 3× DDR3- $1219 1333 X5650 2.66 GHz $996 E5645 2.4 GHz 80 W $958 2× QPI 5.86 L5640 2.26 GHz Yes $996 DP Server Xeon N/A 60 W GT/s L5638 2.0 GHz $958 130 X5677 3.46 GHz 2× QPI 6.4 $1663 W 2010-03- GT/s 16 Gulftown / X5667 3.06 GHz 95 W $1440 Westmere- LGA E5640 2.66 GHz 12 $774 EP 4 (8) 1366 MB [31] E5630 2.53 GHz 80 W $551 2× QPI 5.86 E5620 2.4 GHz $387 GT/s 3× DDR3- L5630 2.13 GHz 1066 $551 L5618 1.86 GHz $530 40 W 2× QPI 4.8 4 (4) L5609 1.86 GHz No $440 GT/s 1× QPI 6.4 3× DDR3- 2010-03- W3680 3.33 GHz $999 GT /s 1333 16 [32] UP Server Xeon 1× QPI 4.8 2010-08- W3670 3.20 GHz $885 GT/s 29 130 2011-02- 6 (12) 990X 3.46 GHz N/A Yes Core i7 W 1× QPI 6.4 3× DDR3- 13 Extreme / $999 Extreme GT/s 1066 2010-03- Performance 980X 3.33 GHz 16 Desktop 1× QPI 4.8 2010-07- Core i7 970 3.2 GHz $885 GT/s 17 2010-03- L3406 2.26 GHz 2× DDR3- $189 UP Server Xeon N/A 30 W 16 1066 L3403 2.0 GHz 2010 -10 $ 2010-04- 680 3.6 GHz $294 733 MHz Yes 73 W 18 670 3.46 GHz $284 Core i5 661 900 MHz 87 W 2010-01- 3.33 GHz $196 2 (4) 660 4 MB 07 Clarkdale LGA [33] 650 3.2 GHz DMI 2× DDR3- $176 Mainstream / 1156 1333 2010-08- Value 560 3.33 GHz 29 Desktop 733 MHz $138 2010-05- 550 3.20 GHz Core i3 73 W 30 540 3.06 GHz No $133 530 2.93 GHz 2010-01- $113 Pentium G6950 2.8 GHz 2× DDR3- 3 MB 07 $87 2 (2) 533 MHz Celeron G1101 2.26 GHz 1066 2 MB OEM Page 7 of 9

Mobile Processors

CPU Clock rate Processor GPU Cores / L3 Release Codename Market Branding & Turbo Clock Turbo TDP Memory Interface Price Threads cache Date Model Standard (1C/2C active rate cores ) 2010-09 640M 2.8 GHz 3.47/3.2 GHz $346 35 -26 766 MHz 620M 2.66 GHz 3.33/3.2 GHz W 2010-01 $332 610E 2.53 GHz 3.2/2.93 GHz -07 OEM 2× DDR3- 2010-09 660LM 2.26 GHz 3.06/2.8 GHz 1066 $346 -26 25 640LM 2.13 GHz 2.93/2.66 GHz 566 MHz $332 W 2010-01 620LM / Core i7 2.0 GHz 2.8/2.53 GHz 4 MB -07 $300 620LE 2010-09 680UM 1.46 GHz 2.53/2.16 GHz $317 -26 2010-05 660UM 1.33 GHz 2.4/2.0 GHz 18 2× DDR3- $289 500 MHz -25 W 800 640UM 1.2 GHz 2.26/1.87 GHz $305 2010-01 620UM / 1.06 GHz 2.13/1.76 GHz -07 $278 620UE 580M 2.66 GHz 3.33/2.93 GHz 2010-09 $266 560M 2.66 GHz 3.2/2.93 GHz -26 $260 35 2× DDR3- 540M 2.53 GHz 3.06/2.8 GHz 766 MHz $257 Yes W 1066 2010-01 520M / 2.4 GHz 2.93/2.66 GHz -07 $225 520E 2010-09 560UM 1.33 GHz 2.13/1.86 GHz $250 -26 18 2× DDR3- 2010-05 540UM 1.2 GHz 2.0/1.73 GHz 500 MHz $250 2 (4) W 800 -25 2010-01 520UM 1.06 GHz 1.86/1.6 GHz $241 -07 Core i5 2011-01 480M 2.67 GHz 2.93/2.93 GHz * DMI * PCIe 1 -09 Mainstream / x16 2010-09 460M 2.53 GHz 2.8/2.8 GHz * Socket: Arrandale Value 35 2× DDR3- -26 766 MHz µPGA- Mobile W 1066 2010-06 450M 2.4 GHz 2.66/2.66 GHz 988 / BGA- -26 1288 2010-01 430M 2.26 GHz 2.53/2.53 GHz -07 2010-10 470UM 1.33 GHz 1.86/1.6 GHz 3 MB 18 2× DDR3- -01 500 MHz W 800 2010-05 430UM 1.2 GHz 1.73/1.47 GHz -25 2010-09 380M 2.54 GHz -26 2010-06 OEM 370M 2.4 GHz 35 2× DDR3- 667 MHz -20 W 1066 350M 2.26 GHz 2010-01 Core i3 330M / 2.13 GHz -07 330E 2010-10 380UM 1.33 GHz 18 2× DDR3- -01 500 MHz W 800 2010-05 330UM 1.2 GHz -25 P6200 2.13 GHz n/a No 2010-09 P6100 2.00 GHz 35 2× DDR3- -26 667 MHz W 1066 2010-06 Pentium P6000 1.86 GHz -20 18 2× DDR3- 2010-05 U5400 1.20 GHz 500 MHz W 800 -25 2 (2) 2010-09 P4600 2.00 GHz $86 35 2× DDR3- -26 667 MHz P4500 / W 1066 2010-03 Celeron 1.86 GHz 2 MB P4505 -28 OEM U3400 / 18 2× DDR3- 2010-05 1.06 GHz 500 MHz U3405 W 800 / 1066 -25 Page 8 of 9

Successor

The successor to Nehalem and Westmere is Sandy Bridge .

Intel CPU core roadmaps from NetBurst and P6 to Skylake

References

1. ^ I Am Nehalem (http://www.metacafe.com/watch/830178/i_am_nehalem/) , http://www.metacafe.com/watch/830178/i_am_nehalem/ 2. ^ Intel Details Upcoming New Processor Generations (http://www.intel.com/pressroom/archive/releases/20070328fact.htm) , Intel Corporation, 2007-03- 28 , http://www.intel.com/pressroom/archive/releases/20070328fact.htm 3. ^ Gruener, Wolfgang (2008-08-10), Nehalem = i7: Intel unveils new Core processor brand (http://www.tgdaily.com/content/view/38818/135/) , TG Daily , http://www.tgdaily.com/content/view/38818/135/ 4. ^ QInside Nehalem: Intel's Future Processor and System (http://realworldtech.com/page.cfm?ArticleID=RWT040208182719&p=8) 5. ^ "Intel's dual teamed approached to micro-architecture development" (http://pc.watch.impress.co.jp/docs/2008/0129/kaigai412.htm) (in Japanese), PC Watch , 2008 -01 -29 , http://pc.watch.impress.co.jp/docs/2008/0129/kaigai412.htm 6. ^ Botezatu, Bogdan (2008-04-22), Intel: No Overclocking for Mainstream Nehalems (http://news.softpedia.com/news/Intel-No-Overclocking-for- Mainstream -Nehalems -84019.shtml) , Softpedia , http://news.softpedia.com/news/Intel -No -Overclocking -for -Mainstream -Nehalems -84019.shtml 7. ^ NO EXECUTE! (http://www.emulators.com/docs/nx24_hot_chips.htm) , http://www.emulators.com/docs/nx24_hot_chips.htm 8. ^ Intel says no to 28nm, focuses on 22nm: Ivy Bridge/Haswell & Larrabee (http://brightsideofnews.com/news/2009/4/16/intel-says-no-to-28nm2c-focuses -on-22nm-ivy-bridgehaswell--larrabee.aspx) , http://brightsideofnews.com/news/2009/4/16/intel-says-no-to-28nm2c-focuses-on-22nm-ivy-bridgehaswell- -larrabee.aspx 9. ^ Smalley, Tim (2007-09-19), Westmere is Nehalem's successor (http://www.bit-tech.net/news/2007/09/19/westmere_is_nehalem_successor/1) , bit- tech.net , http://www.bit -tech.net/news/2007/09/19/westmere_is_nehalem_successor/1 10 . ^ Carry-Less Multiplication and Its Usage for Computing The GCM Mode – Intel Software Network (http://software.intel.com/en-us/articles/carry-less- multiplication-and-its-usage-for-computing-the-gcm-mode) , 2008-04-11, http://software.intel.com/en-us/articles/carry-less-multiplication-and-its-usage- for -computing -the -gcm -mode , retrieved 2009 -03 -01 11 . ^ Fuad Abazovic (2008-09-16), Westmere 32nm to improve Nehalem features (http://www.fudzilla.com/processors/processors/processors/westmere-32nm -to-improve-nehalem-features) , Fudzilla.com, http://www.fudzilla.com/processors/processors/processors/westmere-32nm-to-improve-nehalem-features, retrieved 2009 -03 -01 12 . ^ Westmere-EX 10 core CPUs announced by Intel at IDF (http://www.tweaktown.com/news/16724/westmere_ex_10_core_cpus_announced_by_intel_at_idf/index.html) 13 . ^ High -End x86: The Nehalem EX Xeon 7500 and Dell R810 (http://www.anandtech.com/show/3648/xeon -7500 -dell -r810/4) 14 . ^ AMD launches 12-core server chips, Intel counters with the 8-core Xeon 7500 (http://www.engadget.com/2010/03/30/amd-launches-12-core- opteron-server-chips-intel-counters-with-t/) , engadedget.com, 2010-03-31, http://www.engadget.com/2010/03/30/amd-launches-12-core-opteron-server- chips -intel -counters -with -t/ , retrieved 2010 -03 -31 15 . ^ Nebojsa Novakovic (2009-02-12), Intel's next bunch of fun CPUs moves to 2010 (http://www.theinquirer.net/inquirer/opinion/976/1050976/intel-bunch- fun-cpus-moves-2010) , CNN International, http://www.theinquirer.net/inquirer/opinion/976/1050976/intel-bunch-fun-cpus-moves-2010, retrieved 2009- 03 -01 16 . ^ Intel Xeon Processor 5500 Series Product brief, (Document Number: 321579-001US) (http://www- 2000.ibm.com/partnerworld/ap/kr/intel_xeon_5500_prodbrief.pdf) , Intel, 2009-04-01, http://www- 2000.ibm.com/partnerworld/ap/kr/intel_xeon_5500_prodbrief.pdf , retrieved 2010 -08 -27 17 . ^ Core i7 to make leap to Xeon in early 2009 (http://legacy.macnn.com/articles/08/11/13/xeon.i7.in.early.2009/) , Legacy.macnn.com, http://legacy.macnn.com/articles/08/11/13/xeon.i7.in.early.2009/ , retrieved 2008 -11 -24 18 . ^ Fuad Abazovic (2009-01-28), Nehalem based Xeon comes Mar 29th (http://www.fudzilla.com/processors/processors/processors/nehalem-based-xeon- comes -mar -29th) , Fudzilla.com , http://www.fudzilla.com/processors/processors/processors/nehalem -based -xeon -comes -mar -29th , retrieved 2009 -01 -28 19 . ^ Intel Xeon Processor 3500 Series (http://www.intel.com/cd/channel/reseller/asmo-na/eng/products/server/processors/3500/feature/index.htm) , Intel, 2009 -04 -01 , http://www.intel.com/cd/channel/reseller/asmo -na/eng/products/server/processors/3500/feature/index.htm , retrieved 2009 -04 -10 20 . ^ a b c d Teglet, Traian (2008-11-13), Intel to Add New Nehalem Xeon Processor (http://news.softpedia.com/news/Intel-to-Add-New-Nehalem-Xeon- Processors -97856.shtml) , softpedia , http://news.softpedia.com/news/Intel -to -Add -New -Nehalem -Xeon -Processors -97856.shtml , retrieved 2008 -11 -13 21 . ^ "Intel Core i7 Processor Extreme Datasheet, Volume 2, (Document Number: 320835- 002)" (http://download.intel.com/design/processor/datashts/320835.pdf) . Intel. 2008-11-01. http://download.intel.com/design/processor/datashts/320835.pdf . Retrieved 2009 -03 -24 . 22 . ^ a b Worrel, Jon (2009-02-09), Core i7 950 and 975 to replace 940 and 965 (http://www.fudzilla.com/processors/processors/processors/core-i7-950-and- 975-to-replace-940-and-965) , Fudzilla, http://www.fudzilla.com/processors/processors/processors/core-i7-950-and-975-to-replace-940-and-965 , retrieved 2009 -02 -10 23 . ^ Intel to launch new Core i7 960 and (http://www.guru3d.com/news/intel-to-launch-new-core-i7-960-and-celerons/) , http://www.guru3d.com/news/intel -to -launch -new -core -i7 -960 -and -celerons/ 24 . ^ Intel Core i5-750 (http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3585) , AnandTech, 2009-06-17, http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3585 25 . ^ Intel Quietly Announces Core i5 (http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3585) , Xtreview, 2009-06-26, http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3585 26 . ^ Intel Xeon Processor 5000 SequenceTechnical Documents (http://www.intel.com/p/en_US/products/server/processor/xeon5000/technical-documents) , http://www.intel.com/p/en_US/products/server/processor/xeon5000/technical -documents 27 . ^ Intel Xeon Processor 5500 Series Datasheet Volume 2 (http://www.intel.com/Assets/PDF/datasheet/321322.pdf) , Intel, March 2009, http://www.intel.com/Assets/PDF/datasheet/321322.pdf , retrieved 2009 -05 -01 28 . ^ Bell, Brandon (2009-02-10), Intel CPU Roadmap 2009–2010 (http://www.firingsquad.com/hardware/intel_32nm_westmere_roadmap/page2.asp) , FS Media, Inc , http://www.firingsquad.com/hardware/intel_32nm_westmere_roadmap/page2.asp , retrieved 2009 -03 -01 29 . ^ CPU list (http://www.hwinfo.com/Lists/cpu.htm) , http://www.hwinfo.com/Lists/cpu.htm 30 . ^ Intel Launches New Xeon Chips with Up to Ten Cores (http://www.xbitlabs.com/news/cpu/display/20110405135321_Intel_Launches_New_Xeon_Chips_with_Up_to_Ten_Cores.html) , http://www.xbitlabs.com/news/cpu/display/20110405135321_Intel_Launches_New_Xeon_Chips_with_Up_to_Ten_Cores.html Page 9 of 9

31. ^ Intel pushes workhorse to six cores (http://www.theregister.co.uk/2010/03/16/intel_xeon_5600_launch/) , http://www.theregister.co.uk/2010/03/16/intel_xeon_5600_launch/ 32. ^ Intel Launches Its Most Secure Data Center Processor (http://sanfrancisco.dbusinessnews.com/viewnews.php?article=bwire/20100316005652r1.xml) , http://sanfrancisco.dbusinessnews.com/viewnews.php?article=bwire/20100316005652r1.xml 33. ^ Intel Clarkdale Processor (http://xtreview.com/addcomment-id-7818-view-Intel-clarkdale-processor.html) , XTREVIEW, 2009-02-09, http://xtreview.com/addcomment-id-7818-view-Intel-clarkdale-processor.html, retrieved 2009-03-01 Further reading

■ InfoWorld review: Intel's Westmere struts its stuff (http://www.infoworld.com/d/hardware/infoworld-review-intels-westmere-struts-its-stuff-588) , InfoWorld, 2010-03-16, http://www.infoworld.com/d/hardware/infoworld-review-intels-westmere-struts-its-stuff-588 ■ IDF: Intel Clarkdale Up Close and Personal (http://www.xbitlabs.com/articles/cpu/display/clarkdale-sneakpeek.html) , X-bit Labs, 2009-09-24, http://www.xbitlabs.com/articles/cpu/display/clarkdale-sneakpeek.html ■ Intel Core i7 Processors: Nehalem and X58 Have Arrived (http://hothardware.com/Articles/Intel-Core-i7-Processors-Nehalem-and-X58-Have- Arrived/) , Hot Hardware, 2008-11-03, http://hothardware.com/Articles/Intel-Core-i7-Processors-Nehalem-and-X58-Have-Arrived/ ■ Intel Core i7 CPU & Nehalem Architecture Review (http://www.hardcoreware.net/reviews/review-372-1.htm) , hardCOREware.net, 2008-11-03, http://www.hardcoreware.net/reviews/review-372-1.htm ■ Intel Nehalem Core i7 Series Complete Review (http://www.pcper.com/article.php?aid=634) , PC Perspective, 2008-11-03, http://www.pcper.com/article.php?aid=634 ■ Intel Nehalem Core i7 940 Review (http://xtreview.com/addcomment-id-6524-view-Intel-core-i-7-940-review.html) , Xtreview, 2008-10-01, http://xtreview.com/addcomment-id-6524-view-Intel-core-i-7-940-review.html ■ Altavilla, Dave (2008-03-17), Intel Showcases Dunnington, Nehalem and Larrabee Processors (http://www.hothardware.com/Articles/Intel_Showcases_Dunnington_Nehalem_and_Larrabee_Processors/) , HotHardware, http://www.hothardware.com/Articles/Intel_Showcases_Dunnington_Nehalem_and_Larrabee_Processors/ ■ Shrout, Ryan (2008-03-28), Intel Slides and Nehalem architecture information (http://www.pcper.com/article.php?aid=382&type=expert) , PC Perspective, http://www.pcper.com/article.php?aid=382&type=expert ■ Stokes, Jon (2007-03-28), Intel drops a Nehalem bomb on AMD's Fusion: integrated graphics, on-die memory controller, SMT (http://arstechnica.com/news.ars/post/20070328-intel-aims-nehalem-at-amds-fusion-integrated-graphics-on-die-memory-controller-smt.html) , Ars Technica, http://arstechnica.com/news.ars/post/20070328-intel-aims-nehalem-at-amds-fusion-integrated-graphics-on-die-memory-controller-smt.html ■ Lal Shimpi, Anand (2007-09-18), Nehalem: Single die, 8-cores, 731M transistors (http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx? i=3101&p=2) , AnandTech, http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3101&p=2 ■ Lal Shimpi, Anand (2008-11-03), Nehalem - Everything You Need to Know about Intel's New Architecture (http://www.anandtech.com/show/2594/1) , AnandTech, http://www.anandtech.com/show/2594/1 ■ David Kanter (2010-04-04). "Inside Nehalem: Intel's Future Processor and System" (http://www.realworldtech.com/page.cfm? ArticleID=RWT040208182719) . realworldtech.com. http://www.realworldtech.com/page.cfm?ArticleID=RWT040208182719. Retrieved 2010-12- 16. ■ Holland, Maggie (2007-09-19), IDF 2007: Intel debuts Nehalem (http://www.itpro.co.uk/news/125370/idf-2007-intel-debuts-nehalem.html) , IT Pro, http://www.itpro.co.uk/news/125370/idf-2007-intel-debuts-nehalem.html ■ (in Spanish) Everything we know about Nehalem (http://www.chw.net/Articulos/Intel/Todo-lo-que-sabemos-de-Intel-Nehalem-200801051919.html) , CHW.net, 2008-01-05, http://www.chw.net/Articulos/Intel/Todo-lo-que-sabemos-de-Intel-Nehalem-200801051919.html ■ Stokes, Jon (2008-04-09), What you need to know about Intel's Nehalem CPU (http://arstechnica.com/articles/paedia/cpu/what-you-need-to-know- about-nehalem.ars) , Ars Technica, http://arstechnica.com/articles/paedia/cpu/what-you-need-to-know-about-nehalem.ars ■ Torres, Gabriel (2008-03-17), Details on the Forthcoming Intel Nehalem Processor (http://www.hardwaresecrets.com/article/535) , Hardware Secrets , http://www.hardwaresecrets.com/article/535 ■ Shimpi, Anand Lal (2008-06-05), The Nehalem Preview: Intel Does It Again (http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3326) , AnandTech , http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3326 ■ Shimpi, Anand Lal (2008-08-21), Nehalem – Everything You Need to Know about Intel's New Architecture (http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3382) , AnandTech, http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx? i=3382 ■ First Look at Nehalem Microarchitecture (http://www.xbitlabs.com/articles/cpu/display/nehalem-microarchitecture.html) , X-bit Labs, 2008-11-02, http://www.xbitlabs.com/articles/cpu/display/nehalem -microarchitecture.html External links

■ Nehalem processor (http://www.intel.com/technology/architecture -silicon/next -gen/) at Intel .com

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Intel 80486 Source: http://en.wikipedia.org/w/index.php?oldid=478139102 Contributors: 16@r, 7265, AVB, Aaroncrick, Ad88110, Alecv, Amatulic, Andrei Stroe, AnnaFrance, Anomalocaris, Anss123, AnthonyQBachler, Arch dude, Arndbergmann, Awitko, B jonas, Bender235, Betriebsnudel, Bigdumbdinosaur, Blenheimears, Bloodshedder, Bobblewik, Bongwarrior, Bookandcoffee, Boskar, Bunnyhop11, Cfabbrumd, Chris the speller, Conversion script, Crusadeonilliteracy, Damicatz, Dan100, Darin-0, Dcoetzee, Denniss, Destynova, Dicklyon, Dmsar, DocWatson42, Donarreiskoffer, Dorkbert, Durova, Emperorbma, Ericd, FleetCommand, FrankWilliams, Frap, Gene Nygaard, GoldDragon, Greg L, GregorB, Ham Pastrami, Hellcat fighter, HenkeB, Hooperbloob, Iain.mcclatchie, Imperator3733, Imroy, Ivan Shmakov, Ixfd64, Jackelfive, Jannex, Jeberle, Jerome Charles Potts, Jerryobject, Jphill19, Jpk, Jsmaye, Jwigton, Katieh5584, Kenyon, Lanpaper, LeaveSleaves, Libro0, Lightmouse, LtNOWIS, Lucid, Lupine Proletariat, MARQUIS111, MSTCrow, Magus732, Martyx, Matt Britt, Matthiaspaul, Mdd4696, Mikko Paananen, Miyagawa, MonkeyKingBar, Moogsi, Morio, Morkork, Muchness, Mwtoews, Nat682, Nickispeaki, ONjA, Ondenc, Pantergraph, Peter1912, Piano non troppo, Pnm, Poor Yorick, Posix memalign, Rechlin, Richardcavell, Rilak, Roo72, RoyBoy, Sarenne, Scientus, Seraphimblade, Shadowjams, Shigernafy, Silas S. Brown, Skl1983, Slogsweep, Starnestommy, Stephen Gilbert, SubcommandanteM, Swaaye, TakuyaMurata, Tarquin, Template namespace initialisation script, TheJosh, Theaveng, Thesquire, Tktktk, TobleRone, Tom verbeure, Tracer9999, Uucp, Van helsing, VanHelsing.16, Vkem, VladislavNedelev, Vossanova, Vykk, Wernher, Wrp103, Yarvin, Yellowstone6, Yuhong, Yurik, Zergrush Rhys, 294 anonymous edits

Pentium Source: http://en.wikipedia.org/w/index.php?oldid=477531330 Contributors: A:-)Brunuś, Arndbergmann, Axl, Caltrop, Chris the speller, CliffC, Coolguy6662, Czarkoff, DHR, Denniss, Doru001, FleetCommand, Fourohfour, Frap, Furrykef, GFHandel, Glane23, Greg L, Guy Harris, Guy Macon, Hammersoft, HenkeB, Highcc, Jagged 85, Jphill19, Juventas, KDesk, Kudret abi, Letdorf, Maksdo, Manop, Mattius92, Mdwh, Morio, Neolandes, NeonMerlin, Nurg, Observ, Ofus, Peoplesyak, Pol098, R!SC, R'n'B, Rjwilmsi, Ronz, SFC9394, Sirsai, Spacepotato, Stemonitis, Thetechnotoast, Thue, Vegaswikian, ViperSnake151, Vitkovskiy Roman, Vossanova, 129 anonymous edits

P5 (microarchitecture) Source: http://en.wikipedia.org/w/index.php?oldid=478462433 Contributors: 170.65.128.xxx, 172.130.49.xxx, 1exec1, 99bluefoxx, Academic Challenger, Addshore, Agentbla, Aij, Airplaneman, Alansohn, Aldie, Alecv, Alerante, AlexProfesor, [email protected], Alinor, AlphaPyro, Aluvus, Amatulic, AndriuZ, AndyLandy, Anetode, Antilived, Apoltix, Arndbergmann, Audriusa, Austriacus, Axel Bavaria, BWCNY, BerndSinger, Beyond silence, Bk0, Bomazi, BorgHunter, Bovineone, Brian0918, Bryan Derksen, Bumm13, Caltas, Catharticflux, Chowbok, Chris S, Chris the speller, Chrisf8657, Christopherlin, Coffee, Conversion script, CoolFox, Crusadeonilliteracy, Cybercobra, DHR, Dalef, Damian Yerrick, Dan100, DanMatthewsUK, DaveJB, DaveOinSF, Daveadams, Dcook32p, Defaultuser, Denniss, DerHexer, Derangedfirewire, DerekL, Dforest, Dittaeva, Djlee, Donarreiskoffer, Donreed, Doyley, Dr , Dynabee, Ed g2s, Enviroboy, Eric Kvaalen, Everyking, Ewlyahoocom, Faradayplank, Fences and windows, Fernvale, Fischer.sebastian, Fourohfour, Fran McCrory, Frap, Fuzzynyanko, GHe, Glider87, Gona.eu, GregorB, Guy Harris, Ham Pastrami, Hannes Hirzel, HenkeB, Heron, Homerjay, Howcheng, Iain.mcclatchie, Imperator3733, Imroy, Iorsh, Ipsign, Ixfd64, Jabencarsey, Jagged 85, Jannex, Jdlowery, Jeltz, Jerryobject, Jj137, JohnWhitlock, Josh the Nerd, Jovianeye, Jphill19, Jpk, Jusdafax, KUsam, Krash, Ksyrie, Lavenderbunny, LeeSI, Letdorf, LittleDan, Lusheeta, Lzur, Macdonaldd, Madhero88, Manop, MarkMLl, Markhobley, Markpeak, Maurice Carbonaro, Mav, Max Naylor, Mdwh, Michael Hardy, Mikeblas, Mikiemike, Mkill, Mloiselle, Morio, Morkork, Msikma, NJA, NeonMerlin, NetRolller 3D, Nurg, Observ, Oliphaunt, P-unit, Pakaran, Palica, Pcap, Peter1912, Plasticup, Plek, Plugwash, Plutor, Pooua, Pritish.04, R'n'B, Rabhyanker, Remingtonhill1, Richardcavell, Rilak, Rjwilmsi, Roadrunner, Ronz, Ruud Koot, Rvalles, Sarenne, Sergei Frolov, Seth Nimbosa, SimonKoch, Sjakkalle, Smjg, Souch3, Spacepotato, Spellage, Stan Shebs, Stubbleboy, Superchad, Swaaye, Tannin, The Thing That Should Not Be, Therealcolletepierre, Tom verbeure, Typhoon, Uriyan, UserGoogol, UtherSRG, Uzume, Visite fortuitement

prolongée, Vossanova, Walnutjk, Wengier, Wereon, Wernher, Wiarthurhu, Wikifan12345, Winhunter, WojPob, Yarvin, Yggdræsil, Youssefsan, Ysangkok, Zundark, 醜 い 女, 399 anonymous edits

P6 (microarchitecture) Source: http://en.wikipedia.org/w/index.php?oldid=478418055 Contributors: Agentbla, AlistairMcMillan, Aluvus, Andros 1337, Anirvan, ArachanoxReal, Arndbergmann, Artoftransformation, Bgold, Blazar, Blound, Bobblewik, Brianski, Cburnett, CecilWard, Chbarts, DGerman, Damian Yerrick, David Latapie, Denniss, Ergosteur, Frankchn, Frap, Guy Harris, Iambk, Il palazzo, Imperator3733, Jigen III, Jimys salonika, Jukeboxlord, KuatofKDY, Kyro38, Letdorf, Letowskie, Levin, Longshot14, MARQUIS111, MCBastos, Milan Keršláger, Morio, Optikos, Pixie2000, Qutezuce, R'n'B, Rilak, Sarenne, Saxbryn, StephenHecht, Swaaye, Swid, The Wild Falcon, The hardcore icon the sandman, Timmh, Tra, Uzume, Visite fortuitement prolongée, Vossanova, 117 anonymous edits Article Sources and Contributors 61

Nehalem (microarchitecture) Source: http://en.wikipedia.org/w/index.php?oldid=473448041 Contributors: -Majestic-, 1exec1, A5b, AgentJ38, Airplaneman, Ajtouchstone, Alainkaa, Alinor, Althepal, Aminorex, Anastrophe, Andi47, Andros 1337, Angelsfreeek, ArachanoxReal, Arch dude, Arndbergmann, Ary29, Baadcatj, BaldPark, Belg4mit, Bernd vdB, Blacksmith tb, Blizzard777, Bmatthewshea, Bob A, Bork, Bsautter, Bub's, BulletZ, Calwiki, Canterwoodboy, Capricorn42, Carlosguitar, Chowbok, Cncxbox, Coldpower27, Conti, DMCer, Dadu, Damon Mah, Darin-0, David Latapie, Ddoomdoom, Debresser, Dogcow, Doradus, Dsbos, Duduong, Echrei, Fenix*NBK*, Fernvale, Fivemack, Flamingspinach, Frap, GRevolution824, Garion96, Geeko2, Geoffeg, Gioto, GoingBatty, Goodone121, Gunnish1337, Guy Harris, Gyrobo, Hervegirod, Hu12, HumphreyW, Ilaiho, Imperator3733, Insane101, Irrªtiºnal, Ixfd64, JLaTondre, Jasper Deng, Jayayess1190, Jbolden1517, Jdenyc, Jgp, Jjalocha, Joachimv, Joblack, Joffeloff, Johnuniq, JoshuaKuo, Julesd, Juliancolton, Jyro117, KCinDC, KDesk, KelleyCook, Kevin j morse, Keyser Söze, Kinema, Kohtala, Kyng, Lathrop1885, LeiZhu, Leipzig3, Letowskie, Levil, Little Professor, Llloic, Lordmetroid, Lycurgus, Lyoko is Cool, MFago, MacintoshWriter, Makelelecba, Manop, Masudr, Mattdhodges, Maxwellversion2, Memoryhole, Mgz, MichaelsProgramming, Morio, MuzikJunky, Nemesiscavalry, NetRolller 3D, Newone, NickCT, Nicoli nicolivich, NoErr, NotHugo, Nyat, Observ, OlEnglish, Optikos, OrkMan2072, OwenBlacker, P2501, Paranoidmage, PawełMM, Petri Krohn, Philosofool, Podzemnik, Põhja Konn, QTCaptain, Ramckay, Ramu50, Ratemonth, RekishiEJ, Retpyrc, Retroneo, Rjwilmsi, Rmshro0, Rob Cranfill, Ronark, RoyBoy, Salamurai, Saxbryn, Serjio-pt, Simon Brady, Simonsarris, Skilltim, Snydeq, Sobbybutter, Soruly, Soumyasch, Sreyan, Standalones, Stannered, Stemonitis, Sulimo, Syrthiss, Technorj, The Wild Falcon, The doctor23, ThierryVignaud, Toehead2001, Tokek, Tommy Kronkvist, Tommy2010, Tracer9999, Tradlos, [email protected], Txuspe, Urvabara, Uzume, Vectro, Vermaden, Visite fortuitement prolongée, Vossanova, WhiteTimberwolf, Winterspan, Wolf-17x, Xpclient, Xyzzyva, Yakiv Gluck, Ynhockey, Zarel, Zuxy, 830 anonymous edits Image Sources, Licenses and Contributors 62 Image Sources, Licenses and Contributors

Image:KL_Intel_D8086.jpg Source: http://en.wikipedia.org/w/index.php?title=File:KL_Intel_D8086.jpg License: GNU Free Documentation License Contributors: Konstantin Lanzet Image:Wyprowadzenie mikroprocesora 8086.JPG Source: http://en.wikipedia.org/w/index.php?title=File:Wyprowadzenie_mikroprocesora_8086.JPG License: Public Domain Contributors: Cwbm (commons), JWBE, Maniac, Mikhail Ryazanov, 2 anonymous edits Image:Intel 8086 block scheme.svg Source: http://en.wikipedia.org/w/index.php?title=File:Intel_8086_block_scheme.svg License: Creative Commons Attribution-ShareAlike 3.0 Unported Contributors: Harkonnen2 Image:KL USSR KP1810BM86.jpg Source: http://en.wikipedia.org/w/index.php?title=File:KL_USSR_KP1810BM86.jpg License: GNU Free Documentation License Contributors: Konstantin Lanzet Image:Oki 80c86a.jpg Source: http://en.wikipedia.org/w/index.php?title=File:Oki_80c86a.jpg License: Public Domain Contributors: Alecv Image:KL Intel TD8088.jpg Source: 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