Intel® Processor Graphics: Architecture & Programming
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THINKBOOK Plus Competitive Comparison Guide
THINKBOOK Plus Competitive Comparison Guide Modernize Multitasking WHY DUAL DISPLAY 10.8“ e-ink display on the cover for increased productivity. Take notes, review documents, get the most important updates even when the lid is closed. MODERNIZE MULTITASKING Dual display for enhanced productivity. Switch between apps and tasks seamlessly, work effectively when the lid is open or closed. PRODUCTIVITY - BOOSTING FEATURES Powered by the latest Intel® processors and backed by high-speed memory, ThinkBook Plus can power through intensive tasks with ease. BUSINESS - GRADE SERVICES ThinkBook Plus comes with advanced-level support that is designed to expedite problem resolution and give customers a superior service experience. ThinkBook Plus is the first PC with an e-ink display on the A-cover, in addition to the main display. At the time of ship support, there is no device in the market that is an exact match. So the most similar devices from a customer’s usage perspective have been selected for comparison. A DUAL DISPLAY DEVICE TO HELP YOU BE MORE PRODUCTIVE Smart Power On: Fingerprint reader on the power button Smart Info: take quick notes during meetings, keep track of the important notifications—all on the 10.8-inch e-ink display on the A-cover Modern Standby: Receive emails and updates even while the lid is closed Skype for Business Hot Keys: instant connectivity with one key to answer and one to hang up COLLABORATE SEAMLESSLY RESPOND FASTER REVIEW & ANNOTATE EASILY CREATE INTUITIVELY E-Reader: read, review, or annotate documents quickly -
X86 Assembly Language Syllabus for Subject: Assembly (Machine) Language
VŠB - Technical University of Ostrava Department of Computer Science, FEECS x86 Assembly Language Syllabus for Subject: Assembly (Machine) Language Ing. Petr Olivka, Ph.D. 2021 e-mail: [email protected] http://poli.cs.vsb.cz Contents 1 Processor Intel i486 and Higher – 32-bit Mode3 1.1 Registers of i486.........................3 1.2 Addressing............................6 1.3 Assembly Language, Machine Code...............6 1.4 Data Types............................6 2 Linking Assembly and C Language Programs7 2.1 Linking C and C Module....................7 2.2 Linking C and ASM Module................... 10 2.3 Variables in Assembly Language................ 11 3 Instruction Set 14 3.1 Moving Instruction........................ 14 3.2 Logical and Bitwise Instruction................. 16 3.3 Arithmetical Instruction..................... 18 3.4 Jump Instructions........................ 20 3.5 String Instructions........................ 21 3.6 Control and Auxiliary Instructions............... 23 3.7 Multiplication and Division Instructions............ 24 4 32-bit Interfacing to C Language 25 4.1 Return Values from Functions.................. 25 4.2 Rules of Registers Usage..................... 25 4.3 Calling Function with Arguments................ 26 4.3.1 Order of Passed Arguments............... 26 4.3.2 Calling the Function and Set Register EBP...... 27 4.3.3 Access to Arguments and Local Variables....... 28 4.3.4 Return from Function, the Stack Cleanup....... 28 4.3.5 Function Example.................... 29 4.4 Typical Examples of Arguments Passed to Functions..... 30 4.5 The Example of Using String Instructions........... 34 5 AMD and Intel x86 Processors – 64-bit Mode 36 5.1 Registers.............................. 36 5.2 Addressing in 64-bit Mode.................... 37 6 64-bit Interfacing to C Language 37 6.1 Return Values.......................... -
Multiprocessing Contents
Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References ............................................. -
IXP400 Software's Programmer's Guide
Intel® IXP400 Software Programmer’s Guide June 2004 Document Number: 252539-002c Intel® IXP400 Software Contents INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. The Intel® IXP400 Software v1.2.2 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. -
NS-PWLC563 PWLC563-C 14-0314 TIP GDE V1.Indd
Tip Compatibility Guide Ultrabook Charger Guide de compatibilité des connecteurs Chargeur pour Ultrabook Guía de compatibilidad de las puntas Cargador para Ultrabook NS-PWLC563/NS-PWLC563-C Before using your new product, please read these instructions to prevent any damage. Avant l’utilisation de ce produit neuf, lire ces instructions afi n d’éviter tout dommage. Antes de usar su producto nuevo, lea estas instrucciones para evitar cualquier daño. To locate the correct tip for your Ultrabook: 3 Identifi er le numéro du modèle du connecteur. 1 Find your Ultrabook manufacturerModel / Modèle (Acer, / Modelo Dell, HP, etc.) in Model / Modèle / Modelo Para identifi car la punta correcta para su Ultrabook: the table. 1 Identifi que el fabricante de su Ultrabook (Acer, Dell, HP, 2 Find your Ultrabook model (Aspire, Tablet, ThinkPad, etc.) etc.) en la tabla. 3 Find the tip model number. 2 Identifi que el modelo de su Ultrabook (Aspire, tableta, Pour identifi er le connecteur correct pour l’Ultrabook : ThinkPad, etc.) 1 Rechercher le fabricant de l’Ultrabook (Acer, Dell, HP, etc.) 3 Identifi que el número del modelo de punta. dans le tableau. 2 Trouver le modèle de l’Ultrabook (Aspire, Tablet, Thinkpad, etc.) Model / Modèle / Modelo Model / Modèle / Modelo Acer Aspire M5-481PT-6488 N1 Acer Aspire S3-391-9813 N1 Acer Aspire M5-481PT-6644 N1 Acer Aspire S3-951 N1 Acer Aspire M5-481T N1 Acer Aspire S3-951-6432 N1 Acer Aspire M5-481TG N1 Acer Aspire S3-951-6464 N1 Acer Aspire M5-581T N1 Acer Aspire S3-951-6646 N1 Acer Aspire M5-581T-6405 N1 Acer Aspire -
The Intel X86 Microarchitectures Map Version 2.0
The Intel x86 Microarchitectures Map Version 2.0 P6 (1995, 0.50 to 0.35 μm) 8086 (1978, 3 µm) 80386 (1985, 1.5 to 1 µm) P5 (1993, 0.80 to 0.35 μm) NetBurst (2000 , 180 to 130 nm) Skylake (2015, 14 nm) Alternative Names: i686 Series: Alternative Names: iAPX 386, 386, i386 Alternative Names: Pentium, 80586, 586, i586 Alternative Names: Pentium 4, Pentium IV, P4 Alternative Names: SKL (Desktop and Mobile), SKX (Server) Series: Pentium Pro (used in desktops and servers) • 16-bit data bus: 8086 (iAPX Series: Series: Series: Series: • Variant: Klamath (1997, 0.35 μm) 86) • Desktop/Server: i386DX Desktop/Server: P5, P54C • Desktop: Willamette (180 nm) • Desktop: Desktop 6th Generation Core i5 (Skylake-S and Skylake-H) • Alternative Names: Pentium II, PII • 8-bit data bus: 8088 (iAPX • Desktop lower-performance: i386SX Desktop/Server higher-performance: P54CQS, P54CS • Desktop higher-performance: Northwood Pentium 4 (130 nm), Northwood B Pentium 4 HT (130 nm), • Desktop higher-performance: Desktop 6th Generation Core i7 (Skylake-S and Skylake-H), Desktop 7th Generation Core i7 X (Skylake-X), • Series: Klamath (used in desktops) 88) • Mobile: i386SL, 80376, i386EX, Mobile: P54C, P54LM Northwood C Pentium 4 HT (130 nm), Gallatin (Pentium 4 Extreme Edition 130 nm) Desktop 7th Generation Core i9 X (Skylake-X), Desktop 9th Generation Core i7 X (Skylake-X), Desktop 9th Generation Core i9 X (Skylake-X) • Variant: Deschutes (1998, 0.25 to 0.18 μm) i386CXSA, i386SXSA, i386CXSB Compatibility: Pentium OverDrive • Desktop lower-performance: Willamette-128 -
Technical Product Summary Classic/PCI I486 Baby-AT Motherboard
INTEL OEM PRODUCTS AND SERVICES DIVISION PRELIMINARY - REV 0.1 ® Technical Product Summary Classic/PCI i486TM Baby-AT Motherboard Models: BP4S33AT BP4D33AT BP4D266AT Preliminary Version 0.1 April, 1993 Order Number PRELIMINARY Classic/PCI i486 Baby-AT Motherboard Technical Product Summary · Page 1 INTEL OEM PRODUCTS AND SERVICES DIVISION PRELIMINARY - REV 0.1 Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel Corporation retains the right to make changes to these specifications at any time, without notice. Contact your local sales office to obtain the latest specifications before placing your order. The following are trademarks of Intel Corporation and may only be used to identify Intel products: 376Ô i750â MAPNETÔ AboveÔ i860Ô MatchedÔ ActionMediaâ i960â MCSâ BITBUSÔ Intel287Ô Media MailÔ Code BuilderÔ Intel386Ô NetPortÔ DeskWareÔ Intel387Ô NetSentryÔ Digital StudioÔ Intel486Ô OpenNETÔ DVIâ Intel487Ô OverDriveÔ EtherExpressÔ Intelâ ParagonÔ ETOXÔ intel inside.Ô PentiumÔ ExCAÔ Intellecâ ProSolverÔ Exchange and GoÔ iPSCâ READY-LANÔ FaxBACKÔ iRMXâ Reference Pointâ FlashFileÔ iSBCâ RMX/80Ô Grand ChallengeÔ iSBXÔ RxServerÔ iâ iWARPÔ SatisFAXtionâ ICEÔ LANDeskÔ SnapIn 386Ô iLBXÔ LANPrintâ Storage BrokerÔ InboardÔ LANProtectÔ SuperTunedÔ i287Ô LANSelectâ The Computer Inside.Ô i386Ô LANShellâ TokenExpressÔ i387Ô LANSightÔ Visual EdgeÔ i486Ô LANSpaceâ WYPIWYFâ i487Ô LANSpoolâ IntelTechDirectÔ MDS is an ordering code only and is not used as a product name or trademark. MDS is a registered trademark of Mohawk Data Sciences Corporation. CHMOS and HMOS are patented processes of Intel Corp. Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. -
NS-PWLC563-C Ultrabook Charger Tip Compatibility Guide
Skip to content Manuals+ User Manuals Simplified. INSIGNIA NS-PWLC563/ NS-PWLC563-C Ultrabook Charger Tip Compatibility Guide Home » Insignia » INSIGNIA NS-PWLC563/ NS-PWLC563-C Ultrabook Charger Tip Compatibility Guide Contents [ hide 1 Tip Compatibility Guide Ultrabook Charger 1.1 To locate the correct tip for your Ultrabook: 2 Related Manuals: Tip Compatibility Guide Ultrabook Charger Before using your new product, please read these instructions to prevent any damage. To locate the correct tip for your Ultrabook: 1. Find your Ultrabook manufacturer (Acer, Dell, HP, etc.) in the table. 2. Find your Ultrabook model (Aspire, Tablet, ThinkPad, etc.) 3. Find the tip model number. Model Acer Aspire M5-481PT-6488 N1 Acer Aspire M5-481PT-6644 N1 Acer Aspire M5-481T N1 Acer Aspire M5-481TG N1 Acer Aspire M5-581T N1 Acer Aspire M5-581T-6405 N1 Acer Aspire M5-581T-6807 N1 Acer Aspire M5-581TG N1 Acer Aspire M5-581TG-6666 N1 Acer Aspire S3 N1 Acer Aspire S3 (MS2346) N1 Acer Aspire S3-391 N1 Acer Aspire S3-391-323a4G12add N1 Acer Aspire S3-391-323a4G52add N1 Acer Aspire S3-391-53314G12add N1 Acer Aspire S3-391-6407 N1 Acer Aspire S3-391-6423 N1 Acer Aspire S3-391-6448 N1 Acer Aspire S3-391-6466 N1 Acer Aspire S3-391-6470 N1 Acer Aspire S3-391-6616 N1 Acer Aspire S3-391-6676 N1 Acer Aspire S3-391-6899 N1 Acer Aspire S3-391-73514G12add N1 Acer Aspire S3-391-73514G25add N1 Acer Aspire S3-391-9415 N1 Acer Aspire S3-391-9445 N1 Acer Aspire S3-391-9499 N1 Acer Aspire S3-391-9606 N1 Acer Aspire S3-391-9695 N1 Model Acer Aspire S3-391-9813 N1 Acer Aspire -
Embedded Intel486™ Processor Hardware Reference Manual
Embedded Intel486™ Processor Hardware Reference Manual Release Date: July 1997 Order Number: 273025-001 The embedded Intel486™ processors may contain design defects known as errata which may cause the products to deviate from published specifications. Currently characterized errata are available on request. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or oth- erwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel’s web site at http:\\www.intel.com Copyright © INTEL CORPORATION, July 1997 *Third-party brands and names are the property of their respective owners. CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS .................................................................................................. -
Energy Per Instruction Trends in Intel® Microprocessors
Energy per Instruction Trends in Intel® Microprocessors Ed Grochowski, Murali Annavaram Microarchitecture Research Lab, Intel Corporation 2200 Mission College Blvd, Santa Clara, CA 95054 [email protected], [email protected] Abstract where throughput performance is the primary objective. In order to deliver high throughput performance within a Energy per Instruction (EPI) is a measure of the amount fixed power budget, a microprocessor must achieve low of energy expended by a microprocessor for each EPI. instruction that the microprocessor executes. In this It is important to note that MIPS/watt and EPI do not paper, we present an overview of EPI, explain the consider the amount of time (latency) needed to process factors that affect a microprocessor’s EPI, and derive a an instruction from start to finish. Other metrics such as MIPS 2/watt (related to energy•delay) and MIPS 3/watt historical comparison of the trends in EPI over multiple 2 generations of Intel microprocessors. We show that the (related to energy•delay ) assign increasing importance recent Intel® Pentium® M and Intel® Core™ Duo to the time required to process instructions, and are thus microprocessors achieve significantly lower EPI than used in environments in which latency performance is what would be expected from a continuation of historical the primary objective. trends. 2. What Determines EPI? 1. Introduction Consider a capacitor that is charged and discharged With the power consumption of recent desktop by a CMOS inverter as shown in Figure 1. microprocessors having reached 130 watts, power has emerged at the forefront of challenges facing the V microprocessor designer [1, 2]. -
Intel® Itanium® Architecture Assembly Language Reference Guide
Intel® Itanium® Architecture Assembly Language Reference Guide Copyright © 2000 - 2003 Intel Corporation. All rights reserved. Order Number: 248801-004 World Wide Web: http://developer.intel.com Intel(R) Itanium(R) Architecture Assembly Lanuage Reference Guide Page 2 Disclaimer and Legal Information Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. This Intel® Itanium® Architecture Assembly Language Reference Guide as well as the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. -
Analysis of the Intel 386 and I486 Microprocessors for the Space Station Freedom Data Management System
NASA Technical Memorandum 103862 Analysis of the Intel 386 and i486 Microprocessors for the Space Station Freedom Data Management System Yuan-Kwei Liu (NA_A-TM-I03862) ANALYSIS OF THE INTEL 386 N_I-25687 AND i48& MICkOPROCESSORS FOR THE SPACE STATION FREEOQM OATA MANAGEMENT SYSTEM (NASA) 24 p CSCL 09B Unclas G3/02 0020605 May 1991 NASA National Aeronaut;cs and Space Administration NASA Technical Memorandum 103862 Analysis of the lntel 386 and i486 Microprocessors for the Space Station Freedom Data Management System Yuan-Kwei Liu, Ames Research Center, Moffett Field, California May 1991 NationalAeronautics and Space Administration Ames Research Center Moffett Field, California 94035-1000 1. SUMMARY This report analyzes the feasibility of upgrading the Intel 386 a microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 a microprocessor. It is part of an effort funded by the National Aeronautics and Space Administration (NASA) Space Station Freedom Advanced Development program. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (space) qualification schedule, and performance. The advantages of the i486 over the 386 are lower power consumption and higher floating- point performance in speed. The i486 on-chip cache, however, has neither parity check nor error detection and correction circuitry. In space, the probability of having the contents of the cache altered, is higher than on the ground due to the higher radiation exposure. Therefore, it is necessary to measure the performance of the i486 with the cache disabled.