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Communication Theory II Microprocessor (COM 9323) Lecture 2: Review on Intel Family Ahmed Elnakib, PhD Assistant Professor, Mansoura University, Egypt Feb 17th, 2016 1 Text Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey, Prentice Hall, 2009 2. Assembly Language for x86 processors, 6th edition, K. R. Irvine, Prentice Hall, 2011 References: 1. Computer Architecture: A Quantitative Approach, 5th edition, J. Hennessy, D. Patterson, Elsevier, 2012. 2. The 80x86 Family, Design, Programming and Interfacing, 3rd edition, Prentice Hall, 2002 3. The 80x86 IBM PC and Compatible Computers, Assembly Language, Design, and Interfacing, 4th edition, M.A. Mazidi and J.G. Mazidi, Prentice Hall, 2003 2 Lecture Objectives 1. Provide an overview of the various 80X86 and Pentium family members 2. Define the contents of the memory system in the personal computer 3. Convert between binary, decimal, and hexadecimal numbers 4. Differentiate and represent numeric and alphabetic information as integers, floating-point, BCD, and ASCII data 5. Understand basic computer terminology (bit, byte, data, real memory system, protected mode memory system, Windows, DOS, I/O) 3 Brief History of the Computers o1946 The first generation of Computer ENIAC (Electrical and Numerical Integrator and Calculator) was started to be used based on the vacuum tube technology, University of Pennsylvania o1970s entire CPU was put in a single chip. (1971 the first microprocessor of Intel 4004 (4-bit data bus and 2300 transistors and 45 instructions) 4 Brief History of the Computers (cont’d) oLate 1970s Intel 8080/85 appeared with 8-bit data bus and 16-bit address bus and used from traffic light controllers to homemade computers (8085: 246 instruction set, RISC*) o1981 First PC was introduced by IBM with Intel 8088 (CISC**: over 20,000 instructions) microprocessor oMotorola emerged with 6800. Apple Macintosh computers started to use 68000 series of microprocessors. 5 *RISC: Reduced Instruction Set Computers **CISC: Complex instruction set computers 8085 Intel Microprocessor o 16 bit address bus to select an address between 64kbyte memory o 8 bit data bus to fetch 8 bits to its internal registers 6 Simple Microprocessor Architecture 7 Early 8-bit Microprocessors o Only Intel and Motorola (IBM also produces Motorola-style microprocessors) continue successfully to create newer and improved versions of the microprocessor o Motorola has sold its microprocessor division, named now Freescale Semiconductors. o Inc. Zilog still manufactures microprocessors, but remains in the background, concentrating on microcontrollers and embedded controllers (Z-80, a machine language compatible with 8085) instead of general-purpose microprocessors. 8 Intel Microprocessors Family till 2001 9 10 11 Intel Microprocessor core (P) versions 12 First Linear/physical Generation Prominent consumer CPU brands Notable (new) features introduced address space 1978 Intel 8086, Intel 8088 and clones First x86 microprocessors 1st Intel 80186, Intel 80188 and 16-bit / 20-bit Hardware for fast address calculations, clones, NEC V20/V30 fast multiplication and division 1982 16-bit ((14+16)- MMU, for protected mode and a 2nd Intel 80286 and clones bit segmented) / larger address space 24-bit 32-bit instruction set, MMU with paging, 3rd (IA-32) 1985 Intel 80386 and clones, AMD Am386 PGA132 socket L1 cache and pipelining introduced into 3rd/4th 1992 Cyrix Cx486SLC, Cyrix Cx486DLC the 386 platform, PGA132 socket RISC-like pipelining, 4th (FPU) 1989 Intel 80486 and clones, AMD Am486 integrated x87 FPU (80-bit), on- 32-bit ((14+32)- chipcache, PGA168 socket Am5x86, Cyrix 5x86, Pentium bit segmented) / Partial Pentium's specification brought 4th/5th 1997 OverDrive 32-bit into the 486 platform Superscalar 64-bit databus, faster 5th 1993 Pentium, Pentium MMX, Rise mP6 FPU, MMX (2× 32-bit),Socket 7 AMD K5, Cyrix 6x86, Cyrix MII, Nx586 (1994), IDT/Centaur-C6, Cyrix III- Discrete microarchitecture (µ-op 5th/6th 1996 Samuel (2000), VIA C3-Samuel2 / VIA translation) 13 C3-Ezra (2001) Brands of processors implementing the x86 instruction set (x86 History) First Linear/physical Gneration Prominent consumer CPU brands Notable (new) features introduced address space µ-op translation, conditional move instructions, Out-of-orderregister 1995 Pentium Pro renaming, speculative 32-bit ((14+32)-bit execution, PAE (Pentium Pro), in- segmented) / 36-bit package L2 cache (Pentium Pro), Socket 8 physical (PAE) 6th SSE (2× 64-bit), on-die L2 Cache 1997 Pentium II/III, Celeron, Xeon (Mendocino, Coppermine),SLOT 1 or Socket 370 On-die L2-Cache (K6-III, Cyrix III 32-bit ((14+32)-bit 1997 AMD K6/2/III, Cyrix III-Joshua (2000) Joshua), 3DNow!, no PAE support, Super segmented) / 32-bit Socket 7 (K6-2) Pentium M, VIA C7 (2005), Intel Optimized for low thermal design power, 6th/7th 2003 Core(2006) four pumped FSB 32-bit ((14+32)-bit Superscalar FPU, wide design (up to three 1999 Athlon, Athlon XP segmented) / 36-bit x86 instr./clock),Slot A or Socket A 7th physical (PAE) Deeply pipelined, high 2000 Pentium 4 frequency, SSE2, hyper-threading,Socket 478 14 Brands of processors implementing the x86 instruction set (x86 History) First Prominent consumer Linear/physical Generation Notable (new) features introduced CPU brands address space Pentium 4 Prescott F/506/516/5 7th/8th 64-bit / 36-bit EM64T technology introduced, very deeply pipelined, very 2005 x1/6xx,Celeron (x86-64) physical high frequency, SSE3, LGA 775 socket, CMP D 3x1/3x6/355, Penti um D AMD64 processor (excluding 32-bit Sempron), on-die Athlon 64, Athlon 64 64-bit / 40-bit memory controller, HyperTransport, CMP, virtulisation 2003 X2 (2005), Sempron( physical (AMD-V) on some models, Socket 2004), Opteron 754/939/940 or AM2 socket Intel 64 processor, low power, multi-core, lower clock 64-bit / 36-bit frequency, SSE4 (Penryn), wide dynamic execution, µ-op 2006 Intel Core 2 8th (x86-64) physical fusion, macro-µ-op fusion, virtulisation (Intel VT) on some models AMD Phenom, AMD 64-bit / 48-bit Monolithic quad-core, SSE4a, HyperTransport 2007 Phenom II (2008) physical 3, AM2+ orAM3 socket Out-of-order, superscalar, 64-bit (integer CPU), hardware- 64-bit / 36-bit 2008 VIA Nano based encryption; very low power; adaptive power physical management 15 Brands of processors implementing the x86 instruction set (x86 History) First Prominent consumer CPU Linear/physical Generation Notable (new) features introduced brands address space Intel Core i3, Core QuickPath, native memory controller, on-die L3 cache, i5 and Core modular, Intel HD Graphics introduced onto CPU chip i7(Nehalem/Westmere) (Clarkdale), LGA 1366 (Nehalem) or LGA 1156 socket 2008 64-bit / 36-bit In-order but highly pipelined, very-low-power, some Intel Atom physical models (Diamondville) with 32-bit (integer CPU), on- 8th/9th die GPU (Penwell, Cedarview) AMD APU C, E and Z Series (Bobcat) Out-of-order, 64-bit (integer CPU), on-die GPU; low 2011 AMD APU A and E Series power (Bobcat), Socket FM1 (Desktop) (Llano) 64-bit / 48-bit AMD APU A Series physical SSE5/AVX (4× 64-bit), highly modular design, (Bulldozer, Trinity and later) integrated on-die GPU, Socket FM2 or Socket FM2+ 2011 Intel Core i3, Core 64-bit / 40-bit i5 and Core i7 (Sandy Internal Ring connection, GPGPU, LGA 1155 socket 9th(GPGPU) physical Bridge/Ivy Bridge) Intel Core i3, Core 64-bit / 44-bit AVX2, FMA3, TSX, BMI1, and BMI2 instructions, LGA 2013 i5 and Core physical 1150socket i7(Haswell/Broadwell) 16 Brands of processors implementing the x86 instruction set (x86 History) First Prominent consumer Linear/physical Generation Notable (new) features introduced CPU brands address space Intel Core i3, Core Out-of-order, 64-bit (integer CPU), AVX3, integrated 10th i5 and Core 2015/2016 on-die southbridge, integrated on-die x86 MIC (SoC,MIC) i7(Skylake/Kaby array GPU Lake/Cannonlake) Transmeta 32-bit ((14+32)- VLIW design with x86 emulator, on-die memory 2000 Crusoe, Transmeta bit segmented) / controller Efficeon 32-bit EPIC architecture with an on-package engine (pre- 32-bit ((14+32)- Intel Itanium IA-32 2006 chips, later using IA-32 Execution Layer) that Others 2001 bit segmented) / compatibility mode provides backward support for most IA-32 N/A applications (MIC pilot) Many Integrated Cores (62), In- 2012 Intel Xeon Phi (Larrabee) order P54C with x86-64, very wide vector unit, LRBni instructions (8× 64-bit) 17 Report 02: Due to Feb. 25th , 8.30 AM o Individually o Use the internet to make a report on I3, I5, and I7 technology o Report will be delivered by hand before the lecture 18 Computer Architecture 19 The Memory Map in Personal Computers o Real (conventional Memory): 1. TPA: Transient Program Area 2. System Memory o XMS: Extended memory Area 20 TPA: Transient Program Area o Holds the DOS (disk operating system) Available for operating system and other programs application programs that control the computer system oThe TPA is a DOS concept and not really applicable in Windows oThe TPA also stores any currently active or inactive DOS application programs oThe length of the TPA is 640K bytes 21 TPA: Interrupt vector o Interrupt vector: access features of DOS, basic I/O system (BIOS), and applications oThe system BIOS is a collection of programs stored in either a read-only (ROM) or flash memory that operates many of the I/O devices connected to your computer system. oThe system BIOS and DOS communications areas contain transient data used by programs to access I/O devices and the internal features of the computer system. These are stored in the TPA so they can be changed as the DOS operates. 22 TPA: IO.SYS o IO.SYS: a program that loads into the TPA from the disk whenever an MSDOS system is started. oThe IO.SYS contains programs that allow DOS to use the keyboard, video display, printer, and other I/O devices often found in the computer system.
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