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Intel® 80333 I/O Processor Intel® 80333 I/O Processor Specification Update April 2006 The Intel® 80333 I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are doc- umented in this specification update. Order Number: 305435-011US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, VoiceBrick, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2006, Intel Corporation. All rights reserved. 2 Contents Contents Revision History ......................................................................................... 5 Preface ....................................................................................................... 6 Summary Table of Changes....................................................................... 7 Identification Information .......................................................................... 13 Non-Core Errata ....................................................................................... 14 Core Errata............................................................................................... 27 Specification Changes.............................................................................. 31 Specification Clarifications........................................................................ 33 Documentation Changes.......................................................................... 48 3 Contents THIS PAGE INTENTIONALLY LEFT BLANK 4 Revision History Date Version Description Added: • A-1 stepping information to all Summary tables and to Table 1, “80333 Die Details” on page 13 and Table 2, “80333 Device ID Registers” on page 13 April 2006 011 • Status change of Erratum 35 • Status change of Specification Change 6 • Status change of Specification Clarification 52 • Documentation Change 4 Added: February 2006 010 • Non-Core Errata 36 • Specification Clarification 52 Added: January 2006 009 • Non-Core Errata 35 • Specification Change 6 Added: • Revised Specification Clarification 9 December 2005 008 • Specification Clarification 49, 50, and 51 • Documentation Change 3 October 2005 007 Added Specification Clarification 47 and 48 Added: • Non-Core Errata 33 and 34 August 2005 006 • Specification Clarification 45 and 46 • Documentation Change 2 Added: June 2005 005 • Non-Core Errata 32 • Specification Change 5 Added: May 2005 004 • Non-Core Errata 31 • Specification Change 3 and 4 Added: April 2005 003 • Non-Core Errata 30 • Specification Clarification 44 Added: • Specification Change 1 and 2 March 2005 002 • Documentation Change 1 • PB-free markings in Table 1 February 2005 001 Initial release Specification Update 5 Intel® 80333 I/O Processor Preface Preface This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published. Affected Documents/Related Documents Title Order Intel® 80333 I/O Processor Developer’s Manual 305432 Intel® 80333 I/O Processor Datasheet 305433 Intel® 80333 I/O Processor Design Guide 305434 Intel® 6700PXH 64-bit PCI Hub Specification Update 302706 Nomenclature Errata are design defects or errors. These may cause the behavior of the Intel® 80333 I/O Processor1 (80333) to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification. Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification. Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification. Note: Errata remain in the specification update throughout the product’s life cycle, or until a particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.). 1. ARM architecture compliant. 6 Specification Update Intel® 80333 I/O Processor Summary Table of Changes Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® 80333 I/O Processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: Codes Used in Summary Table Stepping X: Errata exists in the stepping indicated. Specification Change or Clarification that applies to this stepping. (No mark) or (Blank box): This erratum is fixed in listed stepping or specification change does not apply to listed stepping. Page (Page): Page location of item in this document. Status Doc: Document change or update will be implemented. Fixed: This erratum has been previously fixed. No Fix: There are no plans to fix this erratum. Plan Fix: This erratum may be fixed in a future stepping of the product. Row Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. Specification Update 7 Intel® 80333 I/O Processor Summary Table of Changes Non-Core Errata (Sheet 1 of 2) Stepping No. Page Status Errata A-0 A-1 1 XX14 No Fix CAS latency of three not supported for DDR-II On-Die Termination (ODT) 2 XX14 No Fix Legacy power fail mechanism does not work 3 XX14 No Fix A_REQ64# and B_REQ64# initialization pattern timing violation in PCI-33 mode 4 XX15 No Fix Secondary Bus Number register (PEBSBBNR) provides incorrect bus number 5 XX15 No Fix Boundary scan multi-chip module implementation 6 XX15 No Fix PCI Express* traffic class (TC) bit[2] ignored for malformed packet checks 7 XX16 No Fix Auto-Refresh command also generates a Precharge All command on DDR bus 8 XX16 No Fix Coalesced writes to 32-bit memory can cause data corruption 9 XX17 No Fix ATU passing rules operation in PCI mode 10 XX17 No Fix Secondary bus PCI RST# pulse prior to the rising edge of PWRGD 11 XX18 No Fix VPD Data Register bit[19] is not read/write 12 XX18 No Fix PCI Express* Correctable Error Mask Bits 13 XX18 No Fix DMA CRC result is byte-reversed
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