The History of the 4004
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Federico Faggin nty-five years ago, in November 71, an advertisement appeared in In April of 1969, Intel agreed to develop a Synaptics, Inc. Electronic News: “Announcing a new set of calculator chips for a Japanese firm. era in integrated electronics, a micropro- The firm consisted of two companies: Marcian E. Hofflr. grammable computer on a chip.” The ad was Electro-Technical industries handled prod- placed by Intel Corporation of Santa Clara, uct development, and Nippon Calculating Teklicon California, then just over three years old. From Machines Company handled marketing. The that modest but prophetic beginning, the calculators bore the brand name Busicom. Stanley Mazor microprocessor market has grown into a Busicom intended to use the chip set in sev- multibillion-dollar business, and Intel has eral different models of calculators, from a BEA Systems maintained a leadership position, particularly low-end desktop printing calculator to cal- in microprocessors for personal computers. culator-like office machines such as billing Masatoshi Shima In 1968, Bob Noyce and Gordon Moore, machines, teller machines, and cash regis- who had both just left Fairchild Semicon- ters. The firm made arrangements for three VM Technology Inc. ductor, founded Intel Corporation, and oper- of its engineers to come to Intel to finish the ations began in September of the same year. logic design for the calculator chips and to The new company was committed to devel- work with Intel personnel to transfer the oping semiconductor mainframe memory designs into silicon. The three engineers from products using both bipolar and MOS (metal- Japan-Masatoshi Shima and his colleagues oxide-semiconductor) technologies. Bipolar Masuda and Takayama-arrived in late June. processes offered faster access times, while Intel assigned Marcian E. Hoff Jr. to act as MOS processes promised higher chip com- liaison to the Japanese engineers. Hoff had plexity-that is, more memory bits per chip. received his PhD from Stanford University Rather than use the established technologies in 1962 and had remained there as a of the day, Intel was determined to use new research associate working on electronic bipolar and MOS processes similar to those neural networks until he joined Intel in Fairchild Semiconductor had just developed. September 1968. At Stanford, Hoff had pro- For the MOS products, Intel chose a self- grammed and built hardware interfaces for aligned P-channel silicon-gate process. IBM model 1620 and 1130 computers. He Intel intended to produce proprietary was Intel’s twelfth employee and received memory products, rather than a specific the title manager of applications research. product for each customer. Though this Hoff‘s duties were to help define Intel strategy offered high potential sales volume, products, meeting with customers and mar- it increased the design time. To optimize its keting personnel as necessary. In addition, revenue stream, therefore, Intel remained as Intel products became available, he open to limited custom work, hoping that would develop applications information to customers would be ready to use the prod- help customers use those products. ucts as soon as they were working. The However, because in early 1969 the prod- company did not project custom products ucts were still in development, and there to reach the high sales volumes it expected were limited opportunities to question of the proprietary products, but it hoped potential customers, Hoff had taken on sev- The 4004 design team they would provide an important source of eral tasks peripheral to his primary duties. revenue until the memory products were Although Hoff was only supposed to act tells its sto y. established. as liaison to the Busicom engineering team, IO /€€€Micro 0272-1732/96/$5.00 0 1996 IEEE SYNC RESET SYNC RESET Qo 01 Q9 Qo Ql 09 010 011 019 terconnection 1- the 4001/4002 set can have U ontains 1,280 nibbles addressable 4-bit I/O PO put ports via the 400 1- doubles the am 1- chip can store curiosity about the calculator led him to study the design. design in commercial products since 1968, using transistor- His first reaction was surprise at how complex the calcula- transistor logic (TTL) and ROM. tor logic was, particularly when compared to the general- Hoff expressed some of his concerns about packaging and purpose digital computers he had used. In addition, the design complexity to Intel’s upper management-designing interconnections between the various chips were extensive, that many chips could be a daunting task for the limited chip requiring large and expensive packages. Having attended design staff. Bob Noyce particularly encouraged him to pur- several meetings on the project’s cost objectives, Hoff sue an alternative design if one appeared feasible. became concerned that the packaging requirements alone Hoff was initially reluctant to deviate too far from the orig- might prevent Intel from meeting those objectives. inal Busicom design. While some aspects of the proposed Busicom had proposed a ROM-based, macroinstruction chip set were similar to those of other calculators of the day, programmable decimal computer consisting of seven differ- it also included some novel capabilities. Most notable were ent LSI chips: program control, decimal arithmetic unit, tim- the use of ROM for macroinstruction storage and a special- ing logic, ROM, shift register, printer control, and output ized instruction set that would allow various calculator- ports. Busicom had already successfully implemented this intensive machines to use the same chips. Another innovative December 1996 11 Address Sent to ROM From CPU - feature was the variable amount of shift register memory that silicon area than the shift register cell. the design could use, with the different calculator models One of the first modifications to the Busicom design Hoff having different numbers of memory registers. considered was adding subroutine capability to the instruc- Like many calculators of the day, Busicom’s design used tion set. Subroutines of simple instructions could replace shift registers for memory. Shift registers are quite fast for more complex instructions, which should allow simplifica- the arithmetic calculations, display, and printing that calcu- tion of the hardwired logic. Although the Busicom engineers lators require, but are slow for operations requiring random appeared unreceptive to Hoff‘s proposals, with Noyce’s access. Shift registers used six transistors per bit, like static encouragement, Hoff continued exploring options. RAM, but a shift register cell was smaller than the RAM cell. Hoff began to consider the design of a general-purpose The shift register’s size advantage, however, was offset by computer that might be programmed to perform calculator increased control logic complexity and slower speed for ran- functions. The computer would fetch program instructions dom access. Any access to even a portion of a memory reg- from a ROM into an arithmetic chip. The arithmetic chip ister required a complete scan through that register. Such would interpret the instructions, reading and writing as nec- slow memory access would make a conventional CPU archi- essary to DRAM chips. The arithmetic chip would also have tecture too slow to be practical. local “scratch-pad” registers. During the time the arithmetic chip was fetching program instructions from ROM, the DRAMS could be refreshed, since no instruction execution Intel had just begun working on dynamic MOS RAM,using would be occurring at that time. The data quantum would be a three-transistor cell. Hoff, aware of that development, 4 bits to allow binary-coded decimal (BCD) arithmetic. thought that if he could solve its refresh problem in the cal- Hoff performed these studies of a general architecture in culator environment, the DRAM would be an ideal alterna- July and August of 1969. During this time, he believed the tive to the shift register memory. Unlike the shift register, the Busicom team was unresponsive to his idea. On the con- DRAM could be accessed in as small a quantum as desired. trary, Busicom engineers recognized that Hoff‘s proposal of In addition, the three-transistor DRAM cell used even less a general-purpose CPU was more advantageous than their 12 IEEEMicra SYNC TEST RESET P ? Q t II INTERNAL RESET Block diagram of the 4004 CPU The 4004 conrains 16 genera-purpose +bit registers; .'Chi" indicates command). There is :tlso a reset pin IC) ini- one +hit accumulator: ;t four-le\~rl.12-hit push-clonm tialize the system ancl ;I test input pin. Tcst pro\,idcs on~' address stack containing the program counter and three of the conditions in the conclitiond jump instruction (ICs,, return aclcltesws fot suhioutine nesting; a hinary and clrc- allc~nhgrhr 400.4 to pol1 extt~rnslclc-viccas LAICYgcric~-~~~ioii imal arithmetic unit; instruction rcgictcr. dccoder, ;ind con- procc'ssor5 rl$ilced Test \\.it11 a much more con\.enient trol logic; timing logic; bus control; and misccllmcous inrcrrupt facility. conrnd. A~llic~ughsr.\,r.r.rl prior ~~otii~~utcrdrc1~itec.ttrre.i inspirccl In addition to the pins required for the +bit tristatc data the iOOr (l'Dl'-8. IHJl 1620, ancl so on), it is unique in bus, tho-phase clock, po\\.er,aid ground, the 4)O i has a inany aspects. Its main value resides in its siinplicity mcl SYN(: timing output pin ancl fi\v control lines tor addrccs- econoiii!' ol "m~ssentialingrctlients, giwm tl~!in)- ing the tWl and tOOL chips ((;\I K0.V and CM MM0 5; itcd CapabiliticS of 1CI70 scmiconductor technology. design The concept was still incomplete, however, and In September 1969, Stanley Mazor joined Intel from required additional features to function satisfactorily in Fairchild, where he had been since 1964, and where he had Busicom's products Certain calculator functions, such as helped design the Symbol computer. After Mazor arrived, decimal adjust and keyboard processing, required too many progress began to accelerate.