2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA) Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension Industrial Product Chen Chen, Xiaoyan Xiang, Chang Liu, Yunhai Shang, Ren Guo, Dongqi Liu, Yimin Lu, Ziyi Hao, Jiahui Luo, Zhijian Chen, Chunqiang Li, Yu Pu, Jianyi Meng*, Xiaolang Yan, Yuan Xie and Xiaoning Qi The T-Head Division, Alibaba Cloud Email:
[email protected] Abstract—The open source RISC-V ISA has been quickly domain-specific workload (e.g., machine learning accelerators, gaining momentum. This paper presents Xuantie-910, an industry network processing, security enclave, storage controllers and leading 64-bit high performance embedded RISC-V processor supercomputing), thereby boosting processing efficiency and from Alibaba T-Head division. It is fully based on the RV64GCV instruction set and it features custom extensions to arithmetic reducing design cost; iii) RISC-V is becoming a mainline plat- operation, bit manipulation, load and store, TLB and cache form in Unix/Linux OS. The toolchains like GNU/GCC/GDB operations. It also implements the 0.7.1 stable release of RISC- and LLVM are getting mature, further improving software V vector extension specification for high efficiency vector pro- experience and driving down software development cost. cessing. Xuantie-910 supports multi-core multi-cluster SMP with cache coherence. Each cluster contains 1 to 4 core(s) capable of Admittedly, compared with the X86, ARM, MIPS [16]– booting the Linux operating system. Each single core utilizes the [18], PowerPC, SPARC [11], [20], [21], [23], [30], openRISC state-of-the-art 12-stage deep pipeline, out-of-order, multi-issue [14], [24], [26] and other ISAs under the hood of popular superscalar architecture, achieving a maximum clock frequency GPUs and DSPs, RISC-V is still in its infancy.