94 Chapter 5. LOGIC AND FAULT SIMULATION
pMOS Va transistors DD c b a C to gate a c terminals of a b c C transistors b c 0 0 1 C b nMOS 0 1 1 transistors 1 0 1 11 0 Ground
(a) Static CMOS NAND structure. (b) NAND logic function.
Figure CMOS implementation of a NAND logic gate