HC17.15.10.S1T3 Super Companion Chip with Audio Visual Interface For

SuperSuper CompanionCompanion ChipChip withwith AudioAudio VisualVisual InterfaceInterface forfor CellCell ProcessorProcessor

Takayuki Mihara 1, Hiroki Muroga 1, Hiroshi Doi 1, Tadashi Yabuta 1, Yoichiro Iwagami 1, Kenichi Ishii 1, Naohiko Okamoto 1, Kazuki Iwata 1, Yoshimasa Aoyama 1, Takeshi Takamiya 1, Naoki Sugawa 2

1. Toshiba Corporation 2. Toshiba Microelectronics Corporation

Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

To provide software based digital consumer solutionsolution forfor CellCell processorprocessor such as Digital TV, Audio Visual Server, etc.

To establish GHz high bandwidth connection betweenbetween CellCell andand ultraultra highhigh speed peripherals on Super Companion Chip (SCC).

SDTV Satellite ･･･ PC Monitor

Terrestrial HDTV ･･･ -Multi Recording -Time Shift Play CATV -Multi Screen Streaming DTV ･･･ Key Feature： Home Internet Real Time Audio Network Web, Streaming Video Processing

(PPE) LS LS LS LS LS LS LS LS Synergistic Processor Element (SPE) EIB Dual XDR DRAM channels Flexible I/O Interface L2 L1 PXU MIC BEI

Element Interconnect Bus PPE XIO FlexIO

Dual XDRTM SCC

Resource Management Capability  Reserve Memory & I/O Bandwidth for up to four tasks. Isolation Facility  Each SPE is isolatable from outside for flexible secure programming. Multi OS Support  Run multiple OSs simultaneously. e.g. Linux + Real-time OS

Jun. 25, 2005 Copyright c 2005 Toshiba Corporation. All right reserved. 6 FeaturesFeatures ofof SCCSCC For Real Time Processing SCC internal bus has the bandwidth reservation capability for the each resources. -TDM arbitration For Tight Security The HW random number generator and several kinds of HW Encryption/Decryption functions are implemented. For Multi OS Support Every bus master module have the address space restriction mechanism. To prevent the IO resource conflict between OSs.

Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

For versatile A/V system -DDR2 DRAM I/F for Video RAM. -Video output / Audio output. -Video input / Audio input. -Digital AV equipment connection I/F (IEEE1394). -Digital tuner I/F (TS I/F).

For computer system -Standard PC I/F (PCI-Express,PCI,USB2.0). -High-speed Network I/F (Giga Bit Ethernet). -Storage device I/F (Parallel ATA).

CellO Processor I

XDR-DRAM X 25.6GB/s FlexIO

5GB/s 5GB/s FlexIO DDRI2 DRAM 2.6GB/s SCC V-DAC/HDMI HD Output 555MB/s D-Tuner 5MB/s V-DAC SD Output (D4, S2,CVBS) D-Tuner 27MB/s A/V A-Tuner A-DAC 2ch ♪♪ ♪ NTSC S/PDIF A/D A-Tuner Modem TEL S,CVBS+Audio 50MB/s PC IEEE1394

CellO Processor I

XDR-DRAM X 25.6GB/s FlexIO

5GB/s 5GB/s

FlexIO DDRI2 DRAM 2.6GB/s SCC AV

PCI express 2.0GB/s Giga Bit Ether 1Port 250MB/s x4 Link USB2.0 PCI 4 Ports 60MB/s PC 133MB/s 4 slot ATA 133 AC’97 2 Ports 133MB/s 133MB/s Audio/Codec

Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

Jun. 25, 2005 Copyright c 2005 Toshiba Corporation. All right reserved. 12 From BS Digital Audio/VisualAudio/Visual ProcessingProcessing StepsSteps Tuner < Digital Broadcasting > TS Input 1. Multi2 Descramble Demux

Audio Audio Dec DAC Output

Video Dec I/P Scaling α Correction NTSC En Video or HDMI Output

VCR Scaling α Correction NTSC En Output Character 6.7. 5. 4. Descramble

2. 3. Scramble HDD

Jun. 25, 2005 Copyright c 2005 Toshiba Corporation. All right reserved. 13 Audio/VisualAudio/Visual datadata flowflow Taking digital broadcasting and Outputting A/V data with time shift function. 1. 2. 3. TS I/F FlexIO Cell XDR FlexIO

4. 5. ATA I/F FlexIO Cell XDR FlexIO

6. 7. DMAC DDR2 Video Output 6. Audio Output :SCC from/to Cell :Data Transfer in SCC

Jun. 25, 2005 Copyright c 2005 Toshiba Corporation. All right reserved. 14 DataData ProcessingProcessing FlowFlow 1. Transferring the data from TS I/F to Cell Processor. 2. Processing the data with XDR. 3. Recording the data on HDD. 4. Reading the data on HDD. 5. Processing the data with XDR. 6. Transferring the data from XDR to DDR2, Audio I/F. 7. Transferring the data fromDDR2 to Video out I/F.

Digital Tuner

Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

Jun. 25, 2005 Copyright c 2005 Toshiba Corporation. All right reserved. 16 InternalInternal BusBus HierarchyHierarchy Cell Processor 5.0GB/s 5.0GB/s MBUS DMAC FlexIO 2.66GB/s 2.66GB/s Video DDR2 Out TBUS Real Time Best Effort PCI- PCI Processing express Processing

HBUS SBUS

Enc/ IEEE Video Audio Audio USB ATA GbE TS In Dec GBUSC 1394 In In Out GBUS

EBUS DMA SIO PIO I2C Timer

Jun. 25, 2005 Copyright c 2005 Toshiba Corporation. All right reserved. 17 KeyKey ArchitectureArchitecture (1/2)(1/2) Internal Bus Architecture  Quality of Service (QoS) -Bandwidth allocation by bus arbitration mechanism.(with priority in every cycle. TDM .)  Hierarchical Architecture -Dividing the bus according to the required features. Real time bus and Best effort. DDR2 memory interface  Dedicated DMA controller -For streaming data.

Jun. 25, 2005 Copyright c 2005 Toshiba Corporation. All right reserved. 18 KeyKey ArchitectureArchitecture (2/2)(2/2) Other Features  Virtual Channel Mechanism To avoid blocking for data flow. Stuck or Long Latency Legacy I/O traffic VC0

VC1 Video Data traffic

 Multiple thread mechanism Multi/Single threads are alternative.  Pipelined data processing  Data ordering mechanism

•Virtual Channel/Thread correspond to Cell functionality Master Path : 8 Slave Path : 4 •Priority Control

•High bandwidth XDR DDR2 DDR2 XDR •4 Virtual Channel(thread) •Multi/Single threads

The each maximum bus bandwidth(2.66GByte/s) is sufficient for the every required module bandwidth.

2.66GByte/S

The bandwidth allocation mechanism can satisfy the BUS requirement from each module/bus bridge.

Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

Process 90nm CMOS Process 7 Layer Cu Frequency -333MHz Package PBGA[FC],1385pin, 40mm□,1mm pitch Chip Size 12.71mm x 12.71mm VDD Core: 1.2V I/O: Multiple voltages for various peripherals

Background What is Super Companion Chip(SCC)? Processing Flow SCC Architecture Technology and Chip Implementation Conclusion

Super Companion Chip for “Cell” processor system has been successfully developed. Both rich audio visual features supporting HD and PC I/O features are integrated onon thethe chip.chip. Simultaneous 48 MPEG-2 SD stream decoding has been demonstrated by utilizing SCC’s high bandwidth bus with QoS capability.