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The Datasheetarchive STP2011PGA-50 July 1997 MSI DATA SHEET MBus-to-SBus Interface DESCRIPTION The STP2011 MBus-to-SBus Interface (MSI) provides an interface between the MBus and the SBus and controls access to the I/O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem and the I/O Subsystem. The STP2011 sits between MBus and SBus and serves the following purposes: 1. MBus Arbitration The MBus arbiter supports up to five masters including the MSI itself. A parallel arbitration scheme is used by the arbiter to reduce arbitration overhead. The arbiter assumes no real-time requirement from the master devices. 2. MBus Monitoring The STP2011 monitors MBus operation. If the bus operation takes more than 200 microseconds to complete, it assumes the bus master is trying to access a non-existent device. It forces a termination and signals an error condition to the bus master. * 3. SBus Arbitration The SCSI Interface and SBus slots are SBus Master devices. A round-robin scheme is used to arbitrate for ownership of the SBus and no real-time requirement is assumed. 4. SBus Monitoring The STP2011 monitors the SBus during an access to SBus devices. If the access does not get response within 256 SBus clock cycles, the access is forced to terminate and an error is returned. Devices that have long access latency should issue an SBus retry acknowledge to allow later reconnection. 1 MSI STP2011PGA-50 MBus-to-SBus Interface BLOCK, LOGIC, AND TYPICAL APPLICATION DIAGRAMS MBus Interface SBus Interface • MBus Control Protocol • SBus Control Protocol MBus Interface SBus Interface • MBus Arbiter • SBus Arbiter • SBus Monitor Data Buffer JTAG Interface IOMMU • Internal Scan • 16 Full Assoc. Entries Test Signals Misc. Signals • Boundary Scan • LRU Replacement • TLB Flush Figure 1. STP2011 Block Diagram 64 MAD[63:0] DBRI_BR MAS DBRI_BG MBB ESC_BR e c a MERR ESC_BG f r e MRDY t 32 n I * MRTY SB_D[31:0] s u MBR[3:0] 28 B M MBG[3:0] SB_A[27:0] MCLK SB_SIZ[2:0] e MSI_INT SB_RD c a f SB_AS r STP2011 e t n SB_ACK[2:0 I ] s u B 2 SB_LERR S - k SB_BR[5:0] c JTAGDI o l JTAGTMS SB_BG[5:0] C & SB_SEL[3:0 JTAGCLK G TESTEN ] A T SB_CLK J Logical Connections SEL_ESC SEL_SEC Figure 2. STP2011 Logical Connections 2 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50 SBus Device STP2011 MBus/SBus s u Interface B S MBus SBus Module Device s u B I/O Subsystem M Memory Subsystem MBus Module Figure 3. STP2011* Typical Application July 1997 3 MSI STP2011PGA-50 MBus-to-SBus Interface SIGNAL DESCRIPTIONS MBus Interface Signal Type Description MAD[63:0] I/O MBus Address, Data and Control Bus. During the address phase, MAD[35:0] contains the physical address PA[35:0]. The remaining signals MAD[63:36] on the bus contain the transaction-specific information which will be described in the MBus specification. MAS I/O MBus Address Strobe. This signal is asserted by the bus master during the very first cycle of the bus transaction. MBB I/O MBus Busy. This signal is asserted as an output during the entire transaction. MERR I/O MBus Error transaction status bit. This bit is one of the three bits used to encode the transaction status. MRDY I/O MBus Data Ready. This bit is one of the three bits used to encode the transaction status. MRTY I/O MBus Retry. This bit is one fo the three bits used to encode the transaction status. MBR[3:0] Input MBus Bus Request signal. This signal is asserted by an MBus master to acquire bus ownership. MBG[3:0] Output MBus Bus Grant signal. The MSBI determines the next owner of the MBus by the assertion of this signal. MCLK Input MBus Clock. MSI_INT Output Interrupt caused by page fault or write error. * JTAG Interface Signal Type Description JTAGDI Input JTAG Data Input. JTAGTMS Input JTAG Enable. JTAGCLK Input JTAG Clock Input. JTAGDO Output JTAG Data Output. TESTEN Input For testing pads and JTAG three-state access, low during normal operation. 4 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50 SBus Interface Signal Type Description SB_D[31:0] I/O SBus Data, also some transfer information on SB_D[31:23] SB_PA[27:0] I/O SBus Physical Address, also SB_D[59:32] SB_SIZ[2:0] I/O SBus Transfer Size, also SB_D[62:60] SB_RD I/O SBus Transfer Directon, also SB_D[63] SB_AS Output SBus Address Strobe SB_ACK[2:0] I/O SBus Transfer Acknowledgment SB_LERR Input SBus Late Data Error SB_BR[5:0] Input SBus Request SB_BG[5:0] Output SBus Grant SB_SEL[3:0] Output SBus Slave Select, Expansion SBus ports SB_CLK Input SBus Clock SEL_SEC Output SBus Slave Select for STP2014 (SEC) SEL_ESC Output SBus Slave Select for SCSI/Ethernet (SEC) DBRI_BR Input DBRI Bus Request DBRI_BG Output DBRI Bus Grant ESC_BR Input SCSI/Ethernet (ESC) DVMA Request ESC_BG Output SCSI/Ethernet (ESC) DVMA Grant* SYS_RESET Input System Reset July 1997 5 MSI STP2011PGA-50 MBus-to-SBus Interface ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings [1] Symbol Parameter Rating2 Units VCC DC supply voltage +7 V VIN Input voltage range GND £ VIN £ VCC V IIN DC input current ±10 mA TS Storage temperature –40 to +125 °°C 1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages are defined with respect to ground. Functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. Referenced to GND. Recommended Operating Conditions Symbol Parameter Min Typ Max Units VCC DC supply voltage 4.75 5.0 5.25 V TA Ambient temperature 0 – 70 °°°C * 6 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50 DC Characteristics Symbol Parameter Conditions1 Min Typ Max Units VIH Input high voltage 4.75 < VCC < 5.25 2.0 – – V VIL Input low voltage 4.75 < VCC < 5.25 – – 0.8 V VOH Output high voltage IOH = –4.0, –8.0 mA 2.4 4.5 – V VOL Output low voltage IOL = 4.0, 8.0 mA – 0.2 0.4 V IIL Input leakage current VCC = Max, VIN = VCC or –10 ±1 10 µA GND IIPU Input pull-up current VCC = Max, VIN = GND or –175 – –2 µA 3.5 V 3-state output VCC = Max, VOUT = GND or IOZ –10 ±1 10 µA leakage current VCC 3-state output current I V = GND or 3.5 V –175 – –2 µA OZU with pull-up OUT P-channel output IOSP4 short circuit current VCC = Max, VOUT = GND –140 –70 –25 mA (4 mA output buffers)2 P-channel output IOSP8 short circuit current VCC = Max, VOUT = GND –280 –140 –50 mA (8 mA output buffers)2 N-channel output * IOSN4 short circuit current VCC = Max, VOUT = VCC 30 75 140 mA (4 mA output buffers)2 N-channel output IOSN8 short circuit current VCC = Max, VOUT = VCC 60 150 280 mA (8 mA output buffers)2 Quiescent supply I V = V or GND – – 2 mA DD current IN CC Dynamic supply I V = Max, f = 40 MHz – – 500 mA CC current CC 1. Specified at VCC equals 5 V ± 5% at ambient temperature over the specified range. 2. Not more than one output may be shorted at a time for a maximum duration of one second. July 1997 7 MSI STP2011PGA-50 MBus-to-SBus Interface AC Characteristics: MBus Output Signal Timing 40 MHz 50 MHz With System Load 100 pF Load Symbol Signal Name Reference Min Max Min Max Units Tdo MBG[3:0] MCLK+ 4.0 12.6 – 12.6 ns Tdo MAD[63:00] MCLK+ 3.4 18.4 – 14.0 ns Tdo MRDY MCLK+ 3.3 16.9 – 15.0 ns Tdo MERR MCLK+ 3.3 16.9 – 15.0 ns Tdo MRTY MCLK+ 3.3 16.9 – 15.0 ns Tdo MAS MCLK+ 3.3 17.3 – 15.0 ns Tdo MBB MCLK+ 3.3 17.3 – 15.0 ns AC Characteristics: SBus Output Signal Timing 40 MHz 50 MHz Symbol Parameter Min Max Min Max Units Tsi Setup time to clock 15 15 ns * Tdo Output delay from clock 30 22.5 ns Toh Output hold from clock 2.5 2.5 ns Thi Input hold time from clock 1.5 1.5 ns 8 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50 AC Characteristics: MBus Input Signal Timing 40 MHz 50 MHz With System Load With System Load Parameter Signal Name Reference Min Max Min Max Units Tsi MAD[63:00] MCLK+ 3.2 – 3.2 – ns Thi MAD[63:00] MCLK+ -0.3 – 0 – ns Tsi MAS MCLK+ 3.6 – 6.1 – ns Thi MAS MCLK+ -0.3 – 0.4 – ns Tsi MRDY MCLK+ 6.1 – 6.1 – ns Thi MRDY MCLK+ -0.1 – 0.4 – ns Tsi MRTY MCLK+ 5.6 – 6.1 – ns Thi MRTY MCLK+ -0.2 – 0.4 – ns Tsi MERR MCLK+ 5.6 – 6.1 – ns Thi MERR MCLK+ -0.1 – 0.4 – ns Tsi MBB MCLK+ 5.1 – 6.1 – ns Thi MBB MCLK+ 0.4 – 0.4 – ns Tsi MBR[3:0] MCLK+ 7.0 – 5.0 – ns Thi MBR[3:0] MCLK+ 0.2 – 0.2 – ns Tsi SYS_RESET MCLK+ NA * – NA – ns Thi SYS_RESET MCLK+ NA – NA – ns July 1997 9 MSI STP2011PGA-50 MBus-to-SBus Interface TIMING DIAGRAMS SCLK MCLK MAS MAD[63:00] M.A.
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