STP2011PGA-50
July 1997 MSI
DATA SHEET MBus-to-SBus Interface
DESCRIPTION
The STP2011 MBus-to-SBus Interface (MSI) provides an interface between the MBus and the SBus and controls access to the I/O subsystem. The MSI consists of two main functional blocks: the Memory Subsystem and the I/O Subsystem. The STP2011 sits between MBus and SBus and serves the following purposes: 1. MBus Arbitration The MBus arbiter supports up to five masters including the MSI itself. A parallel arbitration scheme is used by the arbiter to reduce arbitration overhead. The arbiter assumes no real-time requirement from the master devices. 2. MBus Monitoring The STP2011 monitors MBus operation. If the bus operation takes more than 200 microseconds to complete, it assumes the bus master is trying to access a non-existent device. It forces a termination and signals an error condition to the bus master. * 3. SBus Arbitration The SCSI Interface and SBus slots are SBus Master devices. A round-robin scheme is used to arbitrate for ownership of the SBus and no real-time requirement is assumed. 4. SBus Monitoring The STP2011 monitors the SBus during an access to SBus devices. If the access does not get response within 256 SBus clock cycles, the access is forced to terminate and an error is returned. Devices that have long access latency should issue an SBus retry acknowledge to allow later reconnection.
1 MSI STP2011PGA-50 MBus-to-SBus Interface
BLOCK, LOGIC, AND TYPICAL APPLICATION DIAGRAMS
MBus Interface SBus Interface • MBus Control Protocol • SBus Control Protocol MBus Interface SBus Interface • MBus Arbiter • SBus Arbiter • SBus Monitor
Data Buffer
JTAG Interface IOMMU • Internal Scan • 16 Full Assoc. Entries Test Signals Misc. Signals • Boundary Scan • LRU Replacement • TLB Flush
Figure 1. STP2011 Block Diagram
64 MAD[63:0] DBRI_BR MAS DBRI_BG MBB ESC_BR e c
a MERR ESC_BG f r
e MRDY t 32 n
I * MRTY SB_D[31:0] s u MBR[3:0] 28 B
M MBG[3:0] SB_A[27:0] MCLK SB_SIZ[2:0] e
MSI_INT SB_RD c a f SB_AS r STP2011 e t n
SB_ACK[2:0 I
] s u B
2 SB_LERR S -
k SB_BR[5:0] c JTAGDI o l JTAGTMS SB_BG[5:0] C
& SB_SEL[3:0
JTAGCLK
G TESTEN ] A
T SB_CLK J Logical Connections
SEL_ESC SEL_SEC
Figure 2. STP2011 Logical Connections
2 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50
SBus Device
STP2011
MBus/SBus s u
Interface B S
MBus SBus Module Device s u
B I/O Subsystem M
Memory Subsystem
MBus Module
Figure 3. STP2011* Typical Application
July 1997 3 MSI STP2011PGA-50 MBus-to-SBus Interface
SIGNAL DESCRIPTIONS
MBus Interface
Signal Type Description MAD[63:0] I/O MBus Address, Data and Control Bus. During the address phase, MAD[35:0] contains the physical address PA[35:0]. The remaining signals MAD[63:36] on the bus contain the transaction-specific information which will be described in the MBus specification. MAS I/O MBus Address Strobe. This signal is asserted by the bus master during the very first cycle of the bus transaction. MBB I/O MBus Busy. This signal is asserted as an output during the entire transaction. MERR I/O MBus Error transaction status bit. This bit is one of the three bits used to encode the transaction status. MRDY I/O MBus Data Ready. This bit is one of the three bits used to encode the transaction status. MRTY I/O MBus Retry. This bit is one fo the three bits used to encode the transaction status. MBR[3:0] Input MBus Bus Request signal. This signal is asserted by an MBus master to acquire bus ownership. MBG[3:0] Output MBus Bus Grant signal. The MSBI determines the next owner of the MBus by the assertion of this signal. MCLK Input MBus Clock. MSI_INT Output Interrupt caused by page fault or write error. *
JTAG Interface
Signal Type Description JTAGDI Input JTAG Data Input. JTAGTMS Input JTAG Enable. JTAGCLK Input JTAG Clock Input. JTAGDO Output JTAG Data Output. TESTEN Input For testing pads and JTAG three-state access, low during normal operation.
4 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50
SBus Interface
Signal Type Description SB_D[31:0] I/O SBus Data, also some transfer information on SB_D[31:23] SB_PA[27:0] I/O SBus Physical Address, also SB_D[59:32] SB_SIZ[2:0] I/O SBus Transfer Size, also SB_D[62:60] SB_RD I/O SBus Transfer Directon, also SB_D[63] SB_AS Output SBus Address Strobe SB_ACK[2:0] I/O SBus Transfer Acknowledgment SB_LERR Input SBus Late Data Error SB_BR[5:0] Input SBus Request SB_BG[5:0] Output SBus Grant SB_SEL[3:0] Output SBus Slave Select, Expansion SBus ports SB_CLK Input SBus Clock SEL_SEC Output SBus Slave Select for STP2014 (SEC) SEL_ESC Output SBus Slave Select for SCSI/Ethernet (SEC) DBRI_BR Input DBRI Bus Request DBRI_BG Output DBRI Bus Grant ESC_BR Input SCSI/Ethernet (ESC) DVMA Request
ESC_BG Output SCSI/Ethernet (ESC) DVMA Grant* SYS_RESET Input System Reset
July 1997 5 MSI STP2011PGA-50 MBus-to-SBus Interface
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings [1]
Symbol Parameter Rating2 Units
VCC DC supply voltage +7 V
VIN Input voltage range GND £ VIN £ VCC V
IIN DC input current ±10 mA
TS Storage temperature –40 to +125 °°C
1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages are defined with respect to ground. Functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. Referenced to GND.
Recommended Operating Conditions
Symbol Parameter Min Typ Max Units
VCC DC supply voltage 4.75 5.0 5.25 V
TA Ambient temperature 0 – 70 °°°C
*
6 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50
DC Characteristics
Symbol Parameter Conditions1 Min Typ Max Units
VIH Input high voltage 4.75 < VCC < 5.25 2.0 – – V
VIL Input low voltage 4.75 < VCC < 5.25 – – 0.8 V
VOH Output high voltage IOH = –4.0, –8.0 mA 2.4 4.5 – V
VOL Output low voltage IOL = 4.0, 8.0 mA – 0.2 0.4 V
IIL Input leakage current VCC = Max, VIN = VCC or –10 ±1 10 µA GND
IIPU Input pull-up current VCC = Max, VIN = GND or –175 – –2 µA 3.5 V
3-state output VCC = Max, VOUT = GND or IOZ –10 ±1 10 µA leakage current VCC 3-state output current I V = GND or 3.5 V –175 – –2 µA OZU with pull-up OUT P-channel output IOSP4 short circuit current VCC = Max, VOUT = GND –140 –70 –25 mA (4 mA output buffers)2 P-channel output IOSP8 short circuit current VCC = Max, VOUT = GND –280 –140 –50 mA (8 mA output buffers)2 N-channel output * IOSN4 short circuit current VCC = Max, VOUT = VCC 30 75 140 mA (4 mA output buffers)2 N-channel output IOSN8 short circuit current VCC = Max, VOUT = VCC 60 150 280 mA (8 mA output buffers)2 Quiescent supply I V = V or GND – – 2 mA DD current IN CC Dynamic supply I V = Max, f = 40 MHz – – 500 mA CC current CC
1. Specified at VCC equals 5 V ± 5% at ambient temperature over the specified range. 2. Not more than one output may be shorted at a time for a maximum duration of one second.
July 1997 7 MSI STP2011PGA-50 MBus-to-SBus Interface
AC Characteristics: MBus Output Signal Timing
40 MHz 50 MHz With System Load 100 pF Load Symbol Signal Name Reference Min Max Min Max Units
Tdo MBG[3:0] MCLK+ 4.0 12.6 – 12.6 ns
Tdo MAD[63:00] MCLK+ 3.4 18.4 – 14.0 ns
Tdo MRDY MCLK+ 3.3 16.9 – 15.0 ns
Tdo MERR MCLK+ 3.3 16.9 – 15.0 ns
Tdo MRTY MCLK+ 3.3 16.9 – 15.0 ns
Tdo MAS MCLK+ 3.3 17.3 – 15.0 ns
Tdo MBB MCLK+ 3.3 17.3 – 15.0 ns
AC Characteristics: SBus Output Signal Timing
40 MHz 50 MHz Symbol Parameter Min Max Min Max Units
Tsi Setup time to clock 15 15 ns * Tdo Output delay from clock 30 22.5 ns
Toh Output hold from clock 2.5 2.5 ns
Thi Input hold time from clock 1.5 1.5 ns
8 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50
AC Characteristics: MBus Input Signal Timing
40 MHz 50 MHz With System Load With System Load Parameter Signal Name Reference Min Max Min Max Units
Tsi MAD[63:00] MCLK+ 3.2 – 3.2 – ns
Thi MAD[63:00] MCLK+ -0.3 – 0 – ns
Tsi MAS MCLK+ 3.6 – 6.1 – ns
Thi MAS MCLK+ -0.3 – 0.4 – ns
Tsi MRDY MCLK+ 6.1 – 6.1 – ns
Thi MRDY MCLK+ -0.1 – 0.4 – ns
Tsi MRTY MCLK+ 5.6 – 6.1 – ns
Thi MRTY MCLK+ -0.2 – 0.4 – ns
Tsi MERR MCLK+ 5.6 – 6.1 – ns
Thi MERR MCLK+ -0.1 – 0.4 – ns
Tsi MBB MCLK+ 5.1 – 6.1 – ns
Thi MBB MCLK+ 0.4 – 0.4 – ns
Tsi MBR[3:0] MCLK+ 7.0 – 5.0 – ns
Thi MBR[3:0] MCLK+ 0.2 – 0.2 – ns
Tsi SYS_RESET MCLK+ NA * – NA – ns
Thi SYS_RESET MCLK+ NA – NA – ns
July 1997 9 MSI STP2011PGA-50 MBus-to-SBus Interface
TIMING DIAGRAMS
SCLK
MCLK
MAS
MAD[63:00] M.A. Data
MRDY
MBB
SB_SEL
SB_AS
SB_PA[27:00] Address
SB_D[31:00] Data
SB_SIZ[2:0] * SB_RD
SB_ACK[2:0] Rdy
Figure 4. MBus Single Write (1, 2, 4 Bytes) to SBus Device With No Error
10 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50
SCLK
MCLK
MAS
MAD[63:00] M.A. D0 D1 D2 D3
MRDY
MBB
SB_SEL
SB_AS
SB_PA[27:00] Address
SB_D[31:00] Word 0 Word 1 ...... Word 7
SB_SIZ[2:0]
SB_RD
SB_ACK[2:0] *Rdy Rdy Rdy
Undetermined amount of delay
Figure 5. MBus Burst Write (32 Bytes) to SBus Device With No Error – Burst Enabled
July 1997 11 MSI STP2011PGA-50 MBus-to-SBus Interface
SCLK
MCLK
MAS
MAD[63:00] M.A. Data
MRDY
MBB
SB_SEL
SB_AS
SB_PA[27:00] Address
SB_D[31:00] Data
SB_SIZ[2:0]
SB_RD
SB_ACK[2:0] Rdy *
Figure 6. MBus Single Read (1, 2, 4 Bytes) From SBus Device With No Error
12 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50
SCLK
MCLK
MAS
MAD[63:00] M.A. D.0 D.1
MRDY
MBB
SB_SEL
SB_AS
SB_PA[27:00] Address
SB_D[31:00] Word 0 Word 1 Word 2 Word 3
SB_SIZ[2:0]
SB_RD
SB_ACK[2:0] Rdy Rdy* Rdy Rdy
Figure 7. MBus Burst Read (16 Bytes) From SBus Device With No Error – Burst Enabled
July 1997 13 MSI STP2011PGA-50 MBus-to-SBus Interface
PACKAGE INFORMATION
279-Pin Plastic Pin Grid Array (PPGA) Pin Assignments
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A2 VCC D4 MAD43 H5 MAD56 N19 GND U5 SB_D29 A3 GND D5 MAD42 H15 MAD12 P1 VCC U6 SB_A1 A4 VCC D6 MAD41 H16 MAD7 P2 SB_D10 U7 SB_A4 A5 GND D7 MAD32 H17 MAD5 P3 SB_D11 U8 SB_A7
A6 VCC D8 MRTY H18 MAD4 P4 SB_D18 U9 SB_A12 A7 GND D9 MERR H19 GND P5 SB_D20 U10 SB_A15
A8 VCC D11 MRDY J1 GND P15 SB_BG1 U11 SB_A18 A9 GND D12 MAD30 J2 MAD61 P16 SB_BG2 U12 SB_A21
A10 VCC D13 MAD27 J3 MAD63 P17 SYS_RESET U13 SB_A24 A11 GND D14 MAD21 J4 MAD60 P18 MSI_INT U14 SB_A27
A12 GND D16 MAD20 J5 MAD62 P19 VCC U18 SB_BR2 A13 VCC D18 MAD15 J15 MAD3 R1 GND U19 GND A14 GND D19 VCC J16 MAD1 R2 SB_D13 V1 VCC A15 GND E1 GND J17 MAD2 R3 SB_D16 V2 SB_D21
A16 VCC E2 MAD50 J18 MAD0 R4 SB_D22 V3 SB_D27 A17 GND E3 MAD48 J19 GND R6 SB_D24 V4 SB_D28
A18 GND E5 JTAGTMS K3 VCC R7 SB_D30 V5 SB_D31 A19 VCC E7 MAD37 K4 MCLK R8 SB_A5 V6 SB_A2 B1 GND E8 MAD35 K5 GND R9 SB_A11 V7 SB_A6
B2 VCC E9 MAS K15 GND R10 SB_CLK V8 SB_A8 B3 MAD40 E11 MBB K16 VCC R11 SB_A19 V9 SB_A10 B4 MAD38 E12 MBR2 K19 VCC R12 SB_SIZ0 V10 SB_A13 B5 MAD36 E13 MAD25 L1 GND * R13 SB_SIZ2 V11 SB_A16 B6 MAD33 E15 JTAGDO L2 SB_D0 R14 SB_ACK1 V12 SB_A20 B8 MBR1 E16 MAD19 L3 SB_D2 R15 SB_BG0 V13 SB_A22 B12 MBR0 E17 MAD16 L4 SB_D1 R16 SB_BR0 V14 SB_A26 B13 MAD31 E18 MAD13 L5 SB_D3 R17 ESC_BR V15 SB_SIZ1 B14 MAD29 E19 GND L15 SEL_ESC R18 DBRI_BR V16 SB_AS
B15 MAD26 F1 GND L16 SB_SEL2 R19 GND V19 VCC B16 MAD23 F2 MAD53 L17 SEL_SEC T1 VCC W1 VCC B17 MAD22 F3 MAD52 L18 SB_SEL3 T2 SB_D15 W2 GND
B19 VCC F4 MAD45 L19 GND T3 SB_D19 W3 GND C1 VCC F16 MAD18 M1 VCC T4 SB_D23 W4 VCC C2 MAD46 F17 MAD11 M2 SB_D4 T6 SB_D26 W5 GND
C4 JTAGDI F18 MAD10 M3 SB_D5 T7 SB_A0 W6 VCC C5 MAD39 F19 GND M4 SB_D7 T8 SB_A3 W7 GND
C6 MAD34 G1 VCC M5 SB_D12 T9 SB_A9 W8 VCC C7 MGB3 G2 MAD57 M15 SB_RD T10 SB_A14 W9 GND
C8 MBG1 G3 MAD55 M16 DBRI_BG T11 SB_A17 W10 VCC C9 MBR3 G4 MAD51 M17 SB_SEL0 T12 SB_A23 W11 GND C12 MBG0 G5 MAD49 M18 SB_SEL1 T13 SB_A25 W12 GND
C13 MBG2 G15 MAD14 M19 VCC T14 SB_ACK0 W13 VCC C14 MAD28 G16 MAD9 N1 GND T15 SB_ACK2 W14 GND C15 MAD24 G17 MAD8 N2 SB_D6 T17 SB_BR1 W15 GND
C17 JTAGCLK G18 MAD6 N3 SB_D8 T18 SB_BR3 W16 VCC C18 MAD17 G19 VCC N4 SB_D9 T19 VCC W17 GND C19 GND H1 GND N5 SB_D14 U1 GND W18 GND
D1 GND H2 MAD59 N15 SB_BG3 U2 SB_D17 W19 VCC D2 MAD47 H3 MAD58 N16 ESC_BG U3 TESTEN D3 MAD44 H4 MAD54 N17 SB_LERR U4 SB_D25
14 July 1997 MSI MBus-to-SBus Interface STP2011PGA-50
279-Pin PPGA Package Dimensions
Top View Side View D N J D2 Q1 (Note 4) H Detail A
Dimension Inches Dimension Inches Min 0.067 E1 Max 0.910 A Nom 0.079 E2 Max 0.870 M1 Max 0.091 E3 Ref 1.800 Index A1 Max 0.131 Min 0.050 Mark E2 M E Min 0.028 G Nom 0.065 A2 Nom 0.031 Max 0.080 e Max 0.049 H Max 0.100 Min 0.016 I Max 0.140 b Nom 0.018 J Ref 0.057 Max 0.020 Min 0.189 I Min 0.042 L Nom 0.197 Capacitor Pad N1 A2 (Note 5) b1 Nom 0.050 Max 0.205 (15 Places) A Max 0.058 Min 0.042 Bottom View A1 b2 Ref 0.008 L1 Nom 0.050 D3 * L Min 1.956 Max 0.058 D1 – C – G D Nom 1.960 M Ref 1.80 Max 1.964 M1 Ref 0.80 W V D1 Max 0.910 N Ref 1.70 U D2 Max 0.870 N1 Ref 0.85 T R D3 Ref 1.800 Q1 Min 0.017 P N e Typ 0.100 M Min 1.956 L K E1 E3 E Nom 1.960 J Max 1.964 H G Detail A Section A–A F E A Ø b1 D C B A A b2 Ref 0.030 M C A M B M 1 2 3 4 5 67 8 9 10111213141516171819 Standoff Pin b L1 0.010 M C (4 Places)
Note: 1. Drawing is not to scale. 2. Size of array is 19 x 19. 3. Total number of pins is 279. 4. Envelope for maximum lid. 5. Envelope for integral heat slug. MD92.NZ
July 1997 15 MSI STP2011PGA-50 MBus-to-SBus Interface
ORDERING INFORMATION
Part Number Description STP2011PGA 279-Pin Pin Grid Array (PGA)
Document Part Number: STP2011
*
16 July 1997