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Emcissonfrom L0 \ 001Mm: R United States Patent [19] [11] Patent Number: 4,821,183 Hauris [45] Date of Patent: Apr. 11, 1989 [54] A MICROSEQUENCER CIRCUIT WITH 4,439,827 3/1984 Wilkes ............................... .. 364/21!) PLURAL MICROPROGROM INSTRUCTION 4,446,518 5/1984 Casamatta 364/200 COUNTERS 4,551,798 11/1985 Horvath ............................ .. 364/200 [75] Inventor: Jon F. Hauris, Manassas, Va. FOREIGN PATENT DOCUMENTS 73 Assi ee: Internatio :11 B siness Mach'nes “(H843 8/l932 PCT In“ APPL ' l 1 g“ corpom?gn, Armonk N_Y_ ' 2013923 4/1980 United Kingdom. 21 A LN .: 937772 Primag'Y Examiner-David Y. Eng . [ 1 pp 0 ’ Attorney, Agent, or Firm—H. St. Julian; John E. Hoel 22 F1 d: D .4 1986 [ 1 16 W ’ [51] ABSTRACT [51] Int. Cl.4 .............................................. .. G06F 9/30 A . l I [52] US. Cl. .................................................. .. 364/200 mlcliosequencer ‘.nc “.des at Fast two prcigram count [58] Field of S e at ch 364/200 MS File 900 MS File ers which access microinstrucnons stored in a memory ’ system. A ?rst program counter is cyclicly incremented [56] References Cited to sequentially access rnicroinstructions of a principal U_s_ PATENT DOCUMENTS microprogram. When a particular microinstruction is accessed which indicates that a subroutine will be the gardner e‘ """"""" " next program to be executed, a branched-from address, 3'967’lo4 6/1976 33:21:51‘;smleets' 364/900 representing the microinstruction calling the subrou 3:978:454 8/1976 - ' ' 364/900 tine, is retained in the ?rst program counter. An address 3,991,404 11/1976 364/200 representing the ?rst instruction of the subroutine 15 4,003,033 1/1977 364/200 loaded into a second program counter. The second 4,038,643 7/1977 364/200 program counter is then cyclicly incremented to se 4999329 7/1978 364/200 quentially access microinstructions associated with the 2,159,522 2/ 354/200 subroutine. After the subroutine has been executed, the £133’??? ‘£1979 ?rst program counter is re-enabled and cyclicly incre 4’323’963 4/1982 364/200 merited so that the execution of the principal program is 4:370:729 1/1933 resumed in an orderly manner. 4,429,361 1/1984 Maccianti et al. 364/200 4,438,492 3/ 1984 Harmon, Jr. ct al. ............ .. 364/200 3 Claims, 3 Drawing Sheets emcissonFROM l0 \ 001mm: R" W \14 INSTRUCTION T6 REGISTER '8 J———£L [E-IUK 20 IETzI m 22 Ira- m Ina: 32 Ill! \l6 RD! 24 m LOGIC l NEXT ER i l _,_ _.__ PROCESSOR 26 moczssoam {E3 INSTR.""‘T US. Patent Apr. 11, 1989 Sheet 1 013 4,821,183 FIG ’' FROM PROCESSOR '0\ COUNTERPROGRAM RAM \\2 \14 J msmucnou {76 REG|STER ‘8 DE-MUX 050011511 “20 | | M 22\ UPC! 1- UPCZ - - - UPCn \30 r ' F 52 MUX f \l6 ROM 28 l 24 \ CONTROL OTHER 1001c STORE CONTROL NEXT CNTRL. more car. BUS ADDR 1 . 1 T0 PROCESSOR 2s ; INSTR. ' , UNIT US. Patent Apr. 11, 1989 Sheet 2 0f3 4,821,183 F161 2. ‘ l8 \ 701 * 54I -------- -_ ’ Baum‘ / 56 i \ 68 FETCHW‘ LOAD Wi 22 i W cmLO UPC‘ Q 32 ) ?e | 52 L— 05 __ ROM/ i | * 30 I X PLA I J g Q : cmuPczLD l : i 48 50 , g : 58 46 > i 2\4 CSDR : ‘I l 155 68 l/28| : 42 e2} 60 ‘I: + (58 HTY ,IFORMATI JUMP ' i ‘JUMP ' LOGlC K ' 54 {OR : 4O 64 % 5s5 ‘SUB : FETCH y : [SUB LOW NSTR \ i To : \ . L —————— -—53——-' PROCESSOR ' UN" US. Patent Apr. 11,1989 Sheet 3 013 4,821,183 FIG 3. [so DP MUX/ /86 c00E:> 0500015 A 1 PLA / 82 88 MPG _ ENABLEIDISABLE/RESET ENABLE 90 MPG DISABLE 94/ RESET ‘ a4 PLA f 001111101 00110. CONT BRANCH cm ,92 STORE DATA SELECT HELDS mm 001111101 REG. FIELD ADDR. FIELDS T0 PROCESSOR 4,821,183 1 2 machine cycles in a sequential microcoded micro A MICROSEQUENCER CIRCUIT WITH PLURAL processor in accessing a branched-from address. MICROPROGROM INSTRUCTION COUNTERS SUMMARY OF THE INVENTION BACKGROUND OF THE INVENTION 5 These objects, features and advantages of the inven 1. Field of the Invention tion are accomplished by an improved microsequencer disclosed herein. The microsequencer circuit includes a This invention relates to a data processing system and memory means for storing a plurality of instructions more particularly to a microsequencer circuit used in a therein and a first means for sequentially addressing the sequential type microprocessor for increasing the speed instructions. A second means, responsive to a subrou of microcode/control word access and generation. tine being addressed by the ?rst addressing means, se 2. Background Information quentially addresses instructions associated with the It is known that data processing systems generally addressed subroutine. A branched-from address is comprise a central unit, a main memory and plurality of stored in the ?rst addressing means and a ?rst address of peripheral units connected to the central unit by means the subroutine is loaded in the second addressing means. of a plurality of input/output channels for the exchange An enabling means facilitates the sequential accessing of of information. The data processing system functions by the instructions of the subroutine until the execution processing data according to well de?ned program thereof is completed. Thereafter, the enabling means instructions. From a logical point of view, the central disables the second addressing means and then re-ena unit comprises a control unit and an operative unit. The bles the ?rst addressing means to continue to sequen program instructions are interpreted and executed by tially address instructions stored in the memory means. means of rnicroprograms which are microinstruction Alternately, the microsequencer includes a ?rst pro sequences read from a control memory by the control grammed logic means for generating a ?rst address unit, one microinstruction at a time. Through suitable associated with an instruction. A ?rst counter which decoding the microinstructions generate a set of ele 25 receives an input from the ?rst programmed logic mentary commands, or microcommands, which cause means, combines with the ?rst logic means to sequen the operation of several logic networks of the central tially address microcode stored in a second pro unit in the manner required by the several program grammed logic means. Microcode stored in the second instructions. logic means is then sequentially addressed until a sub Generally, the control unit includes a program routine call is encountered. Thereafter, the ?rst counter counter which enables the control unit to sequentially is disabled and a second counter is enabled in combina~ execute the program instructions. However, the execu tion with the ?rst programmed logic means and the ?rst tion of a program instruction may cause an interruption counter to sequentially access microcode associated in the sequential execution thereof in order to execute a with the called subroutine. After the subroutine has subroutine. All of the information regarding the status been executed, the second counter is disabled and the of the interrupted process must be saved in order to ?rst counter re-enabled so that the ?rst programmed resume such process once the subroutine has been exe logic means and the ?rst counter continued to sequen cuted. One known technique for solving this problem , tially address tthe microcode associated with the in includes a register ?le or RAM partition dedicated to a struction. push-down stack function where each consecutive BRIEF DESCRIPTION OF THE DRAWINGS branched-from address is stored in a last in/?rst out order. This technique requires the skipping of machine This invention will be described in greater detail by cycles in order to access the register ?le or RAM parti referring to the accompanying drawings and the de tion. scription of the best mode that follows. 45 FIG. 1 is a block diagram implementation of a mi Another known technique includes the use of a plu crosequencer circuit in accordance with the principles rality of control store memories. A ?rst control store of the invention. memory contains the primary microinstruction group, a FIG. 2 is a logic implementation of the mi second control store memory contains a branched-to crosequencer circuit of FIG. 1 in accordance with the subroutine microinstruction group and possibly a third principles of the invention. control store memory contains tertiary branched-to FIG. 3 shows an alternate embodiment of the mi subroutine microinstruction groups. In such a con?gu crosequencer circuit of FIG. 1 in accordance with the ration, a branched-from address must be stored prior to principles of the invention. accessing the secondary or tertiary control store memo ries. Moreover, after the subroutine has been executed, DESCRIPTION OF THE BEST MODE FOR machine cycles must be skipped in order to access the CARRYING OUT THE INVENTION branched-from address in order to resume the execution Referring to FIG. 1, there is shown a block diagram of the primary microinstruction group. implementation of a microsequencer circuit 10 in accor Consequently, there is a need for a microsequencer dance with the principles of the invention. A program which overcomes the necessity for skipping machine 60 counter 12 facilitates the sequential execution of a plu cycles in order to access the branched-from address. rality of program instructions stored in a random access OBJECTS OF THE INVENTION memory (RAM) 14. A primary microinstruction group, which includes a plurality of microinstructions, is Therefore it is an object of the invention to provide stored in a control store memory such as a read only an improved microsequencer for a data processing sys 65 memory (ROM) or a programmed logic array (PLA) tern. 16. Additionally, a micro subroutine group, which in It is another object of the invention to provide an cludes a plurality of subroutines each containing a plu improved microsequencer which avoids the skipping of rality of microinstructions associated with the respec 4,821,183 3 4 tive subroutine, is stored in ROM 16.
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