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Xilinx UG200 Embedded Processor Block in Virtex-5 Fpgas Reference Embedded Processor Block in Virtex-5 FPGAs Reference Guide UG200 (v1.8) February 24, 2010 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. © Copyright 2008–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. Embedded Processor Block Reference Guide www.xilinx.com UG200 (v1.8) February 24, 2010 Revision History The following table shows the revision history for this document. Date Version Revision 01/15/08 1.0 Initial Xilinx release with ISE Design Suite 10.1. 03/31/08 1.1 • Updated to remove references to unsupported features. • Changed address 0x55 to reserved in Table 3-4. In Table 3-5 and Table 3-6, changed bits 22 and 23 to reserved. Revised “Request Priority (Level 1 arbitration),” page 43. Updated discussion on “Round-Robin Arbitration,” page 45. Changed bit 23 to reserved in Table 3-37. In Table 3-41, changed bits 14–17 to reserved. In Table 3-43, changed bits 22–24 to reserved. • Changed bit 23 to reserved in Table 4-3. • Updated descriptions of bit 7 and bit 16 in Table 5-1, page 135. • Updated clock frequency ratio discussion on page 149. Updated description of CPMINTERCONNECTCLKNTO1 in Table 6-1, page 147. Updated clock frequency ratio and core reset discussions on page 149. Revised allowed CPMMCCLK ratios in Table 6-2, page 150. • In chapter 9, updated summary on page 169. Revised JTGC440TRSTNEG in Table 9-1, page 170. Added “Connecting PPC440 JTAG Logic Directly to Programmable I/O” and “Connecting PPC440 JTAG Logic in Series with the Dedicated Device JTAG Logic.” •Added to “Non-Storage Instruction Execution,” page 202. Updated timing diagrams and descriptions for Figure 12-13, Figure 12-14, and Figure 12-17. • Changed address 0x55 to reserved in Table 14-9. In Table 14-10 and Table 14-11, changed bits 22 and 23 to reserved. Changed bit 23 to reserved in Table 14-42. In Table 14-46, changed bits 14–17 to reserved. In Table 14-49, changed bits 22–24 to reserved. 05/07/08 1.2 • Added updated DCR addresses and added mnemonics to Table 13-5 and Table 14-52. • Revised Chapter 16, “Additional Programming Considerations,” added “Bit Settings for APU/FPU Usage.” 05/09/08 1.2.1 • Minor typographical change. 05/13/08 1.3 • Corrected the MI_ROWCONFLICT_MASK [0:31] register and MI_BANKCONFLICT_MASK [0:31] register on page 135 and page 269. 09/23/08 1.4 • Added index to document. • Added to the function description of C440TRCTRIGGEREVENTOUT on page 184. • Removed unsupported wildcard UDIs from page 316. UG200 (v1.8) February 24, 2010 www.xilinx.com Embedded Processor Block Reference Guide Date Version Revision 11/25/08 1.5 In Chapter 5, “Memory Controller Interface”: • Revised “Interface Features,” page 132. •In Table 5-1, page 135, revised the descriptions of Rowconflictholdenable, Bankconflictholdenable, Directionconflictholdenable, Autoholdduration, and RMW. •In Table 5-2, page 137, revised the descriptions of MIMCBANKCONFLICT and MIMCROWCONFLICT. • Updated Figure 5-4, page 139, Figure 5-5, page 140, Figure 5-6, page 141, and Figure 5-7, page 142. •Added Figure 5-8, page 142 and Figure 5-9, page 143. • Changed autostall to autohold. In Chapter 13, “DMA Controller”: • Revised “DMA Operation,” page 228. • Updated Figure 13-2, page 231 and Figure 13-5, page 233. • Revised second paragraph after Figure 13-2, page 231. •Added Figure 13-3, page 232, Figure 13-4, page 233, Figure 13-6, page 234, and Figure 13-7, page 235 and associated text. • Revised third paragraph after Figure 13-5, page 233. • Updated “DMA Addressing Limitation,” page 236. •Rewrote “Software/Device Driver Considerations,” page 240. • Corrected bit 30 description in Table 13-13, page 249. • Corrected bit 31 description in Table 13-21, page 255. 01/20/09 1.6 • Added additional information on MCMIREADDATAERR for clarification to the last paragraph of “Interface Features” on page 134. • Updated documentation references. 10/06/09 1.7 • Updated references in “Additional References,” page 13. • Added third paragraph to “Locked Transfers,” page 47. • Updated default value for Bit 27 in Table 4-6, page 108. •Added Table 6-3 and text describing it to “Clock Insertion Delays and PLL Usage,” page 150. 02/24/10 1.8 In the Interface Timings section, page 161, added clarifying text at the end of the section relating to use of synchronous or asynchronous, master or slave DCRs. Embedded Processor Block Reference Guide www.xilinx.com UG200 (v1.8) February 24, 2010 Table of Contents Revision History . 3 Preface: About This Guide Guide Contents . 11 Additional Documentation . 12 Additional References. 13 Additional Support Resources. 13 Typographical Conventions . 14 Online Document . 14 Section I: Introduction Chapter 1: PowerPC 440 Embedded Processor PowerPC 440 Embedded Processor Features . 17 PowerPC 440 Embedded Processor as an IBM PowerPC Implementation . 19 Processor Organization. 20 Superscalar Instruction Unit. 20 Execution Pipelines . 21 Instruction and Data Cache Controllers . 21 Memory Management Unit (MMU) . 22 Timers . 24 Debug Facilities . 24 Processor Interfaces . 25 Processor Local Bus (PLB) . 25 Device Control Register (DCR) Interface . 26 Auxiliary Processor Unit (APU) Port . 26 JTAG Port . 26 Section II: Embedded Processor Block Chapter 2: Embedded Processor Block Overview Embedded Processor Block Components . 29 Crossbar and its Interfaces . 30 Control and other Interfaces . 30 Auxiliary Processor Unit Controller . 31 Direct Memory Access Controller. 31 Chapter 3: Crossbar Overview . 33 Key Features . 34 Embedded Processor Block Reference Guide www.xilinx.com 5 UG200 (v1.8) February 24, 2010 R Hardware Description. 35 Overview . 35 Hardware Interface . 37 Slave Ports . 37 Slave Port PLB Busy Signals . 38 Master Ports . 40 Interrupts. 42 Functional Description . 43 Arbitration. 43 Address Mapping . 51 Pipelining . 53 Miscellaneous Notes . 53 Miscellaneous Signals . 54 Usage Notes and Limitations . 55 Crossbar Limitations for PCI and PCI Express Designs . 55 Device Control Registers (DCRs) . 56 Overview of the DCR Map . 56 Detailed DCR Descriptions. 56 Chapter 4: PLB Interface MPLB Interface . 87 Transaction Types . ..
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