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NAND Gate Design for Ballistic Deflection Transistors

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NAND Gate Design for Ballistic Deflection Transistors 1 NAND Gate Design for Ballistic Deflection Transistors David Wolpert, Student Member , IEEE , Quentin Diduck, Member , IEEE , and Paul Ampadu, Member , IEEE Abstract —This paper presents a NAND gate designed using ballistic deflection transistors (BDTs). Room temperature BDT measurements are captured in an empirical device model to simulate multi-BDT logic design. Measurements from a fabricated BDT NAND gate validate the multi-device model and demonstrate the promise of BDTs for nanoscale circuit design. Index Terms —Ballistic transport, quasi-ballistic transport, device model, two-dimensional electron gas, 2DEG, logic design Fig. 1. Schematic of ballistic deflection transistor under two gate biases. I. INTRODUCTION HE ballistic deflection transistor (BDT) [1][2] is a six- T terminal coplanar structure etched into a two-dimensional electron gas (2DEG). Shown in Fig. 1 (with SEM image in Fig. 2), the BDT consists of a grounded electron source, left and right gates, and three biased drains. The center drain is a pull-up while the left and right drains are outputs. The device dimensions and materials allow electrons to travel quasi- ballistically at room temperature, guided by the central Fig. 2. SEM image of fabricated BDT. −6 deflector and lateral gate potentials. While the dimensions are x 10 4.5 larger than the mean free path (meaning some electrons will Left branch experience scattering events), ballistic properties are still 4 Right branch observed at room temperature, as described in a number of 3.5 other works, including an overview of prior work on room 3 temperature ballistic nanostructures by Song [3], a detailed 2.5 examination of quantum transport in nanoscale devices 2 1.5 presented by Beenakker and Van Houten 0, and a key Output current (A) experiment performed by Hirayama and Tarucha [6]. In the 1 BDT, the steering voltage is much smaller than that required 0.5 0 for gate pinch-off, which, combined with the reduced gate −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 Gate voltage (V) capacitances of the 2DEG, results in an estimated fT in the Fig. 3. Measured output response of the BDT for differential gate inputs. terahertz range. Mateos et al. have shown a 1 THz response in a similar structure, the ballistic rectifier [7]. 2DEG estimated to be about 9 nm thick occurring ~60 nm The BDT has been fabricated in an In 0.53 Ga 0.47 As- deep. Additional information about the process used is In 0.52 Al 0.48 As heterostructure with an InP substrate, with the available in [15]. The device was fabricated using mask layers defined by electron beam lithography, with reactive ion etching used to create the raised mesas shown in the SEM. The Manuscript received December 18, 2008; revised July 1, 2009. This work minimum etch width was 70 nm (the gate-channel spacing), was supported in part by the US National Science Foundation (NSF) under grant ECS0609140, the Air Force Office of Scientific Research (AFOSR) and the etch depth was approximately 130 nm. The electron under grant FA9550-07-1-0032, and the Office of Naval Research (ONR) mean free path was calculated to be 120 nm [15]. under grant N00014-05-1-0052. The measured room temperature response across a range of D. Wolpert and P. Ampadu are with the University of Rochester, Rochester, NY 14623 USA; contact e-mail: [email protected]. differential gate voltages is shown in Fig. 3, with each drain Q. Diduck is with the University of Massachusetts Lowell, Lowell, MA biased at 1 V; using the left branch output of ~4 µA, this 01854 USA. 2 results in a channel conductance of ~4 µS. The gate voltage Vg indicated by the x-axis is the left gate voltage (e.g. at 0.1 V, the left gate voltage is 0.1 V and the right gate voltage is -0.1 V). The output asymmetry is largely caused by asymmetries in contact placement. As shown, differential output currents are achieved even at V g < kT/q, although the differential current is very small. Positive left gate voltage results in larger current through the left output, and positive right gate voltage results in larger current through the right output, with maximum output currents occurring at gate voltages of ~±0.15 V. At gate voltages larger than ~±0.2 V, the output current decreases to a small fixed amount (the amount is determined by the leakage between the gate and Fig. 4. Two-input NAND gate and electron paths. input channel). This decrease at higher voltages is likely caused by the gate voltages pinching off the channel, and improving the NAND gate latency. The proposed design can future experiments with varying source channel widths will be also provide a complimentary output, while [11] and [12] performed to verify this hypothesis. produce only a single output. This paper proposes a technique for designing complex logic functions in a 2DEG with boundary structures and lateral III. TWO -INPUT BDT NAND GATE gate steering. Section II briefly describes related work in the The two-input NAND gate is logically complete; NAND area of logic design with ballistic nanostructures. In Section functionality can be used to construct any complex logic. It is III, the two-input BDT NAND gate design is presented, along thus of immense importance for novel devices to achieve this with simulated and measured results. Conclusions are function if they are to be used in general purpose computation. presented in Section IV. A. Design The NAND gate is created by connecting the source of one II. RELATED WORK BDT to the output drain of another, as shown in Fig. 4. The The principle of switching a current flow between terminals large arrows represent the gate input and output, while the has been around since at least 1992, when Palm and Thylén smaller arrows represent electron paths which depend on the proposed a Y-branch junction (YBJ) fabricated in a 2DEG and input state. The output terminal F is considered logic high in controlled by an applied electric field [13]. Palm and Thylén the absence of electrons and logic low when electrons are later expanded on this work to develop a number of logic passing through it. Following the smaller arrows in Fig. 4, the functions using these devices, which included an inverter, output is only driven low when inputs A and B are both high. NAND and NOR gate [10]. Since the publication of that For all other input combinations the output remains high, with expansion, YBJs have been thoroughly examined and used in a electrons guided either to the left drain or upper right drain. number of novel ways, including the generation of Thus, the overall gate function is A NAND B ( AB ). A complementary outputs [9], rectification [14], and even the differential output (both AB and AB ) is required to drive the design of a half-adder [8]. Indeed, the BDT may also be seen next stage of gates. The AB function may be created by as an extension of the YBJ concept, with an additional pull-up connecting the left drain of BDT 1 (capturing the A = 0 potential through the upper center drain, although the primary electron flow) and the top drain of BDT 2 (capturing the B = 0 motivation for the BDT was Song’s ballistic rectifier [3]. T- electron flow) to a separate terminal AB . branch junctions (TBJs) have also been used to create logic B. Model functionality [12], for example using the center branch of the To estimate the expected functionality before fabrication, a TBJ to pinch off a conductive channel, creating a NAND gate. model of the NAND gate was built in the Cadence Spectre NAND functionality has also been created using a quantum simulator using empirical data from a single BDT. The NAND wire with two co-planar gates, a method with excellent gate model, shown in Fig. 5, consists of two instances of a integration density [11]. single-BDT model. BDT functionality is achieved by feeding The purpose of the proposed work is to provide a method of the output response from Fig. 3 into a pair of piecewise linear creating NAND functionality using the BDT, with two BDTs voltage-controlled current sources (VCCS). Each BDT model connected in a drain-source configuration. In addition to being consists of differential gate voltages, a grounded source, and a the first logic gate fabricated with BDTs, the proposed design leakage resistor connecting the source and center drain. is different from prior work in two major ways. In [9] and Current-to-voltage converters are created using three resistors [10], the output of the first device is used as a gate input to the second device, thus two consecutive YBJs must switch to between V DD =1V and V SS =-1V (the resistors are in the MΩ create the functionality; in the proposed drain-source range, thus standby current should be relatively small), and the configuration, both gate inputs arrive simultaneously, output currents of each VCCS are converted to an output voltage range which matches the input range, to drive the next 3 Fig. 5. Model schematic of BDT NAND gate. Fig. 7. SEM image of BDT NAND gate with experimental setup. A = B = 0. From (1), 2 2 Pc > Pc ⋅ Pi > Pi . (2) These three states are clearly shown in the iF waveform in Fig. 6(a). The value of the intermediate state depends on the Pc/Pi ratio of the BDT, which will be improved as materials and geometries are optimized.
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