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Power Compiler User Guide, Version D-2010.03-SP2 Ii Contents Power Compiler™ User Guide Version D-2010.03-SP2, June 2010 Copyright Notice and Proprietary Information Copyright © 2010 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: “This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of __________________________________________ and its employees. This is copy number __________.” Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Registered Trademarks (®) Synopsys, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS, Certify, CHIPit, Design Compiler, DesignWare, Formality, HAPS, HDL Analyst, HSIM, HSPICE, Identify, Leda, MAST, ModelTools, NanoSim, OpenVera, PathMill, Physical Compiler, PrimeTime, SCOPE, Simply Better Results, SiVL, SNUG, SolvNet, Syndicated, Synplicity, Synplify, Synplify Pro, Synthesis Constraints Optimization Environment, TetraMAX, the Synplicity logo, UMRBus, VCS, Vera, and YIELDirector are registered trademarks of Synopsys, Inc. Trademarks (™) AFGen, Apollo, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Confirma, Cosmos, CosmosLE, CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision, DesignerHDL, DesignPower, DFTMAX, Direct Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, Galaxy Custom Designer, HANEX, HapsTrak, HDL Compiler, Hercules, Hierarchical Optimization plus Technology, High-performance ASIC Prototyping System, HSIM , i-Virtual Stepper, IICE, in-Sync, iN-Tandem, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, Physical Analyst, Planet, Planet-PL, Polaris, Power Compiler, Raphael, Saturn, Scirocco, Scirocco-i, Star-RCXT, Star-SimXT, StarRC, System Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCS Express, VCSi, VHDL Compiler, VirSim, and VMC are trademarks of Synopsys, Inc. Service Marks (SM) MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc. SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. Saber is a registered trademark of SabreMark Limited Partnership and is used under license. All other product or company names may be trademarks of their respective owners. Power Compiler User Guide, version D-2010.03-SP2 ii Contents What’s New in This Release . xvii About This User Guide . xviii Customer Support. xx 1. Introduction to Power Compiler Power Compiler Methodology . 1-2 Power Library Models . 1-3 Power Analysis Technology . 1-3 Power Optimization Technology . 1-5 Working With Power Compiler . 1-6 Library Requirements . 1-6 Command-Line Interface . 1-6 License Requirements . 1-7 Reading and Writing Designs . 1-7 Command Syntax . 1-8 Getting Help. 1-9 Help for a Command. 1-9 Help for a Topic. 1-10 2. Power Compiler Design Flow Power in the Design Cycle . 2-2 Power Optimization and Analysis Flow . 2-3 Simulation . 2-5 iii PowerPower CompilerCompiler UUserser GGuideuide Version D-2010.03-SP2D-2010.03-SP2 Enable Power Optimization . 2-5 Synthesis and Power Optimization . 2-5 Power Analysis and Reporting. 2-5 Power Compiler and Other Synopsys Tools . 2-6 3. Power Modeling and Calculation Defining Power Types . 3-2 Defining Static Power. 3-2 Defining Dynamic Power . 3-2 Switching Power . 3-2 Internal Power. 3-3 Calculating Power . 3-4 Leakage Power Calculation . 3-4 Multithreshold Voltage Libraries . 3-6 Channel-width Based Leakage Power Calculation . 3-6 Internal Power Calculation . 3-8 NLDM Models. 3-9 State and Path Dependency. 3-11 Rise and Fall Power . 3-12 Switching Power Calculation. 3-12 Dynamic Power Calculation . 3-13 Dynamic Power Unit Derivation . 3-13 Multivoltage Power Calculation . 3-14 Using CCS Power Libraries . 3-16 4. Generating Switching Activity Information Format Files About Switching Activity . 4-2 Introduction to SAIF Files . 4-2 Generating SAIF Files. 4-3 Generating SAIF Using VCD Output Files. 4-4 Converting VCD file to a SAIF File . 4-5 Limited SystemVerilog Support in vcd2saif Utility. 4-5 Generating SAIF Files Directly From Simulation . 4-6 Generating SAIF Files From SystemVerilog or Verilog Simulations. 4-6 Generating SAIF File From RTL Simulation . 4-6 Generating SAIF Files From Gate-Level Simulation . 4-7 Contents iv Power Compiler User Guide Version D-2010.03-SP2 Understanding the VCS MX Toggle Commands. 4-8 Generating SAIF Files From VHDL Simulation . 4-13 System Task List for SAIF File Generation from VHDL Simulation. 4-14 Verilog Switching Activity Examples . 4-14 RTL Example . 4-14 Verilog Design Description . 4-15 RTL Testbench . 4-16 RTL SAIF File . 4-17 Gate-Level Example . 4-18 Gate-Level Verilog Module . 4-19 Verilog Testbench . 4-19 Gate-Level SAIF File. 4-20 VHDL Switching Activity Example . 4-22 VHDL Design Description . 4-22 RTL Testbench. 4-22 RTL SAIF File . 4-23 Analyzing a SAIF File . 4-24 5. Annotating Switching Activity Switching Activity That You Can Annotate . 5-2 Annotating the Switching Activity Using RTL SAIF Files . 5-2.
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