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Prostep Ivip CPO Statement Template
CPO Statement of Mentor Graphics For Questa SIM Date: 17 June, 2015 CPO Statement of Mentor Graphics Following the prerequisites of ProSTEP iViP’s Code of PLM Openness (CPO) IT vendors shall determine and provide a list of their relevant products and the degree of fulfillment as a “CPO Statement” (cf. CPO Chapter 2.8). This CPO Statement refers to: Product Name Questa SIM Product Version Version 10 Contact Ellie Burns [email protected] This CPO Statement was created and published by Mentor Graphics in form of a self-assessment with regard to the CPO. Publication Date of this CPO Statement: 17 June 2015 Content 1 Executive Summary ______________________________________________________________________________ 2 2 Details of Self-Assessment ________________________________________________________________________ 3 2.1 CPO Chapter 2.1: Interoperability ________________________________________________________________ 3 2.2 CPO Chapter 2.2: Infrastructure _________________________________________________________________ 4 2.3 CPO Chapter 2.5: Standards ____________________________________________________________________ 4 2.4 CPO Chapter 2.6: Architecture __________________________________________________________________ 5 2.5 CPO Chapter 2.7: Partnership ___________________________________________________________________ 6 2.5.1 Data Generated by Users ___________________________________________________________________ 6 2.5.2 Partnership Models _______________________________________________________________________ 6 2.5.3 Support of -
Power Reduction of a CMOS High-Speed Interface Using Power Gating
FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO Power reduction of a CMOS high-speed interface using power gating Luís Miguel Granja Gomes FOR JURY EVALUATION Mestrado Integrado em Engenharia Eletrotécnica e de Computadores FEUP Supervisor: Prof. João Canas Ferreira Synopsys Supervisor: Engineer Hélder Araújo June 25, 2013 c Luís Gomes, 2013 Resumo A indústria de circuitos VLSI sofreu uma série de revoluções na forma como os chips eletrónicos são projetados. Começou com o uso de linguagens de descrição de hardware e de avançadas ferramentas de trabalho, com o objetivo de diminuir os tempos de projeto e de produção, ao mesmo tempo que circuitos mais rápidos e pequenos eram construídos. A produção de dispos- itivos eletrónicos aumentou significativamente, de tal modo que, hoje, são usados biliões todos os dias. Atualmente, o maior desafio não é só projetar circuitos integrados mais pequenos e rápidos, mas manter esses acréscimos de velocidade e diminuição de tamanho, reduzindo simultaneamente o consumo de potência. Com a diminuição do tamanho da tecnologia e o uso de transístores com tensões de threshold cada vez mais reduzidas, o consumo de potência dinâmica e estática atingiu níveis insuportáveis. Chegou-se a um ponto em que, tanto económica como ambientalmente fa- lando, é obrigatório projetar para reduzir a potência. Synopsys, uma das maiores empresas desta indústria, apresentou um projeto com o objetivo de implementar Power Gating numa das suas interfaces de alta velocidade, como técnica mais eficaz na redução da potência estática. Esta dissertação apresenta as adaptações necessárias para a implementação de Power Gating us- ando ferramentas Synopsys, aplicando-as a um caso de estudo complexo. -
Powerpoint Template
Accellera Overview February 27, 2017 Lu Dai | Accellera Chairman Welcome Agenda . About Accellera . Current news . Technical activities . IEEE collaboration 2 © 2017 Accellera Systems Initiative, Inc. February 2017 Accellera Systems Initiative Our Mission To provide a platform in which the electronics industry can collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products. 3 © 2017 Accellera Systems Initiative, Inc. February 2017 Broad Industry Support Corporate Members 4 © 2017 Accellera Systems Initiative, Inc. February 2017 Broad Industry Support Associate Members 5 © 2017 Accellera Systems Initiative, Inc. February 2017 Global Presence SystemC Evolution Day DVCon Europe DVCon U.S. SystemC Japan Design Automation Conference DVCon China Verification & ESL Forum DVCon India 6 © 2017 Accellera Systems Initiative, Inc. February 2017 Agenda . About Accellera . Current news . Technical activities . IEEE collaboration 7 © 2017 Accellera Systems Initiative, Inc. February 2017 Accellera News . Standards - IEEE Approves UVM 1.2 as IEEE 1800.2-2017 - Accellera relicenses SystemC reference implementation under Apache 2.0 . Outreach - First DVCon China to be held April 19, 2017 - Get IEEE free standards program extended 10 years/10 standards . Awards - Thomas Alsop receives 2017 Technical Excellence Award for his leadership of the UVM Working Group - Shrenik Mehta receives 2016 Accellera Leadership Award for his role as Accellera chair from 2005-2010 8 © 2017 Accellera Systems Initiative, Inc. February 2017 DVCon – Global Presence 29th Annual DVCon U.S. 4th Annual DVCon Europe www.dvcon-us.org 4th Annual DVCon India www.dvcon-europe.org 1st DVCon China www.dvcon-india.org www.dvcon-china.org 9 © 2017 Accellera Systems Initiative, Inc. -
802.11 B/G/N Standalone Wi-Fi + BLE 4.1Module with Integrated Antenna
Product Brief AVIC 802.11 b/g/n Standalone Wi-Fi + BLE 4.1Module with Integrated Antenna Description AVIC is a highly integrated low power single-stream (1x1) IEEE 802.11 b/g/n standalone Wi-Fi + BLE 4.1 Module. This highly tuned certified Module integrates crystals, flash and antenna for easy hardware design. This feature-rich Module using Qualcomm QCA4010 and CSR 8811 SoCs are specially designed for various verticals of Internet of Things (IoT) like Smart Home, Industrial IoT, Smart Retail and Smart City. The AVIC Module includes a suite of communication protocols including HTTP, IPv4v6, TCP, SSL 3.0, TLS1.0, TLS1.1, TLS1.2, DHCP, ICMP, IGMP, MQTT, mDNS and DNS, as well as support for multiple cloud agents like AWS and Azure. Size: 16 mm x 20 mm x 2.1 mm AVIC with integrated low power MCU, it is designed to answer manufacturer demand for easy integration, low power with Applications advanced features while minimizing size, cost and power consumption. This low power highly secure Module with its Smart Home sensor networks integrated security engine is suitable for battery powered portable Smart city sensor networks wireless applications. High performance HID controllers Internet of Things (IoT) sensor networks Smart door locks Features Smart lighting networks Industry-leading single stream IEEE 802.11bgn Wi-Fi and Connected white goods Bluetooth Low Energy (BLE) v4.1 connectivity solution Integrated on-chip application processor and user memory (800 KB) Data rate up to 72.2 Mbps MCS7 HT20 Block Diagram UART, SPI, I2C, I2S, -
JTAG Controller Board Specification
JTAG Controller Board Specification Rice University April 27, 2011 Introduction The board is intended for evaluation of the National Semiconductor JTAG 1149.1. SCANSTA101 System Test Access Master [1]. Its block diagram is shown on Fig.1. The board is build as a VME A24D16 Slave; the dimensions are 6U x 160 mm. The VME interface circuitry is implemented in the Xilinx XCR3128 CPLD. The SCANSTA101 Master provides JTAG access to external devices via two front panel connectors. One 14-pin connector is compatible with the Xilinx JTAG cable (LVTTL levels), and another 16-pin connector is compatible with the JTAG cable for the CSC EMU Trigger Motherboard [2] (LVDS levels). Fig.1: Block Diagram of the JTAG Controller Board 1. SCANSTA101 JTAG Master The SCANSTA101 is designed to function as a test master for the IEEE 1149.1 boundary scan test system. It is an enhanced version, and a replacement for, the SCANPSC100 device. The interface from the SCANSTA101 to the system processor (VME bus master, in our case) is implemented by reading and writing registers, some of which map to locations in the SCANSTA101 memory. Hardware handshaking and interrupt lines are provided as part of the processor interface. The block diagram of the device is shown in Fig.2. The external JTAG slave devices are connected via the front panel connectors. These may be any JTAG- compatible FPGA, programmable memories and others. The internal Test and Debug Interface Port (Fig.2) is not used, although its inputs and outputs are available on the board as a test points. -
Overview of Xilinx JTAG Programming Cables and Reference Schematics for Legacy
R Overview of Xilinx JTAG Programming Cables and Reference Schematics for Legacy XTP029 (v1.0) March 28, 2008 Parallel Cable III (PC3) Summary This technical publication provides an overview of Xilinx JTAG Cables and a reference schematic for the legacy Xilinx Parallel Cable III product (PC3) for educational use. Description Xilinx offers the Hi-Speed Platform Cable USB (PCUSB) and the Parallel Cable IV (PC4) cables. The PC4 cable supports both the IEEE 1284 parallel port interface and IEEE STD 1149.1 (JTAG) standards for in-system programming or embedded debug. These cables are more thoroughly described in the “Overview of Xilinx JTAG Solutions.” For reference purposes, the PC3 product schematic is also provided in this document. Note: The PC3 cable product has been discontinued and replaced by PCUSB and PC4. Both the PCUSB and PC4 cables have expanded capabilities, superior download performance, and robust immunity to system interface sensitivities when compared to the legacy PC3 cable. The PC3 product was first introduced in 1998 and then discontinued in 2002. Software support for PC3 was removed starting in March 2008 with the 10.1 release of Xilinx iMPACT software. Versions of iMPACT software after 10.1 release do not support the PC3 cable. See “Notice of Disclaimer” regarding warranty and support of the PC3 schematic information. Overview of Xilinx recommends the Platform Cable USB (PCUSB) or Parallel Cable IV (PC4) for new Xilinx JTAG designs. The PCUSB and PC4 offer reliable operation, higher speed download, voltage support down to 1.5V, keyed ribbon cable connector for error-free insertion, and improved ground/signal Solutions integrity. -
JTAG Advanced Capabilities and System Design
SCANSTA101,SCANSTA111,SCANSTA112, SCANSTA476 JTAG Advanced Capabilities and System Design Literature Number: SNLA211 SIGNAL PATH designer® Tips, tricks, and techniques from the analog signal-path experts No. 117 JTAG Advanced Capabilities Feature Article ............... 1-6 and System Design Comms Applications .........2 — By David Morrill, Principal Applications Engineer he JTAG bus, originally intended for board-level manufacturing test, has evolved into a multipurpose bus also used for In-System Program- Tming (ISP) of FPGAs, FLASH, and processor emulation. Th is article’s intent is to provide a brief overview of JTAG. Several system-level design options will be proposed, from the simplest board-level JTAG chain through a complex embedded multidrop system. Finally, an appendix is included that contains some useful defi nitions. Overview: What is JTAG? Th e Joint Test Action Group (JTAG) is an industry group formed in 1985 to develop a method to test populated circuit boards after manufacture. Th e group’s work resulted in the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture. Th e terms 1149.1, JTAG, “dot 1”, and SCAN all refer to the same thing, the IEEE 1149.1 Standard for Boundary Scan Test. What is JTAG and what does it do? 1) It is a serial test bus. 2) It adds a Test Access Port (TAP) consisting of four pins to an IC (fi ve with optional RESET) as shown in Figure 1. – TDI (Test Data In) – TDO (Test Data Out) – TCK (Test Clock) – TMS (Test Mode Select) – TRST (Test Reset) JTAG provides access to interconnected digital cells on an IC: 1) with a method of access for test and diagnostics and the – ability to do factory and remote testing and diagnostics, – ability to perform software debug, and – reduce “No-Fault-Found” problems 2) with a method for in-circuit upgrades and the – ability to remotely perform system-wide fi rmware upgrades High Effi ciency. -
Uc1394a Carrier Product Overview
UC1394a Carrier product overview UC1394a Carrier Highly flexible ultra-compact© carrier board with FPGA, IEEE 1394 (FireWire®) + USB interfacing and various I/O Key features Customer benefits ® © Hardware: · micro-line and ultra-compact boards offer the opportunity to directly reduce time to · Highly flexible carrier board for the ultra- © market compact multi chip module (MCM) family ® © ® · micro-line and ultra-compact boards · micro-line bus compatibility allows direct maximize software creativity and minimize connection between micro-line® and ultra- © high density and sensitive high frequency compact products hardware design · Capable to carry UC1394a-1, UC1394a-2 ® © © · micro-line and ultra-compact boards are and further ultra-compact daughter multi the perfect target hardware for system chip modules development, prototyping and volume · User programmable Xilinx SPARTAN II production FPGA with 50 kGates enables various I/O · overall shorter design and system cycles interface- or test pattern- realization for the © ® dramatically reduce development costs ultra-compact -or the micro-line -bus ® © · micro-line and ultra-compact boards are · Onboard FPGA booting Flash with various manufactured according to ISO 9002:2000 available standard FPGA solutions also · CE-qualification ensures first-class product allow to run the system without additional performance and industrial quality FPGA design effort · Attractive quantity pricing · Equipped with interface connectors for IEEE 1394 (FireWire®), USB 1.1 (slave), RS232 and 4 channel analog -
Dataman 48Pro Specification
Dataman 48Pro www.dataman.com • Universal 48 pin ZIF socket accepts both 300/600 mil DIP devices up to 48 pin • Intelligent pin drivers allow varying voltages to be applied to any pin delivering signals without overshoot, increasing The Dataman 48Pro is a universal 48pin driver, PC based programmer programming yield with ISP capabilities with USB 2.0 and parallel connectivity. The 48Pro is built to meet the demands of development labs and field engineers • Pin drivers operate for universal programming. down to 1.8V so you'll Supporting over 22,000 devices with new support being added monthly, be ready to program the Dataman 48Pro can program without the need for a family-specific the full range of module, giving you the freedom to choose the optimal device for your design. Using the built-in, in-circuit serial programming (ISP) connector, tomorrow’s advanced the programmer is able to program ISP compatible chips in circuit. low-voltage devices • ISP capable using the Hardware General JTAG interface • FPGA based totally reconfigurable 48 powerful TTL pindrivers provide H/L/pull_up/pull_down and read capability for each pin of the socket. Advanced pindrivers incorporate high-quality high-speed circuitry to • Multiprogramming deliver signals without overshoot or ground bounce for all supported devices. Pin drivers operate down to 1.8V so you'll be ready to program the full range of today's advanced low-voltage devices support allows one PC • The programmer performs device insertion tests and contact checks before device programming. These to control up to eight capabilities, supported by overcurrent protection and signature-byte check help prevent chip damage due to operator error units programming • Built-in protection circuits eliminates damage to programmer and/or device due to environment or independently or as a operator failure. -
IEEE-SA and How Standardization Can Enhance Your Business and Career Case Study in Electronic Design Automation
IEEE-SA and How Standardization Can Enhance Your Business and Career Case Study in Electronic Design Automation Yatin Trivedi Member, Board of Governors, IEEE-SA Member, Standards Board, IEEE-SA Member, Education Activities Board, IEEE Director of Standards and Interoperability, Synopsys Vienna, March 2015 Contents Standards and EDA Impact of EDA standards Case Study: Successful Standards Standards as Innovation Platform Standards, Business and Career © 2015 IEEE Standards Association Vienna, March 2015 2 1 IEEE Technical Societies/Councils Top-class technical expert base . Aerospace & Electronic Systems . Instrumentation & Measurement . Antennas & Propagation . Lasers & Electro-Optics . Broadcast Technology . Magnetics . Circuits & Systems . Microwave Theory & Techniques . Communications . Nanotechnology Council . Components, Packaging, & Manufacturing . Nuclear & Plasma Sciences Technology . Oceanic Engineering Computer . Power Electronics Computational Intelligence . Power & Energy Consumer Electronics . Product Safety Engineering Control Systems . Professional Communication Council on Electronic Design Automation . Reliability Council on Superconductivity . Robotics & Automation Dielectrics & Electrical Insulation . Sensors Council Education . Signal Processing Electromagnetic Compatibility . Social Implications of Technology Electron Devices . Solid-State Circuits . Engineering in Medicine & Biology . Systems Council . Geosciences & Remote Sensing . Systems, Man, & Cybernetics . Industrial Electronics . Technology Management Council -
Documentation for JTAG Switcher
Documentation for JTAG Switcher 18 October 2019 License The MIT License Copyright (c) 2018-2019 Lauterbach GmbH, Ingo Rohloff Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUD- ING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. i Table of Contents 1 Introduction 2 1.1 IEEE 1149.1 aka JTAG . .2 1.2 JTAG overview . .3 1.3 JTAG chaining . .5 2 JTAG Switcher overview 6 2.1 Motivation . .6 2.2 Basic circuitry . .8 2.3 Design decisions . .9 2.3.1 JTAG Switcher should conform to IEEE 1149.1 . .9 2.3.2 Transparency . .9 2.3.3 First in JTAG chain . .9 2.3.4 JTAG slave TCK clock gating . -
Volume 10, Issue 1 — March 2014
A PUBLICATION OF MENTOR GRAPHICS — VOLUME 10, ISSUE 1 — MARCH 2014 WHAT’S ON Whether It’s Fixing a Boiler, or Getting THE HORIZON? to Tapeout, It’s Productivity that Matters. By Tom Fitzpatrick, Editor and Verification Technologist The Little Things that Can Make Verification Easier Make verification more As I write this, we’re experiencing yet another winter storm here in New England. It started this productive by keeping your focus on verifying your design’s functionality...page 4 morning, and the timing was fortuitous since my wife had scheduled a maintenance visit by the oil company to fix a minor problem with the pipes before it really started snowing heavily. While the kids were sleeping in due to school being cancelled, the plumber worked in our basement to make The advantages of using the Unified Power Format (UPF) sure everything was working well. It turned out that he had to replace the water feeder valve on the standard with Questa See how Questa was able to model the behaviors boiler, which was preventing enough water from circulating in the heating pipes. Aside from being from their UPF specification...page 8 inefficient, this also caused the pipes to make a gurgling sound, which was the key symptom that led to the service call in the first place. As I see the snow piling Pre-silicon validation of IEEE 1149.1-2013 based Silicon up outside my window (6-8 inches and counting), it’s easy to Instruments Verify the functionality picture the disaster that this could have become had we not of the actual chip through what Intellitech calls “silicon instruments.”...page 13 identified the problem early and gotten it fixed.