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Nios II Embedded Processor Design Contest—Outstanding Designs 2005

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Nios II Embedded Processor Design Contest—Outstanding Designs 2005 Nios II Embedded Processor Design Contest Outstanding Designs 2005 Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Foreword Since its introduction in June 2000, Altera’s Nios® and Nios II soft-core processors have rapidly been integrated in a wide range of commercial applications. From video broadcast systems and WiMAX base stations using Stratix II FPGAs to SOHO networking equipment and automotive telematics using Cyclone® II devices, academic and professional designers worldwide have discovered the advantages of using Nios processors. Today, more than 15,000 development kits have been shipped, and over 5,000 companies—including the world’s top 20 original equipment manufacturers (OEMs)—are licensed to use Nios processors. The versatility of the Nios processor is a big factor in our success. Designers can tailor Nios systems with the exact peripherals, memory, and interfaces required, and add their own proprietary functions— their own “secret sauce”—to create a unique competitive advantage. Altera solves the IP integration problem with a tool that allows designers to drag and drop the exact mix of functions required, so they can focus on higher, system-level requirements instead of mundane, error-prone, manual tasks. Plus, Altera® tools work seamlessly with other industry-standard tools, minimizing training time. The soft- core implementation enables easy software and design upgrades, effectively making the design obsolescence-proof. With the added advantages of FPGA flexibility, fast time-to-market, and system integration, designers have a risk-free path to a custom embedded solution. Altera continually cultivates designers in Asia and around the world through our University Program. As part of that program, the Nios II Embedded Processor Design Contest aims to increase student interest in embedded processors, improve their design and creative abilities, and ultimately motivate the continued development of FPGA-based embedded designs. This year, we received 578 qualified entries—nearly three times last year’s number of entries. The significant growth of the program is yet more proof of how rapidly the Nios design community is expanding. The 20 winning entries presented in this book showcase not only the breadth of possibilities that can be addressed using Altera’s embedded solutions—including everything from digital imaging, watermarking and storage centers to an electric network monitoring system and a mechanical control system—but also technology trends in the industry. When designers have the tools and flexibility they need, there are no limits to what they can create. Congratulations to all the Nios II Design Contest winners and their professors. Keep the fires of innovation burning! Jordan S. Plofsky Senior Vice President, Marketing Altera Corporation i Nios II Embedded Processor Design Contest—Outstanding Designs 2005 Preface In today’s competitive environment, the integration of multiple complex computational and processing units to build a System on a Chip (SoC) is an increasingly challenging task. The task of building a SoC involves creating an exact-fit embedded processor with the inclusion of user-defined instructions to accelerate the execution of time-critical software algorithms. Moreover, the SoC needs to be flexible enough to cater for rapid adaptation to design requirements or changing standards, and the ability to update the features and product enhancements through remote deployment. The continual technology advancements in programmable logic, through increased performance and higher density devices, has created an opportunity to design cost effective scalable processor systems for SoC applications. These scalable “soft processors,” implemented using general logic primitives rather than a hard, dedicated block in the programmable logic devices, provide a superior alternative for real-time processing needs in most applications. The SoC designers can choose from any combination of highly customizable features that will bring their products to market faster, extend their products’ life cycle, and avoid processor obsolescence. Altera provides one such flexible soft processor (Nios II). The Altera Nios II processor is a 32-bit RISC soft core with a rich instruction set optimized for embedded applications. It can achieve a performance of over 200 MHz. The Nios II processor is designed to be flexible, giving the user control of a number of features such as the execution units, cache sizes, memory and I/O interfaces, and a flexible bus architecture. The configurability aspect of the Nios II processor allows the user to trade-off features for size to achieve the necessary performance for the target application. The Nios II solution comes with a complete development suite. Tools include Eclipse-based integrated development environment (IDE), embedded software, operating systems, middleware, and debuggers. It is also supported by SOPC Builder, the system-level design and integration tool. To increase the understanding of SoC design methodology and promote its take up by the design engineers and researchers early in their careers, Altera has been successfully conducting an annual Nios Student Design Contest for the Asia-Pacific region. This positive initiative from Altera has encouraged some of the best young talents in the educational institutions in this region to produce exceptionally innovative designs for many challenging DSP and embedded systems problems requiring SoC solutions. Dr. Saeid Nooshabadi Senior Lecturer University of New South Wales, Australia ii Contents Consumer Applications High-Speed Image Evidence Collector Based on Dual Nios II Soft Core Processors, First Prize Lu Xiaofeng, Wu Bainian, and Huang Yan, School of Communication and Information Engineering, Shanghai University.................................................................................................... 1 Passive Digital Camera, First Prize Ji Won Kim, Doe-Hoon Kim, and Seung-Chul Shin, Hanyang & Yonsei University .................... 15 Nios II Processor-Based Hardware/Software Co-Design of the JPEG2000 Standard, Second Prize Mike Dyer, Amit Kumar Gupta, and Natalie Galin, University of New South Wales .................... 24 Embedded Network MP3 Playing System, Second Prize Cai Suwei, Xiao Xingjie, Zhang Jiahao, Southern Taiwan University of Technology ................... 37 Implementation of the H.264/AVC Decoder Using the Nios II Processor, Second Prize Im Yong Lee, Il-Hyun Park, and Dong-Wook Lee, Seoul National University ............................. 67 Spectral Estimation Using a MUSIC Algorithm, Third Prize Jawed Qumar, Indian Institute of Technology, Kanpur.................................................................. 74 Nios II Soft Core-Based Full-Color LED Music Sight Light Control System, Third Prize Zhong Qiubo, Gao Junfeng, and Liu Xiaoping, Harbin University of Science & Technology....... 89 3-D Accelerator on Chip, Third Prize Young-Hee Won, Jin-Sung Park, Woo-Sung Moon, Donga & Pusan University ....................... 109 Industrial Applications Cryptographic Algorithm Using a Multi-Board FPGA Architecture, First Prize G. Ananth and U.S. Karthikeyan, Indian Institute of Technology, Chennai................................. 118 SOPC-Based Word Recognition System, Second Prize S. Venugopal, B. Murugan, S.V. Mohanasundaram, National Institute Of Technology, Trichy .... 136 Intelligent Card Technology-Based Biometrics Identification System, Second Prize Tang Hui, Liu Lulu, and Qin Lunming, Institute of Information Science, School of Computer, Beijing JiaoTong University......................................................................................................... 165 iii Nios II Embedded Processor Design Contest—Outstanding Designs 2005 Real-Time Driver Drowsiness Tracking System, Second Prize Wang Fei, Cheng Huiyao, Guan Xueming, School of Electronic and Information, South China University of Technology.............................................................................................................. 179 High Aberrance AES System Using a Reconstructable Function Core Generator, Third Prize Chen Jian-Hong, Liu Yu, and Shiu Chia-Hau, Department of Computer Science and Information Engineering, I-Shou University ............................................................ 189 Wireless Multifunction Digital Storage Center, Third Prize Chen Zhuo, Dai Nan, and Fang Dongyu, Beijing University of Industry ..................................... 210 Nios II Soft Core-Based Double-Layer Digital Watermark Technology Implementation System, Third Prize, Lian Jiezhen and Ye Qingfeng, China University of Science and Technology......... 217 Portable Vibration Spectrum Analyzer, Third Prize Zhang Xinxi, Song Zhuzhen, and Yao Zongzhong, Institute of PLA Armored Force Engineering .................................................................................................................................. 228 SOPC-Based Servo Control System for the XYZ Table, Third Prize Dai Fuyu, Cai Xing’an, and Chen Jiasheng, Motor Engineering Research Institute,
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