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ELEC3221 Digital IC & Sytems Design Iain Mcnally Koushik Maharatna Digital IC & Sytems Design • Assessment • Books D

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ELEC3221 Digital IC & Sytems Design Iain Mcnally Koushik Maharatna Digital IC & Sytems Design • Assessment • Books D ELEC3221 Digital IC & Sytems Design Iain McNally Integrated Circuit Design Digital IC & Sytems Design Content • – Introduction – Overview of Technologies Iain McNally – Layout – CMOS Processing 15 lectures ≈ – Design Rules and Abstraction – Cell Design and Euler Paths Koushik Maharatna – System Design using Standard Cells – Wider View 15 lectures ≈ Notes & Resources • https://secure.ecs.soton.ac.uk/notes/bim/notes/icd/ 1001 1003 Digital IC & Sytems Design History Assessment 1947 First Transistor • John Bardeen, Walter Brattain, and William Shockley (Bell Labs) 10% Coursework L-Edit Gate Design (BIM) 90% Examination 1952 Integrated Circuits Proposed Geoffrey Dummer (Royal Radar Establishment) - prototype failed... Books • 1958 First Integrated Circuit Integrated Circuit Design Jack Kilby (Texas Instruments) - Co-inventor a.k.a. Principles of CMOS VLSI Design - A Circuits and Systems Perspective 1959 First Planar Integrated Circuit Neil Weste & David Harris Robert Noyce (Fairchild) - Co-inventor Pearson, 2011 1961 First Commercial ICs Digital System Design with SystemVerilog Simple logic functions from TI and Fairchild Mark Zwolinski 1965 Moore’s Law Pearson Prentice-Hall, 2010 Gordon Moore (Fairchild) observes the trends in integration. 1002 1004 History History Moore’s Law Moore’s Law; a Self-fulfilling Prophesy Predicts exponential growth in the number of components per chip. The whole industry uses the Moore’s Law curve to plan new fabrication facilities. 1965 - 1975 Doubling Every Year Slower - wasted investment In 1965 Gordon Moore observed that the number of components per chip had Must keep up with the Joneses2. doubled every year since 1959 and predicted that the trend would continue through to 1975. Faster - too costly Moore describes his initial growth predictions as ”ridiculously precise”. Cost of capital equipment to build ICs doubles approximately ev- ery 4 years. 1975 - 201? Doubling Every Two Years In 1975 Moore revised growth predictions to doubling every two years. Moore’s law is not dead (at least not quite), although there are worries that below 20nm, Growth would now depend only on process improvements rather than on clever processing required for smaller transistors means that cost per transistor is going more efficient packing of components. up rather than down. In 2000 he predicted that the growth would continue at the same rate for an- How will you future engineers increase the number of transistors? other 10-15 years before slowing due to physical limits. 2or the Intels 1005 1007 History Moore’s Law at Intel1 18−core Xeon E5 v3 10,000,000,000 72−core Dual Core Itantium 2 10−core XeonXeon Phi 1,000,000,000 Itantium 2 Westfield−Ex Itantium 100,000,000 Pentium 4 Pentium III 10,000,000 Pentium II Pentium 1,000,000 486 DX 286 386 100,000 8086 10,000 4004 8080 8008 1,000 1970 1980 1990 2000 2010 1Intel was founded by Gordon Moore and Robert Noyce from Fairchild 1006 1947 Point Contact transistor1961 Fairchild Bipolar RTL RS Flip−Flop (4 Transistors) Source: Bell Labs Source: Fairchild Moore’s Law (1965) Number of transistor has doubled every year and will continue to do so until 1975 Moore’s Law (1975) Number of transistors will double every two years 18−core Xeon E5 v3 10,000,000,000 72−core Dual Core Itantium 2 Xeon Phi 1,000,000,000 10−core Xeon Itantium 2 Westfield−Ex Itantium Self−fulfilling 100,000,000 Prophecy Pentium 4 Pentium III 10,000,000 Pentium II Pentium 1,000,000 486 DX 286 386 100,000 8086 10,000 4004 8080 8008 1,000 1970 1980 1990 2000 2010 1000 Overview of Technologies Overview of Technologies Components for Logic All functions can be realized using only the NOR gates1 available in the RTL logic 2 Diode family. PN Bipolar Transistors N P P N N P MOS Transistors Enhancement Depletion Silicon Oxide Insulator G G N−Channel SD SDNNP SUB SUB P−Channel 1Note that an inverter is a special case of a NOR gate with only one input. Field induced N−channel 2NAND gates could be used instead for logic families which support only NAND gates. 2001 2003 Overview of Technologies Overview of Technologies Other Bipolar Technologies TTL NAND Gate ECL OR/NOR Gate A A Z Z B B Z RTL Inverter and NOR gate VCC VCC Z VCC A VCC A A Z Z Z Z B B AB Z Z A AB VEE TTL gives faster switching than RTL at the expense of greater complexity3. The • characteristic multi-emitter transistor reduces the overall component count. ECL is a very high speed, high power, non-saturating technology. • 3Most TTL families are more complex than the basic version shown here 2002 2004 Overview of Technologies Overview of Technologies NMOS - a VLSI technology. CMOS logic V V DD DD CMOS - state of the art VLSI. A A Z Z VDD B B V Z Z DD A AZ A Z AB B Circuit function determined by series/parallel combination of devices. • Depletion transistor acts as non-linear load resistor. • An active PMOS device complements the NMOS device giving: Resistance increases as the enhancement device turns on, thus reducing power • consumption. – rail to rail output swing. The low output voltage is determined by the size ratio of the devices. – negligible static power consumption. • 2005 2007 Overview of Technologies Digital CMOS Circuits Alternative transistors representations for NMOS circuits Alternative transistor representations for CMOS circuits VDD VDD VDD VDD VDD V N−Channel DD P−Channel Depletion Enhancement Z Z Z Z Z A A A A A N−Channel Enhancement N−Channel Enhancement B B B B B Digital CMOS circuits4 tend to use simplified symbols like their NMOS counter- parts. Various shorthands are used for simplifying NMOS circuit diagrams. In general substrate connections are not drawn where they connect to Vdd Substrate connections need not be drawn since all must connect to Gnd. • • (PMOS) and Gnd (NMOS). Since source and drain are indistinguishable in the layout, there is no need to • All CMOS devices are enhancement mode. show the source on the circuit diagram. • Transistors act as simple digitally controlled switches. Note that schematic tools not designed for IC design will usually include inappropriate • 3-terminal symbols. 4in analog CMOS circuits we may have wells not connected to Vdd/GND 2006 2008 Digital CMOS Circuits Digital CMOS Circuits Compound Gate Example Static CMOS complementary gates A A A Z B Z B Z VDD B C C Pull Up Network ,,, Symbol A B Z C D Pull Down Network ,,, For any set of inputs there will exist either a path to Vdd or a path to Gnd. GND • 2009 2011 Digital CMOS Circuits Compound Gates A A B B Z C D Z C E F All compound gates are inverting. • Realisable functions are arbitrary AND/OR expressions with inverted output. • 2010 RTL NOR Gate TTL NAND Gate ECL OR/NOR Gate A Z Z A A B Z B B Z VCC VCC VCC Z Z AB A Z Z B AB VEE NMOS Compund Gate CMOS Compund Gate VDD VDD A A B B Z Z C C Bipolar Transitors with Resistors - MSI/LSI • RTL - NOR TTL - NAND ECL - OR/NOR MOS Transistors (no resistors) - VLSI • NMOS CMOS - No static power! Both allow construction of NOR, NAND & Compound gate (always inverting) 2000 Components for IC Design Components for IC Design Diodes and Bipolar Transistors MOS Transistors Diode Simple NMOS Transistor Thin Oxide Polysilicon G Thick Oxide PN G G S D P N NN SD S NNP D P−substrate SUB SUB SUB P N G Ideal structure - 1D Polysilicon Mask • SD Real structure - 3D • Active Area Mask Depth controlled implants. • 3001 3003 Components for IC Design Components for IC Design Diodes and Bipolar Transistors Simple NMOS Transistor NPN Transistor Active Area mask defines extent of Thick Oxide. • EBC Polysilicon mask also controls extent of Thin Oxide (alias Gate Oxide). • N PN N N-type implant has no extra mask. P N • – It is blocked by thick oxide and by polysilicon. – The implant is Self Aligned. Substrate connection is to bottom of wafer. • EBC – All substrates to ground. NPN Gate connection not above transistor area. • – Design Rule. Two n-type implants. • 3002 3004 Interconnect Components for IC Design Contact Via Metal 2 Layer Resistors Metal 1 Layer Examples for Metal Example for Polysilicon assuming Rs = 0.1 ohms per square assuming Rs = 200 ohms per square N 1 1 2 3 45 6 7 8 9 10 R = 1 1 2 3 4 5 6 7 8 9 10 3 18 17 16 15 14 13 12 11 2 19 420 21 22 23 24 25 26 27 5 R = R = 28 7 36 35 34 33 32 31 30 29 6 37 8 38 39 40 41 42 43 44 45 46 Contact Window Mask Via 1 Mask R = Polycrystaline Silicon (Polysilicon/Poly) Conductors: Diffusion (controlled by Active Area Mask) Metal 1 Metal 2 for larger resistances we need minimum width poly (often combined with a • Crossing conductors on different masks do not interact1. serpantine shape) to save on area • - Explicit contact/via is required for connection. corner squares count as half2 squares • Crossing conductors on the same mask are always connected. for predicatability and matching we may need wider tracks without corners • • 1the exception to this rule is that polysilicon crossing diffusion gives us a transistor 2effective resistance 0.56R ≈ s 3005 3007 Interconnect Components for IC Design Resistance Capacitors ρ l R = B w t t w w s where ρ is the resistivity constant 8 l 3.2 10− Ωm for aluminium l A × 8 1.7 10− Ωm for copper B fringe capacitor × B Since t and ρ are fixed for a paricular mask layer, the value that is normally used is A A ρ the sheet resistance: Rs = t .
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