High-Performance Printable Electronics for Memory and Neuromorphic Application

Home , Printed electronics

Jason Yong Hsien Ming

Submitted in partial fulfilment of the requirements of the degree of Doctor of Philosophy

February 2019

Department of Electrical and Electronic Engineering

School of Engineering

THE UNIVERSITY OF MELBOURNE

Abstract

Solution-process or printable electronics is a potentially new disruptive technology that well suited for the fabrication of low-cost, high performance and transparent electronics with superior compatibility with various available substrates. Present-day conventional complementary metal oxide semiconductor (CMOS) technologies can integrate billions of transistors and contribute to an impressive amount of computational horsepower. Notwithstanding their superior performance, a typical lithographic mask set for the current generation central processor units at a 14 nm CMOS technology node costs approximately $USD 18 million, with wafer production costing nearly $USD 10,000. The total cost of the designing a new 7 nm system on a chip (SoC) exceeds $USD 270 million. The high cost of building electronics is a significant barrier to innovation, and thus new architectures and fabrication methods for low-cost electronics design and fabrication are a research priority area.

Over the past several years, tremendous progress in printing technologies is achieved through various schemes. For instance, novel solution process-based methods are extensively investigated for manufacturing electronics with applications in flexible and wearable devices. For this work, we will be focusing on developing the understanding and techniques for the realisation of printable bio-compatible and bio-degradable electronics. To achieve this, the study will consider various deposition techniques including the usage of new materials to investigate their electrical or chemical properties as well as their feasibility in constructing next-generation electronic components for high-speed applications, medical applications, and other general-purpose applications.

In the first section of this thesis, we will be studying silk fibroin proteins which offer exceptional good mechanical, optical and electrical properties concerning various organic polymer from the aspect of cost and simplicity of handling. We will be fabricating and characterising solution processed memristive devices using silk fibroin as the primary active switching material. It was observed to exhibit significant and consistent bipolar resistive switching characteristics for the Au-Silk Fibroin-Au, Ag-Silk Fibroin-Au and Au break junction memristive devices. In addition to that, experimental observation and physical model of the switching behaviour is proposed in this research to support the idea that the growth and dissolution of conductive filament plays a significant role. In the interest of broadening the use case of silk fibroin memristor devices, we will also be developing the SPICE model and utilising unorthodox logic architectures to perform logical operations. The advancement in silk

ii fibroin-based electronic devices would likely open up new avenues for research into the integration of biocompatible electronics.

Lastly, the realisation of a single transistor, capable of emulating neuronal functioning, is key to the design and fabrication of a highly efficient neural network. In recent years, several research groups have been investigating the various form of electronic devices to achieve similar functionality using resistive switching memristors, electrolyte-gated thin film transistors or hysteresis engineering of transistors. The fabrication of these devices has been heavily reliant on vacuum processes such as a chemical or physical vapour deposition which requires highly specialised equipment and laboratories which may not be readily available due to the high operational cost. Thus, this thesis also investigates the potential of using electrohydrodynamic (EHD) printing techniques to construct electrolyte-gate transistors (EGFET) for the used in artificial neural networks as a low-cost, rapid prototyping approach. The presented experimental outcomes show the emulation of neuronal functions namely, the spike-timing-dependent plasticity, the paired-pulse facilitation, and the dynamic filtering capabilities.

iii

Declaration

This is to certify that:

I. The thesis comprises only my original work towards the PhD except where

indicated in the Preface,

II. Due acknowledgement has been made in the text to all other materials used,

III. The thesis is fewer than 100 000 words in length, exclusive of tables, maps,

bibliographies and appendices.

Signed

Date

23/01/2019

iv Acknowledgement

First and foremost, I would like to convey my sincere gratitude to my principal supervisor Prof. Efstratios Skafidas, for his support throughout the PhD candidature. This thesis would not be possible without his advice and guidance. I would also like to acknowledge helpful suggestions from my co-supervisors and committee members: Dr Ranjith Rajasekharan Unnithan, Dr Babak Nasr and A. Prof. YingTan.

I would like to express my gratitude to the staffs from Experimental Condensed Matter Physics group, Dr Kumaravelu Ganesan for their significant support for the fabrication of the electronic devices presented in this work. I would also like to thank A. Prof. Jing Liang Li from the Institute for Frontier Materials for his help and support with the fabrication of the silk fibroin memristor device.

I would also like to thank the research team in the Centre for Neural Engineering, Dr.Sharafat Hossain, Dr Babak Nasr, Dr Gursharan Chana, Mr You Liang, Mr Yang Yu and others for their company, collaborations and discussion.

Lastly but not least, I would like to thank my parents for their unconditional care and support.

Preface

All the work presented were conducted as part of the PhD candidature at the Centre for Neural Engineering, University of Melbourne, Australia. The fabrication of the solution processed electronics in this work was carried out at the Centre for Neural Engineering in conjunction with the Experimental Condensed Matter Physics group, School of Physics, University of Melbourne and MicroNano Research Facility, Royal Melbourne Institute of Technology.

The work in chapter 3 presents an original work performed during the course of the Ph.D. candidature. All derived work has been suitably acknowledged and cited.

The work in chapter 4 is adapted from my publication: Yong, J., Hassan, B., Liang, Y., Ganesan, K., Rajasekharan, R., Evans, R., Egan, G., Kavehei, O., Li, J., Chana, G., Nasr, B and E Skafidas “A Silk Fibroin Bio-Transient Solution Processable Memristor”. Scientific reports, 7(1), p.14731, 2017. In this work, all co-authors have contributed in analysing and providing research feedback on the experimental outcome. My contribution to this publication was 80%. This publication was accepted for publication by Scientific Report on November 2017.

The work in chapter 5 is adapted from my publication Jason Yong, You Liang, Yang Yu, Md Sharafat Hossain, Andrew Walla, Kumaravelu Ganesan, Ranjith Rajasekharan, Jingliang Li, Babak Nasr and Efstratios Skafidas “Solution-processed organic silk fibroin memristor for resistive logic applications”. In this work, all co-authors have contributed in analysing and providing research feedback on the experimental outcome. My contribution to this publication was 80%. This publication is in revision following peer review by the journal ACS Applied Interfaces and Materials.

The work in chapter 6 is adapted from my publication : : Jason Yong, You Liang, Yang Yu, Basem Hassan, Md Sharafat Hossain, Kumaravelu Ganesan, Ranjith Rajasekharan, Robin Evans, Gary Egan, Gursharan Chana, Babak Nasr and Efstratios Skafidas. “Fully Solution- Processed Transparent Artificial Neural Network using Drop-on-demand Electro- hydrodynamic Printing.” In this work, all co-authors have contributed in analysing and providing research feedback on the experimental outcome. My contribution to this publication was 80%. This publication has been submitted for publication to IEEE Transactions of Electron Devices on January 2019.

List of Figures

Figure 2-1 Typical printable electronics process throughput and feature resolution (Adapted from [10]) ...... 7 Figure 2-2 Piezo element movement for shear-mode ink-jet actuator (Left). Various configuration of thermal ink-jet actuators (Right). (Adapted from [12]) ...... 8 Figure 2-3 Viable ink-jet process route for printable electronics:(A) Direct deposition of functional materials;(B) Deposition of masking layer followed by deposition of functional materials;(C) Selective etching via ink-jet deposition.(Adapted from [12]) ...... 9 Figure 2-4 Illustration depicting the screen-printing process and stencil distortion observed in a printing stroke. (Adapted from [11]) ...... 10 Figure 2-5 Schematic diagram of a gravure printing process. (Adapted from [23]) ...... 11 Figure 2-6 Schematic diagram of a R2R manufacturing process which integrates both vacuum and non-vacuum processes. (Adapted from [24]) ...... 12 Figure 2-7 Time-lapse images of the transformation of the ink meniscus due to an applied voltage. (Adapted from [27]) ...... 13 Figure 2-8 (a) Fabrication of a nanoscale pillar using silver colloidal solution. Scale bar, 1 µm. (b) Optical image of EHD printed transistor on a PI substrate. Scale bar, 50 µm. (Adapted from [33], [34]) ...... 14 Figure 2-9 Photograph showing a 1T1R (single transistor-single memristor configuration) memristor crossbar array integrated with a CMOS-based logic circuitry. (Adapted from [37]) ...... 15 Figure 2-10 Scanning electron microscope (SEM) image of the cross section for the Sericin memristor. (Adapted from [38]) ...... 16 Figure 2-11 Photo-activation of solution-processed metal-oxide semiconductors by deep ultraviolet radiation. Light blue shading illustrates the illumination from the arrays of low- pressure mercury lamps. (Adapted from [51]) ...... 18

Figure 2-12 Schematic layout of an In2O3 nanoparticles based electrolytic gated TFT and the HIM images of the device channel. (Adapted from [53]) ...... 19 Figure 3-1 (a) Relationship between four fundamental electrical quantities. (b) Scanning tunnelling microscope of crossbar memristor structure by Hewlett Packard. (Adapted from [36], [59]) ...... 24

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Figure 3-2 IV characteristics for the switching characteristics of (a) bipolar memristor and (b) unipolar memristor. Red lines denote the LRS and Green lines denotes the HRS...... 26 Figure 3-3 (a) Optical image of a silk fibroin memristive device interposed between two gold electrodes. (b) I-V characteristics of the Au-Silk Fibroin-Au memristive device ...... 26 Figure 3-4 (a) Pristine Au electrodes with 50 µm gap embedded with silk fibroin film. (b) Observation of formation and retention of dendritic structure following the application of 40V...... 27 Figure 3-5 Optical image of the fabricated silver-silk fibroin-gold crossbar memristor device...... 28 Figure 3-6 Switching characteristics of the memristor device showing consistent transition between the low resistance and high resistance state throughout 50 switching cycles...... 28 Figure 3-7 I-V characteristics for Ag-Silk Fibroin-Au memristor devices stimulated with a triangular voltage sweep (in the direction of 1→4) with a current compliance of 1mA (2mA or 3mA for some devices). (a) Typical IV characteristics for ±1V triangular waveform. (b) IV curve for higher on-off switching ratio (>5 order of magnitude) observed on several devices for ±1.5V triangular applied voltage. (c) IV curve for lower on-off switching ratio (≈1 order of magnitude) observed on several devices for ±1V triangular applied voltage. (d) Switching oscillations between on and off states. (e) Failure mode for the memristor devices which exhibits poor off-state characteristics or permanently persists in the on-state...... 29 Figure 3-8 (a) IV characteristics for the formation of an Au break junction. (b) Distribution of the breakdown voltage and current for the Au electrodes...... 30 Figure 3-9 Bipolar switching characteristics of Au/Silk Fibroin break junction device with a ±40V triangular sweeping voltage for junction gap size of (a) < 1µm and (b) > 1µm. Direction of the triangular sweeping voltage is as indicated by the numeric annotation (from 1 → 4) . 31 Figure 3-10 (a), (b), (c) HIM images showing the severe damage of the break junction Au electrodes. (d) Sub-micron break junction with a severely damaged electrode surface...... 31 Figure 4-1 Device structure and fabrication process of the silk fibroin memristor. (a) Photograph of an Au-Silk Fibroin-Pt crossbar memristor device fabricated on a PVA film. (b) Schematic illustration of the fabricated crossbar memristive device. (c) Flowchart illustrating the fabrication process for a bio-resorbable and biodegradation crossbar memristive device. The PVA substrate is drop-casted on a Teflon surface to ease substrate lift off and followed by the spin coating of PMMA to prevent dissolution during silk fibroin deposition. The bottom gold electrodes and top platinum electrodes are patterned via shadow mask e-beam evaporation whilst the switching layer is a solution processed silk fibroin...... 36 viii

Figure 4-2 Helium ion microscopy (HIM) images showing the cross-sectional image on the silk fibroin film interposed between metal electrodes. Imaging was performed via the Helium Ion Microscope, HIM (Carl Zeiss, Orion Nanofab, Peabody MA, USA) operating at an accelerating voltage of 30 and a beam current of approximately 1 pA...... 37 Figure 4-3 Device bio-resorbability and cytotoxicity characteristics. (a) Time sequence of the dissolution of the crossbar memristive device in DI water under ambient conditions. (b) Image of SY5Y neuroblastoma cells proliferating in the presence of the bio-resorbing memristors for 168 hrs. 103 cells/well was selected to be the standard seed cell number in the cytotoxicity test to study the effects of the constituent materials. (c) Time dependent curve for cell viability assessment in SH-SY5Y neuroblastoma cells in direct exposure to the memristive device. Indicated values are means of 8 experimental sets...... 38 Figure 4-4 Electrical characteristics of the silk fibroin memristive device. Measured IV characteristics of the crossbar memristive device fabricated on a glass substrate and a PVA substrate (centre). The Pt electrodes are set at 0 V and the Au electrodes are subjected to a ±5V, 1 Hz triangle voltage waveform with a current compliance of 1µA at room temperature. Photograph of an Au-Silk Fibroin-Pt crossbar memristive device on a glass substrate (left). Photograph of a free-standing Au-Silk Fibroin-Pt crossbar memristive device on a PVA substrate (right)...... 39 Figure 4-5 Surface topography of the silk fibroin film on a) glass substrate and b) PVA substrate. The silk fibroin film produced on the PVA substrate shows significantly larger surface roughness as compared to the silk fibroin film deposited on the glass substrate. The larger surface roughness originates from the Teflon substrate used to ease the lift of process of the silk fibroin film. Imaging were performed using the Agilent 5500 atomic force microscope. 40 Figure 4-6 Endurance characteristics and performance of the silk fibroin memristive device. (a) Endurance characteristics for the untreated and the water annealed Au/SF/Ag memristive devices. (b) Endurance performance of the fabricated memristive device with various combinations of electrode materials, namely, Au-Ag, Au-Pt and Au-Cu. (c) Endurance characteristics for the Au/SF/Ag device with current compliance level of 1 mA and 1 µA. (d) State retention time for the fabricated memristive device with various Au-Ag, Au-Pt and Au- Cu electrode combinations over the course of 96 hrs...... 42 Figure 4-7 FTIR-ATR spectrum of the water annealed and untreated silk fibroin film. It shows -1 -1 the absorption strength ratio of the spectrum 1265 cm and 1235 cm (A1265 / A1235) which is commonly used to determine the crystallinity index. The water annealed silk fibroin films

ix obtained a higher crystallinity index of 0.80 whereas the untreated films had an index of 0.71...... 43 Figure 4-8 Helium ion microscopy (HIM) images showing formations of cracks in untreated silk fibroin film sandwiched between metal electrodes. The bright contrast between the metal electrodes indicates the penetration defects within the silk fibroin silk during the evaporation process. Imaging was performed via the Helium Ion Microscope, HIM (Carl Zeiss, Orion Nanofab, Peabody MA, USA) operating at an accelerating voltage of 30 and a beam current of approximately 0.19 pA. Surface charge compensation achieved with support of the electron flood gun...... 44 Figure 4-9 IV characteristics for an Au-Silk Fibroin-Ag memristor showing the earlier and subsequent cycles. The subsequent read-write cycles show less distinctive off and on resistance state as the memristive device approaches the endurance limit...... 45 Figure 4-10 Chrono-amperometry for Au-Ag electrodes with a bias voltage of 0.8 V to 1 V. The blue, black and green solid line represents a bias voltage of 0.8V, 0.9V and 1.0V respectively. These chrono-amperometry measurements were performed with an ambient temperature of 25 °C, 80 °C, 120 °C and 160 °C...... 45 Figure 4-11 Chrono-amperometry for Au-Pt electrodes with a bias voltage of 1.5 V to 2.5 V. The red, green and black solid line represents a bias voltage of 1.5V, 2.0V and 2.5V respectively. These chrono-amperometry measurements were performed with an ambient temperature of 25 °C, 80 °C, 120 °C and 160 °C...... 46 Figure 4-12Chrono-amperometry for Au-Cu electrodes with a bias voltage of 3.5 V to 4.5 V. The red, green and black solid line represents a bias voltage of 3.5V, 4.0V and 4.5V respectively. These chrono-amperometry measurements were performed with an ambient temperature of 25 °C, 80 °C, 120 °C and 160 °C...... 46 Figure 4-13 State transition time-temperature characteristics of the memristive device and corresponding Arrhenius plot. Arrhenius plot of the measured transition time at different electric potential with various combination of active-inert electrode material: (a) Au-Ag with an applied voltage of 0.8V, 0.9V and 1.0V (b) Au-Cu with an applied voltage of 3.5V, 4.0V and 4.5V (c) Au-Pt. with an applied voltage of 1.5V, 2V and 2.5V. These measurements were extracted from the chrono-amperometry measurements with varied ambient temperature of 25 °C, 80 °C, 120 °C and 160 °C. Indicated values are mean of 10 devices each. See supplementary materials for details. (d) Comparisons of the cyclic voltammograms for various electrodes as shown in the legends. The scan speed is 50 mV/s...... 47 Figure 4-14 Optical image showing the dimension of the crossbar memristive device...... 48 x

Figure 4-15 Simulation geometry definition and process flow. (a) Simulated geometry used in the numerical solver. (b) Simulation algorithm flowchart...... 52 Figure 4-16 Comparison between numerical simulation and experimental IV characteristics of the set/reset process for different combinations of electrode material (a) Cu-Au electrodes (b) Au-Ag electrodes (c) Pt-Au electrodes. The blue dashed curve represents with experimental results; (the black solid line represents experiments while the dashed line shows simulation results). Geometrical and physical parameters are listed in Figure 4-15 and Table 4-3...... 54 Figure 4-17 Surface plot for the temperature distribution and morphology of the conductive filament. The illustration shows the sequential cycle of the SET/RESET process for an applied voltage of (a) 0V, (b) -0.2V, (c) -0.3V, (d) -0.5V, (e) 0.5V, (f) 0.7V using parameters for the Au-Ag electrodes...... 56 Figure 5-1 (a) Optical image of the fabricated 16x16 memristor device array. The crossbar structure is both 15 mm in width and length. (b) Helium ion microscopy (HIM) images showing the cross-sectional image on the silk fibroin film interposed between metal electrodes operating at an accelerating voltage of 30 and a beam current of approximately 1 pA. Scale bar, 100 nm...... 62 Figure 5-2 Typical experimental and numerically modelled IV (current-voltage) characteristics of the fabricated silk fibroin device...... 63 Figure 5-3 (a) Endurance performance of the silk fibroin memristor. (b) State retention time for the fabricated memristors over the course of 96 hrs. The resistance states were measured with an applied voltage 0.5V...... 64 Figure 5-4 The simulation data demonstrating stimulation voltage waveform of the material implication process as well as the subsequent input and output resistance state for a single memristor logic cell...... 67 Figure 5-5 Proposed structure for the implication logic based nth bit subtraction circuit...... 68 Figure 5-6 Excitation voltage waveform for the 1-bit full subtractor circuit with respect to the input, output and intermediate memristor elements for individual stages of the computational process. The red and cyan highlighted waveform indicates the set and conditional pulse for the imply operation respectively whereas the green highlighted waveform indicates the memristor reset process...... 69 Figure 5-7 Simulation data showing the resistance state of the input and output memristor of the proposed full subtraction circuit for all input combination specifically (a) A=0, B=0, BO-

1=0; (b) A=0, B=0, BO-1=1; (c) A=0, B=1, BO-1=0; (d) A=0, B=1, BO-1=1; (e) A=1, B=0, BO-

1=0; (f) A=1, B=0, BO-1=1; (g) A=1, B=1, BO-1=0; and (h) A=1, B=1, BO-1=1 where A is the xi minuend, B is the subtrahend, BO-1 is the borrow in, BO is the borrow out and S is the difference...... 72 Figure 5-8 Proposed structure for the implication logic based nth division circuit...... 73 Figure 5-9 Simulation data showing the resistance state of the input and output memristors of the proposed division circuit for a subset of input combinations specifically (a) A=111, B=10; (b) A=110, B=10; (c) A=110, B=11 and (d) A=101, B=10 in which A , B , Q and R denotes the dividend, divisor, quotient and remainder respectively...... 74 Figure 6-1 Schematic representation of the fully solution processed synaptic network using metal salt combustion precursors and the transistor morphology. (a) ITO solutions were initially spin coated on a glass substrate and thermally annealed. (b) The source, drain and gate electrodes for the co-planar transistor structure was defined by direct write laser-lithography and wet-etching. (c) An EHD deposition technique was used to define the n-type In2O3 channel followed by (d) the deposition of sodium alginate electrolyte using a glass pipette to realise the transistor device. (e) Optical image of the deposition process. Scale bar, 100 μm. (f) Optical image showing the array of transistors...... 80 Figure 6-2 Schematic diagram of the electro-hydrodynamic printer. Schematic diagram of the EHD deposition set-up with the Cr-coated glass pipette connected to the high voltage terminal and an aluminium heat plate acting as the counter electrode. The camera assembly consists of an Imaging Development Systems GmbH USB camera mounted on a Mitutoyo zoom lens and a 10× objective...... 81 Figure 6-3 150μm printhead used to accentuate the four-component cycle of the electrohydrodynamic mechanism for illustration purposes. (a) Taylor cone formation and droplet deposition phase. (b) Relaxation phase of liquid meniscus. Alignments line were drawn to highlight the shape of the liquid meniscus...... 82 Figure 6-4 Optical profilometry measurement of the fabricated electrolyte gated transistors. (a), (b) show the optical images of the fully solution processed EGFET with different width and length (Wa/La ≈ 420 μm / 115 μm, Wb/Lb ≈ 200 μm / 90 μm, Wc/Lc ≈ 100 μm / 90 μm). Scale bar, 200 μm...... 83 Figure 6-5 Helium ion microscopy (HIM) images showing the dimensions of a single printed conductive trace using the EHD deposition system. Imaging was performed via the Helium Ion Microscope, HIM (Carl Zeiss, Orion Nanofab, Peabody MA, USA) operating at an accelerating voltage of 30 and a beam current of approximately 0.19 pA. Surface charge compensation achieved with support of the electron flood gun. Scale bar, 1 μm...... 83

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Figure 6-6 Electrical measurement of the transfer characteristics of the electrolytic gated transistors. (a) Cyclic ID-VG transfer characteristic curve and (b) ID-VD output characteristic curve of the fabricated transistor (W/L = 4). (c) and (d) Optical profilometry images of the fabricated transistors with a W/L ratio of 4 and 1 respectively. Scale bar, 400 μm...... 84 Figure 6-7 Transfer and output characteristics of the fabricated EGFETs with different dimensions. (a), (d) show the transfer and output characteristics for transistor with width, 100 μm and length, 90 μm. (b), (e) show the transfer and output characteristics for transistor with width, 200 μm and length, 90 μm. (c), (f) show the transfer and output characteristics for transistor with width, 420 μm and length, 115 μm...... 85

Figure 6-8 Composition and material analysis of the In2O3, ITO and sodium alginate film. (a) This graph presents the FTIR absorption versus wavenumber of a desiccated sodium alginate film coated on a quartz substrate. (b) Transmittance spectrum of the synaptic network circuit fabricated on a glass substrate indicates the optical clarity of the device. (c), (d) XPS wide-scan analysis spectral of the In2O3 and ITO films...... 86 Figure 6-9 XPS spectra of the In2O3 and ITO film. (a), (c) shows the corresponding peaks for the hydroxyl species, oxygen vacancies (Ovac) and lattice oxygen (M-O) for In2O3 and ITO respectively. (b), (d) show the corresponding peaks for In3d5/2 and In3d3/2 states for In2O3 and ITO respectively. (e) shows the corresponding peaks for the Sn3d5/2 and Sn3d3/2 states of the ITO film...... 87 Figure 6-10 Electrical characteristics of the fabricated metal oxide transistors. Transfer characteristics curve for (a) SiO2 back gated transistor and (b) precursor based Al2O3 back gated transistor. (c) shows the capacitance-frequency curve of the metal oxide dielectrics and the sodium alginate electrolyte. (d) shows an image of the back gated transistors...... 89

Figure 6-11 Optical profilometry of the sol-gel In2O3 film. (a) 3D reconstruction for the cross section of the In2O3 film. (b) Extracted profile along the film surface as indicated...... 90

Figure 6-12 Optical profilometry of the sol-gel Al2O3 film. (a) 3D reconstruction for the cross section of the Al2O3 film. (b) Extracted profile along the film surface as indicated...... 90 Figure 6-13 Performance characteristics of the fabricated metal oxide transistors. (a), (b) and (c) illustrate the statistical distribution of the mobility, sub-threshold swing and threshold voltage respectively for the SiO2 and precursor based Al2O3 back gated as well as the sodium alginate electrolytic gated transistor transistors...... 91 Figure 6-14 Excitatory post-synaptic current. (a) Poisson distributed pre-synaptic spike train (λ-1 = 10 ms). (b) EPSC response triggered by the applied spike train. (c) Biological synapse and the analogous transistor based artificial synapse...... 92 xiii

Figure 6-15 EPSCs responses triggered by a stimulus train for transistor of different dimensions. (a) Poisson distributed input spike train with a λ-1 of 10 ms. (b), (c) show the corresponding

EPSC response for transistors of Wb/Lb ≈ 100 μm / 90μm and Wc/Lc ≈ 200 μm / 90 μm respectively...... 93 Figure 6-16 Short term plasticity exhibited by fabricated synaptic transistors. (a), i Pre-synaptic spike pairs with a time interval, Δt. (a), ii EPSC response from the pre-synaptic spike pairs. (b) Paired pulse facilitation as a function of the pulse interval, Δt, for synaptic transistors of various device dimensions (width and length of the transistor is denoted by W and L respectively). (c) Measured EPSC triggered by spike trains of different frequency. (d) EPSC gain as a function for the spike trains of different frequency...... 94 Figure 6-17 Colour filtering algorithm implemented on an artificial spiking neural network. (a) Schematic diagram of the spike train decoding circuit with various size factor (W/L). The input and summation nodes are represented by the blue and green line respectively. (b), (c) and (d) represents the original, decoded all-colour and decoded red-only 100×100-pixel image respectively...... 95 Figure 6-18 Reconstructed images of the entire artificial neural network circuit with an optical profilometer and image stitching. (a) illustrates the artificial neural network with transistors of similar width and length. (b) illustrates the artificial the two pre-synaptic inputs of reduced transistor width. Scale bar, 2 mm...... 96

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List of Tables

Table 4-1 Electrode combination for silk fibroin memristors and their proposed switching mechanism...... 34 Table 4-2 Electrical, thermal and mechanical properties for Silk Fibroin. The following material properties are used in the simulation model to replicate the experimental data...... 54 Table 4-3 Numerical simulation fitting parameters. The following fitting parameters are used in the simulation model to replicate the experimental data...... 55 Table 5-1 Fitting parameters for the VTEAM model ...... 66 Table 5-2 Translation of material implication to the equivalent conventional logic operations ...... 67 Table 5-3 Computational steps for a full 1-bit memristive subtractor circuit ...... 70

Abbreviations

FET Field Effect Transistor

LRS Low Resistance State

HRS High Resistance State

CMOS Complementary Metal Oxide Semiconductor

SEM Scanning Electron Microscope

HIM Helium Ion Microscope

R2R Roll to Roll

IV Current Voltage

ANN Artificial Neural Network

EGFET Electrolyte Gated Field Effect Transistor

DOD Drop on Demand

RFID Radio Frequency Identification

DUV Deep Ultraviolet

EHD Electrohydrodynamic

ECM Electrochemical Metallisation

AFM Atomic Force Microscope

FTIR Fourier Transformed Infrared

XPS X-ray Photoelectron Spectroscopy

EDL Electric Double Layer

EPSC Excitatory post-synaptic current

PPF Paired Pulse Facilitation

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Table of Contents

Abstract ...... ii

Declaration...... iv

Acknowledgement ...... v

Preface ...... vi

List of Figures ...... vii

List of Tables ...... xv

Abbreviations ...... xvi

Table of Contents ...... xvii

1 Introduction ...... 1

1.1 Motivation ...... 1

1.2 Thesis Organisation ...... 3

1.3 Thesis Contribution ...... 4

1.4 Author’s publication ...... 5

2 Literature Review ...... 7

2.1 Solution Process Deposition Techniques ...... 7

2.1.1 Ink-jet Printing Deposition ...... 8

2.1.2 Flatbed Screen Printing Deposition ...... 10

2.1.3 Roll-to-roll (R2R) Printing Method ...... 11

2.1.4 Electrohydrodynamic Printing Method ...... 13

2.2 Solution-Processed Electronics ...... 15

2.2.1 Solution-Processed Memristors ...... 15

2.2.2 Solution-Processed Metal Oxide TFTs ...... 17

3 Memristors Physical Background and the Realisation of an Organic Memristor...... 23

3.1 Memristor Conduction Model ...... 25

3.1.1 Physical Model ...... 25

xvii

3.2 Metal-Insulator-Metal Memristor with Silk Fibroin ...... 26

3.3 Conclusion ...... 32

4 A Silk Fibroin Bio-Transient Solution Processable Memristor ...... 33

4.1 Introduction ...... 33

4.2 Results and Discussion ...... 36

4.2.1 Electrical and Material Characterisation ...... 36

4.2.2 Numerical Modelling for the Resistive Switching Mechanism ...... 49

4.3 Summary ...... 57

4.4 Methods ...... 58

4.4.1 Device Fabrication ...... 58

4.4.2 Cytotoxicity assessment ...... 59

4.4.3 Electrical Measurement ...... 59

4.4.4 Material Characterisation ...... 59

5 Solution Processed Organic Silk Fibroin Memristor for Resistive Logic Applications . 60

5.1 Introduction ...... 60

5.2 Device fabrication ...... 61

5.3 Device characterisation and Numerical Modelling ...... 63

5.4 Implication Logic ...... 66

5.5 Nth bit implication logic full subtractor ...... 68

5.6 Nth bit implication logic divisor ...... 72

5.7 Conclusion ...... 75

6 Fully Solution Processed Transparent Artificial Neural Network using Drop-on-demand Electro-hydrodynamic Printing ...... 77

6.1 Introductions ...... 77

6.2 Results and Discussion ...... 80

6.2.1 Fully solution processed electrolytic gated transistors...... 80

6.2.2 EGFET Characteristics...... 83

xviii

6.2.3 Comparison studies of In2O3 transistor performance with gating strategy...... 89

6.2.4 Emulation of synaptic functions on electrolytic gated transistors...... 91

6.2.5 Synaptic network for image processing...... 95

6.3 Summary ...... 97

6.4 Methods ...... 99

6.4.1 EHD printer configuration ...... 99

6.4.2 Metal oxide precursor solution synthesis ...... 99

6.4.3 Fabrication of electrolytic gated thin film transistors ...... 99

6.4.4 Material Characterisation and Electrical Measurement...... 100

7 Conclusion and Future Work ...... 101

7.1 Conclusion ...... 101

7.2 Future Work ...... 102

8 Reference ...... 104

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1 Introduction

1.1 Motivation Conventional CMOS fabrication technique is a complicated and expensive multi-step process. The general process scheme for CMOS devices involves the preparation of a silicon substrate, UV resists deposition, UV resists post-baking, UV exposure, pattern development, etching, UV resist stripping and other post-processing such as chemical-mechanical polishing, etc. These are just several of the fundamental steps required in the fabrication of conventional CMOS devices used in conjunction with other complex internal processes to ensure that the devices provide superior performance and fabrication yield for current generation electronics. CMOS processing is primarily a photo-lithography based etching process in which excess materials are removed to form the functional components, leading to high material wastage and ecological hazards. Besides that, the compatible substrates are limited to silicon wafers and other silicon derivatives. On the other hand, direct printing techniques allow for the streamlining of the electronic fabrication process with the two fundamental steps consisting of an additive process followed by other material specific post-processing steps. Thus, the wastage of materials and energy consumption in the manufacturing process can be drastically reduced. In addition to that, room temperature and near atmospheric pressure processing conditions typically associated with direct printing techniques minimizes the complexity of the manufacturing line as well as the machinery involved. Arguably, this is an oversimplified view of the direct printing technique, the prospect of utilising direct printing in the industry is nevertheless profound. In this research, we will be investigating primarily non-impact printing, also known as master-less printing/process.

Printable electronics presents a unique opportunity for the semiconductor industry to complement the conventional fabrication process for the reduction of material wastage and fabrication cost. In recent years, solution process methodologies have been intensively studied as these techniques require fundamentally new approach and materials as compared to more traditional vacuum-based processes. The critical motivations for printable electronics are the possibility of large area processing using either ink-jet based methods or roll-to-roll based processing methods, the reduction in the fabrication cost of micron or sub-micron scale electronics and the environmental compliance for fabricating disposable or one-off electronic devices. In addition, the rapid prototyping capabilities feasible with printable electronics can potentially reduce the entry barriers for the fabrication of low-volume integrated circuits. By 1 introducing newer functional processing materials, the lower capital expenditure, higher material compatibility and suitable substrate topology made possible through printable electronics such as OLEDs, thin/flexible solar cells, biosensing strips and so on. Thus, the versatility of this technology allows for the introduction of a variety of future generation electronics due to the possibility of constructing small form factor electronic devices which are roll-able, flexible as well as conformal. The sizeable target market for these potentially low- cost devices, owing to the processing method, makes them an exciting research field considering the current mainstream trends and the popularisation of newer forms of technology involving flexible wearable electronics, IoT (Internet of things) devices, human-machine interface technologies, medical implants and environmentally friendly electronics.

The recognition of the relevance of the printable electronics market has attracted various industrial and academic research on the feasibility and realisation of such devices. For instance, printable thin film transistors (TFTs) based electronics is reported to reach US$44.25 billion market value in 2021 [1]. Printable consumer grade electronic devices which include flexible displays, radio frequency identification tags, miniaturised monitors, solar cells and biosensors could be fabricated at a fraction of the typically associated cost. While it has yet to reach mainstream in the manufacturing general purpose electronics, printable electronics has established a strong presence in niche markets such as the solar photovoltaic industry in which large scale fully printable Perovskite Solar cells are undergoing extensive research with great commercialisation prospect [2], [3]. In addition, the display technologies industry has invested US$ 6.2 billion into the commercialisation of printable OLED (Organic Light Emitting Diode) displays panels by Samsung in partnership with DuPont [4]. Next-generation high-resolution Quantum Dot based display panels using solution based processes are currently being researched with extensive industrial, financial support [5]. Besides that, the Norwegian printed electronics company, Thin Film Electronics ASA, has developed a fully printable NFC (near field communication) tags as well as the standard RFID tags solutions for use as a tamper-proof product security labelling for product logistics and tracking as well as the monitoring of medical substance administration [6], [7].

In contrast to conventional CMOS processes, a multitude bio-compatible substrate can be used in conjunction with printable electronic techniques to fabricate embedded electronic devices for medical purposes which include, but not limited to silk fibroin substrate, polyethylene naphthalate sheet, PDMS (Polydimethylsiloxane) substrate and a collagen-based substrate. The usage of ink-jet printing technology provides several advantages over the

2 conventional lithography-based manufacturing methods due to their inherent non-contact process of ink-jet printing. This eliminates the interaction between the materials during the deposition/printing process which allows for the integration of novel bio-compatible materials in the field of electronics fabrication. Mass production of organic electronics has been demonstrated by ink-jet printing and screen-printing on cost-effective substrates such as plastics and papers as discussed in previous literature [8]. Moreover, organic electronics have ever since aligned itself for a niche market in low performance and low-cost devices such as disposable electronics and ultra-high-resolution display panels as mentioned previously.

Printing techniques offer a great potential as an exciting candidate for the rapid prototyping and research of novel circuit architectures using thin film transistors, organic memristors and electrolytic gated transistors. Over the past several years, tremendous progress in printing technologies has been made through various schemes. For instance, novel solution process- based methods have been extensively investigated for manufacturing electronics with applications in flexible and wearable devices. Unlike conventional technologies, they are fully additive fabrication processes, able to undertake large area batch electronic fabrication with the added benefit of significant flexibility in the choice of substrate. Furthermore, three- dimensional device architecture can be easily envisaged through vertically integrated solution process-based field effect transistors (FETs) which promises higher circuit density without the need for enhancement of the patterning resolution.

In this thesis, we will be investigating present-day fabrication techniques in the development of solution-processed electronics and will be utilising these techniques to create novel new circuit architecture as well as the characterisation of their fundamental properties and electrical performance.

1.2 Thesis Organisation The thesis is organised as follows:

Chapter 1 provides the introduction and motivation for the research and development of solution-process based electronics.

Chapter 2 provides a literature review on the current research progress in the field of printable electronics. A brief overview of both conventional and novel printing methodologies are introduced. Additionally, this chapter presents on the various material and fabrication techniques specifically for solution-processed memristor device and transistor.

Chapter 3 discusses the physical models governing the memristive switching mechanism of a memristor device. This chapter reveals experimental findings to substantiate the resistive switching mechanism behind the silk fibroin memristors. In addition, this chapter presents experimental findings for the silk memristor in the crossbar or break junction configuration.

Chapter 4 proposed a novel bio-resorbable and bio-compatible solution processable memristor using silk fibroin protein. Besides that, this chapter shows experimental data which highlights the relationship between the memristor performance characteristics, and the combination of electrode used as well as the chemical processing of the silk fibroin layer.

Chapter 5 proposed the usage of a solution processed, organic silk fibroin memristor in the development of a resistive logic circuit. This chapter utilises the experimental data of the silk fibroin memristor and proposes the corresponding mathematical model as well as the development of a SPICE model. This model is then used to provide realistic simulation data that demonstrates the behaviour and operations of the proposed subtractor and division circuit.

Chapter 6 proposed a fully solution-based process technique for the fabrication of an artificial neural network. This work investigates the characteristics of a fully printed electrolytic-gated transistor and the underlying network architecture to perform an elementary image processing operation.

Chapter 7 concluded this these and provided an insight into possible future works for this field of research.

1.3 Thesis Contribution This thesis contributes to the area of solution processed electronics. The main contributions are listed as follows:

 This thesis investigates and verifies the resistive switching mechanism of the silk

fibroin memristor device. The understanding of the switching mechanism provides

insight into developing the various techniques and structural configuration for the

successful fabrication of the memristor device.

 Experimental demonstration of a novel bio-transient and bio-compatible silk fibroin-

based memristor. Further investigation into the resistive switching performance with

respect to the combination of electrode materials used was correlated with a proposed

numerical model. This information can then be used to further enhanced the

performance of the memristor device.

 This thesis investigates the resistive logic circuit architecture by utilising memristors to

perform implication logic. A resistive logic based subtractor and division circuit were

proposed which potentially allows the development of stateful/non-volatile and low

power electronics.

 Finally, this thesis proposed the fabrication of a fully solution-processed artificial

neural network utilising EHD printed electrolyte-gated transistors. Experimental

findings showed that these transistors successfully emulate neuronal functions such as

paired-pulse facilitation, short term plasticity and excitatory post-synaptic current

which were utilised to perform image processing operations.

1.4 Author’s publication Journal papers

Chapter 4: Yong, Jason, et al. A Silk Fibroin Bio-Transient Solution Processable Memristor. Scientific reports (Accepted)

Chapter 5: Yong, Jason, et al. Solution-processed organic silk fibroin memristor for resistive logic applications (Pending)

Chapter 6: Yong, Jason, et al. Fully Solution-Processed Transparent Artificial Neural Network using Drop-on-demand Electro-hydrodynamic Printing, Applied Material and Interfaces (Accepted)

Papers that are not included in this thesis:

 Nasr, Babak, et al. "Self-organized nanostructure modified microelectrode for sensitive

electrochemical glutamate detection in stem cells-derived brain

organoids." Biosensors8.1 (2018): 14.

 Hassan, Basem, et al. "Facile fabrication of an electrolyte-gated In2O3 nanoparticle-

based thin-film transistor uniting laser ablation and inkjet printing." Flexible and

Printed Electronics 3.4 (2018): 042001.

2 Literature Review

2.1 Solution Process Deposition Techniques Conventional micro and nanopatterning techniques have long been associated with lithography. Lithography, a subtractive process, is essentially a planographic patterning process in which patterns are transferred onto the substrate via a photo-mask, in the case of photolithography, or via direct-writing technologies, such as the ion-beam and electron-beam lithography. Photo- lithography allows the patterning of nano-scale features as well as providing a relatively large pattern throughput. Unfortunately, the mandatory requirement of a clean room and the high cost of the lithography mask fabrication impose a large entry barrier for next generation low life cycle electronics such as IoT devices. The individual photo-lithography mask may cost in the range USD $50,000 to USD $2 million (0.25 µm - 45 nm technologies) [9]. Besides that, the chemical processes involved in photo-lithography such as the etching process, photo-resists deposition and development are incompatible with biocompatible and bioresorbable materials.

Figure 2-1 Typical printable electronics process throughput and feature resolution (Adapted from [10])

At present, patterning and printing methodologies which are economical as well as commercially viable in order to strive towards large scale fabrication of printable electronics is a non-trivial problem and is still undergoing intensive research. There has yet to be a well- established standard process for printable electronics in existence as the process of choice

7 highly depends on the requirement of the fabricated devices as well as constraints imposed by the functional material used in the devices. In this chapter, we will be presenting some of the most prominent deposition methods for printable electronics. These sets of unique patterning techniques, coupled with the usage of new materials, are loosely considered as printed electronics and are not just limited exclusively to an inkjet-based system. For commercial application, printing resolution and patterning throughput play a significant role in determining the viability of the deposition method. Figure 2-1 shows the throughput and pattern resolution of the associated printing methodologies.

2.1.1 Ink-jet Printing Deposition Ink-jet printing operates on the basis that tiny droplets ejected from the print-head composing of the solvent and the functional material on a predefined location on the substrate to recreate the digital design which can be categorised into continuous inkjet (CIJ) or drop-on-demand (DOD) methods [10]. In the context of printable electronics, we will primarily focus on the DOD ink-jet printing due to its relevance in this field. DOD ink-jet printing requires an actuation mechanism in order to provide the deterministic ejection of a droplet from the nozzles which the thermal actuation and the piezoelectric actuation. Thermal DOD ink-jet functions by incorporating a resistive heating element adjacent to the nozzle (Figure 2-2) in which localised heating and vaporisation of the solvent/ink forms vapour bubbles that propel minute quantity of ink out of the nozzles. This is followed by the ambient cooling of the nozzle which draws a fresh supply of ink into the nozzle cavity. The repetition of the heating and cooling cycle provides the drop-on-demand characteristics. On the other hand, piezoelectric DOD ink-jet

Figure 2-2 Piezo element movement for shear-mode ink-jet actuator (Left). Various configuration of thermal ink-jet actuators (Right). (Adapted from [12])

Figure 2-3 Viable ink-jet process route for printable electronics:(A) Direct deposition of functional materials;(B) Deposition of masking layer followed by deposition of functional materials;(C) Selective etching via ink-jet deposition.(Adapted from [12]) operates by incorporating piezoelectric elements on the wall of the nozzle where the contraction and expansion of the elements provide the force to eject the appropriate quantity of the ink (Figure 2-2). Typically, lead zirconate titanate (PZT) ceramic elements are used to manufacture the squeeze-mode and the shear-mode nozzle structure [11].

Typically associated with household printing of personal documents, the ink-jet printing technique has firmly established a foothold in medium resolution production of solution processed electronics with relatively high throughput. This ambient condition compatible, mask-less and non-contact deposition method provides various advantages which include the compatibility with most types of substrates, easiness of prototype/design iteration and comparatively lower cost. Figure 2-3 shows several innovative process routes to fabricate electronic devices by using the ink-jet technology for direct deposition of functional material or indirect deposition using ink-jet compatible encapsulation resists. The current ink-jet printer has a typical drop diameter for ink-jet printing is in the range from 10 to 100 µm, with a drop volume from 0.5 to 500 pl. The dimensions of the ejection droplet, aerodynamic drag of the droplets mid-flight, ink viscosity and surface tension play a crucial role in determining the minimum feature size on the final product. In addition, there exist other second-order issues, e.g. micro-satellites, spreading droplet, coffee ring effect and fluid dynamics of the ink, which imposes a practical limitation in terms of the smallest possible feature size as well as the deposition consistency and repeatability [11]. In the practical realisation of printable electronics, special ink design consideration must be accounted such as the suspension stability

9 of the functional materials in the solvent and the dispersant or dispersion interaction with nozzle design. Besides that, oxidation and suspension stability of the inks required stabilisation agents which leads to the negative impact of the characteristics of the deposited materials [12].

2.1.2 Flatbed Screen Printing Deposition Flatbed screen printing has been widely utilised in large scale commercial printing on various types of substrate. Recently, this technique has shown promising prospect primarily in the production of flexible and stretchable electronics [13]. Typically, the technique involves the use of a stencil / patterned mesh, by which viscous ink is forced through with a squeegee to form the desired pattern as shown in Figure 2-4. Thus, the deposition resolution and thickness of the patterns are heavily reliant on the density of the mesh as well as the ink properties used. These stencils can be made of stainless steel, where patterns are laser etched, or polyester mesh, where the patterns are formed by means photolithography of with a photo-polymeric material. A high ink viscosity of up to 50 Pascal is required to produce features size of ≈100 µm in resolution with a layered thickness of up to 100 µm [14]. The advantage of screen printing is the less stringent requirements for the types of substrate and broader range of ink types as compared to other forms of printing methodology. This method is also compatible with planar or non-planar surfaces due to the conformity of the stencil used. For the fabrication of electronic devices, screen printing techniques have been demonstrated to provide the capabilities of mass- manufacturing photovoltaic cells [15], RF antennas [16] and light emitting diodes [17].

Figure 2-4 Illustration depicting the screen-printing process and stencil distortion observed in a printing stroke. (Adapted from [11])

2.1.3 Roll-to-roll (R2R) Printing Method Rotary screen-printing techniques is another mature technology for the fabrication of printed electronics. This printing method is a high throughput and high-resolution process for the fabrication of both active and passive electronics devices [18]. A variety of R2R manufacturing techniques has been proven to be commercially viable in the fabrication of solar cells, tactile sensors, RFID electronics and light emitting diode [19]–[21]. Unlike the flatbed screen printing method, a rotary screen is used for the continuous processing of the web (substrate) with the benefit of inline integration for a multitude of deposition techniques including gravure, ink-jet printing, and imprint lithography. Gravure is the most noteworthy form of the roll-to-roll process due to its relative simplicity, superior resolution and high throughput. As illustrated in Figure 2-5, this process involves the doctoring of inks onto the plate cylinder which is then transferred onto the substrate via hard-contact compression [22]. Recent development in R2R

Figure 2-5 Schematic diagram of a gravure printing process. (Adapted from [23])

manufacturing technologies has also incorporated vacuum-based deposition processes, such as plasma enhanced sputter deposition, physical vapour deposition and ALD (atomic layer deposition). Figure 2-6 shows a subset of possible assemblies used in a typical R2R process line. In this case, nano-imprinting lithography, UV development process and high-vacuum e- beam evaporator are integrated into the process for the fabrication of an optical polariser [18].

Figure 2-6 Schematic diagram of a R2R manufacturing process which integrates both vacuum and non-vacuum processes. (Adapted from [24])

This technique possesses the most versatile capabilities and is not only limited to the fabrication of passive devices but active devices as well. Previously reported literature had demonstrated a fully roll-to-roll processed organic transistors in which multiple layers of various materials are rolled onto each other and etched using a triblock copolymer poly-(ethylene oxide)- poly(propylene oxide)-poly(ethylene oxide) or PEO-PPO-PEO to form the transistor. PMMA (Poly-(methyl methacrylate), GRAPE114 (a polymeric semiconducting ink from BASF), PET (Polyethylene terephthalate) and silver are used as the dielectric, the semiconducting channel, the substrate and the conducting electrodes respectively [23]. In 2014, Dilfer et al. demonstrated a fully R2R fabricated high-performance metal oxide thin film transistor [24]. They successfully presented the capabilities of depositing a 7 nm thick IZO layer via the precursor route to form the semiconductor channels of a transistor which have been conventionally deposited via spin-coating and it not a commercially viable technique.

2.1.4 Electrohydrodynamic Printing Method Electrohydrodynamic (EHD) deposition is a technique that relies on electric fields for creating the necessary forces for propelling inks from the nozzle onto the target substrate instead of mechanical energy, used in an inkjet printer. The principle of the deposition technique is based on the application of electrical potential between the nozzle and a conducting support substrate. Consequently, the mutual coulombic repulsion between mobiles ions near the surface of the liquid meniscus induces tangential stress on the surface, thereby deforming the meniscus into a conical shape, known as a Taylor cone as shown in Figure 2-7 [25]. As the tangential stress overcomes the surface tension of the liquid, nano-droplets of ink are ejected from the cone. Thus, creating the electrohydrodynamic phenomena in which drives the flow of fluid ink out of the nozzle and onto a target substrate. By varying the applied electrical potential, the EHD printer can operate in distinctive modes such as micro-dripping mode and continuous spraying mode [26]. These modes provide the advantage of having large dynamic patterning resolution without the need of multiple nozzles of varying sizes or piezo-electric elements. Besides that, on-demand deposition for an EHD system can be accomplished by applied voltage pulses. Recent advancement has shown that the utilisation of high-frequency pulses for an EHD system can be used to adjust the patterning resolution [27]. In comparison to the conventional inkjet printing, the absence of mechanical components to propel fluid from the nozzle greatly simplifies the print-head development of an EHD printer. In addition, this prevents the generation of satellite droplets which severely impact the patterning resolution [28]. Unlike

Figure 2-7 Time-lapse images of the transformation of the ink meniscus due to an applied voltage. (Adapted from [27])

13 ink-jet printing, the performance of an EHD deposition technique is highly susceptible to the ink properties, nozzle to substrate distance, applied electrical potential on the nozzle and substrate material [29].

Fabrication of two-dimensional or three-dimensional passive structure using the EHD system is an exciting research topic. In 2012, P. Galliker showed that the direct printing of nanostructures is possible with the electrostatic auto-focussing of ink nano-droplets (ENA) [30]. It was demonstrated that with careful application of electrical potential, the formation of the meniscus on the opening end of the pipette in can periodically induce the ejection of nano- droplets and are accelerated on to the substrate. As the solvent in the droplets evaporates, nanoparticles in the colloidal solution will be deposited on the substrate. This approach was capable of realising nano-structures with a width of 50nm and an aspect ratio of 17. Zhang et al. investigated an EHD based process for the fabrication of 3D touch sensor [31]. By appropriately selecting the solvent viscosity and deposition volume, they successfully fabricated a fully printed 3D metal structure by employing the self-sintering and welding mechanism induced by the charge transfer during the deposition process as shown in Figure 2-8a. The integration of EHD printing in the fabrication active devices primarily transistors remains in its infancy stages of research. Kim et al. presented an EHD deposition technique for printing In2O3 based thin film transistor as well as an oligosiloxane passivation layer [32]. In conventional fabrication of electronics, a passivation layer of the semiconductor layer is used to prevent the desorption of oxygen which severely affects the electrical performance of the semiconductor. They demonstrated the direct printing of the UV curable polymer layer by EHD printing presents itself as an excellent gas barrier.

Figure 2-8 (a) Fabrication of a nanoscale pillar using silver colloidal solution. Scale bar, 1 µm. (b) Optical image of EHD printed transistor on a PI substrate. Scale bar, 50 µm. (Adapted from [33], [34])

2.2 Solution-Processed Electronics 2.2.1 Solution-Processed Memristors In recent years, memristors have garnered attention from both the research and industry community as one of the potential candidates as the upcoming memory technology. They typically possess superior performances as compared to conventional charge-based memory due to their lower operating voltage, faster-switching speed and straightforward scalability strategies [33]. These types of memory devices store binary information in the form of distinctive resistance levels namely the low resistance state (LRS) or the high resistance state (HRS). In 2008, Strukov et al. were the first to realise a memristor device by stacking a layer of insulating TiO2 followed by another layer of oxygen deficient TiO2-x layer between platinum electrodes [34]. It was demonstrated that the application of an external bias across the junctions result in the drift of charges dopants and consequently the resistance across these junctions. Since then, various metal oxide based memristor devices using transitional metal have shown promising prospect and can be integrated with conventional complementary metal oxide (CMOS) technologies as shown in Figure 2-9. In an article published in the journal Nature

Electronics, Li et al. demonstrated the integration of a HfO2 memristor crossbar array with the conventional 2µm CMOS technology node using a 1T1R architecture array. The 128 x 64 memristor cell was then used to perform image compression and convolutional filtering operations.

Figure 2-9 Photograph showing a 1T1R (single transistor-single memristor configuration) memristor crossbar array integrated with a CMOS-based logic circuitry. (Adapted from [37])

Figure 2-10 Scanning electron microscope (SEM) image of the cross section for the Sericin memristor. (Adapted from [38])

Recently, solution process deposition techniques have been extensively investigated as a potentially exciting candidate for memristor fabrication using various solution-based insulation material. These techniques are a fully additive fabrication process, capable of large area batch electronic fabrication with the added benefit of significant flexibility in the choice of substrate. Rosa et al. demonstrated a solution process memristor using an IGZO nanoparticle dispersion to form the insulation layer [35]. They reported a low operating voltage of ±1V with an on-off ratio of 10. In addition, organic based resistive memory devices have been extensively studied owing to their appealing characteristics such as the relatively easier manufacturing process, lower production cost and the possibility of integration with printable electronics. Besides that, the use of organic materials as the building block for electronics devices promises to provide renewable and environmentally friendly means for the development of next-generation green electronics as well as transient electronics. As shown in Figure 2-10, Wang et al. have experimented on the usage of Sericin, a by-product of the silk extraction process, to construct a multilevel non-volatile resistive memory [36]. Sericin is a water-soluble protein composed of 18 amino acids which bind silk protein and is discarded during the processing of silk fibres. This research group have demonstrated a Sericin based memristor which exhibited excellent read/write cycles and more importantly three levels of resistance states. Lin et al. showed resistive switching utilising an insulating polymethyl methacrylate (PMMA) layer embedded with Fe3O4 nanoparticles [37]. The spin-coated layer yielded a memristor device with a large memory window of 105 and a fast switching speed on less than 50 ns.

2.2.2 Solution-Processed Metal Oxide TFTs In recent years, organic semiconductor materials have been widely studied and used in electronic devices such as thin film transistors, solar cells and light emitting diode due to their low cost, good processability and compatible with a multitude of substrate types [38], [39]. Organic semiconductors broadly categories into two conjugated polycyclic compounds ( Pentacene, Rubrene, etc. ) and heterocyclic polymers ( Fullerenes, Triphenylamines, etc.) based on their molecular weight [40]. Unfortunately, these materials exhibit low electron mobility and poor stability under ambient conditions. To date, the best reported effective mobility for an-channel organic FET was in the range of 6.5 to 9.8 cm2 V-1s-1 [41]. In comparison, typical inorganic semiconducting materials possess high electron mobility and superior chemical stability. The most well-known inorganic semiconducting material is perhaps silicon which is widely used in present-day conventional manufacturing of electronic integrated circuits. In addition, III–V compounds such as InP, GaAs, and GaN are also inorganic semiconductors exhibiting higher effective mobility compared to that of silicon and have been used in various niche applications primarily RF transistor technologies, optoelectronic devices and high-performance power transistors [42], [43].

However, the stringent requirements for the deposition and processing of these materials in the fabrication of thin film transistors and their corresponding circuitry limit their prospect for producing low cost, flexible or transparent electronics. Consequently, there exists an ongoing quest for alternative materials which possesses the ideal material characteristics without any compromising the electrical performance. At present, various solution-processed metal oxide semiconductors such as In2O3, NiO, IGZO, SnO2, and ZTO are found to be suitable materials for the large area fabrication of conventional electronics and optoelectronics [44]–[46]. In addition, these semiconducting materials can be deposited via solution process techniques. The most promising technique for the derivation of metal oxide is the precursor process route. The precursor route involves the dissolution of metal salts such as nitrates, acetate or chloride in a suitable solvent to produce the precursor inks. These precursor inks can be patterned via the aforementioned printing techniques followed by an annealing process in which these salts

Figure 2-11 Photo-activation of solution-processed metal-oxide semiconductors by deep ultraviolet radiation. Light blue shading illustrates the illumination from the arrays of low-pressure mercury lamps. (Adapted from [51]) decomposed into their corresponding metal oxides. Depending on the annealing conditions, a high-quality crystalline metal oxide thin films can be derived [47].

In a study conducted by Kim et al., solution processed In2O3, ZTO and IZO field effect transistors (FETs) were fabricated using a novel sol-gel combustion process. It was demonstrated to achieve an effective mobility of up to 9.4 cm2 V-1s-1, 7.34 cm2 V-1s-1 and 9.78 cm2 V-1s-1 respectively [44]. The sol-gel combustion processing involves the inclusion of chemical additions, namely ammonium hydroxide and acetylacetone, in conjunction with the solvents to effectively lower the activation energy required for the formation of metal oxides, thus, lowering the annealing temperature. Rim et al. reported for the first-time low temperature, deep ultraviolet radiation (DUV) assisted annealing process for fabricating the sol-gel metal oxide transistors as depicted in Figure 2-11. The integration of DUV irradiation (primary spectral at 184.9 nm and 253.7 nm) induces a photochemical reaction which promotes the formation of metal oxides [48]. They have shown that the optimised DUV IGZO thin film FETs were achieving high effective mobility of 84.4 cm2 V-1s-1 with a maximum processing temperature of about 70 °C.

On the other hand, solution-processed metal oxide films transistors can be fabricated using nanoparticles of the corresponding metal oxides. This technique involves the dispersion of nanoparticles of suitable size, typically < 50nm, in a solvent and is stabilised by electrostatic or steric stabilisation. Electrostatic stabilisation of a nanoparticle is a form of kinetic stabilisation method which involves the counterbalancing of Van der Waals attraction forces

Figure 2-12 Schematic layout of an In2O3 nanoparticles based electrolytic gated TFT and the HIM images of the device channel. (Adapted from [53]) and the repulsive coulombic forces between nanoparticles. These phenomena can be achieved by the careful selection of dispersion media as well as the particle aggregate sizes [49]. In the case of steric stabilisation, suspension of nanoparticles in a solvent is achieved by the adsorption of polymer additives of the particle surface. These polymer additives serve as an insulation layer which prevents the coagulation or aggregation [50]. The fabrication of metal oxide FETs via the nanoparticle methodologies typically required no annealing processes and can be accomplished at room temperature. Unfortunately, as a consequence of the inherent physical properties of the nanoparticles, the synthesised metal oxide films typically exhibit significant porosity and non-uniformity which severely impacts the electrical performance of the fabricated electronic devices as shown in Figure 2-12. In 2011, Dasgupta et al. reported on the development of high mobility, inkjet-printed In2O3 transistor at room temperature. They synthesised an In2O3 dispersion in ethanolamine which printed on an in-plane transistor with sputtered ITO serving as electrodes. These fabricated transistors showed effective mobility of 0.8 cm2 V-1s-1 and an operating voltage of 1.0V [51]. Fukuda et al. successfully demonstrated a coprecipitation method of the synthesis of IGZO nanoparticles which was used to produce a solution process IGZO TFT. Their methodology involves the spin-coated of suspended IGZO nanoparticle solution on a silicon oxide wafer followed by the sintering at 400 °C to produce the desired electrical properties [52].

2.3 Memristive and Neural Network Circuitry 2.3.1 Resistive Logic Circuit Memristors are typically a two-terminal device implemented as a MIM (metal-insulator-metal) structure by which the insulation layer undergoes physio-chemical reaction upon the application of an electrical potential, inducing a change in electrical conductivity across the terminals. The most common models used to explain the resistive switching mechanism is the formation and rupturing of conductive filaments within the insulation layer which can be explained with the electrochemical metallisation process or the valance change mechanism [53]–[55]. These physical properties of a memristor manifest as the modulation of resistance on the terminals, allowing for the non-volatile encoding of logical information. The focus in the integration of memristive devices with conventional electronics has been primarily focused on the data storage applications. Recently, memristors have been used to also perform logical operations using a variety of novel computing architectures such as the hybrid memristor ratioed logic-CMOS architecture, the memristor aided logic architecture and the material implication architecture [56]–[58]. These architectures allow the binary operations to be performed and their logical information to be stored within the same device. A multitude of logical operations has always been utilised to develop an abstract understanding of a Boolean logic. However, only three of those logic operations are implemented in the field of digital electronics and computing, namely, the OR, the AND, and the NOT operations as these are readily implementable in conventional CMOS technologies.

Figure 2-13 (a) Illustration of a memristor logic cell. (b) The truth table for the material implication logic.

On the other hand, memristive element allows the intrinsic hardware implementation of a fourth logical operation termed material implication. In this context, we will denote the logical

20 operations as ‘→’ by which ‘A → B’ means A implies B. The basic building block of a material implication logic is as shown in Figure 2-13a and the truth table of the corresponding logic operations are shown in Figure 2-13a b. Based on the illustration, the block consists of two memristor device, A and B, which are connected to a load resistor, RL. The configuration can be easily realised by a crossbar array of memristor in which the top electrodes were driven by tri-state voltage drivers, VA and VB whereas the bottom electrodes were connected to a multiplexer. To perform an implication logic, conditional toggling was performed in which a toggling voltage pulse is applied on device A and a conditional voltage pulse is applied on device B simultaneously. The switching behaviour due to the interaction between the set and conditional voltage pulse highly depends on the states of the memristor. The material implication logic operations can be described as followed: in cases where A = 0 (high resistive state), the voltage divider is unaffected and thus, B is set by the potential difference caused by the conditional pulse; for A = 1 (low resistive state), the voltage divider is shorted and B is unaffected by the conditional pulse [56].

2.3.2 Neural Network Circuitry Synaptic transistors have been primarily fabricated using physical and chemical vapour deposition (PVD / CVD) techniques, or by means of CMOS based processes. Shibata et. al. proposed a neuron MOSFET or neuMOS device with multiple input gates that were capacitively coupled with an additional floating gate to emulate the integration of multiple pre- synaptic inputs [59]. Large neural network implementations on CMOS technologies are not without their limitations. Advanced implementations of large-scale networks comprise of 30,000 custom high-performance CMOS compute processors but only emulate a fraction of the brain in non-real time at an energy budget of 1W per chip. In contrast, the typical human brain consumes approximately 20 W [60], [61]. New devices and modelling approaches are required that are both cheaper and more power efficient. Three terminal transistors devices emulate biological synapses via the modulation of the channel conductance are an alternative approach. Electrolytic-gated thin film transistors are recipients of significant attention due to their potential in low-cost electronics and neuromorphic computing [8]. In recent years, a broad spectrum of electrolyte-gated transistors scheme has been proposed such as sodium alginate gated IZO transistors, graphene oxide based IZO transistors and methyl cellulose gated IZO transistors [62]–[64]. More recently, Zhu et. al. proposed an in-plane synaptic transistor by lateral coupling of the indium zinc oxide (IZO) layer sputtered on a phosphorus-doped nanogranular SiO2 proton conductive film [65]. These biologically inspired artificial synapses are

21 capable of performing basic neuromorphic functions ranging from short-term plasticity, long- term plasticity, pulse-pair facilitation and spike-timing-dependent plasticity [66]–[68]. Unfortunately, these devices are difficult to build and require the usage of vacuum-based physical deposition techniques, specifically, magnetron sputtering, atomic layer deposition and e-beam evaporation.

Figure 2-14 An artificial afferent nerve consisting of a pressure sensor, ring oscillator and a synaptic transistor. (Adapted from [69])

In 2018, Kim et. al. incorporated a ion gel-gated transistor and a tactile sensor to form an artificial mechanoreceptor as shown in Figure 2-14 using conventional fabrication methodology. These methods, whilst having advanced the field, are expensive, with modifications to architectures and network layouts requiring many months between design modifications and availability of the ANN for testing. Furthermore, these fabrication approaches are available to a select few, and therefore restrict accessibility by the scientific community to be able to quickly execute and test new architectures and systems.

3 Memristors Physics and the Realisation of an Organic Memristor

Memory devices can be categorised into non-volatile and volatile memories. In the computing discipline, conventional volatile and non-volatile memory devices possess advantages and disadvantages over one another. Thus, they operate in distinct domains and address mutual exclusive computing functionalities. Volatile memories can achieve substantially higher operational speed and lower power consumption, although they require to be actively powered in order to preserve the stored information. On the other hand, non-volatile memories can retain digital information passively but operate at significantly lower operational speed. In addition to that, non-volatile memories have low fabrication cost as compared to their volatile counterpart. Motivated by these limitations, the research communities have been actively researching and developing new forms of a memory device which possesses the superior performance while maintaining the lower fabrication cost such as phase change and resistive random-access memories.

In 1971, Leon Chua postulated the existence of a fourth fundamental passive electrical circuit element in addition to the conventional resistance, capacitance and inductance. This postulation was based on the missing definition in the pairwise mathematical equation that relates the four basic circuit parameters, namely charge, current, voltage and magnetic flux. These pairwise equations, illustrated in Figure 3-1a, established itself as the fundamental law of electricity and magnetism, Ohm’s law (resistance), Faraday’s law (inductance) and Gauss Law (capacitance). However, the sixth mathematical relationship which describes the change of flux with charge is without a real world physically representation. He later coined the term memristor, an acronym for memory resistor, to describe such a device [70], [71].

Figure 3-1 (a) Relationship between four fundamental electrical quantities. (b) Scanning tunnelling microscope of crossbar memristor structure by Hewlett Packard. (Adapted from [36], [59])

Prior to 2008, charged-controlled memristor was emulated with both active and passive electrical components since physical realisation of a resistive switching device were debatable [72]. Despite the absence of a consensus on the feasibility of a memristor device, researchers have been observing ’defective’, or molecular switching behaviour in nano-crossbar electrode arrays of Rotaxane and Catenane compounds as discussed in the literature [73], [74]. This ‘defective’ behaviour was later understood to be a typical resistive switching characteristic. Researchers in Hewlett Packard was the first to observe and characterise resistive switching behaviour between crossbar arrays of titanium dioxide sandwiched between platinum electrodes as shown in Figure 3-1b. The constructed TiO2 device relies on the strong electric fields generated due to the nano-scale structure of the crossbar in order to produce observable non-linearities in the ionic transport. The 5 nm thick titanium oxide, consisting of an insulating

TiO2 layer and an oxygen-deficient TiO2-x layer, functions as the active switching layer in the proposed device where drifting of oxygen vacancies under an electric field alters the thickness of both the stoichiometric and non-stoichiometric oxide layers of titanium oxide [34]. This chapter will be discussing the various types of switching mechanism and their corresponding mathematical model.

3.1 Memristor Conduction Model 3.1.1 Physical Model In a memristor structure, the insulation layer represents the most crucial component material which dictates their resistive switching characteristics such as the conduction mechanism, operation voltage/polarity, memory window, switching speed and retention endurance [75]. The switching mechanism for a memristive device can be categories into a filament type or barrier type. Figure 3-2 illustrates the switching mechanism for a filament type memristor. In this section, we will be focusing on the filament type switching mechanism. The filamentary switching mechanism can be further classified into a valence change and electrochemical metallisation (ECM) resistive switching. ECM switching memristors utilise a combination of the electrochemically unstable electrode, such as copper or silver, in conjunction with an inert electrode, such as gold or platinum, with an insulating electrolyte stacked between them [54], [76], [77]. On the application of adequate electrical potential, conductive filaments across the metal terminals are formed, inducing a low resistance state. For an electrochemical metallisation memristive device, these conductive filaments are formed from the oxidation metallic atom followed by the electromigration and electrocrystallisation metallic cations within the insulation layer [78]. The reversal and dissolution of these conductive filaments are widely believed to be caused by thermal decomposition due to Joule heating [79]. Thus, the resistive switching mechanism is assisted by two crucial components namely, the thermal and electric field component. This form resistive switching has been widely observed in the organic insulating layers, binary metal oxides, chalcogenides and halides [54], [55], [80], [81]. Literature has shown that electric field dominant memristors exhibit bipolar switching characteristics whereas thermal-affect dominant devices exhibit unipolar switching properties [82]. Figure 3-2 shows the distinctive current-voltage (IV) characteristics for the switching characteristics between a bipolar and unipolar memristor.

Figure 3-2 IV characteristics for the switching characteristics of (a) bipolar memristor and (b) unipolar memristor. Red lines denote the LRS and Green lines denotes the HRS.

3.2 Metal-Insulator-Metal Memristor with Silk Fibroin In this section, we investigated the resistive switching properties of silk fibroin using different combinations of metal electrodes for both the cathode and anode of the memristor device. The initial device was fabricated by compressing silk fibroin between two Au coated glass slides which forms an active switching layer of approximately 125 µm as shown in Figure 3-3a. Figure 3-3b shows the measured I-V characteristics of the fabricated Au-silk fibroin-Au device. The IV characteristics of the devices are measured after the initial electro-forming process is performed. To characterise the resistive switching performance, the device is subject to a ±40V triangular voltage signal. The devices exhibit a low resistance state before reaching the threshold voltage of approximately 14V where the device gradually transitions to a high resistance state as well as the retention of the states after the applied voltage is removed which indicates non-volatility. Reversing the bias voltage triggers the reversal process in which the

Figure 3-3 (a) Optical image of a silk fibroin memristive device interposed between two gold electrodes. (b) I-V characteristics of the Au-Silk Fibroin-Au memristive device

26 high-resistance state transitions to the low-resistance state. The fabricated device exhibited an on/off ratio of approximately five times which is reasonably low as both electrodes have the same degree of inertness, resulting in a significantly poorer off characteristics of the device as both electrodes undergo oxidation and electro-crystallisation of similar degree. Figure 3-6 shows the state retention endurance of the fabricated memristive device across 50 switching cycles. It is demonstrated that the silk fibroin memristor retains the resistive state admirably well after 50 consecutive switching cycles without significant degradation in both the high and low resistance state.

Figure 3-4 (a) Pristine Au electrodes with 50 µm gap embedded with silk fibroin film. (b) Observation of formation and retention of dendritic structure following the application of 40V.

To visualise the formation and growth of the conductive filament, we have fabricated a metal junction with a 50 µm gap on a microscope slide which was then subjected to a voltage of 40V. The metal functions were fabricated via photolithography followed by the deposition of 10 nm of chromium (Cr) and 50 nm of silver (Ag) using the e-beam evaporator at a pressure of 10-5 Torr. The silk fibroin solution was then deposited on the junctions and dried in an ambient environment for 30 mins. Figure 3-4a and b show the optical image of the pre- and post-application of an electrical potential across the junction. In Figure 3-4b, we can observe the formation of the dendritic structure caused by the oxidation of the silver electrodes and subsequently electro-crystallisation of the silver cations into metallic silver. Next, we investigated the resistive switching properties of the silk fibroin memristor by silver as the active electrode and gold as the inert electrode. For this form of memristor device, a 20nm Cr adhesion layer with a 50nm Au layer is thermally evaporated onto a glass slide. Laser ablation is then used to pattern the desired structured for the bottom Au electrode followed by the spin- coating of 5% silk fibroin solution at 1000 rpm. The deposited silk fibroin layer was then dried

27 under ambient conditions for 30 mins. Next, 50nm of Ag top electrode is e-beam evaporated through a polyimide shadow mask to form the desired pattern. The fabricated device is as shown in Figure 3-5.

Figure 3-7a show the retention of state for the silk fibroin memristor as the input voltage is lower than the resistive switching threshold. On the other hand, Figure 3-7b and c show the transition from a high resistance state to a low resistance when the device is subjected to a triangular voltage signal of amplitude ±1.5V. The voltage sweep direction is as indicated by the arrows in the ascending order of their numbering. By using different current compliance (1mA, 2mA and 5mA) during the set process, we can potentially increase the memory window

Figure 3-5 Optical image of the fabricated silver-silk fibroin-gold crossbar memristor device.

Figure 3-6 Switching characteristics of the memristor device showing consistent transition between the low resistance and high resistance state throughout 50 switching cycles.

28 of the memristor device by up to an order as shown in Figure 3-7b. However, the increase in current compliance increases the risk of damaging the silk fibroin layer resulting in a catastrophic failure of the device, shown in Figure 3-7c.

Figure 3-7 I-V characteristics for Ag-Silk Fibroin-Au memristor devices stimulated with a triangular voltage sweep (in the direction of 1→4) with a current compliance of 1mA (2mA or 3mA for some devices). (a) Typical IV characteristics for ±1V triangular waveform. (b) IV curve for higher on-off switching ratio (>5 order of magnitude) observed on several devices for ±1.5V triangular applied voltage. (c) IV curve for lower on-off switching ratio (≈1 order of magnitude) observed on several devices for ±1V triangular applied voltage. (d) Switching oscillations between on and off states. (e) Failure mode for the memristor devices which exhibits poor off-state characteristics or permanently persists in the on-state.

We also investigated the resistive switching characteristics and performance of the silk fibroin memristor with a break junction structure. For this device, a 20nm Cr adhesion layer with a 50nm Au layer is thermally evaporated onto a glass slide. This is followed by the patterning of a narrow V-like channel on the gold electrodes using a laser ablation technique. In order to create the break junction, the electrodes were then subject to linearly increasing bias voltage. As shown in Figure 3-8a, the initial monotonic increased current indicates the resistive region. Further increase in bias voltage will cause a non-monotonic change in the current which indicates that electro-migration is occurring. The constriction of the conductive channel due to electro-migration further increases the localised heating in the vicinity of the breakage area which will induce the melting of the gold electrode leading to a sudden spike in current followed by the complete breakdown of the channel. Figure 3-8b shows the distribution of the breakdown voltage and current of the break junction indicating a reasonably tight distribution of break off gap is induced during junction breakdown. Next, a 5% silk fibroin solution was spin-coated onto the break junction device at 1000 rpm and left to dry under an ambient environment for 30 mins. Figure 3-9 shows the I-V characteristics of the break junction memristor device with respect to their gap size. It can be observed that a smaller gap produces a relatively consistent switching characteristic with a larger on/off ratio and consistent

Figure 3-8 (a) IV characteristics for the formation of an Au break junction. (b) Distribution of the breakdown voltage and current for the Au electrodes.

Figure 3-9 Bipolar switching characteristics of Au/Silk Fibroin break junction device with a ±40V triangular sweeping voltage for junction gap size of (a) < 1µm and (b) > 1µm. Direction of the triangular sweeping voltage is as indicated by the numeric annotation (from 1 → 4)

Figure 3-10 (a), (b), (c) HIM images showing the severe damage of the break junction Au electrodes. (d) Sub-micron break junction with a severely damaged electrode surface.

31 hysteresis loop whereas the break junction device with larger gaps produces inconsistent switching characteristics. Unfortunately, these devices tend to breakdown after the 6th switching cycle as the electrode disintegrates due to the electrochemical process involved. Besides that, the short life-cycle of the device is also contributed by the fact that the gaps are fairly large, ranging from ≈ 300nm to 2.5µm. These large gaps require the application of a substantially higher electrical potential and result in irreversible damages to the silk fibroin layer.

3.3 Conclusion In conclusion, this chapter highlights the various physical model used to describe the resistive switching mechanism of the memristor device as well as the classification and physics behind different resistive switching types. We have demonstrated the fabrication and characterisation of a silk fibroin-based memristor devices utilising a combination of gold electrodes and silver electrodes. In addition to that, we have characterised the performance of both the crossbar and break junction configuration of the memristive device. The presented findings indicate that the resistive switching for a silk fibroin-based memristor can be explained with the electrochemical metallisation model. This substantiated by the dependency on the active and inert electrodes for the resistive switching performance as well as the formation of dendritic structure, in line with conventional electro-metallisation and electro-crystallisation theory. Besides that, the findings presented from the break junction memristor device indicates that the thickness of the silk fibroin layer plays an important role in regulating the resistive switching behaviour of the memristor. Larger lateral or vertical thickness typically requires higher electric potential to induce the migration of cations across the insulating layer which has shown to damage the silk fibroin layer and result in poor memory retention of the fabricated device.

4 A Silk Fibroin Bio-Transient Solution Processable Memristor

Today’s electronic devices are fabricated using highly toxic materials and processes which limits their applications in environmental sensing applications and mandates complex encapsulation methods in biological and medical applications. This chapter presents a fully resorbable high-density bio-compatible and environmentally friendly solution processable memristive crossbar arrays using silk fibroin protein which demonstrated bipolar resistive switching ratio of 104 and possesses programmable device lifetime characteristics before the device gracefully bio-degrades, minimizing impact to the environment or to the implanted host. Lactate dehydrogenase assays revealed no cytotoxicity on direct exposure to the fabricated device and supported their environmentally friendly and biocompatible claims. Moreover, the correlation between the oxidation state of the cations and their tendency in forming conductive filaments with respect to different active electrode materials has been investigated. The experimental results and the numerical model based on electro-thermal effect shows a tight correspondence in predicting the memristive switching process with various combinations of electrodes which provides insight into the morphological changes of conductive filaments in the silk fibroin films.

4.1 Introduction Bio-resorbable, environmentally friendly, transient integrated circuits represent a new class of electronics which pave the way towards new possibilities in the fields of environmental monitoring, biomedical diagnostics, sensors and the emerging field of electroceuticals. These new class of devices are capable of robust and reliable operation even when embedded within living tissue, and without causing deleterious inflammatory reactions [83]. Importantly, they can dissolve away after use, circumventing the need for their retrieval and disposal from the environment or in biological applications removal and reducing risk associated with added surgical procedures. Furthermore, these electronics can be designed with the desirable device lifetime transience via adaptation of the constituent materials, by which they can subsequently resorb through hydrolysis or metabolic action at varying timepoints [83]. Silk fibroin, extracted from the Bombyx Mori silkworm cocoon, represents an interesting novel biomaterial endowed with outstanding mechanical, electrical and optical properties [84]–[87]. Silk fibroin has been proposed to be an ideal material for producing a variety of high-performance biocompatible

33 and flexible electronics devices, such as transistors, memory devices, and optical and optoelectronic components [85]–[88]. In addition, its high solubility in water, with adjustable dissolution rates [89], [90] via the use of various encapsulating materials such as polycaprolactone[91] or thermally embossed and laminated silk fibroin[84] represent another distinct advantage for environmentally friendly disposable electronics.

To date, there have been many attractive reports of biocompatible and bio-resorbable transient integrated electronics where silk fibroin has been used as passive component. It has been employed as substrate or conformal platform in the building of functional solid-state devices such as transistors, RFIDs and micro electrode arrays in field of bioresorbable, implantable applications [85], [86]. It is also worth mentioning that there are other biomaterials such as egg albumen [92], PMMA/PHEMA [93], sericin [36], and eumelanin [94] that have been used to construct memristive devices. Interestingly, silk has been shown to exhibit resistive switching characteristics as well and has been used as an active building block of various biocompatible and flexible memristors fabricated on solid substrates such as glass, polythioesters and silicon.[88], [95] However, the full resorbability of such silk based memory resistors, which plays an important role in their full biodegradability, remains a challenge with respect to fulfilling the demands of environmental friendly and sustainable electronics. In this work, we demonstrate for the first time a fully bioresorbable high density memristor configured as crossbar arrays which is fabricated on solution processable substrate, Poly-(vinyl alcohol) (PVA). This class of memristor provides a completely water soluble and fully resorbable component for emerging implantable and/or disposable electronics. The PVA substrate is used due to its superior elasticity (Young modulus of 13.5 GPa) [96], tuneable solubility in aqueous

Table 4-1 Electrode combination for silk fibroin memristors and their proposed switching mechanism.

Electrode material combination Proposed Switching Ref mechanism Al-fibroin-ITO Oxidation and reduction of [23] silk fibroin protein chain Mg-fibroin-Mg Electrochemical metallization [35] Al-fibroin-ITO Oxidation and reduction of [31] silk fibroin protein chain Ag-fibroin-Au Electrochemical metallization [74]

34 solution [97] and ease of preparation. This substrate can be prepared without additional post- treatment whereas crystallised silk fibroin based substrate not only requires an extended period to achieve the desirable mechanical strength for the substrate, it limits the transient capabilities of the fabricated device due to the insolubility of crystallised silk fibroin [98], [99].

There has also been limited attention in understanding the switching mechanism of silk based memristors which could offer more comprehensive information about optimum electrode combinations or the physiochemical alteration of the silk fibroin. In recent studies, different bipolar switching mechanisms have been proposed for the silk fibroin based memristive devices. M.K. Hota et al. describe a mechanism associated with a localised oxidation and reduction of silk fibroin protein chains, leading to an increase or decrease in resistance [88]. In contrast, Wang et al. explain the switching mechanism as the typical electrochemical metallisation memory (ECM) in which metal ions from the oxidation of the active electrode migrate through a solid electrolyte and electro-crystallises to form conductive filaments during the SET cycle [99]. The RESET cycle involves localised heating on these conductive filaments via joule heating leading to its dissolution. However, we believe there has yet to be substantial work in exploring the effects of various electrode materials on the silk fibroin memristor and how it relates to the electrical performance. Up to now, several studies have been carried out on silk based memristors which are fabricated based on various material combinations with the underlying switching mechanism having been interpreted inconsistently as is indicated in Table 4-1.

In this chapter, we report on the development process of the bio-transient memristive device fabricated on a solution processable PVA substrate with a focus on the effects of electrode materials on the switching mechanism. For comparison and simplicity purposes, we have also fabricated similar electronics on glass substrates. The findings on the impact of different combinations of active and inert electrodes with respect to the electrical characteristics and performance of the crossbar memristive device strongly support the electrochemical metallisation model. To further elaborate on our experimental observations, we investigated the influence of silk fibroin crystallinity in addition to measuring the electrochemical response over a variety of active electrodes. Moreover, a mathematical model of the growth and dissolution of conductive filament is proposed and simulated to elucidate the physical mechanism behind the observed phenomena. Our results provide important, novel insights into the development of future robust and non-volatile bio-transient memory devices.

4.2 Results and Discussion 4.2.1 Electrical and Material Characterisation

Figure 4-1 Device structure and fabrication process of the silk fibroin memristor. (a) Photograph of an Au-Silk Fibroin-Pt crossbar memristor device fabricated on a PVA film. (b) Schematic illustration of the fabricated crossbar memristive device. (c) Flowchart illustrating the fabrication process for a bio-resorbable and biodegradation crossbar memristive device. The PVA substrate is drop-casted on a Teflon surface to ease substrate lift off and followed by the spin coating of PMMA to prevent dissolution during silk fibroin deposition. The bottom gold electrodes and top platinum electrodes are patterned via shadow mask e-beam evaporation whilst the switching layer is a solution processed silk fibroin.

We have developed a crossbar memristive device that consists of silk fibroin switching layer stacked between an active electrode and an inert electrode supported on a spin-cast substrate of PVA. Figure 4-1a show a crossbar memristor fabricated with 50 nm gold (Au) and 50 nm platinum (Pt) electrodes to ensure bio-transient capabilities. Practically, a thin Cr layer (~ 10 nm) is introduced in the interface between the PVA substrate and the electrodes to promote adhesion which has demonstrated no increase in cytotoxicity. It has been shown that Cr in its pure metallic form does not contribute to any adverse health effects [100]–[103]. The device consists of a ten by ten active and inert electrode arrays. A shadow mask along with e-beam evaporation was used to pattern and deposit the active electrodes arrays on the various substrates primarily glass or PVA and followed by spin coating silk fibroin films. Fig. 1b and 36

The transient characteristics were evaluated by the immersion of the device in de-ionised (DI) water under ambient conditions. Figure 4-3a show a time sequence of images illustrating the dissolution process of the crossbar patterned memory. The crossbar device showed rapid disintegration within 2 minutes and complete dissolution within 30 minutes. This dissolution process is due to silk degradation in water. This characteristic is crucial for in vivo applications as the silk fragments subsequently degraded through proteolytic mechanisms and resorbed without leaving traces of the fabricated device [104]. It is important to note that silk fibroin, used as the functional constituent, is a biocompatible product, approved by the Food and Drug Administration (FDA) for a number of different clinical applications [105]. For this investigation, we chose to assess cytotoxicity, a component of biocompatibility, of all the materials and fabrication steps of our fabricated device via the lactate dehydrogenase cytotoxicity (LDH) (Promega, US). We have employed the lactate dehydrogenase cytotoxicity (LDH) (Promega, US) assay to evaluate any cellular membrane damage associated with the

Figure 4-3 Device bio-resorbability and cytotoxicity characteristics. (a) Time sequence of the dissolution of the crossbar memristive device in DI water under ambient conditions. (b) Image of SY5Y neuroblastoma cells proliferating in the presence of the bio-resorbing memristors for 168 hrs. 103 cells/well was selected to be the standard seed cell number in the cytotoxicity test to study the effects of the constituent materials. (c) Time dependent curve for cell viability assessment in SH-SY5Y neuroblastoma cells in direct exposure to the memristive device. Indicated values are means of 8 experimental sets. memristor. This enabled us to evaluate any gross cellular damage, related to cytotoxicity as determined by the release of LDH from the cytoplasm into the surrounding media following cell death. LDH levels were then detected via colorimetric assay through oxidation of a coloured substrate and read in a plate reader at 490nm [106]. We also included positive controls where all cells were lysed giving a maximal response as well as negative controls containing non-exposed cells and background absorbance measured from the culture media. Figure 4-3b shows the cultured cells in a dish in which a typical memristive device was fragmented and dissolved. Figure 4-3c graphs the levels of apparent cytotoxicity when the fabricated memristor was introduced into SH-SY5Y cells cultures as measured using LDH assay. The results indicate that the presence of the fragmented device in the culture medium did not cause any obvious cytotoxicity. 38

Figure 4-4 Electrical characteristics of the silk fibroin memristive device. Measured IV characteristics of the crossbar memristive device fabricated on a glass substrate and a PVA substrate (centre). The Pt electrodes are set at 0 V and the Au electrodes are subjected to a ±5V, 1 Hz triangle voltage waveform with a current compliance of 1µA at room temperature. Photograph of an Au-Silk Fibroin-Pt crossbar memristive device on a glass substrate (left). Photograph of a free-standing Au-Silk Fibroin-Pt crossbar memristive device on a PVA substrate (right).

Next, we investigated the electrochemical properties of the silk fibroin memristors by performing systematic studies. The working principle of the proposed memristive device involves a redox reaction on the electrodes as well as ionic migration within the insulator. On application of the SET voltage, oxidation occurs on the active electrode. The subsequent metallic ions migrate towards inert electrode induced by the applied electric field. This leads to electro-crystallisation and the formation of conductive filaments which result in the rapid reduction in bulk resistance. This transition is termed the SET process. On the other hand, joule heating is raised due to enhanced thermal conductivity of the silk and large current density in percolated filamentary path which causes the dissolution or rupturing of these filaments while applying a RESET voltage, resulting in the rapid increase in bulk resistance and is termed the RESET process [81], [107]. In a typical bipolar memristor device, the SET and RESET voltage are of the opposing polarity.[82] To examine the current-voltage (IV) relationship, a triangle voltage waveform of amplitude 5 V was swept at a frequency of 1 Hz. Figure 4-4 shows the IV characteristics of the Au-Silk Fibroin-Pt memristive device on two different substrates (namely glass and PVA shown in Fig. 3) in which the Au and Pt electrodes serve as the anode and cathode respectively. The fabricated memristive device exhibited non-volatile bipolar switching behaviour where a high resistance state (HRS) and low resistance state (LRS) can be observed via the application of voltage which was also shown to be reversible within the life-

Figure 4-5 Surface topography of the silk fibroin film on a) glass substrate and b) PVA substrate. The silk fibroin film produced on the PVA substrate shows significantly larger surface roughness as compared to the silk fibroin film deposited on the glass substrate. The larger surface roughness originates from the Teflon substrate used to ease the lift of process of the silk fibroin film. Imaging were performed using the Agilent 5500 atomic force microscope. cycle of the device. The voltage was swept in the sequence of 0 V→5 V→0 V→-5 V→0 V with a current compliance level set at 1 µA. By subjecting the active Au electrode to an increasing voltage, the memristor (fabricated on a glass substrate) exhibited a notable change in resistance to a LRS of 5×104 Ω which was recorded during the SET cycle at 3 V. Reversing the polarity of the applied voltage, a RESET cycle was realised in which an abrupt change to a HRS of 0.2×109 Ω occurred at -1.7 V. Remarkably, the fabricated device showed a HRS/LRS ratio of 104 ~ 106 which provides a significantly large margin for differentiating the on to off states ("1" or "0"). The memristor fabricated on a PVA substrate showed a transition from the HRS of 2×1010 Ω to the LRS of 3×106 Ω and vice versa, with an HRS/LRS switching ratio of 102 ~ 104. The SET cycle for the PVA substrate memristor device occurred at a higher voltage of 4.4V whereas the RESET cycle also occurred at -1.7 V. The differences observed in memristive switching between the PVA and glass substrates can be attributed to the non- uniformity of the silk fibroin films as shown by AFM measurements in Figure 4-5. These non- uniformities in silk fibroin thickness resulted in the observed dissimilar resistive switching characteristics. The rough surface of film PVA originated from the Teflon support substrate which impedes the uniform viscous flow of the silk fibroin film leading to a larger thickness and hence, higher operating voltage of the memristor.

One of the key criteria for assessing the memristor performance is the stability of the two resistance states. It has been found that the water annealing process induces crystallinity in the silk fibroin material when incubated in a high humidity environment. The introduction of water molecules disrupts intermolecular cohesive forces between the protein chains and reduces steric hindrance which increases mobility of non-crystalline domains in protein [108]. Therefore, the memristors were treated through a water vapour annealing process to tailor their water solubility and stability; an important step in controlling how fast the devices would dissolve. The water treated and untreated devices were subjected to their respective SET/RESET conditions sequentially and the states were read at a voltage of 0.4V. Devices that had undergone the water annealing treatment exhibited superior endurance characteristics with respect to the untreated devices as depicted in Figure 4-6a. Fourier transformed infrared (FTIR) spectroscopy was performed on both pre- and post-water annealed silk films to verify the degree of crystallinity. Figure 4-7 illustrates the infra-red adsorption spectra of the fibroin film. -1 -1 The absorbance strength ratio of the spectrum 1265 cm and 1235 cm (A1265 / A1235) is commonly used to determine the crystallinity index [109]–[112]. The results show that the water annealed silk fibroin films obtained a higher crystallinity index of 0.80 whereas the untreated films had an index of 0.71. When forgoing the water annealing process, the fabricated devices had a higher tendency to form pinholes in the silk, creating short circuits, during the metal deposition process. This increase in pinholes was attributed to the poorer mechanical strength of the untreated silk fibroin film [113] and the formation of cracks in the film as is shown in Figure 4-8. Thus, the water annealing treatment improves the device yield (the number of fabricated devices with no formation of pin holes) from 41.6% to 81.9% when tested on the 200 fabricated devices.

Figure 4-6 Endurance characteristics and performance of the silk fibroin memristive device. (a) Endurance characteristics for the untreated and the water annealed Au/SF/Ag memristive devices. (b) Endurance performance of the fabricated memristive device with various combinations of electrode materials, namely, Au-Ag, Au-Pt and Au-Cu. (c) Endurance characteristics for the Au/SF/Ag device with current compliance level of 1 mA and 1 µA. (d) State retention time for the fabricated memristive device with various Au-Ag, Au-Pt and Au-Cu electrode combinations over the course of 96 hrs.

Figure 4-7 FTIR-ATR spectrum of the water annealed and untreated silk fibroin film. -1 -1 It shows the absorption strength ratio of the spectrum 1265 cm and 1235 cm (A1265 / A1235) which is commonly used to determine the crystallinity index. The water annealed silk fibroin films obtained a higher crystallinity index of 0.80 whereas the untreated films had an index of 0.71.

The performance of the bio-resorbable memristive device with different combinations of active and inert electrodes, namely Au-Pt, Ag-Au and Cu-Au was also investigated. The fatigue resistance test and retention time test were performed to verify the stability and durability. The results, shown in Figure 4-6b, suggest that Au-Pt and the Cu-Au combinations experience larger degradation in off resistance retention after the 20th cycle in comparison to the Ag-Au combination. Interestingly, the proposed switching mechanism involving the oxidation and reduction of the localised protein chain as discussed in the literature [88] and would be dependent on the work function of the electrodes used. The work function of copper, gold and silver were 4.7 eV, 5.1 eV and 4.73 eV respectively [114]. We have observed large variations in the memristor performance for the Ag-Au and Cu-Au electrode combinations although the copper and silver electrodes have similar work function. This implies that the redox reactions of cations at the interface of silk/electrode plays a critical role in the switching mechanism in addition to the ionic mobility of cations. Overall, the endurance characteristics of the memristive device using various combinations of active and inert electrodes indicate excellent reversibility/reproducibility and acceptable stability prior to the 20th read/write cycle. Current compliance plays an important role in overall device lifetime in addition to the on and off state resistance. We measured that the memory margin increased significantly to an on/off ratio of

Figure 4-8 Helium ion microscopy (HIM) images showing formations of cracks in untreated silk fibroin film sandwiched between metal electrodes. The bright contrast between the metal electrodes indicates the penetration defects within the silk fibroin silk during the evaporation process. Imaging was performed via the Helium Ion Microscope, HIM (Carl Zeiss, Orion Nanofab, Peabody MA, USA) operating at an accelerating voltage of 30 and a beam current of approximately 0.19 pA. Surface charge compensation achieved with support of the electron flood gun.

108 by increasing the current compliance toward a higher level. Figure 4-6C illustrates the measured on/off state resistance for an Au-Ag memristor with two current compliance levels of 1 µA and 1 mA. It was observed that the higher current compliance (1 mA) results in a reduced lifespan of two write cycles whilst the lower compliance current (1 µA) permitted for increased lifespan exceeding 30 write cycles. This behaviour is attributed to joule heating effect which deteriorates the silk fibroin switching layer through intense localised heating [81], [107]. It is worth noting that, as shown in Figure 4-9, the initial device switching characteristics differ from subsequent switching cycles. This is due to initial electroforming process which is commonly observed in ECM type memristive devices [79]. It is believed that morphological change in the electrolyte occurs upon ﬁrst metallic ﬁlament formation leads to a pre-configured electroforming path as an easy transport channel for all upcoming switching processes. Subsequently, the retention performance was evaluated where the fabricated devices memory state was SET and then subjected to the read voltage over the course of 96 hrs (Figure 4-6D). The stability of the memory retention demonstrates the potential of the proposed device in non- volatile memory applications.

Figure 4-9 IV characteristics for an Au-Silk Fibroin-Ag memristor showing the earlier and subsequent cycles. The subsequent read-write cycles show less distinctive off and on resistance state as the memristive device approaches the endurance limit.

Figure 4-10 Chrono-amperometry for Au-Ag electrodes with a bias voltage of 0.8 V to 1 V. The blue, black and green solid line represents a bias voltage of 0.8V, 0.9V and 1.0V respectively. These chrono-amperometry measurements were performed with an ambient temperature of 25 °C, 80 °C, 120 °C and 160 °C.

Figure 4-11 Chrono-amperometry for Au-Pt electrodes with a bias voltage of 1.5 V to 2.5 V. The red, green and black solid line represents a bias voltage of 1.5V, 2.0V and 2.5V respectively. These chrono-amperometry measurements were performed with an ambient temperature of 25 °C, 80 °C, 120 °C and 160 °C.

Figure 4-12Chrono-amperometry for Au-Cu electrodes with a bias voltage of 3.5 V to 4.5 V. The red, green and black solid line represents a bias voltage of 3.5V, 4.0V and 4.5V respectively. These chrono-amperometry measurements were performed with an ambient temperature of 25 °C, 80 °C, 120 °C and 160 °C.

Figure 4-13 State transition time-temperature characteristics of the memristive device and corresponding Arrhenius plot. Arrhenius plot of the measured transition time at different electric potential with various combination of active-inert electrode material: (a) Au-Ag with an applied voltage of 0.8V, 0.9V and 1.0V (b) Au-Cu with an applied voltage of 3.5V, 4.0V and 4.5V (c) Au-Pt. with an applied voltage of 1.5V, 2V and 2.5V. These measurements were extracted from the chrono-amperometry measurements with varied ambient temperature of 25 °C, 80 °C, 120 °C and 160 °C. Indicated values are mean of 10 devices each. See supplementary materials for details. (d) Comparisons of the cyclic voltammograms for various electrodes as shown in the legends. The scan speed is 50 mV/s. The physicochemical properties of the switching characteristics for silk fibroin memristor play an important role in the functional characteristics of the device. Chrono-amperometry and cyclic voltammetry (CV) techniques were employed to study the effects of the various electrodes on the overall performance and electrical characteristics of the memristive device. Figure 4-10, Figure 4-12 and Figure 4-11 illustrate the chrono-amperometry results in which

Figure 4-14 Optical image showing the dimension of the crossbar memristive device. the SET transition time was determined to estimate the Arrhenius parameters. Figure 4-13a-c shows the Arrhenius plot for varying ambient temperatures ranging from 298 K to 433 K with various electric potentials applied to the memristive device. Based on the chronoamperometry measurements, it was observed that the state transition time decreases exponentially with both increasing ambient temperature and with increasing applied voltage. The extraction of the

Ea / k BT effective activation energy, Ea, was calculated via the ln(1/ t set )  e expression, where kB is the Boltzmann constant, T is the ambient temperature and tset is the SET transition time and used to calculate the zero-potential activation energy and the electric potential induced barrier lowering parameter. Figure 4-13D shows the CV measurements for the silk fibroin memristive device for various electrode materials with an area of 41μm × 41μm as depicted in Figure 4-14. These measurements were performed with sweep rate of 50 mV/s whilst the potential window was restricted to a lower amplitude range to prevent the onset of the resistive switching process. The observed peak currents in the cyclic-voltammetric curves are attributed to the dissolution of active electrode material in silk via the oxidation to cations followed by deposition of reduced (neutralized) cations at the silk-counter electrode interface [54]. It should be mentioned that the geometrical characteristics of the proposed memristor device requires the omission of the reference electrode which is typically used in CV measurement to ease the identification of the electrochemical reactions. However, by considering the thermodynamic stability of the ionic species, it is possible to deduce the corresponding partial electrochemical reaction.[54] Referring to the CV measurement for the Ag-Au electrodes, the peak (A) and (B) can be associated with the direct oxidation of Ag to Ag+ and reduction of Ag+ to Ag respectively. Similar assignments of recorded peak currents to their respective reactions at the electrode interface have been previously reported [54], [115], [116]. In this configuration (Ag/Au), the

48 oxidation of the Au electrodes has not occurred because of the consistent ability of our device to retain the off state when subjected to the negative polarity (as shown in Figure 4-9). For the memristor device with Au-SF-Pt configuration, peaks (C) and (D) are proposed to be associated with the direct oxidation of Au to Au+ and reduction of Au+ to Au respectively due to the similarly occurrence of peak current with respect to the Ag electrodes. In the case of the Au- SF-Cu memristor, peaks (E) and (F) can be linked to the oxidation of Cu to Cu+ and Cu to Cu2+ respectively. The peak (G) is associated with the reduction reaction Cu+ to Cu and peak (H) is linked to the reduction reaction of either Cu2+ to Cu [54], [117]. Other partial reactions of the ionic species such the reduction of Cu+ to Cu and Cu2+ to Cu+ could also have occurred [117], [118]. The current peaks of these partial reactions may be obscured by the lower resolution of the two-electrode cyclic voltammetry method. In addition, these current peaks have been observed to fluctuate for different voltage sweep cycles as concentration of these ionic species constantly changes [117]. The studies with different electrode combinations suggest that the switching characteristics are highly influenced by the type of electrodes used which would deviate from the findings that the reduction or oxidation of localised silk fibroin protein chains are the primary factors for the resistive alterations [88]. Furthermore, our studies demonstrate the feasibility of tuning the operating voltage of the memristor device by the selections of electrode material.

4.2.2 Numerical Modelling for the Resistive Switching Mechanism Based on the experimental data, we have observed that the Ag electrodes exhibited the highest likelihood for the formation of conductive filament followed by the Au and Cu electrodes. These observations differ from the expected outcome as would be predicted by their standard electrode potential in which the Cu electrode should have the highest tendency for ionic migration. The likely reason for this phenomenon is that the electrolytic migration rate of metal ions in a thin insulator is limited and can be determined by the following expression[119], [120]:

N z x 2 ρ t  4-1 2 n cV where t is time required for the ions to traverse through a thickness of x, N is the cations density, z is the charge of the cations, ρ is the resistivity of the insulator, nc is the transport number of the cations and V is the applied voltage. From Equation 4-1, metal elements with higher charge cations will require a longer time to migrate along the insulator, resulting in a longer state transition time. Similarly, the transition time can also be reduced by increasing the applied

49 voltage between these electrodes. Thus, the Cu electrode will typically exhibit higher state transition voltage compared to the Ag and Au electrodes to achieve similar state transition time. This is presumably due to the higher thermodynamically stable oxidation state of +2 for the copper element which has been observed in various thin insulators, such as vitreous silica and quartz [119]. Thus, for circumstances in which the electrolytic process is limited by the charge transfer kinetics, e.g. an insulator with low ionic conductivity, the stable oxidation state of the metal ions of the electrodes seems to be the key factor determining the electrical properties and resistive state stability of the memristor device whereas the standard electrode potential of the metal electrodes has less pronounced effect.

Based on our findings, the electrochemical metallisation model proposed for a silk fibroin memristor device can be described in several steps, beginning with the electrochemical dissolution of the active electrodes into their respective ionic species, followed by ionic migration of the cations towards the inert electrodes under high electric field and lastly, the electro-crystallisation of cations to form conductive filaments. On the other hand, the dissolution of these conductive filaments involves the thermally assisted dissolution of metals via joule heating under high electric field of the opposing electric potential. The opposing electric potential ensures the cessation of filamentary growth and promotes the rupturing of these conductive filaments. In addition to silk fibroin, it has been demonstrated that typical dielectrics or insulators such as silicon dioxide, titanium oxide and nickel oxide exhibits electrolytic characteristics provided they are sufficiently thin, usually ranging from tenths to hundredths of nanometres.[115] The SET process involves the application of sufficiently high positive electric potential on the active electrode which leads to an oxidation process on the active electrode-insulator interface as describe by reaction 4-2 [78]:

MMz  ze 4-2 where M, Mz+ and z denotes the metal atoms, metal ions and the charge of the ionic species respectively. It is suggested that primarily Ag+ and Au+ ions are involved for Ag-Au and the Au-Pt electrode combination respectively whereas the Cu+ and Cu2+ ions are involved for the Cu-Au electrode combination. The cations formed from this reaction proceeds to migrate towards the inert electrode due to the high electric field. Lastly, these cations are gradually reduced and electro-crystallised on the inert electrodes and forms conductive filaments which are associated with the SET process. Cyclic voltametric studies in Fig. 5d have revealed the

50 relevant ionic species corresponding to each of the oxidation and reduction process for various electrode combinations.

On the other hand, the RESET process involves the application of a negative electric potential in which these conductive filaments undergo thermal dissolution as well as the reduction to their ionic form, indicated by reaction 4-3, and as suggested by the cyclic voltametric studies.

푀 + ze 푀 4-3

An interesting observation is that metallic ions with higher oxidation states may require the application of a higher electric potential to initiate the oxidation process and can be described by Equation 4-1. To facilitate the oxidation process of the active electrode, a complementary reduction process has to occur on the inert electrode–insulator interface [115]. In the case of a thin film silk fibroin layer, we believe that water content within the silk fibroin film, similar to that of silicon dioxide [54], [117], [118] and tantalum oxide[121], is involved in the reduction process as shown below:

2H푂 + 2e 2OH + 퐻 4-4

2H푂 + 푂 + 4e OH 4-5

Typically, silk fibroin film has an inherent water content of 7.5% under ambient conditions[89]. Several proposed candidates as depicted by reaction 4-4 and reaction 4-5 are used to account for these reduction processes with which may not be the full representation due to the possibility of various other intermediary reactions [78]. These reactions are highly dependent on the chemical properties of the insulator film as well as the adsorption properties of the electrodes used [115]. Numerical modelling of these phenomena can provide an insight of the physical changes within the silk fibroin layer. The ionic migration velocity in an insulator under applied electric field can be expressed as [120]:

푛 푉 푣 = 4-6 N z ρ x where x is insulator thickness, N is the cation density, z is the charge of the cations, ρ is the resistivity of the insulator, nc is the transport number of the cations and V is the applied voltage. The kinetic mechanism of the electro-crystallisation process can be described in form of [122]:

()/RT 4-7 퐽(푡) = 푍Wλ 푒 where J(t) is the rate of nucleus formation, Z0 is the density of nucleation sites, W is the

-1 frequency of nucleus attachment, λ is the Zeldovich factor and GΔ(nc) is the energy barrier for

Figure 4-15 Simulation geometry definition and process flow. (a) Simulated geometry used in the numerical solver. (b) Simulation algorithm flowchart. the conversion of nc number of ions into their solid phase. Despite the theoretical accuracy, it is difficult to correctly ascertain the parameters used in equation 4-6 and 4-7. Conversely, the Arrhenius equation provides a simple closed form expression with similar form for modelling these behaviours and will be fitted to the experimental data.

Here, we introduce a numerical model to further corroborate on the proposed switching behaviour for silk fibroin based memristive and prove mode insight into understanding of the switching mechanism based on the morphological changes of the conductive filament. To facilitate the finite element simulation of the dissolution and growth of the conductive filament, a cylindrical conductive filament is proposed to describe the initial nucleation of the conductive filament which will be used as basis of the resistive transition. The simulation model assumes that the initial electroforming process has occurred and consists of a silk fibroin layer which encapsulates a cylindrical filament of diameter 2 nm in agreement with surface resistivity observation using a conductive atomic force microscopy [88]. The top and bottom electrodes were expressed as single dimensional lines and as the active electrodes, assumed to be an infinite source of cations. This simulated geometry is as shown in Figure 4-15a. A simulation model based on the numerical solution for joule heating (Equation 4-8–4-11) as well as the growth or dissolution of the conduction filament using Equation 4-12–4-13 are performed with

52 simulation package (COMSOL Multiphysics, MATLAB) to realize the state transition behaviour of the memristive device. The simulation process flow is depicted in Figure 4-15b. The following expressions are used to explore the joule heating characteristics for the conductive filament:

k'∇푇 = −γ⃗J ⋅ 퐽⃗ 4-8 훾′ = 푛훾 4-9 k' = n k 4-10 1 4-11 퐽 = 훻휑 γ' where k is the thermal conductivity, γ is the resistivity, T the temperature of the conductive filament, φ the temperature gradient and J is the current density. An additional fitting parameter n is defined to account for the effects due to the development of multiple conductive filaments as well as any non-uniformity, defects and voids in the filaments itself. Based on the Wiedemann-Franz law [123], the thermal conductivity is assumed to exhibit a similar proportionality to n-parameter. These differential equations only accounts for the steady state heat transfer mechanism since the migration of ions, the electro-crystallisation process and the filamentary dissolution process are relatively slower than a typical thermal system [33]. An Arrhenius fitting equation is employed to describe the growth and dissolution of the conductive filaments as they provide a simple yet close approximation of the mathematical behaviour of the Equation 4-6–4-7. The electric field-assisted migration of ions in the silk fibroin layer exhibited a linear dependency with respect to the effective activation energy, Ea,[55], [124] as shown in Figure 4-13. Based on these Arrhenius plots, the extracted zero-potential activation energy, E0, were 0.25, 0.69 and 0.71 whereas the energy barrier lowering parameters, α, are 0.19, 0.13 and 0.08 for the electrode combinations Au-Ag, Au-Pt and Au-Cu respectively

αV 푑rset 4-12 = 퐴 e RT 푑푡 set 푑rreset 4-13 = 퐴 e RT 푑푡 reset where r is the growth or dissolution radius of the conductive filament, A is pre-exponent fitting parameter, E0 is the zero-potential activation energy, R is the Boltzmann constant, T is the temperature, the α is the barrier lowering parameter and V is the applied electric potential. The material parameters for the silk fibroin film, described in Table 4-1, were used in the simulation. The numerical procedure includes two main steps where the coupled Equation 4-8–4-11 were

Table 4-2 Electrical, thermal and mechanical properties for Silk Fibroin. The following material properties are used in the simulation model to replicate the experimental data.

Material Properties Value Ref Thermal conductivity (W / m K) 0.256 [69] Density (kg / m3) 1398 [70] Heat Capacity (J / g K) 0.134+3.696×10-3 T [71] Electrical Conductivity (S / m) 4.4×10-13 [72] Relative Permittivity 6 [73] solved based on a 2D symmetrical model followed by the extraction of the temperature and electric potential profile along the surface of the conductive filament. These data determine the growth or dissolution rate, governed by Equation 4-12–4-13, and are used to update the geometry of the filament as is illustrated in the flowchart in Figure 4-15B. The numerical methods correctly replicated the experimental results when the fitting parameters described in Table 4-3 were used.

Figure 4-16 Comparison between numerical simulation and experimental IV characteristics of the set/reset process for different combinations of electrode material (a) Cu-Au electrodes (b) Au-Ag electrodes (c) Pt-Au electrodes. The blue dashed curve represents with experimental results; (the black solid line represents experiments while the dashed line shows simulation results). Geometrical and physical parameters are listed in Figure 4-15 and Table 4-3.

Figure 4-16a-c shows the comparison between the simulated and experimental IV characteristics for the fabricated memristive device with various combination of electrode material. The numerical model predictions show good correspondence with the measured IV

Table 4-3 Numerical simulation fitting parameters. The following fitting parameters are used in the simulation model to replicate the experimental data.

Fitting Parameters Electrode Combinations Ag-Au Cu-Au Au-Pt

-6 -6 -6 Aset (m/s) 5×10 5×10 5×10

-6 -6 -6 Areset (m/s) 5×10 5×10 5×10 n 4×10-3 8×10-4 5×10-3

characteristics which substantiate their validity for these types of memristive device. The morphological changes in the conductive filament illustrate the device transition from a low resistance state to high resistance state and vice versa. Physical geometry of the conductive filament corresponding to their temperature distribution is illustrated in which Figure 4-17a-d shows the reset transition with increasing negative electric potential whereas Figure 4-17e-f shows the set transition with increasing positive electric potential. The proposed numerical model predicted a localised region of high temperature at approximately ~450K. Several assumptions were made to simplify the simulation process which includes the cessation of filament growth following the formation of a continuous conduction bridge, non-active electrodes are ideally inert and formations of voids in the electro-forming or electrochemical process are ignored. The effects of dissolution due to joule heating during the set process are assumed to be negligible as observed from experimental data. It is observed that the rate of growth of these conductive filaments is in equilibrium with the rate of dissolution and that this translates to the stability of the on-state resistance. The bulk conductivity of silk fibroin has been increased to 400 μS/cm to account for the higher conductivity as observed from the experimental results following the electroforming process. This is presumably caused by the higher concentration of cations and residuals from ruptured conductive filaments in the silk fibroin film.

Figure 4-17 Surface plot for the temperature distribution and morphology of the conductive filament. The illustration shows the sequential cycle of the SET/RESET process for an applied voltage of (a) 0V, (b) -0.2V, (c) -0.3V, (d) -0.5V, (e) 0.5V, (f) 0.7V using parameters for the Au-Ag electrodes.

4.3 Summary We have proposed and demonstrated an environmentally friendly and bio-resorbable memristive device fabricated by interlaying a silk fibroin layer, extracted from the Bombyx Mori silkworm cocoon, between an inert (Pt) and active (Au) metal electrode. The fabricated devices exhibit bipolar switching characteristics with an on / off ratio of >104, a lifecycle of >30 and a state retention time of >96 hrs. This device showed a physical transience of about 30 mins in DI water under ambient conditions. This is a critical step in the development of printable and bio-resorbable electronics which offers great potential to envisage fabrication of on-demand electronics that are used for tailored specific implantable devices and bio-sensors. Furthermore, various combinations of electrode materials were used to study their effects on the switching characteristics of the fabricated device as well as their respective physicochemical properties. Although the standard electrode potential of the metal electrodes does provide slight influences, it was observed that the oxidation states of the cations strongly affects the switching mechanisms of the fabricated memristive devices for systems with low ion mobility. In general, it can be concluded that cations with high stable oxidation states require higher SET / RESET voltage. Thus, the selection of electrode combinations to form the memristive device must account for these factors to avoid haphazard switching characteristics which may lead to erroneous retention of states. A numerical model was proposed, based on the Arrhenius equation, to provide an insight on the morphological alterations during the switching process. This model provides an accurate quantitative description of the resistive switching mechanism with respect to the performed experimental data in this study.

4.4 Methods 4.4.1 Device Fabrication Extraction of silk fibroin protein used for this investigation were carried out as previously described by Kaplan et. al.[125]. Initially, Bombyx Mori cocoon pieces were boiled in 0.02M

Na2CO3 for 30 minutes and rinsed thoroughly with DI water as a degumming process to remove the Sericin protein binding the fibroin fibres. The extracted silk fibroin fibres were then dissolved in 9.3M Lithium Bromide (LiBr) solution at 60°C for 4 h. Subsequently, the obtained solution was dialyzed in DI water using the dialysis membrane with a cut-off molecular weight of 3.5kDa for 72h to remove LiBr impurities followed by centrifugation. The resultant purified silk fibroin solution is freeze dried and preserved for future usage under -40°C refrigeration. The freeze-dried pellets were reconstituted to form 5 wt% silk fibroin solutions and filtered with a 0.2 µm syringe filter. The crossbar memristive device was fabricated on both a flexible biodegradable PVA substrate as well as a glass substrate. A layer of 10 nm Cr and 50 nm Au or 50 nm Pt were evaporated on a glass substrate using a Thermionics VE180 electron-beam evaporator at a pressure of 10-7 Torr. The corresponding gold-coated glass substrate was cleaned with isopropyl alcohol followed by de-ionised water in an ultrasonic bath for 8 minutes. The glass substrate was then patterned using laser ablation lithography (SUSS SLP300) to form the bottom electrodes. The reconstituted silk fibroin solution was spin-coated onto the patterned substrate at 1000 rpm for 1 min followed by water-annealing. The water annealing process involves the material being exposed to a high humidity environment. This was done by storing the device in a water chamber at -25 kPa for a period of 24 hrs. Cross-sectional imaging in Fig. S1 has shown that the spin-coated silk fibroin layer has a thickness of approximately 250 nm. To finalise the device, a 50 nm top electrode (Au, Cr or Ag) was evaporated onto the fibroin layer with the aid of a shadow mask. The bio-resorbable memristive device was initially fabricated by drop-casting PVA on a Teflon substrate followed by the spin-coating of PMMA A2 (2% PMMA / 98% Anisole) at 1000 rpm for 1 min. Similar as mentioned above, a layer of 10 nm Cr and 50 nm Au or 50 nm Pt were evaporated. Next, the reconstituted silk fibroin solution was spin-coated onto the pattern substrate followed by water-annealing in a water chamber. The 50 nm Au top electrode was then e-beam evaporated through a shadow mask. To form the free-standing memristive device, the PVA substrate was lifted off the Teflon supporting structure via mechanical agitation.

4.4.2 Cytotoxicity assessment The LDH assay was performed using the Promega cytotoxic detection kit in conjunction with the Molecular Device SpectraMax M3. A 24 well culture plate was seeded with SH-SY5Y at a concentration of 103 cells/ml. Test wells were prepared with dissolved sections of the memristor together with positive and negative controls as recommended by the LDH assay manufacturer. We tested different incubation times of the cells with the dissolved section (1, 24, 168 hrs) to verify the absence of chronic and acute toxicity. At different time point, the detection of LDH activity was performed by transferring 50µl of culture solution to a 96 well plate together with the 50µl of reaction solution. After 30 minutes, the stop solution was added and 490nm wavelength adsorption was measured.

4.4.3 Electrical Measurement The electrical characterisation for the crossbar memristive devices were performed using the Agilent E5270B Precision IV Analyser in conjunction with a Cascade Microtech Summit Semi-Automated Probe Station and an ERS AirCool thermal regulation system. Chrono- amperometry was measured on the Cascade Microtech Summit Semi-Automated Probe with the chuck temperature set to 25°C, 80°C, 120°C and 160°C with different stimulation voltage supplied via the Agilent IV Analysers. Electrochemical measurement of the cyclic voltammograms (CV), were conducted on an electrochemical workstation at room temperature. CV measurements were carried out with a triangular voltage signal between -3 V and 3 V for Au-Pt and Au-Cu electrodes and between -1 V and 1 V for the Au-Ag electrode at scan rates of 50 mVs-1.

4.4.4 Material Characterisation FTIR-ATR spectrum measurements were obtained using the PerkinElmer FT-IR spectrometer over the 650 to 4000 cm-1 spectra with a resolution of 1 cm-1. AFM was used for the surface morphology and surface roughness analysis of silk fibroin films. AFM images were obtained with Agilent System (Agilent 5500 atomic force microscope) by using a commercially available silicon nitride cantilever with a force constant of 0.08 N m-1.

5 Solution Processed Organic Silk Fibroin Memristor for Resistive Logic Applications

Growing demand for low-cost electronics has motivated the development of novel solution- based techniques due to its potential as a cheap, large scale fabrication methodology. This technique relies heavily on the integration of complex multifaceted areas of semiconductor fabrication and material science, with various aspects still undergoing intensive research and development. The realisation of a high-performance solution-processed memristors remains an important research challenge. Memristors are two-terminal memory devices characterised by their highly non-linear current-voltage relationship. These devices are the building blocks capable not only of data storage but also performing logic computation. This paper presents a solution processed silk fibroin memristor which demonstrated bipolar resistive switching ratio of 105 and possesses a retention time of over 96 hrs without any observable degradation. Moreover, the paper also presents a mathematical model which serves as a reliable design and validation SPICE model. Finally, a 1-bit full subtraction memristor circuit followed by a shift- subtraction memristor based division circuit is presented as a case study.

5.1 Introduction Resistive memory or memristor represents a new class of electronic devices which shows promising application in the future high-density memory technology. Memristors are typically a two-terminal device implemented as a MIM (metal-insulator-metal) structure by which the insulation layer undergoes physio-chemical reaction upon the application of an electrical potential, inducing a change in electrical conductivity across the terminals. The most common models used to explain the resistive switching mechanism is the formation and rupturing of conductive filaments within the insulation layer which can be explained with the electrochemical metallisation process or the valance change mechanism [53]–[55]. These physical properties of a memristor manifest as the modulation of resistance on the terminals, allowing for the non-volatile encoding of logical information.

Conventional metal oxide based memristor devices using transitional metal such as TiO2,

SrTiO3, ZnO and NiO have shown many desireable properties and can be integrated with

60 conventional complementary metal oxide (CMOS) technologies [126]–[129]. Recently, solution process deposition techniques have been extensively investigated as a potentially candidate for memristor fabrication using various solution-based insulation material such as: sericin, sol-gel titanium oxide, PEDOT:PSS or silk fibroin [36], [130]–[132]. Unlike conventional technologies, these techniques are a fully additive fabrication process, capable of large area batch electronic fabrication with the added benefit of significant flexibility in the choice of substrate.

Furthermore, silk fibroin, from the Bombyx Mori silkworm cocoon, is bio-material with interesting mechanical and electrical properties. It has been proposed to be an ideal material for producing a variety of high-performance biocompatible and flexible electronics devices [84], [85], [87]. In addition its adjustable dissolution rates in water, via the use of various encapsulating materials polycaprolactone or thermally embossed silk fibroin, are another advantage when used for transient electronics [89], [91]. In recent work, silk fibroin has been shown to be a suitable candidate for the fabrication of a memristor. A comprehensive study on the switching mechanisms of silk fibroin memristors has been discussed in [88], [95], [99], [131].

The focus in the integration of memristive devices with conventional electronics has been primarily focused on the data storage applications. Recently, memristors have been used to also perform logical operations using a variety of novel computing architectures such as the hybrid memristor ratioed logic-CMOS architecture, the memristor aided logic architecture and the material implication architecture [56]–[58]. These architectures allow the binary operations to be performed and their logical information to be stored within the same device.

In this chapter, we report on the solution process-based fabrication technique and the characterisation of a crossbar silk fibroin-based memristor. The as-fabricated device not only exhibited exceptional resistive switching characteristics with a low operating voltage of 1.2V, it possesses a memory window of 105 throughout 30 switching cycles. We then proposed a numerical model to emulate the memristive characteristics of the fabricated device. Furthermore, we presented, for the first time, a memristor circuit for performing logic operations namely the 1-bit full subtraction and division operations. Results which were validated through SPICE/Spectre simulations. The 1-bit full subtraction circuit cell consists of 8 individual memristor elements which can be cascaded to increase the bit-width and will be used to implement the shift-subtraction based divisor circuit.

5.2 Device fabrication

Figure 5-1 (a) Optical image of the fabricated 16x16 memristor device array. The crossbar structure is both 15 mm in width and length. (b) Helium ion microscopy (HIM) images showing the cross-sectional image on the silk fibroin film interposed between metal electrodes operating at an accelerating voltage of 30 and a beam current of approximately 1 pA. Scale bar, 100 nm.

The proposed crossbar memristive device consists of a spin-coated silk fibroin switching layer stacked between an active electrode and an inert electrode supported on a glass substrate. Figure 5-1a shows a light microscope image of the fabricated 16×16 crossbar memristor array. The memristors are based on a metal-insulator-metal structure which comprises of a silk fibroin layer interposed between a gold (Au) bottom electrode and a silver (Ag) top electrode. The devices were fabricated on a SiO2 substrate where the 10 nm Cr / 50nm Au bottom electrode was patterned via the electron beam evaporator through a shadow mask at a pressure of 10-7 Torr. The insulator layer was then formed by spin-coating a reconstituted silk fibroin solution at a 1000 rpm. Finally, 50nm of Ag was evaporated on the silk film via a shadow mask to form the top electrodes. The preparation of the silk fibroin solution was carried out as previously described in [125]. For completeness the methods are briefly described here. The Bombyx Mori cocoon pieces were boiled in 0.02M Na2CO3 for 30 minutes and rinsed thoroughly with DI water as a degumming process. The extracted silk fibroin fibres were then dissolved in 9.3M Lithium Bromide (LiBr) solution at 60°C for 4 hr followed by dialysis in DI water using a dialysis membrane with a cut-off molecular weight of 3.5kDa for 72h. The purified silk fibroin solution is freeze-dried and preserved for future usage under -40°C refrigeration. The freeze- dried pellets were reconstituted to form 5 wt% silk fibroin solutions and filtered with a 0.2 µm syringe filter. Figure 5-1b shows the cross-sectional imaging of the memristor indicating a silk fibroin layer of 150 nm was deposited.

5.3 Device characterisation and Numerical Modelling To investigate the resistive switching behaviour, the current-voltage (IV) characteristics of the fabricated devices were measured with an Agilent Technologies E5270B. The voltage was swept in the sequence of 0 V → 2 V → 0 V → −2 V → 0 V with a current compliance level set at 1 mA. Figure 5-2 illustrates the typical memristive switching characteristics, pinched hysteresis loop, as the devices were subjected to a 1 Hz triangular voltage waveform of 2V amplitude. No initial electro-forming process was required to induce the resistive switching behaviour for the fabricated device. By subjecting the active silver (Ag) electrode to an increasing voltage, the memristor exhibited a notable change in resistance to the low resistance state of approximately 300 Ω. Reversing the voltage polarity, a reset cycle can be observed with a rapid change to a high resistance state of approximately 40 MΩ. These memristors exhibited a low to high resistance state ratio of 105 which provided a significantly large margin for differentiating the on to off states with a relatively low set voltage of -1.1V and a reset voltage of 1V.

Figure 5-2 Typical experimental and numerically modelled IV (current-voltage) characteristics of the fabricated silk fibroin device.

Stability of the memristor states and their retention capabilities represents some of the key figures of merits for evaluating the performance of a memristor device. Figure 5-3a shows the measured high and low resistance states of the fabricated memristor for a sequence of read and write cycles. The cyclic read and write process was performed by exerting the device to 30 repetitive set and reset cycle in which their resistance was measured at a lower applied voltage of 0.5 V to prevent unintended alteration of the memristive state. Overall, the fabricated silk fibroin memristor device exhibited a stable memristive state throughout the switching cycles.

Figure 5-3b demonstrates the memory retention capabilities of the device over a period of 96 hours. The fabricated silk fibroin memristor performs favourably in comparison to previously reported organic material based memristor such as egg albumen, PMMA/PHEMA and sericin [36], [92], [93].

Figure 5-3 (a) Endurance performance of the silk fibroin memristor. (b) State retention time for the fabricated memristors over the course of 96 hrs. The resistance states were measured with an applied voltage 0.5V.

For the simulation of the resistive logic system, a spice compatible numerical model describing the physical behaviour of the fabricated device is required. At present, several numerical models have been proposed, namely, the linear ion drift model, non-linear ion drift model, Simmons tunnel barrier model, threshold adaptive memristor model (TEAM) and voltage threshold adaptive memristor model (VTEAM) [133], [134]. In addition, a constraining equation, termed window functions, should be introduced into the memristor models to restrict the operational region of the state variable which is the thickness of the active switching layer and provide a more accurate empirical representation of the higher order nonlinearity observed [134], [135]. The VTEAM model in conjunction with the Biolek window function as described in Eq. (5-1)-(5-3) is used. The governing equation of the IV characteristic for the VTEAM model is defined as [133]:

푅 − 푅 5-1 푖(푡) = 푅 + 푤 − 푤 where Ron and Roff are the low resistance state and high resistance state respectively, won and woff are the minimum and maximum allowable state variable, i(t) is the device current and v(t)

64 is the potential difference across the memristor device with respect to time. The temporal progression of the state variable is defined by [71], [133]:

v(t) ⎧k − 1 α f (w) , 0 < v < v v dw(t) ⎪ = 0 ,v

w 5-3 f,(w) = 1 − − signum−i(t) w where p is a fitting parameter. The proposed VTEAM fitting parameters are shown in Table

5-1. The fitting procedure relies on the iteration of koff/on and αon/off in order to minimise the normalised root-mean-square deviation (RMSD) error as depicted by Eq. 5-4.

∑I − I , , 5-4 RMSD = I,T

where T is the number of samples, Imodel,t and Iexp,t are the output current of the corresponding sample, t for the numerical model and the experimental model respectively. The accuracy of the proposed model is validated by the tight agreement between both simulation and experimental results for the silk fibroin-based memristor devices as shown in Figure 5-2 with a normalised RMSD error of 8.97%.

Table 5-1 Fitting parameters for the VTEAM model Fitting Parameters Values kon (nm / s) -1e-3 koff (nm / s) 1e-3 aon 1.5 aoff 1.5 von (V) -1 voff (V) 1 won (nm) 0 woff (nm) 150 p 5 Roff (Ω) 400

5.4 Implication Logic A multitude of logical operations has always been utilised to develop an abstract understanding of a Boolean logic. However, only three of those logic operations are implemented in the field of digital electronics and computing, namely, the OR, the AND, and the NOT operations as these are readily implementable in conventional CMOS technologies. The memristive element allows the intrinsic hardware implementation of a fourth logical operation, material implication. The basic building block of a material implication logic consists of two memristor devices, A and B, which are connected to a load resistor, RL. The configuration can be easily realised by a crossbar array of memristors in which each connecting electrodes are driven by tri-state voltage drivers.

To permit the desired operations of the proposed memristor logic circuit, the selection of the load resistance, RL, is a critical and should typically be chosen between Ron and Roff for the desired electrical properties of the system [56], [136]. For all subsequent implication logic circuits, the load resistance, RL, of 10kΩ was used. To perform implication logic, conditional toggling was performed in which a voltage pulse of -1.5V is applied on device A and a conditional voltage pulse of -0.5 V is applied on device B simultaneously. The switching behaviour due to the interaction between the set and conditional voltage pulse highly depends on the states of the memristor. The material implication logic operations can be described as follows: in cases where A = 0 (high resistive state), the voltage divider is unaffected and thus, B is set by the potential difference caused by the conditional pulse; for A = 1 (low resistive state), the voltage divider is shorted and B is unaffected by the conditional pulse [56]. The spice simulation for the logic operation, A→B, is as shown in Figure 5-4.

Figure 5-4 The simulation data demonstrating stimulation voltage waveform of the material implication process as well as the subsequent input and output resistance state for a single memristor logic cell.

For practical reasons, it is inadequate for the material implication operation to fully realise all the required functions of a logic circuit. Thus, the conventional logic operations can be translated into the implication equivalents as defined in Table 5-2 [137], [138]. In contrast, the equivalent logic requires several implication logic executions to realise the desired binary output. Thus, these memristor-based implication logic operations require lengthy computational sequence and complex control circuitry to implement the fundamental logic operations. Regardless, the usage of these logic equivalents allows the realisation of all arithmetic circuits and can be useful in certain low power stateful applications, or in logic parallelisation circuit architectures [139], [140].

Table 5-2 Translation of material implication to the equivalent conventional logic operations

Conventional Logic Implication Logic Equivalent ¬A A → 0 A ∨ B (A → 0) → B A ∧ B (A → (B → 0)) → 0 A ⊕ B (A → B) → ((B → A) → 0)

5.5 Nth bit implication logic full subtractor Several arithmetic operations have been realised using the proposed resistive logic approach as described in literature namely a full bit adder circuit and a multiplication circuit [141], [142]. Thus far, the resistive logic equivalent of a subtractor circuit has yet to be studied and represents one of the important circuitries in an arithmetic logic unit. This section of the paper will present the simulation model as well as the proposed structure of a 1-bit full subtractor memristor circuit followed by the generalisation of an n-bit subtractor circuitry. The proposed memristor- based subtractor configuration circuit is as shown in Figure 5-5.

Figure 5-5 Proposed structure for the implication logic based nth bit subtraction circuit.

The conventional logic implementation of the proposed subtractor circuit is defined as:

S = (A ⊕ B) ⊕ 퐵퐼 5-5 퐵푂 = (퐴̅ ∙ 퐵) + (퐴 ⊕ B) ∙ 퐵푂 5-6 The material implication logic equivalent of a 1-bit full subtractor can be expressed as the summation bit, Eq. 5-8:

푊 = 퐴 ⊕ B 5-7 = (퐴 → 퐵) → [(퐵 → 퐴) → 0]

푆 = (푊 → 퐵푂) → [(퐵푂) → 푊] → 0 5-8 and the borrow bit, Eq. 5-12:

푋 = 퐴 → (퐵 → 0) 5-9

푌 = (퐴 → 퐵) → [(퐵 → 퐴) → 0] → 0 5-10

푍 = [푌 → (퐵푂 → 0)] → 0 5-11

BO = 푋 → 푍 5-12 The mathematical notations X, W, Y and Z used in this context are the intermediate arithmetic products provided for visual simplicity. The execution of this operations requires 5n+3 th memristor elements as shown in Figure 5-5 where Ai, Bi, and BOi denotes as the i input bits, ith summation bits and the ith borrow out bits respectively. In this serialised approach, a total of 34n computational steps are required as shown in Table 5-3.

Figure 5-6 Excitation voltage waveform for the 1-bit full subtractor circuit with respect to the input, output and intermediate memristor elements for individual stages of the computational process. The red and cyan highlighted waveform indicates the set and conditional pulse for the imply operation respectively whereas the green highlighted waveform indicates the memristor reset process.

The generalised computational steps for performing an n-bit subtraction operation are described in Algorithm 1. In this context, the memristor elements An, Bn, BOn and Sn represents the minuend bit, subtrahend bit, borrow out / borrow in bit and the resultant difference bit.

Memristor elements T1, T2, and T3 are used to perform the required intermediate computational steps without disrupting the input data bits stored in memristor An and Bn. A case study of a 1- bit full subtractor was simulated using the proposed computational steps.

Table 5-3 Computational steps for a full 1-bit memristive subtractor circuit Step Operations Descriptions StepOperationsDescriptions

1 B → T3 T1=B (Copy) 20 BO-1 → T2 T2 = (BO-1 → W)

2 T3 → T1 21 T2 → S S = (BO-1 → W) → 0

3 Reset T3 Reset T3 22 T1 → S S=(W→BO-1) →((BO-1→W) →0)

4 A → T1 T1=A→B 23 Reset T1 Reset T1

5 A → T3 T2=A (Copy) 21 T2 → S S = (BO-1 → W) → 0

6 T3 → T2 22 T1 → S S=(W→BO-1) →((BO-1→W) →0)

7 Reset T3 Reset T3 23 Reset T1 Reset T1

8 B → T2 T2 = B→A 24 Reset T2 Reset T2

9 T2 → T3 T3 = (B→A) → 0 25 T3→ T2 T2 = Y

10 T1 → T3 T3 = (A→B) →((B→A)→ 26 Reset T3 Reset T3 0)

11 Reset T1 Reset T1 27 BO-1→ T3 T3 = BO-1→ 0

12 Reset T2 Reset T2 28 T2 → T3 T3 = Y → (BO-1→ 0)

13 BO-1 → T2 T1=BO-1 (Copy) 29 T3 → BO BO = Z

14 T2 → T3 30 Reset T2 Reset T2

15 Reset T2 Reset T2 31 BO-1 → T2 T2 = BO-1 → 0

16 T3→ T1 T1 = (W→ BO-1) 32 A→ T1 T1 = Ā

17 T3→ S Copy W to T2 33 T1→T2 T2 = Ā→ (BO-1 → 0)

18 S → T2 34 T2→BO BO =X → Z 19 Reset S Reset S

The corresponding control voltage waveform and the output waveform of the simulation are illustrated in Figure 5-6. To perform these computations, the conditional control and set voltages are assigned to -1.5 V and -0.5 V respectively. To recover previously utilised memristor elements, a reset pulse of 3 V is applied to the junction in which the elements will be set to its high resistance state. To evaluate the resistance state of the memristors, a read voltage of -0.5V is used to prevent accidental modification of the element resistance.

Algorithm 1 N-bit subtraction using imply logic

1 for i = 1 to n do 2 if (i = 1) then

3 compute S1 = (W1 → 0) → [(0 → W1) → 0]

4 compute BO1 = X1 → Z1 5 else

6 compute Si = (Wi → BOi-1) → [(BOi-1 → Wi) → 0]

7 compute BOi = Xi → Zi 8 end if 9 end for

It is important to note that these control waveforms are can be grouped into the fundamental operations of an implication logic namely, the copy operation and the imply operation [143] as described in Table 5-3. In the proposed implication logic, the memristor elements are used as both computational and storage element. Thus, the copy operation is crucial in preventing the disruption of in the input data bits as well as any intermediate output data bits. The copy operation consists of two consecutives imply operations and utilises three compute elements (1 input element and 2 compute element). For example, the copy operations of memristor element A to T1 can be achieved via operation A → T2 followed by T2 → T1 where elements T1 an T2 have an initial logic value of 0.

During the initiation and completion of these computational steps, a low voltage signal (-0.5V) is applied on the input and output memristors to evaluate their resistive state, in this context, their logical state where the low resistance state is a logical high and the high resistance state is a logical low. Figure 5-7 shows the logical state the input and output memristor of the proposed full subtraction circuit.

Figure 5-7 Simulation data showing the resistance state of the input and output memristor of the proposed full subtraction circuit for all input combination specifically (a) A=0, B=0, BO-1=0; (b) A=0, B=0, BO-1=1; (c) A=0, B=1, BO-1=0; (d) A=0, B=1, BO- 1=1; (e) A=1, B=0, BO-1=0; (f) A=1, B=0, BO-1=1; (g) A=1, B=1, BO-1=0; and (h) A=1, B=1, BO-1=1 where A is the minuend, B is the subtrahend, BO-1 is the borrow in, BO is the borrow out and S is the difference.

5.6 Nth bit implication logic division Utilising the implication logic subtractive circuit previously described, it is possible to implement an imply divisor circuit. Overall, an nth-bit divisor circuit will consist of an nth-bit subtraction circuit with one bank of n memristor array for the dividend and one bank of m memristor array for the divisor. An additional two banks of memristors are used to store the quotient as well as their partial remainder and three memristors element to support intermediate computational steps.

Figure 5-8 Proposed structure for the implication logic based nth division circuit.

The implementation of a typical CMOS NAND based divisor circuit requires approximately 26n2 transistors [144] whereas the equivalent memristor based divisor circuit requires 3m + 2(n+1) memristor elements, ignoring the transistor driver circuitry. At the time of writing, there has yet to be any publication on a divisor logic circuit using memristor elements. The number of the execution steps for the proposed circuit can be significantly reduced by performing in parallel the imply operations at the expense of a higher number of memristor elements used [141], [142]. In addition, the execution steps of the logic circuit can be streamlined by utilising the MAGIC logic architecture [57], [145]. We will introduce a serialised approach of implementing a memristor-based divisor circuit. In this context, the input elements, A1…n th andB1…m, of n -bit subtraction circuit are termed the dividend and divisor respectively. The computed quotient and remainder are stored in the output elements Q1...m-n and R1...m-1 respectively.

The structures of the proposed n-bit divisor are as shown in Figure 5-8. The operations of the imply logic divisor involves the quotient generation followed by dividend subtraction and remainder generation. Similar to the subtraction memristor circuit, elements T1, T2 and T3 are used as intermediator elements to perform computational steps without the disruption of input data bits. The computational steps involve the subtraction of the divisor (B) by the dividend

(A) in which the partial remainders are piped into the subsequent subtraction stages until all quotient bits are computed. In each subtraction stages, the borrow bit is used to determine the value of the quotient bit. If a dividend is found to be larger than its divisor, the subsequent subtraction operations are skipped followed by the increment of the bit width. Upon completion of each subtraction stage, the bit width of the subtractor will increase to account for the larger bit width of subsequent partial remainders. The subtraction and bit width increment procedure repeat itself until all the corresponding quotient has been computed. Finally, the results are stored in the quotient and remainder memristor arrays

Figure 5-9 Simulation data showing the resistance state of the input and output memristors of the proposed division circuit for a subset of input combinations specifically (a) A=111, B=10; (b) A=110, B=10; (c) A=110, B=11 and (d) A=101, B=10 in which A , B , Q and R denotes the dividend, divisor, quotient and remainder respectively.

The computational process of the divisor circuit is as described by algorithm 2. A case study of a 2-bit divisor and a 3-bit dividend was simulated using the proposed computational steps. Figure 5-9 shows the simulation data for 4 input combinations of dividend, A, and divisor, B. The input combinations are A=111, B = 10; A=110, B = 10; A=110, B = 11; and A=101, B= 10.

Algorithm 2 Shift and Subtract Division using imply logic

1 for i = 1 to m-n do 2 if ( i = 1 ) then

3 compute An...n-m – Bm... 1

4 Qm = ¬ BOn-m 5 else

6 if ( Sn-i...n-m-i > Bm...1 ) then

7 compute Sn-i...n-m-i – Bm...1

8 Qm-i = ¬ BOn-i 9 end if 10 end if

11 Rn-1...1= Sn-1..1 12 end for

5.7 Conclusion In conclusion, we have demonstrated an organic memristor device fabricated by interlaying silk fibroin layer between an inert (Au) and active (Ag) metal electrode. The fabricated devices exhibit bipolar switching characteristics with a memory window of 105, a read-write cycle of > 30 and a state retention time of at least 106 s. Furthermore, a VTEAM model has been used to develop a SPICE validation platform which was used to develop the proposed memristor based subtraction and division circuit. Both the proposed subtraction and division circuit is based on the material implication operations inherent to the memristive device. The proposed scheme utilises 5n+3 memristors for the subtraction circuit and 3m + 2(n+1) memristors where n and m are the bitwidth of the divisor and dividend respectively. However, these techniques require serial execution of the imply operations to obtain the desirable logic outcome. These drawbacks can potentially be alleviated by using alternate design methodologies by implementing the pipe-lining independent of subtraction process at the expense of a higher

75 number of memristor element usage [146]. Currently, the low fabrication yield of solution processed based memristor still presents challenge for developing such circuitry.

The development of a solution-processed silk fibroin memristor represents a critical step in the advancement of printable electronics which not only offers low-cost fabrication of electronics, and it offers excellent potential to envisage fabrication of on-demand electronics that are used for specific implantable devices. In addition, the innate capabilities for a memristor device to perform both computation and information storage present exciting potential in the development of novel convolutional neural network architectures

6 Fully Solution Processed Transparent Artificial Neural Network using Drop- on-demand Electro-hydrodynamic Printing

Artificial neural networks (ANN), deep learning and neuromorphic systems are exciting new processing architectures being used to implement a wide variety of intelligent and adaptive systems. To date, these architectures have been primarily realised using traditional CMOS processes or otherwise conventional semiconductor fabrication processes. Thus, the high cost associated with the design and fabrication of these circuits has limited the broader scientific community from applying new ideas, and arguably, has slowed research progress in this exciting new area. Solution processed electronics offer an attractive option for providing low- cost rapid prototyping of neuromorphic devices. This chapter presents a novel, wholly solution- based process used to produce low cost transparent synaptic transistors capable of emulating biological synaptic functioning and thus used to construct ANN. We have demonstrated the fabrication process by constructing an ANN that encodes and decodes a 100×100-pixel image. Here the synaptic weights were configured to achieve the desired image processing functions.

6.1 Introductions Stochastic based neural networks are an exciting new computing paradigm being applied to image recognition, pattern classification and optimisation problems. In contrast to the conventional Von Neumann computing architectures, these artificial neural networks (ANN), deep learning architectures and neuromorphic computing rely on massive parallel networks for both computing and memory storage based on altering the synaptic strength connecting compute elements within the neural network. These complex ensembles of interconnected networks of neurons have the desirable benefits of being: adaptive; robust to single node failure; have the ability to learn based on previously observed inputs. Critically, they have higher energy efficiency when compared to traditionally Von Neumann architectures [147].

Though the idea of building a neuron-like solid-state device has been conceptualised since the 1990s, synaptic transistors have been primarily fabricated using physical and

77 chemical vapour deposition (PVD / CVD) techniques, or by means of CMOS based processes. Shibata et. al. proposed a neuron MOSFET or neuMOS device with multiple input gates that were capacitively coupled with an additional floating gate to emulate the integration of multiple pre-synaptic inputs [59]. Notwithstanding some significant advantages over their contemporary counterparts, large neural network implementations on CMOS technologies are not without their limitations. Advanced implementations of large-scale networks comprise of 30,000 custom high-performance CMOS compute processors but only emulate a fraction of the brain in non-real-time at an energy budget of 1W per chip. In contrast, the typical human brain consumes approximately 20 W [60], [61]. New devices and modelling approaches are required that are both cheaper and more power efficient.

The realisation of neuromorphic circuits using two terminal devices such as memristors and photonic PCM (phase change material) devices, which imitates neural function via the formation of conductive filaments or alteration of optical properties, are well known [148]– [150]. Three terminal transistors devices emulate biological synapses via the modulation of the channel conductance are an alternative approach. Electrolytic-gated thin film transistors are recipients of significant attention due to their potential in low-cost electronics and neuromorphic computing [8]. In recent years, a broad spectrum of electrolyte-gated transistors scheme has been proposed such as sodium alginate gated IZO transistors, graphene oxide based IZO transistors and methyl cellulose gated IZO transistors [62]–[64]. More recently, Zhu et. al. proposed an in-plane synaptic transistor by lateral coupling of the indium zinc oxide (IZO) layer sputtered on a phosphorus-doped nano-granular SiO2 proton conductive film [65]. These biologically inspired artificial synapses are capable of performing basic neuromorphic functions ranging from short-term plasticity, long-term plasticity, pulse-pair facilitation and spike-timing-dependent plasticity [66]–[68]. Unfortunately, these devices are difficult to build and require the usage of vacuum-based physical deposition techniques, specifically, magnetron sputtering, atomic layer deposition and e-beam evaporation. These methods, whilst having advanced the field, are expensive, with modifications to architectures and network layouts requiring many months between design modifications and availability of the ANN for testing. Furthermore, these fabrication approaches are available to a select few, and therefore restrict accessibility by the scientific community to be able to quickly execute and test new architectures and systems.

Printing techniques offer a great potential as an exciting candidate for ANN fabrication for its compatibility with various large area substrate and its prospective towards low cost rapid

78 prototyping capabilities [151]. Over the past several years, tremendous progress in printing technologies has been made through various schemes. Rim et. al. demonstrated the method for producing solution processed all oxide transistor circuit in conjunction with a deep ultraviolet processing for achieving large fabrication throughput [48]. Unlike conventional technologies, they are fully additive fabrication processes, able to undertake large area batch electronic fabrication with the added benefit of significant flexibility in the choice of substrate.[25], [151], [152] Furthermore, three-dimensional device architecture can be easily envisaged through vertically integrated solution process based field effect transistors (FETs) which promises higher circuit density without the need for enhancement of the patterning resolution.[153], [154]

In this present study, we explore and develop a new solution process methodology for low-cost and effective rapid prototyping of neural networks that is equally applicable to general electronic circuit fabrication. The proposed process is well suited to ANN applications where the transistor switching speed and the reliability of fabrication of any single transistor in a network are not a critical issue.

To the best of our knowledge, this is the first report of fully solution processed, transparent, synaptic transistors in an artificial neural network. Here, we discuss the fabrication of a synaptic transistor and networks based on a co-planar sodium alginate gated indium oxide channel. Furthermore, by exploiting the hydrogenation and hydroxylation of the indium oxide channel, we were able to realise synaptic dynamics, such as spike-timing-dependent plasticity, paired-pulse facilitation, and dynamic filtering, using a single transistor. Moreover, we have successfully fabricated an artificial neural network which emulated synaptic functions for encoding and decoding of visual information. By tuning the device dimensions of the fabricated synaptic transistor, we were able to modulate the synaptic efficacy, thus realising different image processing capabilities. Due to the transparent characteristics of our fabricated devices, they have potential application in display technologies found in virtual reality (VR) and augmented reality (AR) systems in which highly efficient, portable, image processing modules can be integrated onto the viewing lenses thus maximising available substrate real estate.

6.2 Results and Discussion 6.2.1 Fully solution processed electrolytic gated transistors.

Figure 6-1 Schematic representation of the fully solution processed synaptic network using metal salt combustion precursors and the transistor morphology. (a) ITO solutions were initially spin coated on a glass substrate and thermally annealed. (b) The source, drain and gate electrodes for the co-planar transistor structure was defined by direct write laser-lithography and wet-etching. (c) An EHD deposition technique was used to define the n-type In2O3 channel followed by (d) the deposition of sodium alginate electrolyte using a glass pipette to realise the transistor device. (e) Optical image of the deposition process. Scale bar, 100 μm. (f) Optical image showing the array of transistors.

Figure 6-1a-d illustrates the temporal fabrication sequence of the co-planar transistors. Initially, the ITO precursors were spin-coated on a glass slide and subsequently thermally annealed to form the transparent conductive oxide layer. This ITO layer was wet-etched in conjunction with a direct laser lithographical method which defines the source, the drain and gate electrodes of the transistor. For this study, we utilised an electro-hydrodynamic (EHD) deposition

Figure 6-2 Schematic diagram of the electro-hydrodynamic printer. Schematic diagram of the EHD deposition set-up with the Cr-coated glass pipette connected to the high voltage terminal and an aluminium heat plate acting as the counter electrode. The camera assembly consists of an Imaging Development Systems GmbH USB camera mounted on a Mitutoyo zoom lens and a 10× objective. technique, to pattern the In2O3 semiconducting channel. Our in-house EHD printer is illustrated schematically in Figure 6-2 with further details of the physical apparatus available in the methods section. The EHD deposition technique involves the application of electrostatic forces between the print-head and the substrate/counter electrode. When a sufficiently high electrostatic force is applied, the tangential stress deforms the liquid meniscus, on the print- head, into a Taylor cone [25]. The ejection of droplets of the liquid precursor droplets from the cone apex occurs when the applied stress overcomes the surface tension of the droplet [30]. This electric field based deposition method allows for high-resolution patterning in comparison to other conventional direct printing technologies [30]. In general, this process can be described as a four-component cycle; (1) the liquid accumulation phase, (2) Taylor cone formation, (3) droplet deposition and (4) liquid relaxation phase [155], [156]. Figure 6-3a, b illustrates the droplet deposition and meniscus relaxation phase. We observed that pulsation and oscillatory motion of the Taylor cone negatively impacts both the resolution and the repeatability of the printing process. Uncontrollable ejection of droplets has been reported earlier by J.U. Park et al. [25]. Excessive charging of the liquid droplets or the substrate, a phenomenon inherent to EHD systems, can result in erratic behaviour throughout the deposition process which reduces the resolution and quality of the deposited pattern [25], [157]. To address this shortcoming, our

Figure 6-3 150μm printhead used to accentuate the four-component cycle of the electro-hydrodynamic mechanism for illustration purposes. (a) Taylor cone formation and droplet deposition phase. (b) Relaxation phase of liquid meniscus. Alignments line were drawn to highlight the shape of the liquid meniscus.

EHD print-head utilises a high voltage push-pull amplifier architecture in which the initiation and termination of the applied voltage can be precisely tuned to negate the aforementioned oscillatory motion as well as providing the drop-on-demand (DOD) capabilities. We have demonstrated 300 nm patterning resolution as shown by Helium ion microscope (HIM) images in Figure 6-5.

Following the deposition of the ITO electrodes, a glass pipette mounted within the print-head was filled with the In2O3 precursor. With the aid of an integrated microscope, the print-head was aligned over the channel as shown in Figure 6-1e. As the electric field was applied between the nozzle and the aluminium counter electrode, the In2O3 precursor was ejected from the print-head at a controlled temperature of 28○C. The deposited precursor was then thermal annealed at 350○C to form the semiconductor channel. The EHD deposition conditions and configurations are discussed in the Methods section. Finally, the sodium alginate (Na Alg.) electrolyte solution was deposited onto the channel using a pipette and air dried for 30 minutes at room temperature to form the electrolyte gated field effect transistor (EGFET) as seen in Figure 6-1f. Figure 6-4a, b, c illustrate the fabricated transistors with various combinations of channel width and length, namely: 420 μm / 115 μm, 200 μm / 90 μm and 100 μm / 90 μm. The detailed fabrication process with the preparation of the precursors is also described in the method sections.

Figure 6-5 Helium ion microscopy (HIM) images showing the dimensions of a single printed conductive trace using the EHD deposition system. Imaging was performed via the Helium Ion Microscope, HIM (Carl Zeiss, Orion Nanofab, Peabody MA, USA) operating at an accelerating voltage of 30 and a beam current of approximately 0.19 pA. Surface charge compensation achieved with support of the electron flood gun. Scale bar, 1 μm.

Figure 6-4 Optical profilometry measurement of the fabricated electrolyte gated transistors. (a), (b) show the optical images of the fully solution processed EGFET with different width and length (Wa/La ≈ 420 μm / 115 μm, Wb/Lb ≈ 200 μm / 90 μm, Wc/Lc ≈ 100 μm / 90 μm). Scale bar, 200 μm.

6.2.2 EGFET Characteristics.

Figure 6-6a show the transfer characteristics (ID-VG) of the electrolytic gated transistor (EGFET). We observed a hysteresis loop when a cyclic gate voltage was swept from -0.4V to 1V and vice versa. This hysteresis is likely caused by the surface hydrogenation and hydroxylation of the In2O3 surface [158]. The thermodynamically stable hydroxyl bonds on the channel surface require a larger negative gate voltage to initiate the proton desorption [159].

This phenomenon manifests as a change in the threshold voltage and can be observed as an anti-clockwise hysteresis loop on the transfer characteristic [160]. For this application, the observed hysteresis is a crucial property in realising synaptic functions which will be discussed in later sections. The precursor In2O3 channel with 25nm thickness was modulated by a co- planar gate and exhibited the desirable n-type characteristics with an on/off ratio (Ion / Ioff) of 103 with a gate leakage of less than 5 nA. The mean effective mobility and threshold voltage for the fabricated transistors were 0.14 cm2V-1s-1 and -0.39 V respectively. The effective field effect mobility, μFE, is calculated using:

퐿 휕퐼 휇 = 6-1 퐶푊푉 휕푉 where C is the capacitance, whereas the sub-threshold swing, SS, is calculated as:

휕푙표푔 퐼 푆푆 = 6-2 휕푉

Figure 6-7 Transfer and output characteristics of the fabricated EGFETs with different dimensions. (a), (d) show the transfer and output characteristics for transistor with width, 100 μm and length, 90 μm. (b), (e) show the transfer and output characteristics for transistor with width, 200 μm and length, 90 μm. (c), (f) show the transfer and output characteristics for transistor with width, 420 μm and length, 115 μm.

Figure 6-6b illustrates the output characteristics of the EGFET which indicate the transistors can be effectively gated at a low voltage of 0.5V and operates as a depletion type device. The transfer and output characteristics of the fabricated transistor with different channel widths and lengths (seen in Figure 6-6c, d) are shown in Figure 6-7. The transparent precursor ITO electrodes were found to have a sheet resistivity of 610 Ω/□. It was also observed that ohmic contact was formed between the probe-electrode and the electrode-semiconductor junctions. Despite the large 100 μm separation between the coplanar gate electrode and the channel, an electric double layer (EDL) can be induced with an application of gate voltage that modulates the channel due to the large accumulation of charge near the In2O3 surface. It has been extensively reported that the EDL thickness, analogous to that of a gate dielectric thickness, is approximately 1 nm [161]. The accumulation of charge in the sodium alginate electrolyte can describe by the proton transport mechanism in which protons hop between

Figure 6-8 Composition and material analysis of the In2O3, ITO and sodium alginate film. (a) This graph presents the FTIR absorption versus wavenumber of a desiccated sodium alginate film coated on a quartz substrate. (b) Transmittance spectrum of the synaptic network circuit fabricated on a glass substrate indicates the optical clarity of the device. (c), (d) XPS wide-scan analysis spectral of the In2O3 and ITO films. hydroxyl groups and water molecules, thereby polarising the electrolyte layer and generating large capacitance [162]. The FTIR (Fourier transform infrared spectroscopy) spectra of a desiccated sodium alginate film, is shown in Figure 6-8a, exhibited strong wide spectral bands at 3200-3600 cm-1 range that corresponds to the stretching vibrations of the hydroxyl groups. The operational voltage of these transistors was limited to a maximum of 1V drain voltage and 0.5V gate voltage to prevent excessive electrochemical reaction on the interfaces. Consequently, it was observed that the output current versus drain to source voltage characteristic curves lacked a definitive saturation region. The absence of a redox reaction on the electrode surfaces can be inferred by the measured constant gate leakage current which agrees with previously reported results [163]. Figure 6-8b shows the UV-Visible spectrophotometry measurement which indicate that the fabricated transistors are optically transparent, with an optical transmittance of > 80%, between the wavelengths of 390nm and 1500nm.

Figure 6-9 XPS spectra of the In2O3 and ITO film. (a), (c) shows the corresponding peaks for the hydroxyl species, oxygen vacancies (Ovac) and lattice oxygen (M-O) for In2O3 and ITO respectively. (b), (d) show the corresponding peaks for In3d5/2 and In3d3/2 states for In2O3 and ITO respectively. (e) shows the corresponding peaks for the Sn3d5/2 and Sn3d3/2 states of the ITO film.

X-ray photo-electron spectroscopy (XPS) analysis was performed to characterise the chemical composition and chemical states of deposited metal films. Figure 6-8c, d shows the XPS wide- scan spectra which indicates the conversion of the sol-gel precursor to the appropriate metal oxides compound for the In2O3 and ITO films respectively. The integration of the XPS peaks indicates that the atomic ratio of In:O was 1:1.3 which differs from the composition stoichiometric of In2O3. This deviation suggests a higher number of oxygen vacancies within the semiconductor film. The conductive ITO film has an atomic ratio In:Sn:O of 0.11:1:1.52 which corresponds to the composition of high conductivity sol-gel ITO described previously by M.G. Kim et.al.[44] The in-situ tin doping along with the oxygen-deficient defects sites introduce higher carrier density in the ITO film and thus enhanced the electrical conductivity.[164] It can be observed from the wide-scan spectra for both sol-gel deposited metal oxides shows carbon (C1s) contamination peaks. These C1s peaks can be attributed to the incomplete decomposition of the organic solvent and ligands [165].

Figure 6-9a and c show the deconvolution of the oxygen (O1s) peaks for In2O3 and ITO respectively. The peak at 530.2 eV (M-O) originates from the oxygen bond of the metal- oxygen-metal bonds whereas the peak at 531.1 eV (Ovac) is associated with the oxygen vacancy in the metal-oxygen networks [44]. The peak at 532.4 eV is associated with the hydroxyl species. Strong oxygen lattice bond in conjunction with the weak hydroxyl related bond (M- OH) within the metal oxide film suggests an effective decomposition of the metal oxide precursors [45]. Figure 6-9b, d and e show the Gaussian fitted curve for the deconvolution of the In3d and Sn3d peaks of these metal oxide films. The XPS spectra exhibited the characteristic spin-orbit split 3d5/2 and 3d3/2 signals for both In2O3 and ITO films which suggest the indium and tin valency is primarily +3 in the metal oxide film [166].

6.2.3 Comparison studies of In2O3 transistor performance with gating strategy.

Figure 6-10 Electrical characteristics of the fabricated metal oxide transistors. Transfer characteristics curve for (a) SiO2 back gated transistor and (b) precursor based Al2O3 back gated transistor. (c) shows the capacitance-frequency curve of the metal oxide dielectrics and the sodium alginate electrolyte. (d) shows an image of the back gated transistors.

We evaluated the indium oxide transistor characteristics using different dielectric materials and gating configuration. Figure 6-10a, b shows the transfer characteristics of the 100 nm thick silicon oxide and the 120 nm sol-gel based Al2O3 back gated transistors on a p++ silicon wafer respectively. The width and length of these transistors are designed to be 500 μm and 100 μm respectively. The thickness of the sol-gel alumina layer and the sol-gel indium oxide layer were approximately 120nm and 18nm in thickness respectively as determined by optical profilometry (see Figure 6-12 and Figure 6-11). Figure 6-10c shows the capacitance-frequency curve for fabricated transistors with different dielectric materials. The measured capacitance was approximately 8-11 μFcm-2, 0.3-1 μFcm-2 and 4-50 nFcm-2 up to 10 kHz for the sodium alginate electrolyte, sol-gel alumina dielectric and silicon oxide dielectric respectively. Due to the higher capacitance of the electrolytic dielectric, the fabricated EGFET can perform at low

Figure 6-12 Optical profilometry of the sol-gel Al2O3 film. (a) 3D reconstruction for the cross section of the Al2O3 film. (b) Extracted profile along the film surface as indicated.

Figure 6-11 Optical profilometry of the sol-gel In2O3 film. (a) 3D reconstruction for the cross section of the In2O3 film. (b) Extracted profile along the film surface as indicated. operational voltage (< 1 V) which is crucial for low power and portable applications. Figure 6-13a, b and c present the distribution of effective mobility, sub-threshold swing and threshold voltage of the transistors with different gating material. For the sol gel alumina gated transistor, the effective mobility was estimated as 28.3 cm2V-1s-1 with a threshold voltage of -1.05 V and a sub-threshold swing of 0.10 V/decade whereas in the case of silicon oxide gated transistor, the effective mobility was calculated to be 1.50 cm2V-1s-1 with a threshold voltage of -1.77 V and a sub-threshold swing of 1.23 V/decade. As for the sodium alginate electrolytic transistor, the effective mobility was 0.14 cm2V-1s-1 with a threshold voltage of -0.39 V and a sub- threshold swing of 0.87 V/decade. We also observed that the fabricated transistors gated with an oxide-based dielectric exhibited negligible hysteresis behaviour which further emphasises

Figure 6-13 Performance characteristics of the fabricated metal oxide transistors. (a), (b) and (c) illustrate the statistical distribution of the mobility, sub-threshold swing and threshold voltage respectively for the SiO2 and precursor based Al2O3 back gated as well as the sodium alginate electrolytic gated transistor transistors. the surface hydrogenation and hydroxylation at In2O3-electrolyte interface is due to the proton conduction within the electrolyte plays a key role in introducing hysteresis that is needed in this application.

6.2.4 Emulation of synaptic functions on electrolytic gated transistors. The proton conductor and trapping mechanism within the sodium alginate electrolytic transistor, described in the previous section, offers short-term synaptic plasticity capabilities which can be used for information processing and synaptic based computations.[65] Figure 6-14a, b shows the Poisson distributed input spike train and their corresponding excitatory post- synaptic current (EPSC) triggered for a transistor with a width and length of 400 μm and 100 μm respectively. The Poisson distribution methodology provides a reliable and deterministic technique for generating spike trains and has been demonstrated by various in-vitro studies [167]. This form of input stimulus was chosen as a primary means of stimulating the transistor as it closely mimics its biological counterpart. Figure 6-14c illustrates a simplified biological model of the pre-synaptic and postsynaptic terminal. As an action potential reaches the pre- synaptic terminals, ionic binding on the presynaptic membrane trigger the release of synaptic vesicles containing neurotransmitters into the synaptic cleft. These neurotransmitters diffuse across the synaptic cleft and attach themselves onto binding sites on the post-synaptic terminal which initiates the opening of ion channels. The opening of these ion channels results in the production of excitatory or inhibitory postsynaptic currents. Here, the movement of sodium ions into the postsynaptic terminals leads to the production of an EPSC [66].

Figure 6-14 Excitatory post-synaptic current. (a) Poisson distributed pre-synaptic spike train (λ-1 = 10 ms). (b) EPSC response triggered by the applied spike train. (c) Biological synapse and the analogous transistor based artificial synapse.

In comparison to the biological analog, the EPSC were triggered as mobile protons migrated within the sodium alginate electrolyte towards the In2O3 channel. Here, the co-planar gate is analogous to the pre-synaptic input and the In2O3 channel is analogous to the postsynaptic terminal. As an electric field is applied through the co-planar gate, the mobile protons/ions in the electrolyte form an EDL on the surface of the semiconducting channel.[161], [168] The accumulation of electrons in the oxide induces the formation of a conductive channel which leads to the production of the EPSC. Upon removal of the stimulus, these mobile protons/ions return to their equilibrium state due to the concentration gradient and subsequently induce a charge/current decay in the ESPC [63]. Figure 6-14b shows an EPSC output of the fabricated synaptic transistor (W = 420 μm, L = 115 μm) for a Poisson distribution input spike train of λ-1 = 10 ms for approximate 3.5 s. The EPSC reaches a peak current of 0.24 μA and eventually decays to the noise floor of the measurement apparatus. This depression and refractory-like output characteristics have been observed in real-world biological system as previously described in the literature [169], [170]. Figure 6-15 shows the EPSC response for varying transistor dimensions triggered with a similar Poisson distributed spike train. These EPSC reaches a peak current of 0.082 μA and 0.049 μA before eventually decaying to the noise floor for the synaptic transistors of W/L = 100 μm/90 μm and W/L = 200 μm/90 μm respectively.

Figure 6-15 EPSCs responses triggered by a stimulus train for transistor of different dimensions. (a) Poisson distributed input spike train with a λ-1 of 10 ms. (b), (c) show the corresponding EPSC response for transistors of Wb/Lb ≈ 100 μm / 90μm and Wc/Lc ≈ 200 μm / 90 μm respectively.

The transfer of information in a synaptic neuron network is highly dependent on the dynamic changes in the synaptic weight between neurons and can occur on a timescale from milliseconds to a few seconds [171]. This phenomenon has been identified as short-term synaptic plasticity and is known to play a critical role in cognitive functions [172]. To demonstrate these short-term plasticity behaviours, a pair of consecutive input spikes of 1 V (20 ms pulse width) with inter-spike duration, Δt, ranging from 0.25 ms to 500 ms, were applied to the gate electrode. The EPSC response with a Vds of 0.5 V on the synaptic transistor was measured as illustrated in Figure 6-16a. The paired-pulse facilitation (PPF) is a means of quantifying plasticity mechanism on a neuron and is exclusively a pre-synaptic phenomenon [173]. The PPF manifest when a pre-synaptic neuron is subjected to two stimulus spikes consecutively which results in larger postsynaptic responses for the second stimulus spike than the initial spike [174]. Thus, the PPF ratio is defined as the ratio of the amplitude for the second

EPSC to the first EPSC (β2 / β1). Figure 6-16b shows the PPF ratio for the synaptic transistor with a different combination of channel width and length as a function of the spike interval. The maximum PPF ratio was 1.9, 1.85 and 1.78 for W/L of 4, 2 and 1 respectively at

Figure 6-16 Short term plasticity exhibited by fabricated synaptic transistors. (a), i Pre-synaptic spike pairs with a time interval, Δt. (a), ii EPSC response from the pre- synaptic spike pairs. (b) Paired pulse facilitation as a function of the pulse interval, Δt, for synaptic transistors of various device dimensions (width and length of the transistor is denoted by W and L respectively). (c) Measured EPSC triggered by spike trains of different frequency. (d) EPSC gain as a function for the spike trains of different frequency.

Δt = 0.25 ms. The PPF behaviour in an EGFET has been described in the literature as the accumulation of protons at the interface of the semiconductor channel coupled with slow equilibrium dynamics of ions [65], [67]. Here, the initial pre-synaptic spike induces the accumulation of protons at the sodium alginate – indium oxide interface during the formation of the EDL. In the absence of pre-synaptic stimulus, the EDL gradually diminishes as ions are redistributed into their equilibrium states. Upon the application of a secondary stimulus, in rapid succession, a stronger EPSC response is triggered as the pre-existing EDL remains in effect due to the slow ion dynamics. Thus, a shorter inter-spike interval produces a higher facilitation ratio resembling to those observed in a biological system [171].

The fabricated synaptic transistors were also shown to be capable of the dynamic filtering of spiking information based on the stimulus frequency. In Figure 6-16c and d, the EPSC response and gain was measured for an input spike train consisting of 20 stimulus spikes

(1 V, 20 ms) of varying frequency with a constant VDS of 0.5V applied across the source and drain electrodes. Figure 6-16c shows clearly that the peak response of the EPSC increases with

94 the applied frequency which suggests the behaviour of a high pass filter. Figure 6-16d illustrates the EPSC gain in relation to the applied frequency which was defined as the amplitude ratio of the initial and last post-synaptic response of the transistor. These frequency- dependent synaptic responses are considered a fundamental mechanism in various neural computation such as sound localisation [175].

6.2.5 Synaptic network for image processing.

Figure 6-17 Colour filtering algorithm implemented on an artificial spiking neural network. (a) Schematic diagram of the spike train decoding circuit with various size factor (W/L). The input and summation nodes are represented by the blue and green line respectively. (b), (c) and (d) represents the original, decoded all-colour and decoded red-only 100×100-pixel image respectively.

The integration of the post-synaptic response of neurons was is one of the basic functions of neuronal computation in a neural network [176]. To demonstrate the potential of these synaptic transistors, we have fabricated a single layer synaptic neural network as illustrated in Figure 6-17a. The synaptic network was composed of three pre-synaptic inputs and a single postsynaptic output. These individual pre-synaptic transistors were subjected to a spatio- temporally correlated pre-synaptic stimulus which was integrated by a post-synaptic transistor to generate the specific pattern of synaptic output. An external comparator and sampler were used in conjunction to the fabricated neural network post-synaptic output as a buffered firing

Figure 6-18 Reconstructed images of the entire artificial neural network circuit with an optical profilometer and image stitching. (a) illustrates the artificial neural network with transistors of similar width and length. (b) illustrates the artificial the two pre- synaptic inputs of reduced transistor width. Scale bar, 2 mm. circuit and digital interface. As the integrated EPSC signal exceeds a predefined threshold value, a spike was triggered based on the integrate-and-fire mechanism. The post-synaptic summing synaptic transistor was biased with a VDS of 0.5 V and the source of the transistor was connected to a transconductance amplifier followed by the firing circuit. To demonstrate the image processing capabilities, we chose an image of a ladybug defined in a pixel grid of 100×100 pixels as shown in Figure 6-17b. The pre-synaptic input test sequence was based on a Poisson distributed spike train corresponding to the RGB values of the image as determined by Equation 6-3:

(훼휆) 푃(푛) = 푒 6-3 푛! where P(n) is probability of a spike, λ is the firing rate, n is the stimulus window length and α is the normalised RGB colour value. The test sequence for the synaptic network was generated with a stimulus window length of 8192 samples and a maximum firing rate of 100 Hz. For simplicity, the encoding of the input stimulus was split into three input channels, namely the red, green and blue colour as depicted in Figure 6-17a and the stimulus event were mutually exclusive (no simultaneous inputs within the same time frame). The pre-synaptic test sequence of a pixel colour was encoded in the form of a latency temporal coding scheme or “time-of- arrival” code. More sophisticated versions of this coding scheme have been observed in biological systems such as echolocation, auditory localisation as well as visual system.[177]

The post-synaptic response of the ANN was decoded based on the spike density within the latency window and was then correlated with the strength of the pixel colour. The decoded RGB values is described by Equation 6-4:

1 푅퐺퐵(푖) = 퐸 (푡), 푤ℎ푒푟푒 푖 ∈ {1,2,3} 6-4 푇 where RGB is the normalised colour strength, TW is the window length, E(t) is the post-synaptic response as a function of time, Ti is the latency window and i specifies the latency window of a specific colour. To show an influence of the synaptic strength and their influence on the colour filtering operations, we fabricated two sets of ANNs in which one of the networks had two pre-synaptic transistors of reduced width, namely the green and blue pre-synaptic input transistors. (see Figure 6-18a, b). Both sets of ANNs had the summing post-synaptic transistor of the same device dimensions. Figure 6-17c and d show the reconstructed images for the fabricated synaptic neural network. Here, we have demonstrated the capabilities of altering the coefficient of the filtering operation by means of changing the weight of the synaptic transistor or the dimensions of the channel.

6.3 Summary The human brain consists of billions of neurons each connected to other neurons, forming a network of over 100 trillion synapses. These neurons relay information within the network via a combination of chemical and electrical stimuli. Chemical neurotransmission occurs between synapses whereby an arriving action potential (electrical stimulus) triggers the release of synaptic vesicles containing neurotransmitters into the synaptic cleft. Released neurotransmitters diffuse across the synaptic cleft and bind to the receptors on the post-synaptic membrane [178]. This initiates the opening of ion channels on the post-synaptic terminals, increasing the permeability of the membrane in which chemical ions can easily flow through the synaptic membrane, leading to the depolarisation and production of a post-synaptic potential and current [179]. Modulating the synaptic strength of the neurons, quantified by the post-synaptic responses, is proposed to be the mechanism behind synaptic plasticity or associative learning as described by the Hebbian learning rule.

The realisation of a single electronic transistor, capable of emulating neuronal functioning, is key to the design and fabrication of a highly efficient ANN. In recent years, the neural network research community has been investigating various type of electronic devices to achieve similar functionality using resistive switching memristors, electrolyte-gated thin film transistors and

97 hysteresis engineering of transistors. Typically, transistors exhibit synaptic functionality by virtue of their hysteresis properties. For electrolyte gated transistors, these are primarily caused by slow ion dynamics of the electrolyte-based dielectric. On the other hand, memristors emulate synaptic functions by exploiting the diffusive characteristic that is intrinsic to their on- off switching mechanism [65], [149], [180]. The fabrication of these neuromorphic computing devices has been reliant on vacuum processes such as a chemical or physical vapour deposition. These processes require highly specialised equipment and laboratories which may not be readily available due to the high operational cost.

In this work, we have successfully developed a protocol for fabricating a fully solution process transparent synaptic transistor. This method offers a simplified way of fabricating low- cost, large area ANNs as well as general purpose microelectronics. In addition, we have experimentally demonstrated that the sodium alginate gated In2O3 gated transistor can form the basic building block for realising an ANN. The presented EGFET intrinsically possesses short- term synaptic plasticity capabilities which can be exploited to imitate synaptic functions such as the paired pulse facilitation, dynamic filtering and EPSC integration. The emulation of these synaptic functions is due to the hydrogenation and hydroxylation of In2O3 surface which introduces profound hysteresis properties in the fabricated transistors. By altering the dimension of the EGFET, we have shown that synaptic strength of these transistors can be tuned to suit the application at hand.

Importantly, the ANN, fabricated using these transistors, has been shown to be capable of performing image processing operations. Here, we have shown the capabilities to fabricate ANN with multiple pre-synaptic inputs via solution processes methodologies. At present, the device dimensions of the proof of concept synaptic transistor are large, in the order of a 100 μm, however EHD deposition methods are capable of nanometre pattern resolution. EHD printing is superior compared to conventional ink-jet printing due to the higher achievable resolution by means of print-head nozzle size reduction. Sub-micron patterning using EHD printing system still represents an interesting research area in terms of improving the reproducibility and development of a live visualisation system. Besides that, the usage of solution process metal oxide (non-silicon based) transistor creates a pathway for fabricating flexible 3D circuit architectures for higher density electronics and to mimic more closely the 3D architecture of the brain. This will allow the development of more sophisticated neural network in the future with much greater complexity with regards to their neural computations. Finally, the availability of low-cost, solution process rapid prototyping tools for the fabrication

98 of ANNs will greatly enhance research in the field of artificial intelligence by increasing their accessibility to a broader research community namely; the neuroscience and the artificial intelligence research communities.

6.4 Methods 6.4.1 EHD printer configuration The EHD printer setup is shown in Figure 6-1 which consists of a Newport XY100 linear x-y stage and two Scientifica micro-manipulators. The micro-manipulators were used as the print- head work distance controller and the camera aligner. The print-head composed of a glass pipette, tip diameter of 5μm, connected via a platinum wire to a custom-built high voltage pulse width modulator. The counter substrate was constructed out of aluminium with an electronic heat pad adhered onto the bottom. Glass pipettes were drawn using a Stutter P-97 pipette puller from glass capillaries of outer diameter, 1.0 mm and inner diameter 0.58mm. The outer layer of these pipettes was coated with a 50 nm thick Cr layer using a Thermionics VE180 electron- beam evaporator at a pressure of 10-7 Torr. Prior to the deposition process, the glass pipettes were loaded with the metal oxide precursors and mounted onto the print-head.

6.4.2 Metal oxide precursor solution synthesis Each of the 0.1 M indium oxide and aluminium oxide precursor solutions were prepared by dissolving 0.03 g In(NO3)3·xH2O and Al(NO3)3·9H2O in 1 ml of 2-methoxyethanol respectively. The 0.1 M indium tin oxide precursor solution, with an In:Sn ratio of 9:1, was prepared by dissolving 0.03g In(NO3)3·xH2O with 0.002g SnCl2·2H2O in 1 ml of 2- methoxyethanol. Lastly, 10μl of acetylacetone and 7μl of ammonium hydroxide were added to each of the precursor solutions followed by 8 hours of stirring. The 4wt% sodium alginate solution was prepared by dissolving alginic acid sodium salt in de-ionised water followed by mechanical stirring. ITO etchant was obtained by adding 3 wt% Ferric (III) Chloride to deionised water and buffered in a 1:1 volume ratio with a solution of 37% hydrochloric. All reagents used as is for synthesis were purchased from Sigma Aldrich.

6.4.3 Fabrication of electrolytic gated thin film transistors The electrolytic gated transistors were fabricated on a 1 mm-thick Thermo-Scientific microscope glass slide. The prepared ITO solutions were spin coated at 3000 rpm for 60s onto the glass slide followed by thermal annealing at 350 °C in an inert nitrogen environment. The source and drain electrodes were later defined with a SUSS MicroTec SLP300 laser direct write

○ lithography and subsequently wet-etched at 80 C with the buffered FeCl3 etchant. Using our in-house built electro-hydrodynamic printer, the In2O3 semiconducting layer was deposited on the channel. An applied voltage of 600 V at 50 % duty cycle was used between the print head and the substrate with a working distance of 15μm. The stage translation speed in the x-y plane was limited to 100μm s-1. Lastly, the sodium alginate electrolyte solution deposited onto the channel using a glass pipette followed by natural desiccation process at room temperature for 30 min under ambient condition.

To characterise the properties of the indium oxide precursor back gated transistors, a thermally grown 100nm silicon oxide on a heavily doped p type silicon wafer as well as a sol gel-based alumina coated silicon wafer was used respectively. The aluminium oxide layer on the silicon wafer was deposited via spin coating of alumina precursor at 3000 rpm followed by thermal annealing at 350 ○C for 1 hr. This process was repeated 5 times to achieve the desired dielectric thickness (see Figure 6-12). The prepared In2O3 precursors was then spin coated at 3000 rpm and thermally annealed at 350○C for 1 hr. The 50nm Cr source and drain electrodes were deposited using a Thermionics VE180 electron-beam evaporator at a pressure of 10-7 Torr with the aid of a shadow mask.

6.4.4 Material Characterisation and Electrical Measurement. The electrical characterisation of the transistors and synaptic circuit were performed using the Agilent E5270B Precision IV Analyser in conjunction with a Cascade Microtech Summit Semi-Automated Probe Station. FTIR measurements were performed using a Thermofisher NicoletTM iSTM50 FTIR spectrometer. UV-Vis spectrophotometric measurements were performed using an Agilent Technologies Cary 300. The morphology of precursor root printed functional materials was investigated via helium-ion beam microscopy (HIM) (Carl Zeiss, Orion Nanofab, Peabody MA, USA), where accumulated charges on glass substrates were suppressed by the electron beam flood gun. HIM images were captured at a0n accelerating voltage of 30 kV and the ion beam current was approximately 0.2 pA. Optical profilometry measurements were performed using a Bruker ContourGT. X-ray photoelectron spectroscopy (XPS) measurements were carried out on a Kratos Axis Ultra XPS.

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7 Conclusion and Future Work

7.1 Conclusion This thesis proposed a new approach for the realisation of electronic devices using novel solution-based processes. The proposed combination of electrohydrodynamic printing, spin- coating and low-temperature annealing techniques demonstrated is capable of fabricating active elements such as transistors and memristor which have shown comparable performance to devices fabricated using conventional methodologies. Using this approach, we explored the potential for using solution-based processes to implement various computational architectures from resistive logic circuitries to artificial neural networks. At present, the conceptualisation of the fully printed or solution-process electronics remains a challenge as new materials and chemicals must be identified with comparable performance to their vacuum-process counterpart. In this work, we will be addressing a subset of these challenges with the proposal of a new form of solution processed memory device and transistors.

In chapter 3, we discussed on the existing physical models governing the memristive switching mechanism. In addition, we study the resistive switching characteristics of a silk fibroin-based memristors and the effects of differential structural configuration for the device. Several experiments provided insights to support claims that the electrochemical metallisation mechanism is the principles behind the resistive switching characteristics of a silk fibroin-based memristor device.

In chapter 4, we demonstrated a bio-resorbable and bio-compatible solution processable memristor using silk fibroin protein interlaid between an inert (Pt) and active (Au) metal electrode. The fabricated memristor exhibited bipolar resistive switching ratio of 104, a lifecycle of > 30 switching cycles and possesses programmable device lifetime characteristics before the device gracefully bio-degrades, minimizing impact to the environment or the implanted host. In addition, we conducted a lactate dehydrogenase assays on the fabricated device to reveal no cytotoxicity on direct exposure which supports the environmentally friendly and biocompatible claims. We also investigated and successfully shown the prospects of improving the silk fibroin memristor performance by increasing the crystallinity of the silk layer via water annealing. Moreover, the correlation between the oxidation state of the cations and their tendency in forming conductive filaments with respect to different active electrode materials was investigated which showed metallic element with lower stable oxidation state

101 operates at a lower voltage. Finally, we proposed a mathematical model based on electro- thermal effect which showed a tight correspondence with respect to the experimental data in predicting the memristive switching process with various combinations of electrodes. We also conducted a simulation which provides insight into the morphological changes of conductive filaments in the silk fibroin films.

In chapter 5, we extended the study of chapter 4 by utilising our better understanding of the resistive switching mechanism of the silk fibroin memristor and the corresponding fabrication techniques. In this chapter, we develop a mathematical model and the SPICE model for emulating the resistive switching characteristics of the fabricated silk fibroin memristor. This model was used to validate the electrical behaviour and operations of the proposed an nth bit subtractor and nth bit division circuit using implication logic.

In chapter 6, we presented a fully solution-based process technique used to produce low cost transparent synaptic transistors capable of emulating biological synaptic functioning. These synaptic transistors were fabricated using a sol-gel precursor route in which metal nitrate solution was deposited to form both the conductive and semiconductor layers. By exploiting the hysteresis characteristics of the fabricated transistor gated with a sodium alginate electrolyte, we have imitated several synaptic functions namely, the paired-pulse facilitation, dynamic filtering and EPSC integration. At present, artificial neural network architectures have typically been realised using traditional CMOS processes or otherwise simulated entirely in software running on classical computer processors and therefore have put them out of scope for many applications. Furthermore, the high cost of design and fabrication of custom circuits has limited the broader scientific community from applying new ideas, and arguably, has slowed research progress in this exciting new area. Using the fabricated synaptic transistors, we have demonstrated the fabrication process by constructing an ANN that encodes and decodes a 100×100-pixel image. Finally, we reconfigured the synaptic weights by modulation of the channel width to achieve the desired image processing functions primarily the colour isolation or filtering process.

7.2 Future Work The proposed silk fibroin memristor device proposed in chapter 3, 4 and 5 can be further studied for their use in the construction of high performance artificial neural networks. Convolution neural networks are a subset of the neural network architecture in which multiple convolutional kernel layers are used to analyse information. This architecture significantly

102 reduces the complexity of network structure and implementation due to the translational invariance advancing through the layers. Conventional neural networks typically rely on high- performance arithmetic logic units to perform the floating-point computation on the input data and weights, thus have power consumption and memory usage. Utilising the silk fibroin memristor array, we can potentially develop a hardware-accelerated binary convolutional neural network which only requires relatively simple logic operations to provide fast information throughput and comparable accuracy. In addition to that, the material availability and low cost of synthesizing this material can pave the way towards future low-cost and environmentally sustainable electronics.

For the work presented in chapter 6, a different approach to the implementation of the artificial neural network can be investigated. This is work utilises only a subset of the possible neuronal functions found in a biological system primarily the short-term plasticity properties. Studies can be performed to emulate the long-term plasticity properties which are a crucial neuronal function that may enable these networks to perform complex operations such as image recognition, pattern identification and so on. On the other hand, this works presented several back-gated transistors as a comparison for the EGFETs. These transistors can be further developed and investigated to produce staggered bottom-gated transistors using a combination of aluminium oxide and indium oxide sol-gel precursor which can be utilised in conjunction with the EGFET to construct a fully operational neural network. In contrast to the conventional CMOS process, the usage of the high resolution EHD rapid prototyping methodology significantly reduces the manufacturing cost due to the absence of a photolithography mask.

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Minerva Access is the Institutional Repository of The University of Melbourne

Author/s: Yong, Jason Hsien Ming

Title: High-performance printable electronics for memory and neuromorphic application

Date: 2019

Persistent Link: http://hdl.handle.net/11343/225642

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