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Marcelo Marques Implementação Em FPGA De Um Detector ASK/FSK Para Balizas De Sinalização Ferroviária

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Marcelo Marques Implementação Em FPGA De Um Detector ASK/FSK Para Balizas De Sinalização Ferroviária Departamento de Universidade de Aveiro Electrónica, Telecomunicações e Informática 2019 Marcelo Implementação em FPGA de um Detector Marques ASK/FSK para Balizas de Sinalização Ferroviária Departamento de Universidade de Aveiro Electrónica, Telecomunicações e Informática 2019 Marcelo Implementação em FPGA de um Detector Marques ASK/FSK para Balizas de Sinalização Ferroviária (FPGA-based Implementation of an ASK/FSK Detector for Railway Sig- nalling Balises) Dissertação apresentada à Universidade de Aveiro para cumprimento dos requesitos necessários à obtenção do grau de Mestre em Engenharia Elec- trónica e Telecomunicações, realizada sob a orientação científica do Professor Doutor Arnaldo Silva Rodrigues de Oliveira, Professor auxiliar do Departa- mento de Electrónica, Telecomunicações e Informática da Universidade de Aveiro e sob a orientação empresarial do Mestre Nefi Carvalho, BTM Man- ager da empresa CAF Signalling. o júri / the jury presidente / president Professor Doutor Adão Paulo Soares da Silva Professor Auxiliar, Universidade de Aveiro vogais / examiners committee Professor Doutor Arnaldo Silva Rodrigues de Oliveira Professor Auxiliar, Universidade de Aveiro (orientador) Professor Doutor Sérgio Ivan Fernandes Lopes Professor Adjunto, Escola Superior de Tecnologia e Gestão Instituto Politécnico de Viana do Castelo agradecimentos / Desejaria agradecer ao orientador Professor Doutor Arnaldo Rodrigues de acknowledgements Oliveira por todo o incentivo, motivação e disponibilidade. Da mesma forma agradeço ao Engenheiro Mestre Nefi Carvalho pelo incentivo, motivação, disponibilidade e pela possibilidade de visitar e conhecer a CAF Signalling. Para a minha família e amigos um grande obrigado por todo o incentivo que me prestaram, principalmente nos momentos em que a motivação estava mais longe. Palavras-chave ASK, FSK, Detector de Modulação, FPGA, ERTMS, Sinalização Ferroviária Resumo Esta dissertação insere-se na área de telecomunicações, mais concretamente nos sistemas de telecomunicações na sinalização ferroviária. O trabalho foi proposto pela empresa CAF Signalling e tem como objectivo a implemen- tação de uma função de segurança que assegura a interoperabilidade entre sistemas de Proteção Automática de Comboios (ATP), ERTMS e KER, dis- tinguindo entre Eurobalisas e balisas KER. Ao longo do trabalho o detector foi modelado em Simulink e convertido em código VHDL.A fase final da dissertação consiste na implementação em FPGA de um detetor de tipo de balisa capaz de operar em condições não ideais. O funcionamento do de- tector foi avaliado com sinais de teste e sinais reais em condições ideais, de ruído AWGN e ruído pulsante. Keywords ASK, FSK, Modulation Detector, FPGA, ERTMS, Railway Signalling Abstract This dissertation is inserted in the telecommunications field, specifically rail- way signalling telecommunications systems. This project was proposed by CAF Signalling and aims at implementing the safety function to assure the in- teroperability of both Automatic Train Protection Systems (ATP) systems, ERTMS and KER. Namely, distinguish Eurobalises and KER type balises. Throughout the work the detector is modelled in Simulink and converted to VHDL code. The final step of this dissertation is the implementation on the FPGA of a robust balise type detector capable of detecting the balise type under ideal and non-ideal conditions. The performance of the detector was evaluated with real and test balise signals under ideal conditions, AWGN noise and pulsing noise. Contents Contents i List of Figures v List of Tables ix Acronyms xi 1 Introduction 1 1.1 Scope . .1 1.2 Motivation . .3 1.3 Objectives . .4 1.4 Structure of the Dissertation . .4 2 Fundamental Concepts 7 2.1 Railway Signalling Systems . .7 2.1.1 Balise . .7 2.1.2 EBICAB . .8 2.1.3 European Train Control System (ETCS) . .9 2.2 Interoperability . 11 2.3 Digital Modulation Methods . 11 2.3.1 ASK Modulation . 11 2.3.1.1 ASK Balise Signal Properties . 12 2.3.1.2 ASK Balise Signal Deviations . 12 2.3.2 FSK Modulation . 12 2.3.2.1 Continuous Phase Frequency-Shift Keying (CPFSK) Modulation 13 2.3.2.2 Eurobalise Signal Properties . 13 2.3.2.3 Eurobalise Signal Deviations . 13 2.3.2.4 Comparing FSK and ASK Signals . 13 2.4 Noise . 13 2.4.1 Additive White Gaussian Noise (AWGN) . 14 2.4.2 Disturbance Noise . 14 2.5 Safety . 15 2.5.1 Safety Integrity Level (SIL) . 15 2.6 Conclusion . 15 i 3 Architecture Modelling and Simulation 17 3.1 Balise Reference and Test Signals . 17 3.1.1 Test Signal Generator . 19 3.1.1.1 Telegram Step . 19 3.1.1.2 Signal Electrical Characteristics . 19 3.1.1.3 Balise Passage Step . 20 3.1.1.4 Output Step . 20 3.1.2 Noise Generation . 20 3.1.2.1 Adding AWGN . 20 3.1.2.2 Adding Disturbance Noise . 21 3.1.3 Validation of Test Signals with Laboratory Equipment . 21 3.1.4 Results . 21 3.1.5 Real-World Signals . 23 3.2 Algorithm Components . 24 3.2.1 Fast Fourier Transform (FFT) . 24 3.2.2 Frequency Zoom . 24 3.2.3 Frequency Thresholding . 24 3.2.4 Bandwidth Calculation . 25 3.2.5 Signal classification . 25 3.2.6 Majority decision . 25 3.3 Simulink Model . 26 3.3.1 Filtering . 26 3.3.2 FFT Block . 26 3.3.3 Frequency Index Counter . 28 3.3.4 Complex to Absolute Block . 28 3.3.5 Frequency Zoom Block . 28 3.3.6 Frequency Thresholding Blocks . 29 3.3.7 Bandwidth Calculation Block . 29 3.3.8 Signal Type Block . 29 3.3.9 Majority Decision Block . 30 3.3.10 Disturbance Detector Block . 30 3.4 Behaviour Simulation with Test Signals . 31 3.4.1 Ideal Conditions . 31 3.4.2 Added AWGN . 34 3.4.3 Added Disturbance Noise . 36 3.5 Behaviour Simulation with Real World Signals . 38 3.5.1 Simulation results - added AWGN . 41 3.5.2 Simulation results - Disturbance Noise . 41 3.6 Response Time . 46 3.7 Conclusion . 47 4 Implementation and Testing 49 4.1 VHDL Code Generation . 49 4.1.1 Fixed-Point Data Convertion . 49 4.1.2 HDL Coder . 50 4.2 Functional Simulation . 52 4.3 Synthesis and Implementation . 53 ii 4.4 FPGA Tests . 54 4.4.1 Nexys 4 . 54 4.4.2 Agilent 16822A . 55 4.4.3 FPGA Tests - Ideal Conditions . 55 4.4.4 FPGA tests - added AWGN . 60 4.4.5 FPGA Tests - Disturbance Noise . 62 4.5 Conclusion . 65 5 Conclusion 67 5.1 Future Work . 67 Bibliography 69 iii iv List of Figures 1.1 A Fixed Railway Signal. https://www.networkrail.co.uk/ [accessed October 10, 2019]. .1 1.2 A train about to pass over a railway balise. https://new.siemens.com/global/ en/products/mobility/rail-solutions/rail-automation/automatic-train-control/ european-train-control-system.html [accessed October 15, 2019]. .2 1.3 A map of the signalling systems used in different countries in Europe. https:// ec.europa.eu/transport/modes/rail/ertms/general-information/history_ ertms_it [accessed December 28, 2019]. .3 1.4 Block diagram of the communication between ERTMS and the STM. Adapted from [1]. .4 2.1 Block diagram of the communication between train and balise. http://www. railsystem.net/balise/ [accessed October 10, 2019]. .8 2.2 Train passing over an EBICAB balise. http://www.railsystem.net/balise/ [accessed October 10, 2019]. .8 2.3 ETCS trackside components. http://www.youngrailpro.com/yrp-attend-ertms-etcs-conference-2018/ [accessed October 11, 2019]. .9 2.4 ETCS operation levels 1 (a), 2 (b) and 3 (c). http://www.railsystem.net/ balise/ [accessed October 10, 2019]. 10 2.5 Representation of the different signalling components on a train. Adapted from [17]. 11 2.6 EBICAB ASK symbol. 12 2.7 Damped oscillation typical of disturbance noise. Retrieved from [16]. 14 3.1 High level diagram of the architecture of the detector. 18 3.2 Signal generator block diagram. 19 3.3 Test signal generator app. 19 3.4 Balise radiation pattern depending on air-gap distance. ..
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