Scalability in Compiler Development

Open Source Tools for Electronic Systems

Jeremy Bennett

Open Source Tools

Picprog CGEN AVRDUDE GHDL gpsim Texinfo

IRSIM

Simulation Documentation Front End Layout

gpsim Texinfo GHDL IRSIM

Backend Architectural Modeling Picprog AVRDUDE CGEN Debug & Test

Compiler Tool Chains

Processor Cores

Environments Organizations

Simulation Documentation Front End Layout

Texinfo

Debug & Test Architectural Modeling Backend CGEN

Compiler Tool Chains Processor Cores

Environments Organizations

OpenRISC 1200

OpenRISC 1200 ● 32-bit Harvard RISC architecture Power Inst W – MIPS/DLX like instruction set Mgmt MMU i s – first in OpenRISC 1000 family h B – originally developed 1999-2001 J o CPU n T Debug Inst ● Open source under the A Unit Cache e G ALU – GNU Lesser General Public License

– allows reuse as a component Tick Data W ● Configurable design Timer MMU i s h – caches and MMUs optional B o – core instruction set Data n PIC ● Cache e Source code Verilog 2001 – approx 32k lines of code

TCP/IP USB JTAG RSP GDB I/F Server RSP

(gdb)(gdb) targettarget remoteremote :51000:51000

Firmware World Hardware World

Hand-written TLM 2.0 TLM JTAG Model CGEN

Simulation or JTAG CA model Debugger Protocol simulation (GDB RSP)

Emulation Debugger JTAG or FPGA (GDB) driver

Silicon JTAG driver

TLMTLM JTAG JTAG Interface Interface

Debugger (GDB)

Golden SystemC TLM Model Verilator SystemC RTL Model

=== gcc Summary ======gcc Summary ===

# of expected passes 52753 # of expected passes 52677 # of unexpected failures 152 # of unexpected failures 228 # of expected failures 77 # of expected failures 77 # of unresolved testcases 122 # of unresolved testcases 122 # of unsupported tests 716 # of unsupported tests 716

● We can identify two types of problem – tests which fail due to timing out with RTL, but not due to slower model – tests which give a different result with RTL ● These are candidates for possible RTL errors ● Used commercially by Adapteva Inc – 50-60 RTL errors eliminated pre-tape out

Verilator's History

● 1994: Paul Wesson, Core Logic Group at DEC – for Verilog co-sim with C model of DEC Alpha ● Developed further by Duane Galbi – widely deployed at DEC ● 1998 DEC open source the code ● Since 2001 developed as part of Veripool – led by Wilson Snyder – on 3rd generation rewrite

reg [2:0] count;

initial begin count = 3'b000; end

always @(posedge clk) begin count <= count + 1; end endmodule

$ verilator -cc --trace count.v --exe main.cpp

$ cd obj_dir

$ ls Vcount_classes.mk Vcount__Syms.h Vcount.cpp Vcount__Trace.cpp Vcount.h Vcount__Trace__Slow.cpp Vcount.mk Vcount__ver.d Vcount__Syms.cpp Vcount__verFiles.dat

#include #include "Vcount.h" int main () { Vcount *top = new Vcount;

for (int i = 0; i < 16; i++) { top->clk = i % 2; top->eval (); cout << "iteration " << setw (2) << I << ", clock " << (int) top->clk << ", count " << setw (2) << (int) top->count << endl; } }

$ make -f Vcount.mk …

$ ./Vcount iteration 0, clock 0, count 0 iteration 1, clock 1, count 1 iteration 2, clock 0, count 1 iteration 3, clock 1, count 2 ... iteration 11, clock 1, count 6 iteration 12, clock 0, count 6 iteration 13, clock 1, count 7 iteration 14, clock 0, count 7 iteration 15, clock 1, count 0

... #include int main () { Verilated::traceEverOn(true); VerilatedVcdC* tfp = new VerilatedVcdC; Vcount *top = new Vcount;

top->trace (tfp, 99); tfp->open ("simx.vcd");

for (int i = 0; i < 16; i++) { top->clk = i % 2; top->eval (); tfp->dump (i); }

tfp->close(); }

● Synthesis semantics – 2-state – zero delay ● Very fast – Processor models, typically 50Hz – 500kHz ● Free – no license fees!!!

Which FOSS C/C++ Compiler Tool Chain?

● GCC based tool chain – nearly 30 years old – ~50 targets in the official distribution – big community – supports C++14, proving ground for C++17 etc – complete set of tool chain components (linker, debugger) – copyleft license ● LLVM based tool chain – 10 years old – ~15 targets in the official distribution – big community – supports C++14, proving ground for C++17 etc – complete set of tool chain components (linker, debugger) – very permissive license ● SDCC – approx 15 years old – 5 processor families in the official distribution – small community – supports most of C99, C11 – own set of tool chain components – copyleft license Copyright © 2016 Embecosm. Freely available under a Creative Commons license Organizations

“Free the Last Nanometre”

● Free and Open Source Silicon Foundation “FOSSi is a non-profit foundation with the mission to promote and assist free and open digital hardware designs and their related ecosystems. FOSSi operates as an open, inclusive, vendor-independent group.” ● LibreCores.org – making it happen – support open standards development & use – support community events and organize regular events – encourage industry participation in FOSS IP design – assist individuals and organizations with opening work

Documentation Choices

● Doxygen – Javadoc for all languages ● LibreOffice / OpenOffice – officially mandated for HMG work ● TeX, LaTeX and Texinfo Texinfo – widely used for FOSS documentation ● DITA and DocBook – XML structured documentation – many output formats ● Think about the license