DOCSLIB.ORG

View the 2020 EDS Awards Brochure

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
View the 2020 EDS Awards Brochure IEEE Electron Devices Society Awards to be presented during the virtual 2020 IEEE International Electron Devices Meeting December 2020 2020 IEEE Electron2014 Devices Society IEEE ElectronAward RecipientsDevices Society Award Recipients IEEE EDS Fellows - Class of 2020 EDS Paul Rappaport Award EDSEDS George J.J. Ebers E. Smith Award Award JoachimEDS Leo N. Esaki Burghartz Award EDS Distinguished Service Award EDSProfessor Education Jacobus W. Award Swart EDS Education Award Juin J. Liou Professor Chennupati Jagadish (2019) & Professor V. Ramgopal Rao EDS Lester F. Eastman Award EDS DistinguishedProfessor Asif Service Khan Award EDS J.J.Yuan Ebers Taur Award Professor Arokia Nathan EDS Celebrated Member Professor Robert W. Dutton EDS MEMBERS ELECTED FELLOW 20142020 IEEE Fellow is a distinction reserved for select IEEE IEEEmembers Electron whose extraordinary Devices accomplishments Society in any of theAward IEEE fields of Recipients interest are deemed fitting of this prestigious grade elevation. Only lists IEEE/EDS Fellows that would like to be recognized at the 2020 IEDM EDS J.J.Geoffrey Ebers Burr Award Ting-chang Chang JoachimChion N. ChuiBurghartz Barbara De Salvo Muhammad Hussain EDS EducationBenjamin Iniguez Award JuinMartin J. Kuball Liou Wallace Lin Po-tsun Liu EDS DistinguishedDurgamadhab Service Misra Award Bich-yen Nguyen ShoulehYuan TaurNikzad Byung-gook Park Ravi Todi 2014 IEEE Electron Devices Society Award Recipients EDS PAUL RAPPAPORT AWARD The Paul Rappaport Award was established in 1984 to recog- nize the best EDSpaper appearingJ.J. Ebers in a fastAward turn around archival publication of the IEEE Electron Devices Society, targeted to the IEEE TransactionsJoachim on Electron N. Burghartz Devices. Winning Paper: EnhancedEDS Reliability Education of 7nm Process Award Technology Featuring EUV Juin J. Liou Authors: Kihyun Choi, Hyun Chul Sagong, Wonchang Kang, Hyunjin Kim, Jiang Hai, Miji Lee, Bomi Kim, Mi-ji Lee, EDSSoonyoung Distinguished Lee, Hyewon Shim, Service Junekyun Award Park, YoungWoo Cho, HwaYuan Sung Taur Rhee and Sangwoo Pae 2014 IEEE Electron Devices Society Award Recipients EDS GEORGE E. SMITH AWARD The George E. Smith Award was established in 2002 to rec- ognize the bestEDS paper J.J.appearing Ebers in a fastAward turn around archival publication of the IEEE Electron Devices Society, targeted to the IEEE ElectronJoachim Device Letters. N. Burghartz Winning Paper: "Large-AreaEDS 1.2-kV Education GaN Vertical Award Power FinFETs With a Record Switching Figure of Merit" Juin J. Liou Authors: Yuhao Zhang, Min Sun, Josh Perozek, Zhihong Liu, Anmad Zubair, Daniel Piedra, Nadim Chowdhury, EDSXiang Distinguished Gao, Kenneth Shepard Service and Tomas Palacios Award Yuan Taur 2014 IEEE Electron Devices Society Award Recipients EDS LEO ESAKI AWARD The EDS Leo Esaki Award was established in 2019 to recog- nize the best paperEDS appearing J.J. Ebers in a fast Award turn around archival publication of the IEEE Electron Devices Society, targeted to the IEEE JournalJoachim of Electron DevicesN. Burghartz Society. Winning Paper: FerroelectricEDS HfO2 Education Tunnel Junction Award Memory with High TER and Multi-level Operation Featuring Metal JuinReplacement J. Liou Process Authors: Masaharu Kobayashi, Yusaku Tagawa, Fei Mo, EDS DistinguishedTakuya Saraya and Toshiro Service Hiramoto Award Yuan Taur EDS DISTINGUISHED SERVICE AWARD The EDS Distinguished Service Award was established in 1993 by the IEEE Electron2014 Devices Society. The Award is presented annually and is intended to recognize and honor outstanding service to the Electron IEEEDevices ElectronSociety and its sponsored Devices activities. Society PREVIOUSAward AWARD Recipients WINNERS 1994 Friedolf M. Smits 1995 Lewis M. Terman 1996 Alfred U. Mac Rae 1997 George E. Smith 1998EDS J.J. W. EbersDexter Johnston, Award Jr. 1999 John R. Brews 2000Joachim Michael N. BurghartzS. Adler 2001 H. Craig Casey, Jr. 2002 Lucian A. Kasprzak 2003 Frederick H. Dill 2004 Louis C. Parrillo EDS2005 Education Cary Y. Yang Award 2006 Steven J. Hillenius 2007Juin Richard J. S.Liou Muller 2008 Hiroshi Iwai 2009 Tak H. Ning 2010 Marvin H. White 2011 Ilesanmi Adesida EDS Distinguished2012 Douglas P. ServiceVerret Award 2013 Cor L. Claeys 2014Yuan Yuan Taur Taur 2015 - 2016 Renuka P. Jindal 2017 Paul K.L. Yu 2018 Shuji Ikeda 2019 Albert Z. H. Wang 2020 EDS DISTINGUISHED SERVICE AWARD RECIPIENT PROFESSOR 2014JACOBUS W. SWART Jacobus W. Swart received his B. Engineering and Dr. Engineering De- grees in 1975 and 1981 respectively, from the Polytechnic School of the IEEE ElectronUniversity of São Paulo, Devices Brazil. After his Dr. Degree, Society he worked at the following institutions: K. U. Leuven, Belgium, 1982-83, as a pos-doc.; AwardCTI, Campinas, 1984; Recipients University of São Paulo, 1985-88, as Assistant Professor; SID Microeletrônica, 1986, as process engineering; RTI, USA, 1991, as a Visiting Scientist and since 1988 at State University of Camp- inas, as Full Professor until retirement in 2013, when he assumed a po- sition as collaborator professor. He served as director of the Center for Semiconductor Components, from April 1998 to April 2005. From May 2007 until June 2011 he was on leave from theEDS University J.J. to serve Ebers as General Director Award of CTI, a national research cen- ter. During this time he was the coordinator of the IC Brazil program, leading ASIC design training centers and a network of local design houses. He was the leader of a large research network in Brazil, calledJoachim INCT NAMITEC, from N. 2001 Burghartz until 2016. Since 2013 he provides service to imec, Belgium, as their representative in Brazil. Dr Swart has published around 300 papers in Journals and Conferences covering his reseach work on materials, fabrication processing, device characterization and modelling and ASIC design. He is ranked as fellow researcher, level 1A (highest) atEDS CNPq and isEducation a Fellow of the São Paulo Award State Academy of Science and of National Engineering Academy. He is a Life Fellow of IEEE and servedJuin on different J. Liou positions for EDS, as secretary, BoG mem- ber, Distinguished Lecturer, member of many committees, Region 9 Subcommittee for Re- gions and Chapters (SRC) Chair, founder and chair of South Brazil EDS chapter and advisor of EDS student chapter at UNICAMP. He was member and/or chair of many organizing conference committees in Region 9, especially in Brazil, including conferences as SBMicro, ICCDCS and LAEDC.EDS He was president Distinguished of SBMicro Sociedty for two Service terms, and promoted Award the SBMicro con- ference as a technically co-sponsered conference of EDS. Yuan Taur Jacobus was born in The Netherlands in 1950 and emigrated to Brazil with his parents and ten brothers and sisters in 1958, as farmers. He was the only one that did not followed the farm- ing profession. He met and married Nilza during undergraduate studies and they have three children: Hugo, Laura and Julia, two Electronics Engineers and one Economist. Presently, he and Nilza are blessed with ten grandchildren. PROFESSOR JACOBUS W. SWART KEY POSITIONS HELD EDS/IEEE Service Activities 2014 2002-2006 EDS South-Brazil Chapter Chair 2003-Present EDS UNICAMP Student Chapter Advisor IEEE2004-Present Electron EDS Distinguished Lecturer Devices Society 2006-2008 EDS Newsletter co-Editor 2006-2015Award EDS Membership Committee Recipients Member 2007-2016 EDS Education Committee Member 2008 ICCDCS Program Chair 2008-2011 EDS Region 9 Subcommittee for Regions and Chapters (SRC) Member 2012-2017 EDSEDS Region 9 J.J.Subcommittee Ebers for Regions Award and Chapters (SRC) Chair 2012-2017 EDS Region 9 Outstanding Student Paper Award Committee Chair 2013-2017 EDSJoachim VLSI Technology and N. Circuits Burghartz Technical Committee Member 2014-2015 EDS Constitution & Bylaws Review AdHoc Committee Chair 2014-2016 EDS BoG Elected Member 2014-2017 EDS Awards Committee Member 2016-PresentEDS IEEE Cledo BrunettiEducation Award Committee MemberAward 2017-2019 EDS BoG Elected Member 2017-2019 EDS Fellow EvaluationJuin Committee J. Liou Member 2018-2019 EDS Secretary 2018-2019 EDS Newsletter Committee Chair 2018-2019 EDS Early Career Award Committee Member 2018-2019EDS Distinguished EDS Publication Committee Member Service Award 2018-2019 IEEE Cledo Brunetti Award Committee Chair 2019-Present LAEDC OrganizingYuan Committee Taur Member 2020-Present EDS Region 9 Outstanding Student Paper Award Committee Member 2001-2008 SBMicro Organizing Committee Member 2020 SBMicro General Chair EDUCATION AWARD The EDS Education Award2014 was established in 2006 by the IEEE Electron Devices Society. IEEE Electron Devices Society The Award is presented annually and is intended to recognize Awarddistinguished Recipients contributions to education within the fields of interest of the IEEE Electron Devices Society. EDS J.J. Ebers Award PREVIOUS AWARD WINNERS 2006Joachim Mark N. S. BurghartzLundstrom 2007 Meyya Meyyappan 2008 Robert W. Dutton 2009EDS Education David L. Pulfrey Award 2010 Sorab K. Ghandhi Juin J. Liou 2011 Chenming Hu 2012 Jesús Del Alamo EDS2013 Distinguished Charvaka DuvvuryService Award 2014 Juin J. Liou 2015 RogerYuan T. Taur Howe 2016 Hiroshi Iwai 2017 Mansun Chan 2018 Muhammad Ashraful Alam 2019 EDUCATION AWARD RECIPIENT PROFESSOR CHENNUPATI JAGADISH “For distinguished and sustained2014 contributions globally to education, training and mentoring in the field of interest of the IEEE Electron Devices Society” IEEE ElectronProfessor Chennupati Devices
Load more

Recommended publications
  • Simulation and Design of Germanium-Based Mosfets For
    UNIVERSITY OF CINCINNATI Date:___________________ I, _________________________________________________________, hereby submit this work as part of the requirements for the degree of: in: It is entitled: This work and its defense approved by: Chair: _______________________________ _______________________________ _______________________________ _______________________________ _______________________________ Simulation and Design of Germanium-Based MOSFETs for Channel Lengths of 100 nm and Below A Thesis submitted to the Division of Graduate Studies and Research of The University of Cincinnati in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE (M.S.) in the department of Electrical and Computer Engineering of the College of Engineering March, 2007 by Martin Keith Arnold Jr. B.S. (Physics and Mathematics), Northern Kentucky University Highland Heights, KY, USA. Thesis Advisor and Committee Chair: Dr. Kenneth P. Roenker ABSTRACT Conventional silicon MOSFETs are rapidly approaching the end of the roadmap for conventional scaling techniques. As a result, alternative device designs, such as transport-enhanced FETs along with other semiconductor technologies, such as multi- gate transistors, are being investigated. Transport-enhanced FETs simply employ new materials in the channel region of MOSFETs with higher carrier mobilities and velocities than silicon. Since the electron and hole mobilities in germanium are considerably larger than those of silicon, Ge-based MOSFETs are being considered as a replacement for conventional Si MOSFETs for both p- and n-channel transistors for CMOS applications. Long-channel Ge MOSFETs have already been demonstrated exhibiting considerable performance enhancements over comparable Si devices. The Ge devices in these studies showed improvements over the Si devices in the output drain current, effective mobility, and small signal transconductance.
    [Show full text]
  • Welcome from the General Chair
    WELCOME FROM THE GENERAL CHAIR On behalf of the entire IEDM committee, I would like to welcome you to the 2010 IEEE International Electron Devices Meeting to be held December 6-8, 2010 in San Francisco. The IEDM continues to be the world’s premier venue for presenting the latest breakthroughs and the broadest and best technical information in electronic device technologies. This year we have a strong collection of both contributed and invited papers that will be presented by industrial and academic leaders and students from around the world. Short summaries of each paper are available on the IEDM web site, which we encourage everyone to visit – http://www.ieee.org/conference/iedm. This year, we will continue to distribute an abbreviated digest at the meeting, along with electronic versions of the complete abstracts, to more effectively leverage modern electronic content distribution capabilities. The full digest will be available on the IEEE Xplore website and the DVD package offered by the IEEE Electron Devices Society after the conference. In addition to the many regular paper sessions - and the always informative and entertaining IEDM Luncheon on Tuesday - we will again feature several special sessions. Meikei Ieong On Sunday December 5, 2010, two short courses will be offered: “15nm CMOS Technology” and General Chair “Reliability and yield of advanced integrated technologies”. These courses have been organized and will be presented by internationally known leading researchers active in their respective areas of technology. The topics have broad appeal to IEDM participants with material suitable for newcomers as well as experts in the field.
    [Show full text]
  • Complementary Metal Oxide Semiconductor Pdf
    Complementary metal oxide semiconductor pdf Continue High-speed Ge photodetector is monolithically integrated with a large cross-section of silicon on the insulator waveguideDazeng Feng, Shing Liao, Po Dong, Ning-Ning Feng, Hong Liang, Dawei Cheng, Cheng-Chi Kung, Joan Fong, Roshanak Shafiyha, Jack Cunningham, Ashok W. Krishnamurti High- Speed Polysilicon CMOS photodeter for telecommunications and datacomark current analysis in high-speed Germanium pctor-n wave Chen. Verheijen. De Hain, G. Lepage, D. De Koster, S. Balakrishnan,. Absil, G. Roelkens and J. Van Campenhout more... For other purposes, see CMOS (disambiguation). The CMOS inverter integrated circuitry (non-logical gate) Additional Metallic Semiconductor Oxide (CMOS), also known as complementary-symmetrical metal-oxide-semiconductor (COS-MOS), is a type of metal-oxide-semiconductor field-field transistor (MOSFET) manufacturing process that uses additional and symmetrical p-type pairs. CMOS technology is used to build integrated circuit chips (IC), including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic schemes. CMOS technology is also used for analog circuits such as image sensors (CMOS sensors), data converters, RFS circuits (RFOS) and highly integrated transceivers for many types of communication. Mohamed M. Atallah and Dovon Kang invented MOSFET at Bell Labs in 1959 and then demonstrated the manufacturing processes of PMOS (p-type MOS) and NMOS (n-type MOS) in 1960. These processes were later combined and adapted into an additional PROCESS by Chi-Tan Sahom and Frank Wanlass at Fairchild Semiconductor in 1963. RCA commercialized the technology with the brand name COS-MOS in the late 1960s, forcing other manufacturers to look for a different name, which leads to the fact that by the early 1970s CMOS became the standard name of the technology.
    [Show full text]
  • A 480-Mhz RISC Microprocessor in a 0.12- M Leff CMOS Technology with Copper Interconnects
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 11, NOVEMBER 1998 1609 A 480-MHz RISC Microprocessor in a 0.12- m Leff CMOS Technology with Copper Interconnects Chekib Akrout, John Bialas, Miles Canada, Duane Cawthron, James Corr, Bijan Davari, Senior Member, IEEE, Robert Floyd, Stephen Geissler, Ronald Goldblatt, Robert Houle, Paul Kartschoke, Diane Kramer, Peter McCormick, Member, IEEE, Norman Rohrer, Gerard Salem, Ronald Schulz, Lisa Su, Member, IEEE, and Linda Whitney Abstract—This paper describes the performance improvements SPECint95 and SPECfloat95 ratings of 20 and 12, respectively, of a reduced instruction set computer (RISC) microprocessor that at 480 MHz with a 1-MB L2 cache running at 240 MHz and has migrated from a 2.5-V technology to a 1.8-V technology. The a60 bus frequency of 96 MHz. The 60 bus is the high- 1.8-V technology implements copper interconnects and low ttt speed 32- and 64-bit processor bus interface used throughout field-effect transistors in speed-critical paths and has an vvve of 0.12 """m. Global clock latency and skew are improved by using the PowerPC family of processors. copper wires, and early mode timings are improved by reducing clock skew and adding buffers. These enhancements, along with III. TECHNOLOGY an environment of 2.0 V, 85C, and with a fast process, produced a 480-MHz RISC microprocessor. The 2.5-V CMOS technology, with a field-effect transistor (FET) of 0.18 m, has five interconnect levels made of Index Terms—CMOS, copper, low threshold, microprocessor, PowerPC, reduced instruction set computer (RISC).
    [Show full text]
  • Review Article Advanced MOSFET Technologies for Next Generation
    JOURNAL OF Journal of Engineering Science and Technology Review 11 (3) (2018) 180 - 195 Engineering Science and estr Technology Review J Review Article www.jestr.org Advanced MOSFET Technologies for Next Generation Communication Systems - Perspective and Challenges: A Review Himangi Sood1, Viranjay M. Srivastava2,* and Ghanshyam Singh3 1Department of Electronics and Communication, Jaypee university of Information Technology, Waknaghat, Solan – 173234, India. 2Department of Electronic Engineering, Howard College, University of KwaZulu-Natal, Durban – 4041, South Africa. 3Department of Electrical and Electronics Engineering Sciences, Auckland Park Kingsway Campus, University of Johannesburg, PO Box 524, Johannesburg - 2006, South Africa. Received 21 February 2018; Accepted 19 July 2018 ___________________________________________________________________________________________ Abstract In this review, authors have retrospect the state-of-art dimension scaling and emerging other non-conventional MOSFET structures particularly, the Double-Gate (DG) MOSFET and Cylindrical Surrounding Double-Gate (CSDG) MOSFET. These are presented for the future devices to reduce the short channel effects for the next generation communication system as the dimension of device approaches to the nanometer regime. The discussion on advantages and compact modeling approaches of both the MOSFETs have been presented. Moreover, these compact models are very useful to understand the physical characteristics of devices and also necessary for the circuit simulators, which
    [Show full text]
  • Applications of Nanotechnology in Electronics Pdf
    Applications of nanotechnology in electronics pdf Continue Part of a series of articles on Nanoelectronics Single-Molecular Electronics Molecular Scale Molecular Logic Gate Molecular Wires Solid-State Nanocircuitry Nanowires Nanolithography NEMS Nanosensor Moore Law Multigate Device Semiconductor Device Manufacturing List of Examples of Semiconductor Nanoionics Nanophotonics Nanomechanics Science Portal Electronics Portal Technology portal portal portalvte Part of a series of articles on Nanotechnology Stories Organization Popular Culture Outline Impact and Applications Nanomedicine Nanotoxicology Green Nanotechnology Dangers Regulation of Fuller Nanomaterials Carbon Nanoparticles Nanoparticles Molecular Self-Assembly Self-Assembling Supramolecular Assemblage DNA Nanoelectronics Molecular Scale Electronics Nanolithography Moore Law Semiconductor Device Manufacturing Semiconductor Scale The Electron microscope microscope microscope Super resolution microscopy Nanotribology Molecular nanotechnology Molecular Nanorobotics Mechano molecular engineering science portalvte Nanoelectronics refers to the use of nanotechnology in electronic components. The term covers a wide range of devices and materials, with a common characteristic that they are so small that interatomic interactions and quantum-mechanical properties must be studied extensively. Some of these candidates include: hybrid molecular/semiconductor electronics, one-dimensional nanotubes/nanowires (e.g. silicon nanowires or carbon nanotubes) or advanced molecular electronics. Nanoelectronic
    [Show full text]
  • SRC 2000 Annual Report
    Jack Kilby Dedication There are few living men whose insights and professional accomplishments have changed the world. Jack Kilby is one of these men. There are few living men whose insights and professional accomplishments have changed the world. Jack Kilby is one of these men. His invention of the integrated circuit — the intellectual property policies by guiding microchip — some 30 years ago at Texas their formulation and participating in their Instruments (TI) provided the conceptual implementation. More recently, he proposed and technical foundation for modern micro- the Landmark Innovation Award the first of electronics. This was the key breakthrough which was presented by Mr. Kilby to Prof. that enabled the high-speed computers, Farhang Shadman at TECHCON 2000. More large-capacity semiconductor memories, importantly, Jack has made himself available network appliances, and complex controllers to consult and guide SRC throughout its nine- that characterize today’s information age. teen-year existence. He has been, and is, an On December 10, 2000, Mr. Kilby was important part of the successful development awarded the Nobel Prize in Physics for his of cooperative research in semiconductor pioneering and revolutionary work. technology. Jack Kilby has been an integral part of SRC’s In recognition of his lifetime of accomplish- evolution. He participated actively in SRC’s ments, of the recognition of his achievements summer studies in which he provided key per- through award of the Nobel Prize, and his spectives in debates on strategic organization contributions to cooperative research in directions and seminal insights on semicon- semiconductors, the Semiconductor Research ductor technology issues. Jack also played Corporation dedicates this annual report to a key role in the development of SRC’s Jack S.
    [Show full text]
  • Technology Directions for the 21 St Century Volume I
    /, "T" / NASA Contractor Report 198478 Technology Directions for the 21 st Century Volume I Giles F. Crimi, Henry Verheggen, William Mclntosh, and Robert Botta Science Applications International Corporation McLean, Virginia May 1996 Prepared for Lewis Research Center Under Contract DAEA32-96-D4)001 National Aeronautics and Space Administration PREFACE It has been said that the only thing that is constant is change. This adage is well borne out in both the understanding of space and the pursuit of that understanding. In the last twelve months, the scientific studies of our universe, made possible by spectacularly successful flight programs such as the Hubble Space Telescope, Galileo, and Magellan, almost daily have expanded our understanding of the universe and the planets in our solar system. Here on Earth, the space business has also undergone a similar revolutionary process. In the ever complex requirement to balance the pursuit of meaningful science programs with the shrinking availability of funding, NASA has entered the era of having to do more with less. Our focus has shiftedto designing faster, cheaper, and better missions without compromising safety or scientific value. Therefore, our technology strategiesmust correspondingly change to accommodate this new approach. Technology application and systems acquisition must emphasize standardized, multi-use services and operationsconcepts,levemgcd with thoseof our industrialparmers,internationalcounterparts, and academia, as appropriate.Movement toward privatizationof space businesswillbe requiredto bettershare rewards, exchange technicalknowledge, and increaseoperationalefficiencics.These changes are no longer options,but are essentialto sustainingour economy and assuring the continued technologicalleadershipof our Nation. One common thread to the success of our flight programs has been the reliable communication of each bit of information from the spacecraftto the ultimate user.
    [Show full text]
  • IEEE ANDREW S. GROVE AWARD RECIPIENTS (Formerly the IEEE Jack A
    IEEE ANDREW S. GROVE AWARD RECIPIENTS (Formerly the IEEE Jack A. Morton Award) 2022 – HEIKI RIEL “For contributions to materials for IBM Fellow, Lead IBM Research nanoscale electronics and organic light- Quantum Europe & Africa, Zurich, emitting devices.” Switzerland 2021 – HIDEAKI AOCHI “For pioneering and sustained Senior Expert, Institute of Memory contributions to high-density, three- Technology Research and dimensional flash memory.” Development, Kioxia Corporation, Kanagawa, Japan AND RYOTA KATSUMATA Deputy General Manager, Advanced Memory Development Center, Kioxia Corporation, Mie, Japan AND MASARU KITO Group Manager, Advanced Memory Development Center, Kioxia Corporation, Mie, Japan 2020 – EVELYN L. HU “For pioneering contributions to Tarr-Coyne Professor microelectronics fabrication technologies of Applied Physics and Electrical for nanoscale and photonic devices.” Engineering, John A. Paulson School of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, USA 2019 – DIGH HISAMOTO “For pioneering work in the manufacturing Chief Senior Scientist, of three-dimensional double-gate MOSFET Hitachi; Ltd., Tokyo, Japan devices.” 2018 - GURTEJ S. SANDHU “For contributions to silicon CMOS process Senior Fellow, Director, Emerging technology that enable DRAM and NAND Memory Technologies R&D, Micron memory chip scaling.” Technology Inc., Boise, Idaho, USA 2017 - SORIN CRISTOLOVEANU “For contributions to silicon-on-insulator Director of Research, The French technology and thin body devices.” National Centre for
    [Show full text]
  • 1 Analytical Design and Numerical Verification of P
    Analytical Design and Numerical Verification of p- Channel Strained Silicon-Germanium Hetero MOSFET Item Type text; Electronic Dissertation Authors Gopal, Mohan Krishnan Publisher The University of Arizona. Rights Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. Download date 28/09/2021 14:14:00 Link to Item http://hdl.handle.net/10150/195905 1 ANALYTICAL DESIGN AND NUMERICAL VERIFICATION OF P-CHANNEL STRAINED SILICON-GERMANIUM HETERO MOSFET by Mohan Krishnan Gopal Copyright Mohan Krishnan Gopal 2008 A Dissertation Submitted to the Faculty of the DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING In Partial Fulfillment of the Requirements For the Degree of DOCTOR OF PHILOSOPHY In the Graduate College THE UNIVERSITY OF ARIZONA 2008 2 THE UNIVERSITY OF ARIZONA GRADUATE COLLEGE As members of the Dissertation Committee, we certify that we have read the dissertation prepared by Mohan Krishnan Gopal entitled “Analytical Design and Numerical Verification of p-Channel Strained Silicon-Germanium Hetero MOSFET” and recommend that it be accepted as fulfilling the dissertation requirement for the Degree of Doctor of Philosophy ________________________________________________________________ ____ Date: November 25, 2008 John R. Brews, Ph.D. _____________________________________________________________________ Date: August 1, 2008 Harold G. Parks, Ph.D. _____________________________________________________________________ Date: August 1, 2008 Olgierd A. Palusinski, Ph.D. Final approval and acceptance of this dissertation is contingent upon the candidate’s submission of the final copies of the dissertation to the Graduate College.
    [Show full text]