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Simulation and Design of Germanium-Based Mosfets For UNIVERSITY OF CINCINNATI Date:___________________ I, _________________________________________________________, hereby submit this work as part of the requirements for the degree of: in: It is entitled: This work and its defense approved by: Chair: _______________________________ _______________________________ _______________________________ _______________________________ _______________________________ Simulation and Design of Germanium-Based MOSFETs for Channel Lengths of 100 nm and Below A Thesis submitted to the Division of Graduate Studies and Research of The University of Cincinnati in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE (M.S.) in the department of Electrical and Computer Engineering of the College of Engineering March, 2007 by Martin Keith Arnold Jr. B.S. (Physics and Mathematics), Northern Kentucky University Highland Heights, KY, USA. Thesis Advisor and Committee Chair: Dr. Kenneth P. Roenker ABSTRACT Conventional silicon MOSFETs are rapidly approaching the end of the roadmap for conventional scaling techniques. As a result, alternative device designs, such as transport-enhanced FETs along with other semiconductor technologies, such as multi- gate transistors, are being investigated. Transport-enhanced FETs simply employ new materials in the channel region of MOSFETs with higher carrier mobilities and velocities than silicon. Since the electron and hole mobilities in germanium are considerably larger than those of silicon, Ge-based MOSFETs are being considered as a replacement for conventional Si MOSFETs for both p- and n-channel transistors for CMOS applications. Long-channel Ge MOSFETs have already been demonstrated exhibiting considerable performance enhancements over comparable Si devices. The Ge devices in these studies showed improvements over the Si devices in the output drain current, effective mobility, and small signal transconductance. The purpose of this study is to examine the performance capabilities and scaling behavior of short channel Ge-based n-MOSFETs using a commercial numerical device simulator from ISE Corporation. This thesis will describe the results of DC and small signal AC simulations of the device’s transistor characteristics and compare them with those for a silicon device of the same geometry and size. We will also examine the effects of variations in the device structure on the Ge MOSFET’s performance, including the transconductance and high frequency response. ACKNOWLEDGEMENTS I would like to express my gratitude to the faculty and students of the University of Cincinnati for making my stay here a pleasant experience. In particular, I would like to thank Dr. Kenneth P. Roenker for his continuous guidance and advice throughout the course of my stay. His contribution to this work is immense and I thank him for the time and effort he has invested ensuring its completion. I also wish to thank Dr. Punit Boolchand and Dr. Marc Cahay for investing their time to serve on my thesis defense committee. I would like to thank my former and present lab members; Aniket, Joe, Yajun, Subbu, and Saumitra for their helpful advice and the various discussions we had, both technical and otherwise. It was fun to be a part of this research group and share time in the laboratory. I wish to express my gratitude to my friends and family for being a constant source of support over the past two years. I especially wish to thank my parents for their guidance, patience, and understanding. Without their continuous encouragement and support I would have fallen astoundingly short of pursuing something so ambitious. CONTENTS 1. Introduction 15 1.1 Moore’s Law 16 1.2 MOSFET Scaling Theories and Limitations 18 1.2.1 Scaling Theories 18 1.2.2 Scaling Complications and Limitations 21 1.3 Silicon-on-Insulator Technology 23 1.4 Innovative New MOSFET Designs 26 1.5 Advantages of Ge-Based MOSFETs 27 1.6 Previous Works Reported on Ge-Based MOSFETs 29 1.6.1 Experimental Reports 30 1.6.2 Transistor Modeling Reports 37 1.7 Current Ge-Based MOSFET Research Focus 45 2. Device Simulation Framework 54 2.1 Simulation Software 55 2.2 Numerical Techniques 56 2.3 Simulation Models 58 2.3.1 Mobility Models 58 2.3.1.1 Doping-Dependent Mobility Degradation 59 2.3.1.2 High Field Saturation 61 - 1 - 2.3.1.3 Mobility Degradation at Interfaces 63 2.3.2 Bandgap Narrowing 65 2.3.3 Shockley-Read-Hall Recombination 66 2.3.3.1 SRH Recombination Doping Dependence 67 Model 3. Modeling Results for Baseline Germanium MOSFETs 72 3.1 Long-Channel Germanium MOSFET 73 3.1.1 Device Structure 73 3.1.2 Device Performance 77 3.1.2.1 Transfer Characteristics 78 3.1.2.2 Subthreshold Characteristics 79 3.1.2.3 Output Current-Voltage Characteristics 80 3.1.2.4 Small Signal Transconductance 83 3.1.2.5 Current Gain and Cutoff Frequency 84 3.1.2.6 Unilateral Power Gain and Maximum 85 Frequency of Oscillation 3.2 Short-Channel Germanium-on-Insulator MOSFET 88 3.2.1 Device Structure 88 3.2.2 Device Performance 91 3.2.2.1 Transfer Characteristics 91 3.2.2.2 Subthreshold Characteristics 92 3.2.2.3 Output Current-Voltage Characteristics 94 - 2 - 3.2.2.4 Small Signal Transconductance 97 3.2.2.5 Current Gain, Cutoff Frequency and 98 Maximum Frequency of Oscillation 3.2.2.6 Investigating Carrier Transport in Simulated 102 GOI MOSFET 4. Variations in Device Design and Effects on Device Performance 107 for Germanium-on-Insulator MOSFET 4.1 Effects of Variation in Gate Dielectric Material 109 4.2 Effects of Variation in Gate Oxide Thickness 120 4.3 Effects of Variation in Channel Doping 127 4.4 Effects of Variation in Channel Length 133 4.5 Summary and Conclusions 139 5. Conclusion and Future Work 143 5.1 Conclusion 143 5.2 Future Work 146 - 3 - LIST OF FIGURES Figure 1.1 A plot of Moore’s Law (the number of components per chip as a function of time) as originally predicted in 1965, as well as his alteration to the slope (1975) due to the limit on the density, taking effect around 1980. Figure 1.2 Illustration of the principles of constant electric field scaling for MOSFETs. Figure 1.3 (a) Measured IS-VD output characteristics of Ge PFET. (b) Measured IS- VD subthreshold characteristics at low drain biases for Ge PFET. (c) Transconductance characteristics of Ge PFET and Si control PFET. (d) Effective mobility extracted from Ge PFET, Si control PFET, and the universal Si hole mobility. Figure 1.4 (a) Measured IS-VD output characteristics of n-channel Ge MOSFET activated at 500 °C. (b) Linear transfer characteristics of Ge MOSFETs activated at 500 °C and 400 °C. (c) Subthreshold characteristics of Ge MOSFETs activated at 500 °C and 400 °C. Figure 1.5 (a) Measured ID-VG characteristics of Ge n-MOSFET. (b) Extracted effective electron mobility as a function of effective electric field for bulk Ge with different surface treatment and HfO2 deposition compared to that for Si control n-MOSFETs. - 4 - Figure 1.6 (a) Measured ID-VD output characteristics and (b) measured ID-VG output characteristics for n-channel Ge MOSFETs with laser annealing (LA) and rapid thermal annealing (RTA). Figure 1.7 Extracted effective electron mobility versus effective electric field for Ge n-MOSFETs with LA and RTA and a HfO2/Si control device. Figure 1.8 (a) Electron drift velocity versus electric field in undoped Ge at 77 K, 190 K, and 300 K. (b) Calculated electron effective mobility versus inversion charge, (c) Electron velocity along the channel, and (d) ID-VD output characteristics for control-SOI, strained-SOI, and GeOI n-MOSFET. Figure 1.9 Carrier drift velocity as a function of electric field for Si, Ge, and GaAs. Figure 1.10 Cross-sectional schematic diagram and a list of parameters for simulated GOI n-MOSFETs. Figure 1.11 (a) The intrinsic performance CgVg/Ion as a function of Ioff for n- and p- GOI MOSFETs at Vds = 1 V. (b) The ratio of pMOS and nMOS intrinsic delay as a function of the channel length. Figure 1.12 (a) Simulated and experimental effective electron mobility versus the effective electric field for Si and Ge. (b) Comparison of the drive current of GOI and SOI devices with various gate lengths. (c) Relationship between off-state leakage current and drive current of GOI and SOI devices. (d) Intrinsic delay (CV/I) versus gate length of GOI and SOI with body thicknesses. Figure 1.13 (a) Comparison of simulated results with experimental data of the carrier drift velocity versus the effective electric field in Ge. (b) Effective - 5 - electron mobility as a function of the surface roughness factor L for Ge and Si at different electric field strengths. (c) Electron mobility versus electric field curves for both, their simulation results and proposed model, as well as a comparison to the Si electron universal mobility curve. Figure 1.14 International Technology Roadmap for Semiconductors (ITRS) prediction for the future of SOI technology beyond the 90 nm node. Figure 3.1 A cross-section schematic diagram of the long-channel Ge MOSFET used for this simulation study. Figure 3.2 Dopant profile results obtained from DIOS simulation, based on implant information from Shang et. al. Figure 3.3 (a) Magnified image of the channel region of the MOSFET showing the device mesh. (b) Magnified image of the MOSFET at the end of the source and beginning of the channel. Figure 3.4 Transfer characteristics of the Ge MOSFET, compared to the Si device, at VD = 0.5 V. A VT of 1.49 and 1.25 V was extracted for the Ge and Si devices, respectively. Figure 3.5 Subthreshold characteristics of Ge MOSFET, compared to Si MOSFET, at VD = 0.5V.
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