UNIVERSITY OF CINCINNATI

Date:______

I, ______, hereby submit this work as part of the requirements for the degree of: in:

It is entitled:

This work and its defense approved by:

Chair: ______

Simulation and Design of Germanium-Based MOSFETs

for Channel Lengths of 100 nm and Below

A Thesis submitted to the

Division of Graduate Studies and Research of

The University of Cincinnati

in partial fulfillment of the

requirements for the degree of

MASTER OF SCIENCE (M.S.)

in the department of

Electrical and Computer Engineering

of the College of Engineering

March, 2007

by

Martin Keith Arnold Jr.

B.S. (Physics and Mathematics), Northern Kentucky University

Highland Heights, KY, USA.

Thesis Advisor and Committee Chair: Dr. Kenneth P. Roenker ABSTRACT

Conventional silicon MOSFETs are rapidly approaching the end of the roadmap for conventional scaling techniques. As a result, alternative device designs, such as transport-enhanced FETs along with other semiconductor technologies, such as multi- gate transistors, are being investigated. Transport-enhanced FETs simply employ new materials in the channel region of MOSFETs with higher carrier mobilities and velocities than silicon. Since the electron and hole mobilities in germanium are considerably larger than those of silicon, Ge-based MOSFETs are being considered as a replacement for conventional Si MOSFETs for both p- and n-channel transistors for CMOS applications.

Long-channel Ge MOSFETs have already been demonstrated exhibiting considerable performance enhancements over comparable Si devices. The Ge devices in these studies showed improvements over the Si devices in the output drain current, effective mobility, and small signal transconductance. The purpose of this study is to examine the performance capabilities and scaling behavior of short channel Ge-based n-MOSFETs using a commercial numerical device simulator from ISE Corporation. This thesis will describe the results of DC and small signal AC simulations of the device’s transistor characteristics and compare them with those for a silicon device of the same geometry and size. We will also examine the effects of variations in the device structure on the Ge

MOSFET’s performance, including the transconductance and high frequency response.

ACKNOWLEDGEMENTS

I would like to express my gratitude to the faculty and students of the University of Cincinnati for making my stay here a pleasant experience. In particular, I would like to thank Dr. Kenneth P. Roenker for his continuous guidance and advice throughout the course of my stay. His contribution to this work is immense and I thank him for the time and effort he has invested ensuring its completion. I also wish to thank Dr. Punit

Boolchand and Dr. Marc Cahay for investing their time to serve on my thesis defense committee. I would like to thank my former and present lab members; Aniket, Joe,

Yajun, Subbu, and Saumitra for their helpful advice and the various discussions we had, both technical and otherwise. It was fun to be a part of this research group and share time in the laboratory.

I wish to express my gratitude to my friends and family for being a constant source of support over the past two years. I especially wish to thank my parents for their guidance, patience, and understanding. Without their continuous encouragement and support I would have fallen astoundingly short of pursuing something so ambitious.

CONTENTS

1. Introduction 15

1.1 Moore’s Law 16

1.2 MOSFET Scaling Theories and Limitations 18

1.2.1 Scaling Theories 18

1.2.2 Scaling Complications and Limitations 21

1.3 Silicon-on-Insulator Technology 23

1.4 Innovative New MOSFET Designs 26

1.5 Advantages of Ge-Based MOSFETs 27

1.6 Previous Works Reported on Ge-Based MOSFETs 29

1.6.1 Experimental Reports 30

1.6.2 Transistor Modeling Reports 37

1.7 Current Ge-Based MOSFET Research Focus 45

2. Device Simulation Framework 54

2.1 Simulation Software 55

2.2 Numerical Techniques 56

2.3 Simulation Models 58

2.3.1 Mobility Models 58

2.3.1.1 Doping-Dependent Mobility Degradation 59

2.3.1.2 High Field Saturation 61

- 1 - 2.3.1.3 Mobility Degradation at Interfaces 63

2.3.2 Bandgap Narrowing 65

2.3.3 Shockley-Read-Hall Recombination 66

2.3.3.1 SRH Recombination Doping Dependence 67

Model

3. Modeling Results for Baseline Germanium MOSFETs 72

3.1 Long-Channel Germanium MOSFET 73

3.1.1 Device Structure 73

3.1.2 Device Performance 77

3.1.2.1 Transfer Characteristics 78

3.1.2.2 Subthreshold Characteristics 79

3.1.2.3 Output Current-Voltage Characteristics 80

3.1.2.4 Small Signal Transconductance 83

3.1.2.5 Current Gain and Cutoff Frequency 84

3.1.2.6 Unilateral Power Gain and Maximum 85

Frequency of Oscillation

3.2 Short-Channel Germanium-on-Insulator MOSFET 88

3.2.1 Device Structure 88

3.2.2 Device Performance 91

3.2.2.1 Transfer Characteristics 91

3.2.2.2 Subthreshold Characteristics 92

3.2.2.3 Output Current-Voltage Characteristics 94

- 2 - 3.2.2.4 Small Signal Transconductance 97

3.2.2.5 Current Gain, Cutoff Frequency and 98

Maximum Frequency of Oscillation

3.2.2.6 Investigating Carrier Transport in Simulated 102

GOI MOSFET

4. Variations in Device Design and Effects on Device Performance 107

for Germanium-on-Insulator MOSFET

4.1 Effects of Variation in Gate Dielectric Material 109

4.2 Effects of Variation in Gate Oxide Thickness 120

4.3 Effects of Variation in Channel Doping 127

4.4 Effects of Variation in Channel Length 133

4.5 Summary and Conclusions 139

5. Conclusion and Future Work 143

5.1 Conclusion 143

5.2 Future Work 146

- 3 - LIST OF FIGURES

Figure 1.1 A plot of Moore’s Law (the number of components per chip as a function

of time) as originally predicted in 1965, as well as his alteration to the

slope (1975) due to the limit on the density, taking effect around 1980.

Figure 1.2 Illustration of the principles of constant electric field scaling for

MOSFETs.

Figure 1.3 (a) Measured IS-VD output characteristics of Ge PFET. (b) Measured IS-

VD subthreshold characteristics at low drain biases for Ge PFET. (c)

Transconductance characteristics of Ge PFET and Si control PFET. (d)

Effective mobility extracted from Ge PFET, Si control PFET, and the

universal Si hole mobility.

Figure 1.4 (a) Measured IS-VD output characteristics of n-channel Ge MOSFET

activated at 500 °C. (b) Linear transfer characteristics of Ge MOSFETs

activated at 500 °C and 400 °C. (c) Subthreshold characteristics of Ge

MOSFETs activated at 500 °C and 400 °C.

Figure 1.5 (a) Measured ID-VG characteristics of Ge n-MOSFET. (b) Extracted

effective electron mobility as a function of effective electric field for bulk

Ge with different surface treatment and HfO2 deposition compared to that

for Si control n-MOSFETs.

- 4 - Figure 1.6 (a) Measured ID-VD output characteristics and (b) measured ID-VG output

characteristics for n-channel Ge MOSFETs with laser annealing (LA) and

rapid thermal annealing (RTA).

Figure 1.7 Extracted effective electron mobility versus effective electric field for Ge

n-MOSFETs with LA and RTA and a HfO2/Si control device.

Figure 1.8 (a) Electron drift velocity versus electric field in undoped Ge at 77 K, 190

K, and 300 K. (b) Calculated electron effective mobility versus inversion

charge, (c) Electron velocity along the channel, and (d) ID-VD output

characteristics for control-SOI, strained-SOI, and GeOI n-MOSFET.

Figure 1.9 Carrier drift velocity as a function of electric field for Si, Ge, and GaAs.

Figure 1.10 Cross-sectional schematic diagram and a list of parameters for simulated

GOI n-MOSFETs.

Figure 1.11 (a) The intrinsic performance CgVg/Ion as a function of Ioff for n- and p-

GOI MOSFETs at Vds = 1 V. (b) The ratio of pMOS and nMOS intrinsic

delay as a function of the channel length.

Figure 1.12 (a) Simulated and experimental effective electron mobility versus the

effective electric field for Si and Ge. (b) Comparison of the drive current

of GOI and SOI devices with various gate lengths. (c) Relationship

between off-state leakage current and drive current of GOI and SOI

devices. (d) Intrinsic delay (CV/I) versus gate length of GOI and SOI with

body thicknesses.

Figure 1.13 (a) Comparison of simulated results with experimental data of the carrier

drift velocity versus the effective electric field in Ge. (b) Effective

- 5 - electron mobility as a function of the surface roughness factor L for Ge

and Si at different electric field strengths. (c) Electron mobility versus

electric field curves for both, their simulation results and proposed model,

as well as a comparison to the Si electron universal mobility curve.

Figure 1.14 International Technology Roadmap for Semiconductors (ITRS) prediction

for the future of SOI technology beyond the 90 nm node.

Figure 3.1 A cross-section schematic diagram of the long-channel Ge MOSFET used

for this simulation study.

Figure 3.2 Dopant profile results obtained from DIOS simulation, based on implant

information from Shang et. al.

Figure 3.3 (a) Magnified image of the channel region of the MOSFET showing the

device mesh. (b) Magnified image of the MOSFET at the end of the

source and beginning of the channel.

Figure 3.4 Transfer characteristics of the Ge MOSFET, compared to the Si device, at

VD = 0.5 V. A VT of 1.49 and 1.25 V was extracted for the Ge and Si

devices, respectively.

Figure 3.5 Subthreshold characteristics of Ge MOSFET, compared to Si MOSFET, at

VD = 0.5V. Subthreshold slopes of 130 and 82 mV/dec were extracted for

the Ge and Si devices, respectively.

Figure 3.6 Output current-voltage characteristics of Ge MOSFET, compared to Si

MOSFET, at VG3 = VT + 0.0V, VG2 = VT + 0.5V, and VG1 = VT + 1.0V.

- 6 - The Ge MOSFET offers at least a 96% increase in IDsat for all gate biases

over the Si MOSFET.

Figure 3.7 Comparison of simulated ID-VD characteristics and experimental results

reported by Shang and colleagues.

Figure 3.8 Small signal transconductance as a function of gate bias for Ge and Si

MOSFETs. The Ge MOSFET yields a peak transconductance of 44.86 µS

while the Si MOSFET has a peak gm of 22.68 µS.

Figure 3.9 Small signal current gain versus frequency showing a cutoff frequency of

1.92 MHz for the Ge MOSFET and 0.78 MHz for the Si MOSFET.

Figure 3.10 Cutoff frequency as a function of gate bias for the Ge and Si MOSFETs.

The cutoff frequency peaks at 1.92 MHz at VG = 3.92 V for the Ge device

and 0.78 MHz at VG = 3.40 V for the Si device.

Figure 3.11 A plot of Mason’s unilateral gain as a function of frequency for the Ge and

Si MOSFETs showing a maximum frequency of oscillation of 27.3 MHz

and 9.04 MHz for the Ge and Si MOSFETs, respectively.

Figure 3.12 Maximum frequency of oscillation as a function of gate bias for the Ge

and Si MOSFETs. fmax peaks at 27.3 MHz at VG = 3.17 V for the Ge

device and 9.04 MHz at VG = 2.51 V for the Si device.

Figure 3.13 A cross-section schematic diagram of the baseline short-channel GOI

MOSFET used for this simulation study [8].

Figure 3.14 (a) Magnified image of the active layer of the MOSFET showing the

device mesh. (b) Magnified image of the MOSFET at the end of the

source and beginning of channel.

- 7 - Figure 3.15 Transfer characteristics of the GOI MOSFET, compared to the SOI

device, at VD = 1.0 V. A VT of 0.45 V was extracted for both devices.

Figure 3.16 (a) Subthreshold characteristics of GOI MOSFET, compared to SOI

MOSFET, at VD = 1.0V. Subthreshold slopes of 105 and 98 mV/dec were

extracted for the GOI and SOI devices, respectively. (b) Magnified view

of subthreshold characteristics at high gate bias illustrating the higher

output drain current for the SOI device.

Figure 3.17 Output current-voltage characteristics of GOI MOSFET, compared to SOI

MOSFET, at VG3 = VT + 0.1V, VG2 = VT + 0.5V, and VG1 = VT + 1.0V.

Figure 3.18 Comparison of simulated ID-VD characteristics and experimental results

reported by Barraud and colleagues for (a) GOI MOSFET and (b) SOI

MOSFET.

Figure 3.19 Small signal transconductance as a function of gate bias for GOI and SOI

MOSFETs. The GOI MOSFET yields a peak transconductance of 1602

µS/ µm while the SOI MOSFET has a peak gm of 1887 µS/ µm.

Figure 3.20 (a) Simulated small signal current gain versus frequency showing a cutoff

frequency of 252.6 GHz for the GOI MOSFET and 317.0 GHz for the SOI

MOSFET. (b) Magnified image of where the current gain drops to unity.

Figure 3.21 Cutoff frequency as a function of gate bias for the GOI and SOI

MOSFETs for VDS = 1.0 V. The cutoff frequency peaks at 252.6 GHz at

VG = 0.61 V for the GOI device and 317.0 GHz at VG = 0.67 V for the

SOI device.

- 8 - Figure 3.22 A plot of maximum frequency of oscillation as a function of gate voltage

for the GOI and SOI MOSFETs showing a fmax of 973.7 GHz and 980.4

GHz for the GOI and SOI MOSFETs, respectively.

Figure 3.23 (a) Longitudinal electric field along the channel, directly below the gate,

of the GOI MOSFET. (b) Electron velocity along the channel of the GOI

and SOI devices.

Figure 4.1 The threshold voltage of the MOSFET as a function of the dielectric

constant of the gate insulator.

Figure 4.2 The ID–VG characteristics of the MOSFETs with all of the different gate

dielectric materials on (a) a linear scale, and (b) a logarithmic scale.

Figure 4.3 Subthreshold slope of the MOSFET versus dielectric constant of the gate

insulator. An improvement of over 16% in the subthreshold slope is seen

between the SiO2 device (κ = 3.9) and the HfO2 device (κ = 23).

Figure 4.4 Drain induced barrier lowering of the MOSFET versus dielectric constant

of the gate insulator. An improvement of approximately 43% in the DIBL

is seen between the SiO2 device (κ = 3.9) and the HfO2 device (κ = 23).

Figure 4.5 Peak small signal transconductance of the MOSFET versus dielectric

constant of the gate insulator. An increase of nearly 300% in the peak gm

is seen between the SiO2 device (κ = 3.9) and the HfO2 device (κ = 23).

Figure 4.6 Peak cutoff frequency of the MOSFET versus dielectric constant of the

gate insulator. A decrease of over 20% in the peak fT is seen from the

SiO2 device (κ = 3.9) to the ZrO2 device (κ = 16).

- 9 - Figure 4.7 Threshold voltage of the MOSFET versus the thickness of the gate

insulator layer showing an ~23% reduction in VT between the MOSFETs

with tox = 0.8 nm and tox = 2 nm.

Figure 4.8 The ID–VG characteristics of the MOSFETs with all of the different gate

thicknesses on (a) a linear scale, and (b) a logarithmic scale.

Figure 4.9 Subthreshold slope of the MOSFET versus the thickness of the gate

insulator layer showing an approximately linear increase in S with

increasing tox.

Figure 4.10 Drain induced barrier lowering of the MOSFET versus the thickness of the

gate insulator layer showing an approximately linear increase in DIBL

with increasing tox.

Figure 4.11 Peak small signal transconductance of the MOSFET as a function of the

thickness of the gate insulator layer showing an ~52% reduction in gm

between the MOSFETs with tox = 0.8 nm and tox = 2 nm.

Figure 4.12 Peak cutoff frequency of the MOSFET as a function of the thickness of

the gate insulator layer showing an ~8% increase in fT between from the

baseline MOSFET to the MOSFET tox = 2 nm.

Figure 4.13 Threshold voltage of the MOSFET as a function of channel doping. The

VT of the device increases, with increasing Nch , for doping concentrations

above 1016 /cm3.

Figure 4.14 Subthreshold slope of the device, illustrating almost no dependence on the

channel doping.

- 10 - Figure 4.15 Drain induced barrier lowering of the MOSFET versus the impurity

concentration in the channel. The DIBL continuously decreases in the

devices with channel doping higher than 1 x 1016 /cm3.

Figure 4.16 Peak small signal transconductance of the GOI MOSFET as a function of

the channel doping. A decrease in the peak gm of less than 1% is observed

as the channel doping is increased to 5 x 1017 /cm3.

Figure 4.17 Peak cutoff frequency of the MOSFET as a function of channel doping.

17 The peak fT of the device decreases to ~243.1 GHz for Nch = 5 x 10

/cm3.

Figure 4.18 Threshold voltage of the MOSFET as a function of the channel length

showing a decrease in VT with decreasing channel length, more commonly

known as the short channel effect.

Figure 4.19 Subthreshold slope of the MOSFET as function of the channel length.

Reasonable values of S were obtained for channel lengths of 30, 40, and

60 nm, however, below 30 nm the subthreshold slope drastically increased

due to hot electron effects.

Figure 4.20 Drain induced barrier lowering as a function of channel length showing a

drastic increase in DIBL as the channel length is scaled down.

Figure 4.21 Small signal transconductance of the MOSFET as a function of channel

length showing a steady increase with decreasing channel length until

about the 20 nm mark, where the peak gm reaches a maximum of ~1660

µS/µm and then rapidly declines.

- 11 - Figure 4.22 Cutoff frequency of the MOSFET versus the length of the channel,

showing drastic increases in fT as LC decreases.

- 12 - LIST OF TABLES

Table 1.1 Scaling Rules for MOSFET Device Parameters and Circuit Performance

Factors

Table 1.2 Carrier Transport Properties of Silicon and Germanium

Table 1.3 Summary of Recently Published Data for Bulk Ge p-MOSFETs and Bulk

Ge n-MOSFETs

Table 2.1 Dimensions Used in Box Discretization Method

Table 2.2 Definitions of Equation Used in Box Discretization Method

Table 2.3 Arora Doping Dependent Mobility Model: Default Parameters for Silicon,

Germanium, and the Edited Parameters for Ge

Table 2.4 Canali Model Parameters for Silicon and Germanium

Table 2.5 Velocity Saturation Model: Default Parameters for Silicon, Germanium,

and the Edited Parameters for Germanium

Table 2.6 Mobility Degradation at Interfaces Model Proposed by Xia et. al.:

Parameters for Silicon and Germanium

Table 2.7 Bandgap Narrowing (Slotboom and de Graaff Model): Default

Parameters for Silicon and Germanium

Table 2.8 Shockley-Read-Hall Recombination Parameters for Silicon and

Germanium

- 13 - Table 2.9 Review of Material Parameters for All Physical Models Used in

Simulations

Table 4.1 Structural Parameters of the Baseline GOI MOSFET

Table 4.2 Gate Insulators and Their Dielectric Constants

- 14 - CHAPTER 1

INTRODUCTION

The idea of the MOSFET, or metal-oxide-semiconductor field-effect-transistor, was first introduced in 1928 in a patent filed by Julius Edgar Lilienfeld [1]. Lilienfeld suggested copper sulfide as the semiconductor layer for his MOSFET. However, like most semiconductors, surface passivation in copper sulfide can be problematic. A high density of interface state can result from insufficient surface passivation, thus leading to a low-performance device, or even device failure [2]. This problem delayed the realization of a functional MOSFET for more than thirty years. A breakthrough occurred in 1958 when Atalla and colleagues discovered silicon dioxide (SiO2) [3], thus, achieving surface passivation for the silicon semiconductor system [2]. And two years later at the Solid

State Device Research Conference in Pittsburgh, Kahng and Atalla successfully demonstrated the first modern silicon MOSFET [4]. Another major breakthrough in

MOSFET technology occurred in 1963 with the discovery of the CMOS (complimentary

MOS) circuit, consisting of both n-channel and p-channel devices fabricated on a single semiconductor substrate. These circuits were capable of extremely low standby power density and high switching power density, thus leading to the construction of CMOS logic circuitry with significantly high packing density [5].

Despite the progress made in MOSFET technology, BJTs (bipolar junction transistors) remained the dominant transistor technology of the 1960’s and 70’s due to

- 15 - their performance benefits over MOSFETs. The emergence of MOSFET technology is a

result of the growth of the computer industry, more specifically, of the development of

the integrated circuit. Integrated circuit designers realized that MOSFETs offered two main advantages over BJTs. These being that MOS technology, when compare to bipolar technology, required a fewer number of processing steps, resulting in reduced costs and larger fabrication yields, and, unlike BJTs, MOSFETs could be scaled down without comprising device performance. In fact, scaling MOSFET dimensions reduces power dissipation, improves speed, and allows for more devices per unit area at a lower cost per device [6]. As a result of their compactness and low power dissipation, MOSFETs surpassed BJTs as the dominant transistor technology and have been the most widely used semiconductor device since the early 1980s. Currently, CMOS and MOSFETs control an astonishing 90% of the semiconductor technology market [7].

1.1 MOORE’S LAW

In 1965, just six years after the invention of the integrated circuit [7], Dr. Gordon

Moore, co-founder of both Fairchild Semiconductor and Intel Corporation, published his

now famous paper predicting the future of integrated circuits. Moore observed an

exponential increase over time in the number of transistors per integrated circuit chip.

From only four data points he predicted what is now known as Moore’s Law; which

simply states that the number of transistors on an integrated circuit chip would double

every year and a half. Moore went on to predict that this trend could continue well into

the future [8].

- 16 - In 1975, Moore gave a speech again regarding the future of integrated circuits and addressing a minor change to his original prediction. He believed that the CCD structure would approach the maximum density practical around 1980, thus limiting the increase in the number of transistors per chip over time. As a result of this limit, the number of transistors per integrated circuit chip would double nearly every two years, as opposed to every year and a half, as he had originally believed [9]. Figure 1 is a plot of Moore’s

Law from his speech in 1975, showing the number of components per chip as a function of time. It shows his original prediction, as well as the alteration he made to his original prediction, taking place around 1980.

Figure 1.1 A plot of Moore’s Law (the number of components per chip as a function of time) as originally predicted in 1965, as well as his alteration to the slope (1975) due to the limit on the density, taking effect around 1980 [9].

Moore’s Law has been used for several decades as the gauge by which device development and scaling is measured, and remarkably, it still holds true today. However,

- 17 - conventional scaling will soon reach its limit and new innovative techniques will be needed to continue Moore’s Law. This research study will investigate material changes, namely germanium (Ge) for silicon (Si), that can be made to MOSFETs in order to enhance device performance and allow continued following of Moore’s Law.

1.2 MOSFET SCALING THEORIES AND LIMITATIONS

In coherence with Moore’s Law, MOSFETs have undergone several decades of aggressive scaling in order to achieve speed, power, and density improvements [10].

This section will present a brief overview of some of the conventional MOSFET scaling theories that were used to achieve this. Following that will be a discussion outlining the crucial limitations of these conventional scaling methods, thus, showing the need for new non-conventional techniques for continued device improvement.

1.2.1 SCALING THEORIES

Figure 1.2 Illustration of the principles of constant electric-field scaling for MOSFETs [11].

- 18 - Figure 1.2 illustrates the basic idea behind scaling, this being that a large device is scaled down in size by reducing all of its dimensions by a common factor α, or κ, to produce a smaller device with similar behavior [11]. Constant field scaling, the most fundamental MOSFET scaling theory, is based on the idea that the MOSFET works on the concept of modifying the electric field in the channel region of the device, in a manner that allows the flow of current between the source and drain electrodes to be controlled. Constant field scaling allows the smaller, scaled device to achieve the same electric-field patterns as the larger device if the applied voltage, as well as all of the key dimensions in the device, including the gate oxide layer, are reduced accordingly.

However, the impurity doping concentrations of the smaller device must be increased to ensure preservation of the electric field patterns within the device [11]. A more thorough list of rules for constant field scaling is shown below in Table 1.1.

Table 1.1 Scaling Rules for MOSFET Device Parameters and Circuit Performance Factors [10].

- 19 - The three most crucial results of constant field scaling are: the circuit density

improves by a factor α2; the speed of the device improves by a factor α; and the power

dissipation per circuit is reduced by a factor α2 [11]. Although, constant field scaling provides a good, initial understanding of the concepts and methods behind scaling

MOSFETs, it is unrealistic to reduce the applied voltage and physical dimensions of the device by the same factor due to an unwillingness to abandon standardized voltage levels

[11]. The power-supply voltage is rarely scaled in proportion to channel length due to circuit compatibility issues. As a result, the oxide field has been increasing in intensity over successive generations of MOSFETs, as opposed to remaining constant. Hence, a new set of generalized rules is needed that would allow for the electric field to increase, yet ensure adequately performing devices. This type of scaling, called generalized scaling [10], requires that the vertical and lateral electric fields change by the same factor, ensuring that the shape of the electric field pattern remain undisturbed. To accomplish this, it is assumed that the electric field intensity changes by a factor κ while the device physical dimensions scale down by a factor α. The applied voltage will then change by the ratio κ/α and the doping concentration must be scaled up in the smaller device by a factor κα. In generalized scaling the carrier velocity in the scaled device tends to be larger than that of the original device as a result of the increase in electric field intensity.

Other benefits of generalized scaling include: a reduction in circuit delay time by a factor between α and κα; an increase in circuit density by a factor α2; and an increase in device speed by a factor κ [10].

- 20 - 1.2.2 SCALING COMPLICATIONS AND LIMITATIONS

As described above, the electric fields inside the MOSFET have been increasing

from one technology generation to the next as a result of the power-supply voltage not

being scaled in proportion with device dimensions [10]. The increasing electric fields

within the device can lead to several problems, commonly known as hot electron effects

and short channel effects [12].

An electron becomes a “hot” electron when it travels from the source to the drain

through the channel and gains kinetic energy at the expense of electrostatic potential

energy in the pinch-off region. An electron at the conduction band edge possesses only

potential energy; as it gains kinetic energy, it will move higher up in the conduction band.

If an electron becomes energetic enough, it can surmount the potential barrier between

the Si channel and the gate oxide. A portion of these hot electrons can pass through the

gate oxide and be collected as gate current resulting in a reduction of the input

impedance. Even worse, some of the electrons can become trapped in the gate oxide

thereby increasing the flatband voltage, and ultimately the threshold voltage. Hot

electrons can also rupture bonds at the Si-SiO2 interface creating interface states, causing stress which could degrade certain device parameters, such as the transconductance and subthreshold slope [12]

A problem known as the short channel effect also occurs during the scaling of

MOSFETs. The short channel effect refers to the relationship between the channel length and threshold voltage of a device. Simply put, as the channel length of a MOSFET is scaled down, the threshold voltage of the device also decreases. This occurs as a result of charge sharing between the source/drain and gate [12]. This effect becomes more

- 21 - pronounced at high drain biases. In the fabrication of short-channel MOSFETs, due to process variability there exists statistical variance in channel length from device to device, chip to chip, wafer to wafer, and lot to lot [10]. These variations in channel length can lead to problems regarding threshold voltage control and circuit operation

[12].

Another problem can arise in MOSFETs with small channel lengths if they are not scaled properly. If the source/drain junctions are too deep or the channel doping is too low, inadvertent electrostatic interactions can occur between the source and drain.

This is known as Drain-Induced Barrier Lowering (DIBL), and can lead to increased

(punch-through) drain current leakage when the gate partially loses control of the channel and high drain current persists nearly independent of gate voltage [10]. In the worst case, it can also lead to breakdown between the source and drain [12].

Reduction of the physical dimensions of a MOSFET is ultimately limited by quantum mechanical tunneling currents due to carriers that are able to pass through various, thin barriers in the device, damaging the device’s behavior. One of the most constraining limits to scaling is tunneling current through the gate oxide layer. Due to this phenomenon, the minimum silicon dioxide gate insulator thickness is in the range of

1.0 to 1.5 nm (nanometers) for high-performance applications [13]. This limit is rapidly approaching as there are devices already in production that possess a gate oxide thickness in that range [14]. Small MOSFETs can also experience body-to-drain junction tunneling currents, as well as direct subthreshold source-to-drain tunneling through the potential barrier below the gate [13]. As physical dimensions continue to decrease, the tunneling,

- 22 - or leakage currents in the device will continue to increase, resulting in increased power

dissipation and degradation in overall device performance.

There are numerous challenges, complications, and limitations involved in scaling

Si MOSFETs. Some of these limits are currently being approached. Intel’s current

silicon technology, the 65-nm Process Technology, is reporting devices with gate lengths

of 35 nm and gate insulator thickness of 1.2 nm [14]. In devices with gate lengths that

short it becomes quite difficult to minimize small channel effects. In addition, the gate

oxide thickness of 1.2 nm is very near the minimum limit of SiO2 required to reduce gate leakage enough to maintain a functional transistor. As previously mentioned, scaling is

not only driven by an enhancement in device performance, but also by the reduction in

unit cost per device that comes with making transistors smaller. Therefore, it is of critical

importance to continue downscaling devices, not only to improve the device, but for the

economic well-being of the electronics industry [15].

1.3 SILICON-ON-INSULATOR TECHNOLOGY

A relatively new technology already impacting the electronics industry is silicon-

on-insulator (SOI) technology. SOI CMOS technology involves building a conventional

MOSFET device on a very thin layer of crystalline silicon. This thin layer of silicon is

separated from the parent substrate by a thick layer of buried SiO2, leaving the devices electrically isolated from the underlying substrate and from each other [10]. The fabrication process of SOI devices, however, can be challenging. This is because it is difficult to produce a thin film of high quality single-crystal silicon sitting on top of an amorphous silicon dioxide layer with no mechanical stress or electrically active defects.

- 23 - However, recent progress in material growth techniques have not only made SOI devices and integrated circuits possible, they have become a commercial success [16].

Below is a list of some of the advantages of SOI MOSFETs over conventional silicon MOSFETs:

• Typically, SOI MOSFETs have significantly low junction capacitances due to the

near elimination of the source and drain junction capacitances, and because the

capacitance through the buried oxide layer to the substrate is minimal [10].

• Due to their full dielectric isolation, SOI devices prevent most of the parasitic

effects that are experienced in conventional Si devices [16].

• SOI CMOS technology involves fewer processing steps than bulk CMOS

technology [16]. Also, SOI CMOS technology is completely compatible with

established CMOS processing technology [10].

• Because their body potential is not tied to ground (it can rise to the same potential

as the source), the threshold voltage of stacked SOI MOSFETs is not degraded by

the body effect [10]

• Long-channel fully depleted (FD) SOI MOSFETs have a steep subthreshold slope

permitting a lower Vt, for the same off current, thus allowing the devices to be

used at a lower supply voltage, making them suitable for low-power applications

[10].

• SOI devices improve the soft-error rate (reduced upset of the stored logic state

due to the collected charge of a junction node, from ionizing radiation that strikes

through the silicon, exceeding a certain threshold), as a result of the presence of

- 24 - the buried oxide significantly reducing the volume susceptible to ionizing

radiation [10].

SOI devices do, however, have a few problems associated with them, these being:

• Short-channel FD SOI MOSFETs are vulnerable to source-drain field penetration

leading to poor short-channel effects. This is a result of the thick buried oxide

layer acting like a wide gate depletion region [10].

• Partially depleted (PD) SOI devices suffer from a phenomenon referred to as

drain current overshoot. In fast gate ramps, the body potential tends to rise with

gate potential, resulting in a reduction the threshold voltage and an increase in the

transient current [10].

• PD SOI MOSFETs generally have a higher off current due to a forward-biased

body-to-source junction at high drain currents [10].

Although the advantages of SOI devices, over conventional Si devices, significantly outweigh the setbacks, it wasn’t until recently that SOI devices were used commercially. Due to advances in material growth, SOI devices are now used for many applications, such as, micro electro-mechanical systems (MEMS), integrated optics, sensors, and their most widely used application, CMOS integrated circuitry [16].

However, like conventional Si MOSFETs, SOI devices are also subject to short-channel effects and the various other limitations of scaling. Therefore, the need for new technology remains.

- 25 - 1.4 INNOVATIVE NEW MOSFET DESIGNS

The International Technology Roadmap for Semiconductors (ITRS) has projected

MOSFETs with a gate length of 9 nm and microprocessors with a chip size between 140

and 280 mm2 containing more than 3 billion transistors by the year 2016 [17]. However, the technology required to reach this prediction is currently unavailable. Therefore, the

MOSFET will require many changes and innovations in order for the ITRS prediction to become a reality. At the present time, the most likely of these changes are: to replace Si with a new material in the channel region to increase the mobility and improve the device’s performance; to replace SiO2 with a material with a higher dielectric constant to

reduce the gate leakage current; to replace polysilicon gates with metal gates to reduce

the gate resistance and improve channel control; and to use more than one gate for better

control of MOSFETs on and off states and to reduce power consumption [18]. In the past

few years these changes, concerning both structural changes and material changes made

to MOSFETs, have been extensively researched. According to the ITRS, the most

promising new technologies utilizing structural technologies to MOSFETs are: ultra-thin

body SOI (silicon-on-insultor) FETs; source/drain engineered FETs; and multiple-gate

FETs [17]. These devices have been reported at length elsewhere, and therefore, will not

be discussed here.

The other possible direction for the future of FET technology is the use of new

materials in the fabrication and design of MOSFETs. The new material changes

demonstrating the most promise for device improvement are; high-κ dielectric and

electrode materials used in the gate stack, materials with improved carrier transport

properties for the conduction channel, and materials with reduced resistance and carrier

- 26 - injection properties used in the source/drain regions of the device [17]. Hence forth, the

issue of primary focus for this paper will be that of transport-enhanced FETs. More

specifically, we will be exploring the performance benefits of Ge-based MOSFETs over

traditional Si MOSFETs.

1.5 ADVANTAGES OF GE-BASED MOSFETS

The basic concept behind transport-enhanced FETs is that enhancing the average

velocity of carriers in the channel region of a MOSFET improves the transistor drive

current thus improving circuit performance. One way to enhance transport is to employ

new channel materials, such as Ge, that possess electron and hole mobilities and carrier

velocities higher than those in silicon [17]. As Table 1.2 illustrates, germanium clearly

has an advantage over silicon with respect to these material properties, making it an attractive alternative to Si for the channel region of MOSFETs. Table 1.2 shows that Ge

has nearly three times the electron mobility of Si, over four times the hole mobility of Si,

and also possesses higher carrier thermal velocities, but comparable though slightly

smaller saturation velocities. Since the MOSFET’s transconductance scales with the

carrier mobility, higher performance devices are expected for both n- and p-channel Ge

MOSFETs.

- 27 - Table 1.2 Carrier Transport Properties of Silicon and Germanium [19][20].

Material Property Silicon Germanium Reference

electron mobility (cm2/V-s) 1750 3800 [19]

hole mobility (cm2/V-s) 450 1820 [19]

electron thermal velocity (cm/s) 2.30 x 107 3.10 x 107 [20]

hole thermal velocity (cm/s) 1.65 x 107 1.90 x 107 [20] electron saturation velocity (cm/s) 1.02 x 107 7.00 x 106 [19]

hole saturation velocity (cm/s) 7.20 x 106 6.30 x 106 [19]

A further improvement in transistor drive current is also anticipated when the Si substrate of a MOSFET is replaced with Ge. This benefit stems from the fact that Ge offers a lower effective mass and lower valley degeneracy than Si, which may provide a higher source injection velocity, leading to a higher drive current and smaller gate delay

[21], thus further improving device performance.

Using germanium, rather than silicon, for MOSFETs provides another advantage due to germanium’s smaller bandgap; it is more compliant with the supply voltage scaling specified by the ITRS [17]. At the same time, Ge’s smaller bandgap also broadens the optical absorption spectrum to cover the dominant telecommunication wavelengths (1.3 µm and 1.55µm) allowing optoelectronic device integration to enhance the functionality of CMOS technology [22].

There is, however, a complication that presents itself in the fabrication of Ge

MOSFETs. The problem with devices built with Ge is that the germanium native oxide

- 28 - (the analog to SiO2) is hygroscopic, that is, readily absorbs water. Moreover, it is

difficult to fabricate useful inversion-mode devices with deposited dielectrics due to large

interface-state densities [23]. Presently, the most effective dielectric material used on Ge

is germanium oxynitride (GeOxNy). It offers improved thermal and chemical stability over the Ge native oxides (GeO and GeO2) and is currently the best known solution to

stabilize Ge surfaces [24]. Other materials (possessing high dielectric constants), such as

ZrO2 [25], HfO2 [26], and HfAlO [27] have also been used in the fabrication of Ge

MOSFETs.

Due to the performance enhancements of Ge devices over comparable sized Si devices, as well as the continuing progress toward improving gate dielectrics for Ge MOS applications, Ge-based MOSFETs have received increased attention in recent years. This is especially true recently since Ge-based MOSFETs are believed to be a promising option to replace conventional Si MOSFETs, as outlined in ITRS [17], as these devices near the end of the technology roadmap. The following section will discuss some previous experimental and device modeling work reported on the device characteristics and performance of Ge-based MOSFETs.

1.6 PREVIOUS WORKS REPORTED ON GE-BASED MOSFETS

This section will focus on some the more important reports, both theoretical and

experimental, describing the development and performance of Ge-based MOSFETs. This

section will serve as a means to highlight the importance of our study and distinguish it

from the others.

- 29 - 1.6.1 EXPERIMENTAL REPORTS

P-channel devices have been the most common reported Ge-based MOSFET, so

we describe results presented in one recent report. In 2003, Shang et. al. [28] reported a

Ge p-channel MOSFET using a GeON and LTO (low-temperature oxide) gate stack,

aluminum gate electrode, and boron implanted self-aligned source/drain. The device has

a ring-type gate with inner and outer radii of 100 and 200 µm, respectively, and so a gate

length of 100 µm (micrometers), i.e., a long channel device. This Ge PFET demonstrated

low gate leakage current (< 10-6 A/cm2) and p+/n junction leakage current on the order of

10-4 A/cm2, which is acceptable for device operation. The device’s output characteristics

are shown below in Figure 1.3, including comparisons to similar Si devices.

(a) (b)

- 30 - (c) (d)

Figure 1.3 (a) Measured IS-VD output characteristics. (b) Measured IS-VG subthreshold characteristics at low drain biases. (c) Transconductance characteristics of the Ge PFET (solid symbol) and the Si control PFET (open symbol). (d) Effective mobility extracted from Ge PFET (solid symbol) and a Si control PFET (open symbol), as well as the universal Si hole mobility (solid line) [28].

The transistor shows good output characteristics in the linear and saturation regions as seen in Figure 1.3 (a). Figure 1.3 (b) shows the Ge device also exhibits good subthreshold characteristics, with a subthreshold swing of 82 mV/dec making it suitable for low-voltage applications. Figure 1.3 (c) shows the Ge device offers more than 2 times the transconductance, and an approximate 40% enhancement of the effective hole mobility over the comparable Si device is shown in Figure 1.3 (d). Together these results show that Ge MOSFETs may be an attractive candidate for future high-performance logic applications [28].

While p-channel Ge MOSFETs have been the most widely reported experimental devices, the focus of this study is n-channel devices, so we will concentrate on these devices. N-channel Ge MOSFETs are reported less often than p-channel devices because they pose a serious challenge during fabrication that frequently leads to poor performing devices. This challenge is that there is a relatively small process window to achieve both

- 31 - a stable gate dielectric stack and a well-activated n+ source/drain. Shang et. al. [29]

demonstrated, for the first time, a self-aligned n-channel Ge MOSFET with fully

activated source/drain, minimized off-state leakage and achieving an on/off current ratio

of ~104. The fabricated devices had a ring-type gate with a channel length of 100 µm.

They used a GeON and LTO (low-temperature oxide) gate stack with a total equivalent gate oxide thickness of ~8 nm, phosphorous implants to form self-aligned source/drain regions (fully activated with a 500°C anneal), and a tungsten gate electrode. Figure 1.4

shows the IS-VD characteristics (a), the linear region transfer characteristics (b), and the subthreshold characteristics (c) for the Ge MOSFETs.

(a) (b)

- 32 - (c)

Figure 1.4 (a) Measured IS-VD output characteristics at gate bias from 1.0 to 3.5 V in 0.5 V steps for devices activated at 500°C. (b) Linear transfer characteristics of devices activated at 500°C compared to devices activated at 400°C showing that the Vt is shifted about 1.0 V for devices annealed at 500°C. (c) Subthreshold characteristics of devices activated at 500°C compared to devices activated at 400°C [29].

The transistor shows good saturation and turn-on characteristics as seen in Figure

1.4 (a) and (b), respectively. As illustrated in Figure 1.4 (c), devices activated at 500°C possess an on-off drain current ratio of ~104 due to minimized off-state current as a result of the improved junction anneal, as well as a reasonably good subthreshold swing of

~150 mV/dec (the optimum subthreshold swing is ~60 mV/dec at room temperature).

2 Although the extracted electron mobility was lower than expected (µeff~100 cm /V-s at

2 Eeff=0.25 MV/cm versus ~120 cm /V-s for silicon) the improved understanding of dopant activation and diffusion in Ge is expected to enable the optimization of Ge MOSFETs as a potential alternative to high performance Si CMOS [29].

W. P. Bai and colleagues [30] recently reported the successful fabrication of Ge n-MOSFETs on lightly doped substrates (≤1x1015 cm-3). This device used a 5 nm film of

HfO2 as the gate dielectric and a 1500 Ǻ (angstrom) film of TaN for the gate electrode,

though no value was given for the channel length. Si control devices were also fabricated

- 33 - for comparison purposes. The results are shown in Figure 1.5. The Ge n-MOSFET

yielded an off-current approximately two orders lower than the on-current, for an on-off

ration of ~100, and an extremely low leakage current (0.64 mA/cm2 at -2 V). Figure 1.5

(a) shows the measured drain current and transconductance as a function of the gate voltage. Note that at Vt=0.04 V the peak gm is ~1.2 µS/µm. Figure 1.5 (b) shows a plot of the effective electron mobility as a function of the effective electric field. The Ge n-

MOSFET demonstrated a 2.5 times enhancement of peak effective mobility as compared to Si control devices [30]. This dramatically higher electron mobility (2.5x) is close to that (2.8x) expected using the known bulk mobilities as given in Table 1.2. Since the transistor’s gain (transconductance) and speed scale up with increased electron mobility, these are encouraging results. These results are the most recent (2006) and the best results reported to date for n-channel Ge MOSFETs.

(a) (b)

Figure 1.5 (a) Measured ID-VG characteristics of Ge n-MOSFET. (b) Extracted effective electron mobility as a function of effective electrical field for bulk Ge with different surface treatment and HfO2 deposition compared to that for Si control n-MOSFETs [30].

- 34 - Table 1.3 summarizes the recent published data from a number of groups for Ge

n-MOSFETs and p-MOSFETs, respectively. It includes fabrication details (substrate

doping, surface treatment, gate dielectric, gate electrode, and effective oxide thickness)

and results (saturation current and peak mobility) on various devices from numerous

recent publications. It illustrates the variety of materials used in fabrication along with

the range of results collected for those devices. It is important to mention that a majority

of these results were measured at a low drain voltage, e.g., VDS ~ 0.1 V. At normal

MOSFET operation, e.g., VDS = 1.0 V or more, velocity saturation can occur in the channel near the drain, therefore, the saturation velocity of the substrate material, in this case germanium, can have a serious impact on device performance.

Table 1.3 Summary of Recently Published Data for Bulk Ge p-MOSFETs and Bulk Ge n-MOSFETs (after Bai et. al. [30]).

[31] [26]

[25]

[32]

[32] [33]

[29] [26]

[34]

[33]

[30]

- 35 -

The most recent results regarding Ge MOSFETs were reported by Zhang et. al

[35] in September 2006. Zhang’s group fabricated n-channel Ge MOSFETs that use a

new laser annealing process for source/drain dopant activation. These long-channel

devices possess a channel length of 20 µm and a HfO2 gate oxide layer with an extracted

equivalent oxide thickness of 1.27 nm. Figure 1.6 (a) shows the measured output

characteristics for n-channel Ge MOSFETs with both RTA (rapid thermal annealing) and

LA (laser annealing) activation. The device with LA offers better Id-Vd characteristics

while exhibiting a larger saturation current than the RTA device (1.64 µA/µm at Vg-

Vt=0.5 V versus 1.47 µA/µm for the RTA device). Figure 1.6 (b) shows the extracted

transfer characteristics of the device with LA, showing a Vt of 0.54 V, approximately

0.20 V lower than the device with RTA (also shown in Figure 1.6 (b)).

(a) (b)

Figure 1.6 (a) Measured Id-Vd output characteristics at gate bias from 0.0 to 0.5 V in 0.1 V steps and (b) Id-Vg characteristics of Ge n-MOSFETs with LA and RTA [35].

- 36 -

Figure 1.7 Extracted effective electron mobility versus effective electric field for Ge nMOSFETs with LA and RTA source/drain activation, and a HfO2 Si control device [35].

Figure 1.7 shows the extracted effective electron mobility as a function of the

effective electric field for the laser annealed and the rapid thermal annealed Ge devices, as well as a Si control device. The Ge device with LA activation exhibits a higher electron mobility at high electric fields when compared to the Ge device with RTA activation. The Ge MOSFET with LA activation also shows an approximate 75 % increase in peak electron mobility over the Si control device [35].

1.6.2 TRANSISTOR MODELING REPORTS

There have been only a few reports of device simulation studies of these Ge

MOSFETs. S. Barraud et. al. [36] performed a simulation study in 2005 using the

Monte-Carlo simulator MONACO investigating the electron transport properties of SOI,

strained-SOI (S-SOI), and germanium-on-insulator (GeOI) n-MOSFETs. All three

20 -3 16 -3 devices possess the same doping (ND=10 cm in source/drain and NA=10 cm in channel) and geometry; a 100 nm layer of semiconductor material (the parent substrate),

- 37 - followed by a 400 nm layer of insulator (SiO2), then a 15 nm layer semiconductor film

(the active region of the device), and a 1 nm gate insulator layer. The effective channel length in all three devices is 40 nm.

(a) (b)

(c) (d)

Figure 1.8 (a) Electron drift velocity versus electric field in undoped Ge at 77 K, 190 K, and 300 K. The continuous lines indicate theoretical results [36], while the closed circles represent experimental data from Nguyen et. al. [37]. (b) Calculated electron effective mobility versus inversion charge for control-SOI (□), strained-SOI (○), and GeOI n-MOSFET (∆) [36]. Also shown are experimental results for the control-SOI MOSFET (●) from Khakifirooz et. al. [38]. (c) Electron velocity along the channel for all three devices, where the bias conditions are VGS-VT=VDS=1 V [36]. (d) ID-VD characteristics with gate biases VGS1=VT+1.0V, VGS2=VT+0.5V, and VGS3=VT+0.1V [36].

- 38 -

Figure 1.8 (a) shows the theoretical results [36], as compared to experimental results [37], for the electron drift velocity as a function of the electric field in undoped Ge at 77 K, 190 K, and 300 K. Note that at room temperature (300 K) the electron drift velocity in Ge saturates at ~7 x 106 cm/sec, as seen in Table 1.2. Figures 1.8 (b) and (c) show the transport properties of the SOI, strained SOI, and GeOI MOSFETs. As these results show, the GeOI device offers ~2 times the effective electron mobility, as well as a significant increase (~20 %) in the peak electron velocity in the channel. Figure 1.8 (d) shows the ID-VD characteristics of all three devices also illustrating a significant increase

(~ 55 % at VGS1=VT+1.0V) in the saturation of the drain current of the GOI device over the SOI device [36]. These results showcase the considerable performance benefits that

GOI MOSFETs exhibit compared to SOI MOSFETs, thus reinforcing promise as a future replacement for SOI devices.

It was mentioned previously that in bulk Ge, the velocity saturates at a lower field with a lower saturation velocity compared to bulk Si [19]. Since we are focusing on n- channel devices, the electron velocity-field characteristics are of greater interest than the hole velocity-field characteristics. As you can see in Figures 1.8 and 1.9 [36,39], the electron velocity of Ge saturates at ~7 x 106 cm/sec, compared to ~1 x 107 cm/sec for Si.

- 39 -

Figure 1.9 Carrier drift velocity as a function of the electric field for Si, Ge, and GaAs [39].

Since the electric field strength along the channel is large near the drain, saturation in the electron velocity in the Ge MOSFET is possible during normal device operation. The MOSFET’s performance thus depends on the combination of the electron’s mobility in the low channel electric field at the source end of the channel and velocity saturation effects at high electric field near the drain end. Therefore, the scaling behavior of Ge MOSFETs with gate lengths in the nanoscale is very important. The scaling properties of both n- and p-channel GOI MOSFETs with channel lengths ranging from 20 nm to 130 nm were examined using device modeling by Du et. al. [40]. Figure

1.10 shows a schematic structure of a GOI n-MOSFET along with the device structure parameters of the devices modeled.

- 40 -

Figure 1.10 A cross-sectional schematic diagram and a list of parameters of the GOI n-MOSFETs 19 -3 used to perform the simulations. Note that NS/D=2 x 10 cm [40].

(a) (b)

Figure 1.11 (a) The intrinsic performance CgVg/Ion as a function of Ioff for n- and p-GOI MOSFETs at Vds=1 V. (b) The ratio of pMOS and nMOS intrinsic delay as a function of the channel length [40].

Figure 1.11 (a) shows the intrinsic performance CgVg/Ion versus Ioff for n- and p- channel devices with various channel lengths while (b) shows the ratio of intrinsic delay of both types of devices, theoretically calculated as a function of the channel length.

These results indicate that both n- and p-channel GOI MOSFETs have favorable scaling

properties in the nanoscale, mainly due to the non-stationary transport near the source side. However, GOI devices can suffer from serious short-channel effects. These can be minimized by reducing the thickness of the active Ge layer [40].

- 41 - An et. al. [41] also examined the scaling capability and device performance of

GOI MOSFETs compared to SOI devices. The MOSFETs modeled were ultra thin-body devices with physical gate lengths of 50, 30, and 20 nm, respectively, and were modeled using DESSIS version 8.0. Results from this report are shown in Figure 1.12.

(a) (b)

(d) (c)

Figure 1.12 (a) Simulated [41] and experimental [39] effective electron mobility versus the effective electric field for Si and Ge. (b) Comparison of the drive current of GOI and SOI devices with various gate lengths [41]. (c) Relationship between off-state leakage current and drive current of GOI and SOI devices [41]. (d) Intrinsic delay (CV/I) versus gate length of GOI and SOI with body thicknesses [41].

- 42 - Figure 1.12 (a) illustrates the consistency of their mobility models versus experimental data for germanium. Figures 1.12 (b) through (d) show results for GOI and

SOI devices for 5 nm and 10 nm body thicknesses with various gate lengths. Figure 1.12

(b) shows a comparison of the drive current for the two devices illustrating a ~30 % higher drive current for the GOI device. The relationship between the off-state leakage current and the drive current is shown Figure 1.12 (c). Figure 1.12 (d) shows that the intrinsic gate delay of GOI devices is comparable with that of SOI as a result of a larger gate capacitance. These results conclude that GOI MOSFETs show substantial scaling capability and are more suitable for high-performance logic and low operating power applications than SOI devices [41].

Another simulation study that is of particular interest was reported by Xia et.al.

[42] in 2005. This study examined the electron and hole mobilities in the inversion layer of Ge MOSFETs. The influence of impurity concentration, substrate bias, and surface roughness on carrier mobilities was considered. Where possible, the results were compared with experimental data to verify their physical models.

- 43 - (a) (b)

(c)

Figure 1.13 (a) Comparison of simulated results [42] with experimental data [39] of the carrier drift velocity versus the effective electric field in Ge. (b) Effective electron mobility as a function of the surface roughness factor L for Ge and Si at different electric field strengths [42]. (c) Electron mobility versus electric field curves for both, their simulation results and proposed model, as well as a comparison to the Si electron universal mobility curve [42].

Figure 1.13 (a) is a plot of the carrier drift velocity versus the effective electric

field for Si and Ge; used as a verification of the physical models used. Figure 1.13 (b)

shows the effective electron mobility in Ge MOSFETs inversion layer, under low and

high effective fields, as a function of the surface roughness. This graph illustrates the

electron mobility’s sensitivity to surface roughness, as well as the substantial increase in

electron mobility from Si to Ge. The effective electron mobility of Ge is plotted against

the effective electric field in Figure 1.13 (c). In this plot, their simulated results were compared to their proposed model for Ge, as well as the Si electron universal mobility

- 44 - (their proposed model for Ge will be described at length in the next chapter). These

results provide an accurate description of the behavior of the carrier mobilities in the

inversion layer of Ge MOSFETs [42].

1.7 CURRENT GE-BASED MOSFET RESEARCH FOCUS

In brief, Ge-based MOSFETs have shown preliminary experimental

improvements, at least for long-channel devices, over their silicon counterparts regarding

device performance. Device modeling results on short-channel devices also show the Ge

MOSFET to be better than it’s Si counterpart, especially at low drain bias. Compared to

Si MOSFETs, Ge MOSFETs yield larger drive current [36], and higher transconductance

[28], due to higher carrier mobility though the carrier saturation velocity is somewhat smaller [19]. At high drain bias, the lower saturation velocity of Ge MOSFETs may limit their performance. In addition, Germanium-on-insulator devices utilize the benefits of two key transistor technologies, i.e., transport-enhanced FETs and SOI technology. GOI devices also have better scalability over planar Ge devices due to the high source/drain

junction leakage concern [40]. Hence, GOI MOSFETs are considered promising as a

potential replacement for conventional planar Si MOSFETs and have been included in

the industry’s projection for the future [43].

- 45 -

Figure 1.14 The ITRS prediction for the future of SOI technology beyond the 90 nm node. Notice that GeOI MOSFETs are predicted to replace SOI MOSFETs around 2013 [43].

However, because Ge has lacked a stable gate dielectric material until recently,

there is a limited amount of published information in reference to the actual, observed

behavior and performance of Ge-based MOSFETs. Our goal for this thesis is to examine

the performance capabilities and scaling behavior of GOI devices to explore how

attractive they are as a candidate to replace conventional Si MOSFETs.

In this thesis, we investigate GOI MOSFET performance capabilities and scaling

behavior using a commercial numerical device simulator from ISE Corporation. Chapter

2 will describe the details of this software, including the device physics modeled, the

basic equations solved, and the provided output results. Also included in this chapter is a

summary of the most important physical properties of germanium used for modeling, and

how they compare to those of silicon. Chapter 3 will describe the physical structure of the baseline GOI MOSFET used, as well as modeling results for this structure. These results will be compared with the results of a similar SOI device in order to illustrate the performance advantages of the Ge device and to examine any limitations. Chapter 4 will

- 46 - provide a detailed simulation study investigating the effects of varying the device structure. In particular, we will examine how changing the gate oxide thickness, gate dielectric, channel length, and channel doping effects the device’s performance in an effort to find a more optimum device structure. Chapter 5 will provide conclusions and some suggestions for future work.

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[25] Chi On Chui, Hyoungsub Kim, David Chi, Baylor B. Triplett, Paul C. McIntyre, and

Krishna C. Saraswat, “A Sub 400°C Germanium MOSFET Technology with High-κ

Dielectric and Metal Gate,” IEDM Technical Digest, pp. 437-440, December 2002.

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Kwong, and D. A. Antoniadis, “Epitaxial Strained Germanium p-MOSFETs with

HfO2 Gate Dielectrics and TaN Gate Electrode,” IEDM Technical Digest , pp. 433–

436, December 2003.

[27] Shiyang Zhu, Rui Li, S. J. Lee, M. F. Li, Anyan Du, Jagar Singh, Chunxiang Zhu,

Albert Chin, and D. L. Kwong, “Germanium pMOSFETs with Schottky-Barrier

Germanide S/D, High-κ Gate Dielectric and Metal Gate,” IEEE Electron Device

Letters, Vol. 26, No. 2, pp. 81-83, February 2005.

[28] H. Shang, H. Okorn-Schmidt, J. Ott, P. Kozlowski, S. Steen, E. C. Jones, H.-S. P.

Wong, and W. Hanesch, “Electrical Characterization of Germanium p-Channel

MOSFETs,” IEEE Electron Device Letters, Vol. 24, No. 4, pp. 242-244, April 2003.

[29] Huiling Shang, Kam-Leung Lee, P. Kozlowski, C. D’Emic, I Babich, E Sikorski,

Meikei Ieong, H.-S. P. Wong, Kathryn Guarini, and W. Haensch, “Self-Aligned n-

Channel Germanium MOSFETs With a Thin Ge Oxynitride Gate Dielectric and

Tungsten Gate,” IEEE Electron Device Letters, Vol. 25, No. 3, pp. 135-137, March

2004.

[30] W.P. Bai, N. Lu, A. Ritenour, M. L. Lee, D. A. Antoniadis, and D.-L. Kwong, “Ge

n-MOSFETs on Lightly Doped Substrates With High-κ Dielectric and TaN Gate,”

IEEE Electron Device Letters, Vol. 27, No. 3, pp. 175-178, March 2006.

[31] Huiling Shang, Harald Okorn-Schmidt, Kevin K. Chan, Matthew Copel, John A.

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SOI and GOI,” IEEE Electron Device Letters, Vol. 25, No. 2, pp. 80-82, February

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[43] The International Technology Roadmap for Semiconductors: 2001 Edition.

(http://www.public.itrs.net)

- 53 - CHAPTER 2

DEVICE SIMULATION FRAMEWORK

This device modeling research study investigates Ge-based MOSFETs with dimensions in the submicron regime, i.e., channel lengths less than 100 nm and gate oxide layers as thin as 1 nm. Also, we investigate devices with various structures and materials, such as germanium-on-insulator (GeOI) devices and the incorporation of high-

κ dielectric materials. Fabrication of such devices would require complex lithographic techniques and sophisticated material growth processes resulting in very high cost. As a result of this high cost and the fabrication challenges, measurements on fabricated devices are not readily available for comparison with simulation results for this research study. However, our modeling study will provide useful insight into the factors limiting device performance and predict trends in device performance due to variations in device structure and design. Where possible, we will include comparisons with published experimental results and/or results from other modeling studies.

In this chapter we will discuss the device modeling software package from ISE

Corporation used in this simulation study of germanium-based MOSFETs. Included in this discussion will be the device physics basis of the software, the material parameter models, such as the field and the doping dependence of the mobility, and the material parameters involved.

- 54 - 2.1 SIMULATION SOFTWARE

Numerical simulations of Ge-based MOSFET structures have been performed with the assistance of a numerical simulator from Integrated Systems Engineering (ISE)

Corporation. This software uses a graphical interface, called GENESISe, to design, organize, and automatically run complete TCAD simulation projects. It supports the design of experiments, extraction and analysis of results, optimization, and uncertainty analysis [1].

The numerical simulator within this package, DESSIS, provides device modeling of the physics underlying the electrical behavior of semiconductor devices. A set of physical device equations that describe the carrier distribution and conduction mechanisms are used to compute terminal currents, voltages, and charges. In the simulator, a real semiconductor device is represented as a ‘virtual’ device whose properties are discretized onto a non-uniform grid, or mesh, of nodes. A virtual device structure is then defined by two files. One is a grid file containing a description of the various regions within the device, i.e., boundaries, types of materials, location of electrical contacts, as well as the location of all the discrete nodes and their connectivity

(the device mesh). The second is a data file containing the doping profiles of the device.

DESSIS uses these files along with various transport equations and built-in physical models to describe the device’s DC and AC characteristics, as well as the device’s internal parameter variations and distributions, such as electrostatic potential, carrier concentrations, carrier mobilities, and carrier velocities. The electrical terminal characteristics of the device are predicted by solving key semiconductor equations, including Poisson’s Equation and the electron and hole continuity equations, at the nodes

- 55 - within the device mesh [1]. DESSIS’s accuracy arises from its accurate description of

the physics of device operation. Advanced numerical simulations utilizing the many

tools provided by ISE’s software were performed in order to obtain a realistic description

of the Ge MOSFET’s behavior. Therefore, the device characteristics presented in this

thesis are reasonable predictions of what can be expected in fabricated structures.

2.2 NUMERICAL TECHNIQUES

DESSIS applies the ‘box discretization’ method to discretize the partial

differential equations (PDEs). This is accomplished by integrating the PDEs over a test

volume, which applies the Gaussian theorem, and discretizing the resulting terms to a

first-order approximation. The box discretization method discretizes each PDE of the form [1]:

→ ∇ • J + R = 0 (2.1) into:

∑κij ⋅ jij + µ(Ωi)⋅ ri = 0 (2.2) j≠i

with values listed below in Table 2.1.

- 56 - Table 2.4. Dimensions Used in Box Discretization Method [1].

Dimension κij µ(Ωi)

1D 1/lij Box length

2D dij /lij Box area

3D Dij /lij Box volume

In (2.2), the physical parameters jij and ri have the values listed in Table 2.2, note that

B()x = x /(ex −1) is the Bernoulli function [1].

Table 2.2. Definitions of Equations Used in Box Discretization Method [1].

Equation jij ri

Poisson ε (ui − uj) − ρi

n d Electron continuity µ (ni ⋅ B(ui − uj )− nj ⋅ B(uj − ui )) Ri − Gi + ni dt

p d Hole continuity µ ()pj ⋅ B(uj − ui)− pi ⋅ B(ui − uj ) Ri − Gi + pi dt d Temperature κ(Ti − Tj) Hi − Tici dt

One special feature of DESSIS is that the actual assembly of the nonlinear equations is

performed elementwise, that is:

⎪⎧⎛ e e ⎞ e e ⎪⎫ ⎜ ij ij ⎟ i i ∑∑⎨⎜ k ⋅ j ⎟ + µ ()Ω ⋅ r ⎬ = 0 (2.3) e∈∈Elements()i) ⎩⎪⎝ j Vertices(e ⎠ ⎭⎪

This expression is equivalent to (2.2), but with the advantage that some material parameters, such as ε, µn, and µp can be handled elementwise, which is beneficial for

numerical stability and physical exactness [1].

- 57 -

2.3 SIMULATION MODELS

2.3.1 MOBILITY MODELS

DESSIS utilizes a modular approach for the description of the carrier mobilities.

For undoped materials, the carrier mobility is simply a function of the lattice temperature

and the material. However, in doped materials, the carriers scatter with impurities,

resulting in a degradation in their mobility [1]. The carrier mobilities are also affected by

various other physical phenomena occurring within the device. They experience

additional degradation as a result of high electric fields in the channel region, and

interactions with the semiconductor-insulator interface. In order to obtain an accurate

description of the carrier mobilities in the MOSFETs modeled in this simulation study, a

physical model was used to describe each of these phenomena listed above, particularly,

their affect on the carrier mobilities.

DESSIS takes the mobility contributions from each of these physical models and

combines them according to Mathiessen’s rule in order to calculate the final mobility [1]:

1 1 1 1 = + + (2.4) µ µdoping µhighfield µinterface

However, since the high-field saturation model is activated, DESSIS computes the final mobility in two steps. First, the low-field mobility is computed according to Equation

2.4, which is then input into Equation 2.5 in order to calculate the final mobility, which is a function of the low-field mobility as well as the driving force F [1]:

- 58 -

µ = f (µlow, F) (2.5)

The subsequent sections contain detailed descriptions of each of these carrier mobility models.

2.3.1.1 DOPING-DEPENDENT MOBILITY DEGRADATION

In doped semiconductors, a degradation of the carrier mobility is experienced due to scattering of the carriers by charged impurity ions [1]. DESSIS supports two models for doping-dependent mobility, the Masetti model [2] which is used as the default model for silicon, and the Arora model [3] which is used as the default model for germanium

[1]. For consistency purposes within this study, the Arora model was used to describe the mobility dependence on the impurity concentrations in both types of MOSFETs, silicon and germanium.

The Arora model, proposed by Narain D. Arora et. al. in 1982, predicts the electron and hole mobility as a function of concentration up to ~1020 cm-3 in the temperature range of 250 K to 500 K [3]. Arora and colleagues fitted experimental data into the following expression for mobility:

µd dop min µ = µ + A* (2.6) ⎛ Ni ⎞ 1+ ⎜ ⎟ ⎝ N0 ⎠

- 59 - αm ⎛ ⎞ ⎛ ⎞αd ⎜ ⎟ ⎜ ⎟ min min • ⎜ T ⎟ d d • ⎜ T ⎟ with µ = A ⎜ ⎟ , µ = A ⎜ ⎟ (2.7) ⎝ T0 ⎠ ⎝ T0 ⎠

⎛ ⎞α N ⎛ ⎞α a ⎜ ⎟ ⎜ ⎟ 0 N • ⎜ T ⎟ a • ⎜ T ⎟ and N = A ⎜ ⎟ , A* = A ⎜ ⎟ (2.8) ⎝ T0 ⎠ ⎝ T0 ⎠

where Ni = ND + NA represents the total concentration of ionized impurities, T0 = 300 K, and T is the lattice temperature [3]. The default parameters used for this model, for silicon and germanium, are shown below in Table 2.3 [1]. However, the data used by

DESSIS for germanium is inconsistent with published data, thus, these parameters were edited to ensure the accuracy of this model. Note that the edited parameters for Ge are obtained from the recent review of the literature by Adachi [4] and are also located in below in Table 2.3.

- 60 - Table 2.3. Arora Doping-Dependent Mobility Model: Default Parameters for Silicon [1], Germanium [1], and the Edited Parameters for Germanium [4].

Symbol Parameter Name Material Electrons Holes Units Si 88 54.3 3 3 2 µmin Ar_mumin Ge (default) 3.9 x 10 1.9 x 10 cm /V-s Ge (edited) 0 0 Si -0.57 -0.57

αm Ar_alm Ge (default) -1.6 -2.3 1 Ge (edited) 0 0 Si 1252 407 2 µd Ar_mud Ge (default) 0 0 cm /V-s Ge (edited) 4.5 x 103 2.9 x 103 Si -2.33 -2.23

αd Ar_ald Ge (default) 0 0 1 Ge (edited) 0 0 Si 1.25 x 1017 2.35 x 1017 17 17 -3 N0 Ar_N0 Ge (default) 1.0 x 10 1.0 x 10 cm Ge (edited) 1.0 x 1017 1.0 x 1017 Si 2.4 2.4

αn Ar_alN Ge (default) 0 0 1 Ge (edited) 0 0 Si 0.88 0.88

Aa Ar_a Ge (default) 0 0 1 Ge (edited) 0.45 0.45 Si -0.146 -0.146

αa Ar_ala Ge (default) 0 0 1 Ge (edited) 0 0

2.3.1.2 HIGH FIELD SATURATION

In high electric fields, the carrier drift velocity is no longer proportional to the electric field strength, rather, the velocity saturates to a finite speed vsat [1]. For our simulation study we used the drift-diffusion version of the Canali model [5] to model this

- 61 - effect. The Canali model originated from the Caughey-Thomas formula [6], but includes

additional temperature-dependent parameters that were fitted by Canali et. al. [5]:

µlow µ(F) = β 1/ β (2.9) ⎡ ⎛ µlow • F ⎞ ⎤ ⎢1+ ⎜ ⎟ ⎥ ⎣⎢ ⎝ vsat ⎠ ⎦⎥

where µlow represents the low-field mobility and the exponent β is temperature-dependent

according to the expression:

⎛ ⎞ βexp ⎜ ⎟ ⎜ T ⎟ 0⎜ ⎟ β = β ⎜ ⎟ (2.10) ⎜ ⎟ ⎝ T0 ⎠

where T represents the lattice temperature and T0 = 300 K [5]. The parameters for this

model are listed below in Table 2.4 for silicon and for germanium [1].

Table 2.4. Canali Model Parameters for Silicon and Germanium [1].

Symbol Parameter Name Material Electrons Holes Units Si 1.109 1.213 β0 beta0 1 Ge 1.109 1.213 Si 0.66 0.17 βexp betaexp 1 Ge 0.66 0.17

The velocity saturation model proposed by Canali et. al. is given by [5]:

- 62 - vsat,exp ⎛ T 0 ⎞ vsat = vsat,0⎜ ⎟ (2.11) ⎝ T ⎠

where T represents the lattice temperature and T0 = 300 K [5]. The default parameters

used for this model, for silicon and germanium, are shown below in Table 2.5 [1].

However, due to discrepancies between the data used by DESSIS and published data

regarding high field saturation in germanium, these parameters were edited to ensure the

accuracy of this model. Note that the edited parameters for Ge are obtained from Adachi

[4] and are also located in below in Table 2.5.

Table 2.5. Velocity Saturation Model: Default Parameters for Silicon [1], Germanium [1], and the Edited Parameters for Germanium [4].

Symbol Parameter Name Material Electrons Holes Units Si 1.07 x 107 8.37 x 106 6 6 vsat,0 vsat0 Ge (default) 7.43 x 10 7.43 x 10 cm/s Ge (edited) 7.00 x 106 6.30 x 106 Si 0.87 0.52

vsat,exp vsatexp Ge (default) 0.87 0.52 1 Ge (edited) 0.87 0.52

2.3.1.3 MOBILITY DEGRADATION AT INTERFACES

High transverse electric fields in the channel region of MOSFETs forces carriers to interact strongly with the semiconductor-insulator interface. As a result, carriers in the

channel are subjected to scattering by acoustic surface phonons and surface roughness

[1]. DESSIS generally uses the Lombardi model [7], along with an additional equation to

include a free carrier and doping dependence in an exponent to describe the mobility

- 63 - degradation caused by these effects. However, due to a lack of data available for

germanium, DESSIS uses the same default parameters for germanium as it does for

silicon in the Lombardi model. Therefore, we chose to implement a model proposed by

Xia et. al. [8] to describe the effect that strong transverse electric fields (in the channel

region of a MOSFET) have on the carrier mobilities. Xia and colleagues investigated

electron and hole mobilities in the inversion layer of Ge MOSFETs, as well as Si

MOSFETs for comparison purposes. They took into account the impact of impurity

concentration, surface roughness scattering, and acoustic and optical phonon scattering

on carrier mobilities. Xia et. al. used the following expression to model the effective

carrier mobility as a function of the transverse electric field [8]:

µ 0 eff µ = ν (2.12) 1+ (Eeff / E 0)

where µ0 is the low-field mobility, E0 is the threshold field, and ν is a fitting parameter

[8]. These parameters are listed below in Table 2.6 for both silicon and germanium.

Table 2.6. Mobility Degradation at Interfaces Model Proposed by Xia et. al. [8]: Parameters for Silicon and Germanium [8].

Symbol Parameter Name Material Electrons Holes Units Si 683.4 229.2 2 µ0 mu0 cm /V-s Ge 2017.8 524.1 Si 6.4 x 105 3.1 x 105 E0 E0 V/cm Ge 2.6 x 105 8.1 x 105 Si 1.6 1.0 ν nu 1 Ge 1.3 1.1

- 64 - Note that this model was implemented into the simulations by using a physical model

interface (PMI) in DESSIS.

2.3.2 BANDGAP NARROWING

Experimental data has shown that at high impurity concentrations (N = 1017 cm-3 or above) the density of energy states no longer possesses a parabolic energy distribution, instead it becomes dependent on the impurity concentration. This results in a reduction of the bandgap due to the broadening of the impurity band along with the formation of bandtails on the conduction and valence band edges. This phenomenon strongly influences the electrical behavior of the device, in particular, the minority carrier charge storage and the minority carrier current flow in heavily doped regions [9]. DESSIS simulates the bandgap narrowing effect using a model established by Slotboom and de

Graaff [9].

⎡ 2 ⎤ ⎛ NA ⎞ ⎛ ⎛ NA ⎞⎞ ∆Eg()NA = Ebgn⎢ln⎜ ⎟ + ⎜ln⎜ ⎟⎟ + 0.5⎥ (2.13) ⎢ ⎝ Nref ⎠ ⎝ Nref ⎠ ⎥ ⎣ ⎝ ⎠ ⎦

In the Slotboom and de Graaff model, the bandgap reduction ∆Eg is strictly a function of the doping concentration NA, and the variables Ebgn and Nref are shown below in Table

2.7 [1].

- 65 -

Table 2.7. Bandgap Narrowing (Slotboom and de Graaff Model): Default Parameters for Silicon and Germanium [1].

Symbol Parameter Name Material Parameter Value Units Si 9.0 x 10-3 Ebgn Ebgn eV Ge 9.0 x 10-3 Si 1.0 x 1017 -3 Nref Nref cm Ge 1.0 x 1017

Note that DESSIS also uses the parameters shown above to describe bandgap narrowing in germanium.

2.3.3 SHOCKLEY-READ-HALL RECOMBINATION

The recombination of electrons and holes through deep levels in the gap is generally referred to as Shockley-Read-Hall (SRH) recombination. Shockley and Read

[10] and Hall [11] mathematically analyzed the recombination of electrons and holes occurring through the mechanism of trapping. A trap was assumed to have an energy level in the energy gap so that its charge may have either of two values differing by one electronic charge. This phenomenon plays an important role regarding the physics of the transistor and is modeled in DESSIS using the subsequent equations following the SRH recombination model [10][11].

2 SRH np − ni, eff Rnet = (2.14) τp()n + n1 +τn(p + p1)

- 66 - Etrap kT with n1 = ni, eff ⋅ e (2.15)

−Etrap kT and p1 = ni, eff ⋅ e (2.16)

where Etrap is the difference between the defect level and the intrinsic level, and can be

found in the Table 2.8 below. The minority lifetimes τn and τp are dependent on the impurity concentration, as shown in the subsequent section.

2.3.3.1 SRH RECOMBINATION DOPING DEPENDENCE MODEL

Shockley-Read-Hall recombination is better described when the doping dependence of the carrier lifetimes is included. The doping dependence of the SRH lifetimes is modeled in DESSIS with the Scharfetter relation [12]:

τmax −τmin dop i min τ ()N = τ + γ (2.17) ⎛ Ni ⎞ 1+ ⎜ ⎟ ⎝ Nref ⎠

This dependence emerged from experimental data and from the theoretical conclusion

that the solubility of a fundamental, acceptor-type defect is strongly correlated to the

doping density [1]. The default parameters used by DESSIS for the SRH recombination

model, for both silicon and germanium, are listed below in Table 2.8 [1].

- 67 - Table 2.8. Shockley-Read-Hall Recombination Parameters for Silicon and Germanium[1].

Symbol Parameter Name Material Electrons Holes Units Si 0 0 Etrap Etrap eV Ge 0 0 Si 0 0 τmin taumin s Ge 0 0 Si 1 x 10-5 3 x 10-6 τmax taumax s Ge 1 x 10-5 3 x 10-6 Si 1 x 1016 1 x 1016 -3 Nref Nref cm Ge 1 x 1016 1 x 1016 Si 1 1 γ gamma 1 Ge 1 1

Since germanium has not been as extensively studied as silicon, parameters like

the ones in the table above are not readily available for germanium. Therefore, DESSIS

uses the default values for silicon to model this phenomenon in germanium. However, it

is more accurate to use the values for silicon than to not model this phenomenon at all.

The final page of this chapter contains a table reviewing all of the material parameters, for Si and Ge, for all of the physical models used in the simulations. The next chapter will discuss the structure of the baseline GOI MOSFET used in this simulation study, including a description of the physical dimensions, doping profiles, device mesh, and other features. The electrical characteristics, simulated by DESSIS, for this structure will also be presented. These results will be presented along with the results of a comparable SOI device in order to illustrate the performance advantages of the Ge device.

- 68 - Table 2.9 Review of Material Parameters for All Physical Models Used in Simulations [1,4,8]

Model Symbol Parameter Name Material Electrons Holes Units Si 88 54.3 3 3 2 µmin Ar_mumin Ge (default) 3.9 x 10 1.9 x 10 cm /V-s Ge (edited) 0 0 Si -0.57 -0.57

αm Ar_alm Ge (default) -1.6 -2.3 1 Ge (edited) 0 0 Si 1252 407 2 µd Ar_mud Ge (default) 0 0 cm /V-s Ge (edited) 4.5 x 103 2.9 x 103 Si -2.33 -2.23 α Ar_ald Ge (default) 0 0 1 Doping- d Ge (edited) 0 0 Dependent Si 1.25 x 1017 2.35 x 1017 Mobility 17 17 -3 N0 Ar_N0 Ge (default) 1.0 x 10 1.0 x 10 cm Ge (edited) 1.0 x 1017 1.0 x 1017 Si 2.4 2.4

αn Ar_alN Ge (default) 0 0 1 Ge (edited) 0 0 Si 0.88 0.88

Aa Ar_a Ge (default) 0 0 1 Ge (edited) 0 0 Si -0.146 -0.146

αa Ar_ala Ge (default) 0 0 1 Ge (edited) 0 0 Si 1.109 1.213 β beta0 1 0 Ge 1.109 1.213 Si 0.66 0.17 β betaexp 1 exp Ge 0.66 0.17 High Field Si 1.07 x 107 8.37 x 106 6 6 Saturation vsat0 vsat0 Ge (default) 7.43 x 10 7.43 x 10 cm/s Ge (edited) 7.00 x 106 6.30 x 106 Si 0.87 0.52

vsat,exp vsatexp Ge (default) 0.87 0.52 1 Ge (edited) 0.87 0.52 Si 683.4 229.2 µ mu0 cm2/V-s 0 Ge 2017.8 524.1 Mobility Si 6.4 x 105 3.1 x 105 Degradation at E E0 V/cm 0 Ge 2.6 x 105 8.1 x 105 Interfaces Si 1.6 1.0 ν nu 1 Ge 1.3 1.1 Si 0 0 E Etrap eV trap Ge 0 0 Si 0 0 Shockley- τmin taumin s Ge 0 0 Read-Hall Si 1 x 10-5 3 x 10-6 Doping τ taumax s max Ge 1 x 10-5 3 x 10-6 Dependent 16 16 Si 1 x 10 1 x 10 -3 Recombination N Nref cm ref Ge 1 x 1016 1 x 1016 Si 1 1 γ gamma 1 Ge 1 1 Model Symbol Parameter Name Material Parameter Value Units Si 9.0 x 10-3 E Ebgn eV Bandgap bgn Ge 9.0 x 10-3 Narrowing Si 1.0 x 1017 N Nref cm-3 ref Ge 1.0 x 1017

- 69 - BIBLIOGRAPHY

[1] ISE TCAD Release 8.5, ISE Integrated Systems Engineering AG, Zurich,

Switzerland, 2003.

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Against Carrier Concentration in Arsenic-, Phosphorus-, and Boron-Doped Silicon,”

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[3] Narain D. Arora, John R. Hauser, and David J. Roulston, “Electron and Hole

Mobilities in Silicon as a Function of Concentration and Temperature,” IEEE

Transactions on Electron Devices, Vol. ED-29, No. 2, pp. 292-295, February 1982.

[4] Sadao Adachi, “Handbook on Physical Properties of Semiconductors, Volume 1:

Group IV Semiconductors,” Kluwer Academic Publishers, Massachusetts, USA,

2004.

[5] C. Canali, G. Majni, R. Minder, and G. Ottaviani, “Electron and Hole Drift Velocity

Measurements in Silicon and Their Empirical Relation to the Electric Field and

Temperature,” IEEE Transactions on Electron Devices, Vol. ED-22, No. 11,pp.

1045-1047, November 1975.

[6] D. M. Caughey and R. E. Thomas, “Carrier Mobilities in Silicon Empirically

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2193, December 1967.

[7] Claudio Lombardi, Stefano Manzini, Antonio Saporito, and Massimo Vanzi, “A

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- 70 - IEEE Transactions on Computer-Aided Design, Vol. 7, No. 11, pp. 1164-1171,

November 1988.

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effective mobilities in germanium MOSFET inversion layer investigated by Monte

Carlo simulation,” Solid-State Electronics, Vol. 49, No. 12, pp. 1942-1946,

December 2005.

[9] J. W. Slotboom and H. C. de Graaff, “Measurements of Bandgap Narrowing in

Silicon Bipolar Transistors,” Solid-State Electronics, Vol. 19, No. 10, pp. 857-862,

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[10] W. Shockley and W. T. Read, “Statistics of the Recombination of Holes and

Electrons,” Physics Review, Vol. 87, No. 5, pp. 835-842, September 1952.

[11] R. N. Hall, “Electron Hole Recombination in Germanium,” Physics Review, Vol.

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[12] Jerry G. Fossum, “Computer-Aided Numerical Analysis of Silicon Solar Cells,”

Solid-State Electronics, Vol. 19, No. 4, pp. 269-277, April 1976.

- 71 - CHAPTER 3

MODELING RESULTS FOR BASELINE

GERMANIUM MOSFETS

The primary focus of this study is to investigate the performance capabilities and scaling behavior of short-channel Ge MOSFETs in order to illustrate their performance advantages over conventional Si MOSFETs, as well as examine the extent of limitations they may have. This chapter will begin to lay the groundwork for this simulation study by presenting modeling results for the baseline germanium-on-insulator (GOI) MOSFET used in this study. The modeling report will first discuss the physical structure of the baseline GOI MOSFET used; including detailed descriptions of the geometry and physical dimensions of the device, along with doping profiles, device mesh, and various other details concerning the structure. The subsequent section will contain the device performance results, simulated by DESSIS [1], for this GOI MOSFET. The device performance results will include results of DC and small signal AC simulations of the device’s transistor characteristics; they will be presented along with the results of a comparable SOI device in order to illustrate the performance advantages, or limitations, of the Ge device.

However, before the short-channel device is presented, a brief section regarding long-channel Ge MOSFETs will be included. This section will be similar to the one

- 72 - described above, however, it will focus on an experimental long-channel device reported

by Shang et. al. in 2004 [2]. The purpose of the long-channel device modeling report is

to verify the device simulator used with actual data from an experimental device, as well

as, provide an insight into what can be expected from short-channel Ge MOSFETs

regarding device operation and performance.

3.1 LONG-CHANNEL GERMANIUM MOSFET

3.1.1 DEVICE STRUCTURE

The baseline long-channel Ge MOSFET used in this simulation study was created

using MDRAW [1]. MDRAW is an ISE TCAD tool which offers a 2-dimensional device

boundary editor, doping and refinement editor, and meshing engine [1]. The device

boundary, i.e., materials, physical dimensions, etc., is defined first, followed by the input

of the doping profiles and device mesh. A schematic diagram of the baseline Ge

MOSFET used is shown in Figure 3.1; details of this structure were obtained from Shang et. al. [2] and are discussed below.

- 73 - 100 µm

3 nm LTO (SiO2) 49 µm 6 nm GeON

source channel drain

100 µm

10 µm

P-type Ge ~5E17/cm^3

200 µm

Figure 3.1 A cross-section schematic diagram of the long-channel Ge MOSFET used for this simulation study [2].

The substrate of the long-channel MOSFET is p-type germanium, doped with

boron at an impurity concentration of 5 x 1017 /cm3. The gate stack consists of a 6 nm

layer of germanium oxynitride (GeON) followed by a 3 nm layer of low-temperature

oxide (SiO2); details of this particular gate stack are reported in [3]. The gate electrode is a tunable workfunction metal, possessing a workfunction consistent with that of tungsten

(4.55 eV), while the source/drain electrodes are ohmic contacts with a contact resistance of 40 Ω-µm. A schematic diagram showing the physical structure and dimensions of the device are shown in the figure above; note that the channel region is 100 µm in length.

The source/drain profiles were not discussed by Shang et. al. [2], however, the details of the source/drain implant were described. The source and drain of the MOSFET were phosphorous implanted at 100 KeV with dose 4 x 1015 /cm2, then annealed using a rapid thermal annealing (RTA) process at 500°C in N2 for 5 minutes [2]. This implant

- 74 - information was entered into a simulation in DIOS (a process simulator for

semiconductor devices allowing simulations of fabrication sequences [1]) to obtain the

results shown below.

Figure 3.2 Dopant profile results obtained from DIOS simulation, based on implant information from Shang et. al. [2].

Figure 3.2 shows the dopant concentrations as a function of depth for the

MOSFET. The dashed line in the plot indicates the substrate doping, i.e., a constant

boron concentration of 5 x 1017 /cm3. The solid line in the plot represents the phosphorus

concentrations in the source/drain regions of the device. It indicates a phosphorous

concentration of 8 x 1018 /cm3 at the surface, a peak concentration of 4 x 1020 /cm3 at a depth of 0.12 µm, and a concentration of 5 x 1017 /cm3 at the junction at a depth of 0.30

µm. This information was then entered into MDRAW as Gaussian profiles to obtain the source/drain doping profiles for the device.

- 75 - The mesh created for this device, shown in the figures below, contains over 6800 nodes (note that the nodes are the mesh points at which key semiconductors equations are solved to determine the electrical characteristics of the device). While the mesh spans the entire device, the majority of these nodes are located in the channel region of the device, with spacing between nodes approximately every 0.4 µm across the channel and 10 nm below the gate. This mesh will enable an accurate description of device behavior and performance. Figure 3.3 (a) shows a magnified view of the device mesh in the channel region of the device created in MDRAW, while (b) is a magnified view of the beginning of the channel, as well as the end of the source profile.

source gate drain

(a)

- 76 - source gate

(b)

Figure 3.3 (a) Magnified image of the channel region of the MOSFET showing the device mesh. (b) Magnified image of the MOSFET at the end of the source and beginning of the channel.

3.1.2 DEVICE PERFORMANCE

This section contains the device performance results of the long-channel Ge

MOSFET described above. For comparison purposes, the simulation results of the Ge device will be shown along with results of a comparable Si device. With the exception of a silicon substrate and a silicon oxynitride gate insulator, the silicon and germanium devices are exactly the same, i.e., they possess the same structure, dimensions, doping, and mesh. The DC simulation results of the two MOSFETs will be discussed first, followed by a discussion of the AC simulation results.

- 77 - 3.1.2.1 TRANSFER CHARACTERISTICS

The transfer characteristics of a MOSFET are illustrated in a plot of the

MOSFET’s output drain current as a function of the input gate voltage at a fixed drain

bias [4]. This plot is primarily used a means to extract the threshold voltage (VT) of the device. Threshold voltage refers to the amount of input gate voltage necessary to open a conductive channel between the source and drain [5], in other words, the gate voltage necessary to turn the device on. Figure 3.4 shows the simulated transfer characteristics of the long-channel Ge MOSFET compared to the Si device. The simulations for both devices used a 0.5 V input drain bias and a gate voltage sweep from -1.0 V to 5.0 V.

Figure 3.4 Transfer characteristics of the Ge MOSFET, compared to the Si device, at VD = 0.5 V. A VT of 1.49 and 1.25 V was extracted for the Ge and Si devices, respectively.

Threshold voltages of 1.49 V and 1.25 V were extracted for the Ge and Si

MOSFETs, respectively. The VT of the Ge device is consistent with the calculated

- 78 - theoretical value, however, it is much lower than the experimental value of 3.5 V

extracted by Shang et. al. [2]. The inconsistencies between the theoretical value and

Shang’s experimental value can be due to slight oxide regrowth during annealing,

combined with the fixed charge from the tungsten sputtering process [2].

3.1.2.2 SUBTHRESHOLD CHARACTERISTICS

The behavior of a MOSFET operating in the subthreshold region (VG < VT) is of particular interest in low-voltage, low-power applications, such as digital logic and memory circuits, because it describes how the MOSFET switches off [6]. The subthreshold slope (S) is typically used as a figure of merit for MOSFETs and is extracted from a plot of drain current on a logarithmic scale as a function of gate bias.

The subthreshold slope is used to determine the ease at which the transistor current can be switched off. A steep subthreshold slope is preferred, while typical values tend to be between 70 and 100 mV/decade [6].

- 79 -

Figure 3.5 Subthreshold characteristics of Ge MOSFET, compared to Si MOSFET, at VD = 0.5V. Subthreshold slopes of 130 and 82 mV/dec were extracted for the Ge and Si devices, respectively.

Figure 3.5 is a plot of the drain current, on a logarithmic scale, as a function of the

gate bias for the Ge and Si MOSFETs. The subthreshold slopes extracted from the plot

are 130 and 82 mV/decade for the Ge device and Si device, respectively. The

subthreshold slope and off-current (~8 x 10-9 A) for the Ge device are comparable to the experimental values of ~150 mV/dec and ~10-9 A reported by Shang et. al. [2]. However, in this region of operation the Si device outperforms this Ge device due to a steeper subthreshold slope and a lower off-current (~1 x 10-14 A).

3.1.2.3 OUTPUT CURRENT-VOLTAGE CHARACTERISTICS

The output current-voltage characteristics of a MOSFET are obtained by plotting

the output drain current as a function of the input drain voltage, at fixed gate voltages.

The drain current increases with drain voltage at low VD, and saturates at a constant value

- 80 - IDsat at high VD, from there IDsat remains essentially constant independent of VD. IDsat represents the largest output current possible for a fixed gate voltage.

Figure 3.6 Output current-voltage characteristics of Ge MOSFET, compared to Si MOSFET, at VG3 = VT + 0.0V, VG2 = VT + 0.5V, and VG1 = VT + 1.0V. The Ge MOSFET offers at least a 96% increase in IDsat for all gate biases over the Si MOSFET.

Figure 3.6 shows output current-voltage characteristics for the Ge and Si

MOSFETs. The devices were simulated at three different gate voltages; VG3 = VT + 0.0

V; VG2 = VT + 0.5 V; and VG1 = VT + 1.0 V. The Ge device possesses significantly

higher drive currents than the Si device. The Ge MOSFET yields a 96% increase in ID1sat, a 108% increase in ID2sat, and a 157% increase in ID3sat over the Si device for gate voltages of 0.0 V, 0.5 V, and 1.0 V, respectively, above the threshold voltage.

- 81 - VGS1 (Shang et. al.) VGS2 (Shang et. al.) VGS3 (Shang et. al.) VGS1 (simulated) VGS2 (simulated) VGS3 (simulated)

20

15 A) u ( ent r r 10 u n C ai r D

5

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Drain Voltage (V)

Figure 3.7 Comparison of simulated ID-VD characteristics and experimental results reported by Shang and colleagues [2].

Figure 3.7 shows the simulated ID-VD characteristics compared to results reported by Shang et. al. [2]. The comparisons were made at three different gate voltages relative to VT to ensure the results weren’t disturbed by threshold voltage differences (VG3 = VT +

0.0 V; VG2 = VT + 0.5 V; and VG1 = VT + 1.0 V). The simulated results possess larger

saturation currents than the experimental results. The discrepancies between the

simulated values and Shang’s experimental value can be due to slight oxide regrowth

during annealing, combined with the fixed charge from the tungsten sputtering process

[2]. Differences may also arise from device to device variations, such as the source/drain contact resistances. The simulated devices possess a contact resistance of 40 Ω-µm, while it was not specified for the experimental device.

- 82 -

3.1.2.4 SMALL SIGNAL TRANSCONDUCTANCE

The transconductance of a MOSFET is essentially a measure of its gain and

becomes particularly important when describing the RF performance of a transistor.

Figure 3.8 Small signal transconductance as a function of gate bias for Ge and Si MOSFETs. The Ge MOSFET yields a peak transconductance of 44.86 µS while the Si MOSFET has a peak gm of 22.68 µS.

Figure 3.8 shows the simulated small signal transconductance (gm) as a function of gate

voltage for both the Ge and Si MOSFETs. The Ge device yields a peak gm of 44.86 µS, nearly twice that of the Si device (peak gm = 22.68 µS). The significantly larger

transconductance of the Ge MOSFET can be attributed directly to its larger carrier

mobilities, in particular, its electron mobility since these are n-channel devices.

- 83 - 3.1.2.5 CURRENT GAIN AND CUTOFF FREQUENCY

The cutoff frequency (fT) is perhaps the most significant figure of merit for a transistor when discussing RF performance. Peak fT is often quoted in the literature for a transistor designed for large-signal digital circuit applications. The cutoff frequency is a measure of the maximum useful frequency of a transistor when it is used as an amplifier and is defined as the frequency at which the small-signal current gain drops to unity [6].

1.0E+07

1.0E+06

1.0E+05 1 2 h ,

in 1.0E+04 a G t

n 1.0E+03 e r r fT (Si)

Cu 1.0E+02 fT (Ge)

1.0E+01

1.0E+00 1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 Frequency (Hz)

Figure 3.9 Small signal current gain versus frequency showing a cutoff frequency of 1.92 MHz for the Ge MOSFET and 0.78 MHz for the Si MOSFET.

Figure 3.9 shows the small signal current gain (the ratio of the output current to the input current [5]) versus frequency for the Ge and Si MOSFETs. The cutoff frequencies were extracted from this plot at the point where the current gain drops to unity and are 1.92 and 0.78 MHz for the Ge and Si MOSFETs, respectively. These are very low fT’s since the channel length is very large, i.e., 100 µm. The devices were simulated at a drain bias of 2.0 V and the results above were extracted at gate voltages of

- 84 - 3.92 and 3.40 V for Ge and Si devices, respectively. Figure 3.10 is a plot of the cutoff

frequency as a function of the gate bias for both devices. The germanium device offers a

larger cutoff frequency than does the silicon device for gate voltages above the threshold

voltage. The Ge MOSFET has a peak fT of 1.92 MHz at VG = 3.92 V, more than 2 times

that of the Si device, which has a peak fT of 0.78 MHz at VG = 3.40 V. Similar to the

transconductance, the peak fT is larger for Ge due to its larger electron mobility than for silicon.

2.0E+06

) 1.5E+06 z H ( y nc 1.0E+06 que e Fr

5.0E+05

0.0E+00 -1012345 Gate Voltage (V)

Figure 3.10 Cutoff frequency as a function of gate bias for the Ge and Si MOSFETs. The cutoff frequency peaks at 1.92 MHz at VG = 3.92 V for the Ge device and 0.78 MHz at VG = 3.40 V for the Si device.

3.1.2.6 UNILATERAL POWER GAIN AND MAXIMUM FREQUENCY OF OSCILLATION

Another important qualitative indicator of the frequency response of a transistor is

the maximum frequency of oscillation, or fmax, which is the frequency at which the unilateral power gain drops to unity [6]. Figure 3.11 shows Mason’s unilateral power

- 85 - gain versus frequency for the Ge and Si MOSFETs. The maximum frequencies of

oscillation were extracted from this plot at the point where the power gain drops to unity

and are 27.3 and 9.04 MHz for the Ge and Si MOSFETs, respectively. The devices were

simulated at a drain bias of 2.0 V and the results shown below were extracted at gate

voltages of 3.17 and 2.51 V for Ge and Si devices, respectively.

180

160 )

B 140 d ( n i

a 120 G

al 100 er at

il 80 n fmax (Si) s U

' 60

n fmax (Ge) 40 Maso 20

0 1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Frequency (Hz)

Figure 3.11 A plot of Mason’s unilateral gain as a function of frequency for the Ge and Si MOSFETs showing a maximum frequency of oscillation of 27.3 MHz and 9.04 MHz for the Ge and Si MOSFETs, respectively.

Figure 3.12 is a plot of the maximum frequency of oscillation as a function of the

gate bias for both devices. The germanium device offers a larger fmax than does the silicon device for gate voltages above the threshold voltage. The Ge MOSFET has a peak fmax of 27.3 MHz at VG = 3.17 V, more than 3 times that of the Si device, which has a peak fmax of 9.04 MHz at VG = 2.51 V. Since the fmax is proportional to the fT, and

- 86 - likewise depend on the electron mobility, the superior properties of the Ge material contribute to the Ge MOSFET’s better performance.

3.0E+07

2.5E+07

) 2.0E+07 z H ( y

nc 1.5E+07 que e

Fr 1.0E+07

5.0E+06

0.0E+00 -1012345 Gate Voltage (V)

Figure 3.12 Maximum frequency of oscillation as a function of gate bias for the Ge and Si MOSFETs. fmax peaks at 27.3 MHz at VG = 3.17 V for the Ge device and 9.04 MHz at VG = 2.51 V for the Si device.

While the results look extremely promising for the germanium device, especially the frequency response, it is important to point out that the results just presented are for a very long-channel device (L = 100µm). As channel lengths are scaled down into the submicron regime, i.e., 100 nm or less, many factors may begin to affect device performance. Short channel effects and hot electron effects may begin to plague device performance. In addition, the longitudinal electric fields within the device will increase as the device is scaled down, which in turn may cause the saturation of the drain current to occur at a much lower voltage due to velocity saturation [6]. This would degrade

- 87 - device performance and is of particular interest for this study since germanium has a lower saturation velocity than does silicon [7]. Nonetheless, it may be possible that short-channel Ge MOSFETs will outperform their Si counterparts. This will be explored in the following section as the modeling results of the baseline short-channel germanium- on-insulator MOSFET are presented and compared to results from a similar SOI device.

3.2 SHORT-CHANNEL GERMANIUM-ON-INSULATOR MOSFET

3.2.1 DEVICE STRUCTURE

The baseline short-channel GOI MOSFET used in this simulation study was created using MDRAW based on a device described by Barraud et. al. [8]. A schematic diagram this GOI device is shown in Figure 3.13 and details of the structure are discussed below.

Figure 3.13 A cross-section schematic diagram of the baseline short-channel GOI MOSFET used for this simulation study [8].

- 88 - The bottom layer, or parent substrate, of this GOI device is a 100 nanometer (nm)

thick layer of germanium. Directly on top of the Ge parent substrate is the buried oxide

layer, which is a 400 nm thick layer of silicon dioxide (SiO2). Located on top of the buried oxide is a 15 nm thick film of crystalline Ge, serving as the active layer of the device. The gate oxide, a 1 nm thick layer of SiO2, is located on top of the active layer, directly in the center of the device. The gate electrode is 44 nm in length and is a tunable workfunction metal, possessing a workfunction of 4.50 eV, while the source/drain electrodes are ohmic contacts with a contact resistance of 40 Ω. The entire device spans

140 nm in length [8].

The source and drain of the device are doped with phosphorus using a Gaussian profile. The phosphorous concentration of the source/drain is a maximum of 1 x 1020

/cm3 at the surface decreasing to a concentration of 1 x 1016 /cm3 at the junction at the bottom of the active layer. The channel of the MOSFET is doped with boron at a constant concentration of 1 x 1016 /cm3. Figure 3.14 (a) shows the doping profiles of the

device in the active layer and Figure 3.14 (b) shows a magnified view of the end of the

source profile and beginning of the channel.

- 89 - source gate drain

(a)

source gate

(b)

Figure 3.14 (a) Magnified image of the active layer of the MOSFET showing the device mesh. (b) Magnified image of the MOSFET at the end of the source and beginning of channel.

- 90 -

The mesh created for this device, shown in the figures above, contains over 2300 nodes. While the mesh spans the entire device, the majority of these nodes are located in the channel region of the device, with spacing between nodes approximately 0.75 nm in the lateral direction and 0.50 nm in the vertical direction just below the gate. A mesh this fine enables an accurate description of device behavior and performance.

3.2.2 DEVICE PERFORMANCE

This section contains the device performance results of the short-channel GOI

MOSFET described above. For comparison purposes, the simulation results of the GOI device will be shown along with results of a comparable SOI device. With the exception of a silicon substrate, the silicon and germanium devices are exactly the same, i.e., they possess the same structure, dimensions, doping, and mesh. The DC simulation results of the two MOSFETs will be discussed first, followed by a discussion of the AC simulation results.

3.2.2.1 TRANSFER CHARACTERISTICS

The transfer characteristics of the GOI and SOI MOSFETs are illustrated in

Figure 3.15. The simulations performed to acquire these results used a 1.0 V input drain bias and a gate voltage sweep from -1.0 V to 5.0 V.

- 91 -

Figure 3.15 Transfer characteristics of the GOI MOSFET, compared to the SOI device, at VD = 1.0 V. A VT of 0.45 V was extracted for both devices.

A threshold voltage of 0.45 V was extracted from the plot for both the GOI and

SOI MOSFETs. Although the threshold voltages of both devices are equal, the Si device

offers higher output drain current than the GOI device at voltages larger than VT. This is the opposite of the result obtained for the long channel devices discussed previously and is somewhat surprising.

3.2.2.2 SUBTHRESHOLD CHARACTERISTICS

Figure 3.16 is a plot of the drain current, on a logarithmic scale, as a function of

the gate bias for the GOI and SOI MOSFETs. The subthreshold slopes extracted from

the plot are 105 and 98 mV/decade for the Ge device and Si device, respectively. Similar

to the long-channel devices, the Si device outperforms this Ge device, in this region of

- 92 - operation, due to a slightly steeper subthreshold slope and a lower off-current, ~3 x 10-14

A compared to ~ 3 x 10-11 A for the GOI device.

(a)

(b)

Figure 3.16 (a) Subthreshold characteristics of GOI MOSFET, compared to SOI MOSFET, at VD = 1.0V. Subthreshold slopes of 105 and 98 mV/dec were extracted for the GOI and SOI devices, respectively. (b) Magnified view of subthreshold characteristics at high gate bias illustrating the higher output drain current for the SOI device.

- 93 -

3.2.2.3 OUTPUT CURRENT-VOLTAGE CHARACTERISTICS

This sections contains the simulated output current-voltage characteristics of the

GOI and SOI MOSFETs, as well as a comparison of these results to those reported by

Barraud et. al. [8]. Figure 3.17 shows output current-voltage characteristics for the GOI and SOI MOSFETs. The devices were simulated at three different gate voltages; VG3 =

VT + 0.1 V; VG2 = VT + 0.5 V; and VG1 = VT + 1.0 V. In each case, the Si device possesses somewhat higher drive currents than the Ge device. The SOI MOSFET experiences an ~17% increase ID1sat, an ~16% increase in ID2sat, and an ~12% increase in

ID3sat when compared to the GOI device. The lower saturation of drain currents

experienced by the GOI device could be a result of velocity saturation in the channel due

to high longitudinal fields in the channel. Remember, while Ge has significantly higher

low-field electron mobility than Si, its electron saturation velocity is lower and saturates

at a lower electric field. This topic will be discussed at length following the presentation

of the device performance results.

- 94 -

Figure 3.17 Output current-voltage characteristics of GOI MOSFET, compared to SOI MOSFET, at VG3 = VT + 0.1V, VG2 = VT + 0.5V, and VG1 = VT + 1.0V.

Figure 3.18 shows the simulated ID-VD characteristics compared to results reported by Shang et. al. [8] for (a) the GOI device and (b) the SOI device. The comparisons were made at three different gate voltages relative to VT to ensure the results weren’t disturbed by threshold voltage differences (VG3 = VT + 0.1 V; VG2 = VT + 0.5 V; and VG1 = VT + 1.0 V). While the simulated results for the SOI device are comparable to

the experimental results for all three gate voltages, the simulated GOI device matches the

experimental data in the linear region but saturates at lower drain currents. The

discrepancies between the simulated values and Barraud’s experimental values can be

due to minor differences in the device structures (the simulated device was based on, not

an exact replica of, the device reported by Barraud and colleagues, as they did not

describe all of the details of the entire device structure). In addition, their reported results

- 95 - are also from simulated devices, therefore, differences in the physical models used to describe device behavior and performance could affect the results, as could differences in the device simulators themselves.

GOI

VGS1 (Barraud et. al.) VGS2 (Barraud et. al.) VGS3 (Barraud et. al.) VGS1 (Arnold) VGS2 (Arnold) VGS3 (Arnold)

3500

3000

) 2500 um A/ u (

2000 ent r r

u 1500 n C ai r 1000 D

500

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Drain Voltage (V) (a)

- 96 - SOI

VGS1 (Barraud et. al.) VGS2 (Barraud et. al.) VGS3 (Barraud et. al.) VGS1 (Arnold) VGS2 (Arnold) VGS3 (Arnold)

2500

2000 ) um / A

u 1500 ( t en r r u 1000 n C ai r D 500

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Drain Voltage (V)

(b)

Figure 3.18 Comparison of simulated ID-VD characteristics and experimental results reported by Barraud and colleagues [8] for (a) GOI MOSFET and (b) SOI MOSFET.

3.2.2.4 SMALL SIGNAL TRANSCONDUCTANCE

Simulation results of the small signal transconductance of the GOI and SOI

MOSFETs will be presented in this section. In order to obtain these results, both devices were simulated at a drain voltage of 1.0 V and an AC analysis was performed at a single frequency of 1 MHz. Figure 3.19 shows the simulated gm as a function of the gate voltage for both the GOI and SOI MOSFETs. The GOI device yields a peak gm of 1602

µS/µm, approximately 15% less than that of the Si device (peak gm = 1887 µS/µm). The reduction in peak transconductance of the GOI MOSFET could be a result of velocity saturation in the channel, again due to high longitudinal electric fields, especially near the

- 97 - drain for the saturation region of device operation. This will also be discussed at length following the presentation of the device performance results.

Figure 3.19 Small signal transconductance as a function of gate bias for GOI and SOI MOSFETs. The GOI MOSFET yields a peak transconductance of 1602 µS/ µm while the SOI MOSFET has a peak gm of 1887 µS/ µm.

3.2.2.5 CURRENT GAIN, CUTOFF FREQUENCY, AND MAXIMUM FREQUENCY OF

OSCILLATION

This section contains AC simulation results of the GOI and SOI MOSFETs showing the frequency response of the devices. In order to obtain these results, both devices were simulated at a drain voltage of 1.0 V and an AC analysis was performed throughout a frequency sweep from 1 Hz to 1 x 1012 Hz.

- 98 - 1.E+12 1.E+11 1.E+10 1.E+09 1 1.E+08 h2 1.E+07 in, 1.E+06 Ga

nt 1.E+05 e r r

u 1.E+04 C 1.E+03 1.E+02 1.E+01 1.E+00 1.E+00 1.E+02 1.E+04 1.E+06 1.E+08 1.E+10 1.E+12

Frequency (Hz) (a)

1.E+01 1 2 h

, n i a G

t fT (Si) rren fT (Ge) Cu

1.E+00 1.E+11 1.E+12 Frequency (Hz) (b)

Figure 3.20 (a) Simulated small signal current gain versus frequency showing a cutoff frequency of 252.6 GHz for the GOI MOSFET and 317.0 GHz for the SOI MOSFET. (b) Magnified image of where the current gain drops to unity.

Figure 3.20 shows the simulated small signal current gain as a function of frequency for the GOI and SOI MOSFETs. The cutoff frequencies were extracted from

- 99 - this plot at the point where the current gain drops to unity and are 252.6 and 317.0 GHz

for the GOI and SOI MOSFETs, respectively. The results above were extracted at gate

voltages of 0.61 and 0.67 V for the GOI and SOI devices, respectively. Figure 3.21

shows a plot of the cutoff frequency as a function of gate bias for both devices. The

germanium device offers a larger cutoff frequency than does the silicon device for gate

voltages between 2.4 and 3.4 V. However, the SOI device possesses a larger fT than the

GOI device for gate voltages less than 2.4 V and larger than 3.4 V. The SOI MOSFET

has a peak fT of 317.0 GHz at VG = 0.67 V, an approximate 20% increase over the GOI

device, which has a peak fT of 252.6 GHz at VG = 0.61 V. These results may be

understood by noting the region of device operation and recalling the boundary between

the linear and saturation regions for the MOSFET. The device is in the linear region of

operation when: VDS < VDSsat = VGS – VT = VGS - 0.45 V, and in the saturation region of operation when: VDS > VDSsat = VGS – VT = VGS - 0.45 V. Thus, for VDS = 1.0 V, and fixed at low VGS, the device is in the saturation mode where velocity saturation in the channel limits the drain current. For VGS ≥ 2.5 V, then VDSsat = 2.5 V – 0.45 V ≈ 2 V >

VDS = 1 V, so the FET is in the linear region so the larger mobility in Ge enables the GOI

FET to outperform the SOI FET.

- 100 - 350

300 ) z

H 250 G (

y 200 nc que

e 150 Fr f f o t 100 u C

50

0 -1012345 Gate Voltage (V)

Figure 3.21 Cutoff frequency as a function of gate bias for the GOI and SOI MOSFETs for VDS = 1.0 V. The cutoff frequency peaks at 252.6 GHz at VG = 0.61 V for the GOI device and 317.0 GHz at VG = 0.67 V for the SOI device.

Figure 3.22 is a plot of the maximum frequency of oscillation as a function of gate

bias for both devices. The germanium device offers a larger fmax than does the silicon device for gate voltages between 0.6 and 3.5 V. The GOI MOSFET has a peak fmax of

973.7 GHz at VG = 0.61 V, slightly less than that of the SOI device, which has a peak fmax of 980.4 GHz at VG = 0.49 V.

- 101 - ) 1000 Hz

G 900 (

n

o 800 i at l l 700 sci

O 600 f 500 cy o n

e 400 u eq

r 300 F

m 200 mu 100 axi

M 0 -1012345 Gate Voltage (V)

Figure 3.22 A plot of maximum frequency of oscillation as a function of gate voltage for the GOI and SOI MOSFETs showing a fmax of 973.7 GHz and 980.4 GHz for the GOI and SOI MOSFETs, respectively.

The reduction in the frequency response of the GOI MOSFET, compared to the

SOI device, will be investigated in the subsequent section, as will the overall

performance of the GOI device, in comparison with the SOI device.

3.2.2.6 INVESTIGATING CARRIER TRANSPORT IN SIMULATED GOI MOSFET

It was suspected that the lower carrier saturation velocity of germanium, relative to silicon, may restrict device performance in short-channel MOSFETs in the saturation

region of device operation. While Ge has a higher electron mobility at low electric fields,

Figure 1.9 shows that the electron drift velocity of bulk Ge saturates at a lower electric

≈ 6 ≈ 3 field with a lower saturation velocity, vsat 7 x 10 cm/sec at E 3 x 10 V/cm, compared

≈ 7 ≈ 4 to bulk Si, vsat 1 x 10 cm/sec at E 3 x 10 V/cm. Simulations were performed to

compare the transport properties of the two devices. The figure below shows the

- 102 - simulated results of the devices working in the saturation region (VG = 0.95 V and VD =

1.0 V).

(a)

(b)

Figure 3.23 (a) Longitudinal electric field along the channel, directly below the gate, of the GOI MOSFET. (b) Electron velocity along the channel of the GOI and SOI devices.

- 103 -

Figure 3.23 (a) is a plot of the longitudinal electric field in the channel region of the GOI device showing a field strength of ~1 x 106 V/cm near the drain end of the channel. In the saturation region of device operation the gate electric field causes pinchoff near the drain end of the channel, which causes the longitudinal electric field in the channel to exceed that needed for velocity saturation in both silicon and germanium.

Figure 3.23 (b) is a plot of the electron velocity along the channel for both devices. The SOI device has a higher electron velocity throughout the entire channel.

Note that in high electric fields, at the drain end of the channel, the electron velocities of both devices saturate to their accepted, respective values listed in Table 1.2. This in turn causes the saturation of the drain current of the GOI device to occur at lower voltages [6] as seen in Figure 3.17, as well as degrade the frequency response of the transistor.

As a result of these velocity saturation problems with the carrier transport within the GOI MOSFET, the GOI FET device performance is inferior to the comparable SOI device. However, we will investigate changes that can be made to the device structure to see if these problems with GOI FET can be alleviated. The next chapter will investigate the effects that varying the device structure has on device performance for the GOI

MOSFET. In particular, we will vary the gate insulator material, gate oxide thickness, channel length, and channel doping and examine how these changes affect device performance.

- 104 - BIBLIOGRAPHY

[1] ISE TCAD Release 8.5, ISE Integrated Systems Engineering AG, Zurich,

Switzerland, 2003.

[2] Huiling Shang, Kam-Leung Lee, P. Kozlowski, C. D’Emic, I Babich, E Sikorski,

Meikei Ieong, H.-S. P. Wong, Kathryn Guarini, and W. Haensch, “Self-Aligned n-

Channel Germanium MOSFETs With a Thin Ge Oxynitride Gate Dielectric and

Tungsten Gate,” IEEE Electron Device Letters, Vol. 25, No. 3, pp. 135-137, March

2004.

[3] Huiling Shang, Harald Okorn-Schmidt, Kevin K. Chan, Matthew Copel, John A.

Ott, P. M. Kozlowski, S. E. Steen, S. A. Cordes, H.-S. P. Wong, E. C. Jones, and W.

E. Haensch, “High mobility p-Channel germanium MOSFETs with a thin Ge

oxynitride gate dielectric,” IEDM Technical Digest, pp. 441-444, December 2002.

[4] Ben G. Streetman and Sanjay Banerjee, “Solid State Electronic Devices,” Prentice

Hall, New Jersey, USA, 2000.

[5] Semiconductor OneSource: Semiconductor Glossary.

(http://www.semiconductorglossary.com)

[6] Yaun Taur and Tak H. Ning, “Fundamentals of Modern VLSI Devices,” Cambridge

University Press, Cambridge, UK, 1998.

[7] Sadao Adachi, “Handbook on Physical Properties of Semiconductors, Volume 1:

Group IV Semiconductors,” Kluwer Academic Publishers, Massachusetts, USA,

2004.

- 105 - [8] S. Barraud, L. Clavelier, and T. Ernst, “Electron transport in thin SOI, strained-SOI

and GeOI MOSFET by Monte-Carlo simulation,” Solid-State Electronics, Vol. 49,

No. 7, pp. 1090-1097, July 2005.

- 106 - CHAPTER 4

VARIATIONS IN DEVICE DESIGN AND

EFFECTS ON DEVICE PERFORMANCE FOR

GERMANIUM-ON-INSULATOR MOSFET

In this chapter we will discuss the importance of various structural parameters in the device design of the GOI MOSFET and their effects on the device performance. The first section will investigate the impact of using alternative dielectric materials with higher dielectric constants (κ) for the gate insulator. The use of high-κ gate dielectrics increases the gate capacitance of the MOSFET, enabling higher drive currents, while avoiding excess leakage currents and other problems associated with the use of very thin

SiO2 gate insulating layers [1]. In the second section we will examine the importance of the thickness of the gate insulating layer. If the gate oxide is too thin, excessive gate leakage currents will occur due to tunneling and degrade device performance. However, as the thickness of the gate oxide increases, the gate capacitance of the device decreases, thereby reducing the number of charges in the channel and drain current at a fixed gate bias [1]. We will both increase and decrease the thickness of the gate oxide layer in the

GOI MOSFET from that of the starting device structure described in the previous chapter and examine how the performance of the device is affected. In a following section we

- 107 - will also vary the impurity concentration in the channel and examine the effects. The

effective mobility of the carriers in the channel of a MOSFET is dependent upon the

channel doping; making channel doping an important parameter in determining the

frequency response of the device. The final section of this chapter will investigate how

scaling down the length of the channel affects the performance of the device. The speed

of the device should increase with a reduction in channel length, however, short channel

effects will become more pronounced and could possibly overshadow these benefits.

Throughout the entire chapter, we will examine specifically how the threshold

voltage (VT), subthreshold slope (S), drain-induced barrier lowering (DIBL), peak

transconductance (gm), and peak cutoff frequency (fT) are each affected by these variations in device design. For reference throughout the remainder of this chapter, Table

4.1 contains the values of the structural parameters of the baseline device that will be examined in the subsequent sections.

Table 4.1 Structural Parameters of the Baseline GOI MOSFET

Structural Parameter Value

gate dielectric material (dielectric constant) SiO2 (3.9)

gate oxide thickness 1 nm

channel doping 1 x 1016 /cm3

channel length 40 nm

- 108 - 4.1 EFFECTS OF VARIATION IN GATE DIELECTRIC MATERIAL

The thickness of the silicon dioxide gate layer of MOSFETs has been

continuously scaled down due to the necessity of maintaining the gate electric field as the

power supply is reduced for the MOSFET. When the silicon dioxide gate layer is scaled

down below a thickness of 3 nm, increased gate leakage current occurs by tunneling of

the charge carriers through the gate dielectric. This leakage current increases

exponentially as the oxide thickness decreases until it becomes problematic in CMOS

operation and eventually exceeds the leakage current specifications set by the ITRS. In

short, excessive gate leakage will ultimately limit SiO2 layer thickness scaling. The leakage current in a MOSFET can be reduced several orders of magnitude by replacing

SiO2 with a thicker material possessing a high dielectric constant (κ). The incorporation of a high-κ dielectric material will increase the gate capacitance of the device, allowing use of a thicker gate dielectric layer, resulting in a reduction of the leakage current and an improvement in the reliability of the gate dielectric [1].

In this section we will investigate how various high-κ gate dielectrics

incorporated into the GOI MOSFET design will affect the device’s performance. Since

experimental Ge MOSFETs have been reported using high-κ gate dielectrics such as

GeON [2], ZrO2 [3], and HfO2 [4], we decided to include these materials as well as Al2O3

in our study. Table 4.1 lists the gate dielectrics used, their respective dielectric constants

(the reference from which this value and other material properties originated), along with

the equivalent oxide thickness (EOT). The equivalent oxide thickness of a material is

essentially the thickness of the silicon dioxide layer that would be required in order to

achieve the same capacitance per unit area as the high-κ material in consideration [1]. It

- 109 - is important to note that the dielectric constant of a material is dependent upon the

manner in which it is grown; therefore, in practice a relatively wide range of values for κ

is possible for a given material. The dielectric constants listed in Table 4.2 are the values

used in this study.

Table 4.2 Gate Insulators and Their Dielectric Constants

Dielectric Material Chemical Symbol Dielectric Constant EOT (Å)

silicon dioxide SiO2 3.9 [5] 10

germanium oxynitride GeON 6.5 [6] 6

aluminum oxide Al2O3 10 [1] 3.9

zirconium dioxide ZrO2 16 [1] 2.438

hafnium dioxide HfO2 23 [1] 1.696

The remainder of this section will present the simulation results of the GOI

MOSFET for each of the gate dielectric materials listed above. The parameters of the

simulations are the same as those used for the baseline structure presented in section 3.2.

Figure 4.1 is a plot of the threshold voltage as a function of the dielectric constant of the gate oxide for a fixed dielectric thickness of 1 nm. Note, the solid line shown in the figure is included as an aid to the eye and not a fit to the data. The threshold voltage of the device grows larger as the dielectric constant of the gate insulator increases, which is contrary to the expected reduction in Vt. The use of a high-κ gate dielectric material

results in an increase in the gate capacitance of the device, as shown in equation (4.1) [1],

- 110 - Aεrε 0 Cox = (4.1) tox

where A is the gate contact area, εr (or κ) the relative dielectric constant of the gate insulator, ε0 the permittivity of free space, and tox the gate oxide thickness [1]. This increase in gate capacitance can be quite large depending upon κ of the material and would in turn increase the output drain current of the device, as seen in (4.2)

W ID = µ Cox(VG −VT )VD (4.2) L

where W represents the width of the gate, L the gate length, and µ the mobility of the carriers in the channel [7]. It is also important to point out that the use of high-κ gate

dielectrics generally results in a minor reduction of the electron mobility in the inversion

layer of MOSFETs due to Coulomb scattering from fixed charges in the dielectric [1].

However, in (4.2), the reduction in mobility is outweighed by the increase in gate

capacitance, and the resulting increased drain current would cause a slight decrease in the

threshold voltage of the device. Equation (4.3) is the classic expression for the threshold

voltage of a MOSFET, showing an inverse dependence on the gate capacitance [8],

4εrqNaψB Vt = Vfb + 2ψB + (4.3) Cox

where Vfb is the flat-band voltage, ψB is the difference between the Fermi level and

intrinsic level, εr is the permittivity, q is the electronic charge, and Na is acceptor impurity

- 111 - density [8]. Equation (4.3) also suggests that as εr increases, Cox increases, so Vt decreases, which is the opposite of what is seen in Figure 4.1.

0.55 ) 0.5 ge (V a old Volt h s e

r 0.45 h T

0.4 0 5 10 15 20 25 Dielectric Constant

Figure 4.1 The threshold voltage of the MOSFET as a function of the dielectric constant of the gate insulator.

The increase in the threshold voltage of the device shown in Figure 4.1 is likely a result of the manner in which Vt was extracted from the data. In this study, the Vt was determined by extrapolating the ID–VG curve at its point of maximum slope and using the intercept of this line with the VG axis to determine the Vt. Figure 4.2 (a) shows the ID–VG characteristics of the MOSFETs with all of the different gate dielectric materials. This figure shows that increasing κ of the gate oxide increases the output drain current at a fixed gate bias, resulting in a steeper slope and thus, a higher threshold voltage. The threshold voltage can also be extracted in another manner by choosing a fixed drain current on a logarithmic scale and using the gate voltage that corresponds to that

- 112 - particular drain current as the threshold voltage. Figure 4.2 (b) shows the ID–VG

characteristics of the MOSFETs with all of the different gate dielectric materials on a

logarithmic scale. It is interesting to note that at drain currents below ~10-4 A/µm, the extracted threshold voltages would follow the pattern shown in Figure 4.1, i.e., an

-4 increase in Vt with increasing κ. However, at drain currents above ~10 A/µm, the

extracted threshold voltages would follow the opposite pattern and decrease with

increasing κ.

(a)

- 113 - (b)

Figure 4.2 The ID–VG characteristics of the MOSFETs with all of the different gate dielectric materials on (a) a linear scale, and (b) a logarithmic scale.

Figure 4.3 shows the subthreshold slope of the MOSFET versus the dielectric

constant of the gate insulator. A significant improvement in the subthreshold swing of

device is noticed as the κ of the gate oxide increases. The baseline structure reported a

subthreshold slope of ~105 mV/decade with a SiO2 gate insulator. This number

progressively decreased, with increasing κ of the gate oxide material, down to ~88

mV/decade for the HfO2 device. The theoretical lower limit for the subthreshold swing is

60 mV/dec [8]. This approximate 16% improvement in the subthreshold slope can also be attributed to the increase in gate capacitance stemming from the use of high-κ dielectric materials. (4.4) shows that the subthreshold slope is inversely related to the gate capacitance, so that, as Cox increases, S decreases toward a more favorable value [7].

- 114 -

kT Cd + Cit S = 2.3 [1+ ] (4.4) q Cox

where Cd is the depletion capacitance in the channel, Cit is the fast interface state capacitance, and Cox is the gate capacitance [7]. For this set of simulations, the Cit was

assumed constant since the study of the interface of silicon with these new dielectrics has

not yet reported the possibility of variations in Cit.

110

105 ) c de

V/ 100 m e (

95 Slop hold s

e 90 r h bt

Su 85

80 0 5 10 15 20 25 Dielectric Constant

Figure 4.3 Subthreshold slope of the MOSFET versus dielectric constant of the gate insulator. An improvement of over 16% in the subthreshold slope is seen between the SiO2 device (κ = 3.9) and the HfO2 device (κ = 23).

Figure 4.4 is a plot of drain induced barrier lowering versus the dielectric constant

of the gate insulator. As the κ of the gate oxide increases, the DIBL of the device is

observed to steadily decrease. The baseline structure reported a DIBL of ~231.9 mV/V

- 115 - with a SiO2 gate insulator, just slightly larger than the ~226.6 mV/V of the GeON device.

The DIBL of the MOSFET then significantly decreases to ~155.3 mV/V for the Al2O3 device, and progressively lower as the value of κ of the gate dielectric material increases.

The HfO2 device showed an approximate 43% improvement in DIBL over the baseline

GOI MOSFET. This trend is expected since the larger the dielectric constant is, the stronger is the gate control over the channel and so the smaller the effect of variation in the drain bias. The nearly two fold reduction in the DIBL in going from SiO2 to HfO2

(the largest κ) is significant and corresponds to a substantial improvement in MOSFET performance.

240 V) V/

m 220 ( g in 200

180 ier Lower rr

Ba 160 ced 140

120 Drain Indu

100 0 5 10 15 20 25 Dielectric Constant

Figure 4.4 Drain induced barrier lowering of the MOSFET versus dielectric constant of the gate insulator. An improvement of approximately 43% in the DIBL is seen between the SiO2 device (κ = 3.9) and the HfO2 device (κ = 23).

- 116 - Figure 4.5 shows the peak small signal transconductance of the MOSFET versus

the dielectric constant of the gate insulator. A significant improvement in the peak gm of the device is observed as the κ of the gate oxide increases. The baseline SiO2 structure

reported a peak gm of ~1602 µS/µm, approximately 50% less than that of the Al2O3

device (~3116 µS/µm), and nearly three times less than that of the HfO2 device (~4750

µS/µm). The improvement in the peak small signal transconductance of the MOSFET is due to an increase in the gate capacitance of the device, where the relationship between the transconductance and the gate capacitance is [9].

µ CoxW gm = (VG −VT ) (4.5) L

Again, it is important to point out that the degradation in mobility, from the use of high-κ

dielectrics, is overshadowed by the increase in Cox.

- 117 - 5000 ) /um

S 4500 nce ( 4000 ducta 3500 anscon 3000 l Tr

2500 all Signa m 2000

Peak S 1500 0 5 10 15 20 25 Dielectric Constant

Figure 4.5 Peak small signal transconductance of the MOSFET versus dielectric constant of the gate insulator. An increase of nearly 300% in the peak gm is seen between the SiO2 device (κ = 3.9) and the HfO2 device (κ = 23).

Figure 4.6 shows that the peak cutoff frequency of the MOSFET steadily

decreases as the κ of the gate oxide increases. The ZrO2 device reported a peak fT of

~197.7 GHz, which is approximately a 21% decrease from that of the baseline SiO2 structure. The reduction in the peak cutoff frequency of the MOSFET is also due to the increase in the gate capacitance of the device. (4.6) shows that the cutoff frequency is proportional to the small signal transconductance and inversely proportional to the gate capacitance of the device [8],

gm fT = (4.6) 2π CoxWL

- 118 - The reduction in the fT of the MOSFET is therefore a result of a larger increase in the gate capacitance (by a factor of ~6) than the increase in the transconductance of ~3 seen in Figure 4.5. However, we note that the degradation in fT seen in Figure 4.6 (~20%) is

not as large as expected (~50%) from the appropriate relationship give by (4.6).

275 )

Hz 250 (G y c en equ

r 225 F f f o t Cu

200 eak P

175 0 5 10 15 20 25 Dielectric Constant

Figure 4.6 Peak cutoff frequency of the MOSFET versus dielectric constant of the gate insulator. A decrease of over 20% in the peak fT is seen from the SiO2 device (κ = 3.9) to the ZrO2 device (κ = 16).

In summary, with the exception of the cutoff frequency, the performance of the

GOI MOSFET improved with the incorporation of high-κ gate dielectrics. The most

pronounced improvements were seen in the HfO2 device (note that hafnium dioxide possesses the highest dielectric constant of the materials used in this study). The HfO2 device yielded an ~16% improvement in the subthreshold slope, an ~43% improvement in the DIBL, and an ~300% increase in peak gm over the baseline SiO2 device.

- 119 -

4.2 EFFECTS OF VARIATION IN GATE OXIDE THICKNESS

The success of the semiconductor industry has relied on the continuous

downscaling of MOSFETs in order to improve integrated circuit performance and reduce

cost. One of the key dimensions of the MOSFET that has been reduced from each

technology generation to the next is the thickness of the SiO2 gate layer. In a MOSFET, the gate capacitance (Cox) is inversely proportional to the gate thickness (tox) (4.1), so that

reducing the thickness of this layer increases the capacitance of the device allowing a

greater number of charges in the channel [1] and improvement in drain current and

transconductance. In this section we will investigate the importance of the thickness of

the gate oxide layer by varying the gate thickness and examining the changes in the

device’s performance. We will present performance results for GOI MOSFETs with gate

oxide thicknesses of 0.8, 1.25, 1.5, and 2.0 nm, compared to the 1 nm tox of the baseline

structure. Again, the parameters of the simulations performed to acquire the following

results are the same as those used for the baseline structure presented in section 3.2. The

following discussion on the performance of the device will be similar to the previous

section in that the change in the gate capacitance of the MOSFET, as a result of changing the oxide thickness, will have a more pronounced affect on the device’s performance than other parameters.

As the thickness of the gate oxide of a MOSFET is increased, the gate capacitance is reduced, causing a reduction in the output current, thus increasing the threshold voltage of the device as expected from (4.3). Figure 4.7, however, is a plot of the threshold voltage of the GOI MOSFET as a function of the thickness of the gate insulator, showing

- 120 - a decreasing trend in VT. A threshold voltage of 0.47 V was obtained for the MOSFET with tox = 0.8 nm and a VT of only 0.36 V was recorded for the device with tox = 2 nm, meaning that the MOSFET experienced more than a 23% reduction in the threshold voltage with an increase in the gate oxide thickness of only 1.2 nm.

0.5

0.45 ) ge (V a

0.4 old Volt h s e r h T 0.35

0.3 0.511.522.5 Oxide Thickness (nm)

Figure 4.7 Threshold voltage of the MOSFET versus the thickness of the gate insulator layer showing an ~23% reduction in VT between the MOSFETs with tox = 0.8 nm and tox = 2 nm.

The reduction in the threshold voltage of the device shown in Figure 4.7 is again a result of the manner in which Vt was extracted from the data. Figure 4.8 (a) shows the

ID–VG characteristics of the MOSFETs with all of the different gate thicknesses. This figure shows that increasing the thickness the gate oxide decreases the output drain current at a fixed gate bias, resulting in a reduced slope and thus, a lower threshold voltage. Figure 4.8 (b) shows the ID–VG characteristics of the MOSFETs with all of the different gate thicknesses on a logarithmic scale. Similar to Figure 4.2 (b), at drain

- 121 - currents below ~10-4 A/µm, the extracted threshold voltages would follow the pattern shown in Figure 4.7, i.e., a decrease in Vt with increasing tox. However, at drain currents

above ~10-4 A/µm, the extracted threshold voltages would follow the opposite pattern and increase with increasing tox.

tox tox tox tox tox

(a)

- 122 - tox tox tox tox tox

(b)

Figure 4.8 The ID–VG characteristics of the MOSFETs with all of the different gate thicknesses on (a) a linear scale, and (b) a logarithmic scale.

Figure 4.9 is a plot of the subthreshold slope of the device as a function of the

gate oxide thickness showing a nearly linear increase in S with increasing tox. The

subthreshold slope of 105 mV/decade for the baseline device was slightly reduced to 103

mV/decade for the device with tox = 0.8 nm. However, the MOSFET with a 2 nm gate

oxide thickness yielded a subthreshold slope of approximately 131 mV/decade. The

degradation of the subthreshold slope, with increasing tox, is a result of the reduction in

the gate capacitance of the device, since S is inversely proportional to Cox (4.4). These results support the downscaling trend in the oxide thickness, which is ultimately limited by the onset of excessive tunneling of carriers to the gate.

- 123 - 140

135 ) c 130 de V/

m 125 e (

120 Slop

hold 115 s e r h

bt 110 Su 105

100 0.5 1 1.5 2 2.5 Oxide Thickness (nm)

Figure 4.9 Subthreshold slope of the MOSFET versus the thickness of the gate insulator layer showing an approximately linear increase in S with increasing tox.

Figure 4.10 is a plot of drain induced barrier lowering versus the thickness of the gate oxide layer, showing that as the tox increases, the DIBL of the device also increases.

The baseline structure reported a DIBL of ~231.9 mV/V with a tox of 1 nm, ~14% larger than the ~203.8 mV/V of the device with tox =0.8 nm. The MOSFET with tox = 2 nm yielded a DIBL value of ~350.8 mV/V, over a 50% increase compared to the baseline

GOI MOSFET. These results similarly point out the need for downscaling of the oxide thickness to reduce this short channel effect.

- 124 - 370

V) 350 V/ m

( 330 g n i r 310 we

Lo 290 ier rr 270 Ba d

e 250 c u d

n 230

ain I 210 Dr

190 0.5 1 1.5 2 2.5 Oxide Thickness (nm)

Figure 4.10 Drain induced barrier lowering of the MOSFET versus the thickness of the gate insulator layer showing an approximately linear increase in DIBL with increasing tox.

Figure 4.11 shows the peak small signal transconductance of the MOSFET versus

the thickness of the gate insulator. A significant improvement in the peak gm of the

device is observed as the thickness of the gate oxide decreases. The peak gm of the

baseline structure (tox = 1 nm) was raised from ~1602 µS/µm to nearly 1900 µS/µm by reducing tox to 0.8 nm. However, the peak gm of the MOSFET was reduced all the way

down to ~903 µS/µm for the device with tox = 2 nm. Referring back to (4.5) shows that the decrease in the transconductance of the device, with increasing tox, is primarily due to the reduction in gate capacitance, though the threshold voltage also changes as seen in

Figure 4.7.

- 125 - 2000 ) 1900 /um S 1800

nce ( 1700 1600 ducta 1500 1400 anscon

l Tr 1300 1200 1100 all Signa

m 1000 900 Peak S 800 0.511.522.5 Oxide Thickness (nm)

Figure 4.11 Peak small signal transconductance of the MOSFET as a function of the thickness of the gate insulator layer showing an ~52% reduction in gm between the MOSFETs with tox = 0.8 nm and tox = 2 nm.

The high frequency capability of the device is also modified by the change in the

oxide thickness. The peak cutoff frequency of the MOSFET steadily increases with

increasing gate oxide thickness as shown in Figure 4.12. The MOSFET with tox = 2 nm yielded a peak fT of 273.8 GHz, more than 8% larger than the 252.6 GHz peak fT reported by the baseline structure (1.0 nm), where the increase in the peak cutoff frequency of the

MOSFET is largely due to the reduction in the gate capacitance of the device. Recall that

(4.6) shows that the cutoff frequency is proportional to the small signal transconductance and inversely proportional to the gate capacitance of the device. Therefore, the increase in the fT of the MOSFET is a result of a larger decrease in the gate capacitance than the decrease in the transconductance.

- 126 - 275

270 ) Hz 265 (G y c

en 260 equ r F

f 255 f o t Cu 250 eak P 245

240 0.5 1 1.5 2 2.5 Oxide Thickness (nm)

Figure 4.12 Peak cutoff frequency of the MOSFET as a function of the thickness of the gate insulator layer showing an ~8% increase in fT between from the baseline MOSFET to the MOSFET tox = 2 nm.

In summary, the performance of the GOI MOSFET becomes increasingly better

as the thickness of the gate oxide is reduced, although the peak cutoff frequency of the

MOSFET decreases by ~3%.

4.3 EFFECTS OF VARIATION IN CHANNEL DOPING

The impurity concentration in the channel region of a MOSFET is an important

parameter to consider when designing the device. It affects the performance of the device, as well as the carrier mobility in the channel, which ultimately influences the transconductance and frequency response of the device [8][9]. In this section, we will vary the boron concentration in the channel region of the GOI MOSFET and examine the changes in the devices performance. We will present performance results for GOI

- 127 - 15 15 16 17 17 MOSFETs with channel doping (Nch) of 1 x 10 , 5 x 10 , 5 x 10 , 1 x 10 , and 5 x 10

3 16 3 /cm , compared to the 1 x 10 /cm Nch of the baseline structure. Again, the parameters

of the simulations performed to acquire the following results are the same as those used

for the baseline structure presented in section 3.2.

Figure 4.13 shows the threshold voltage of the MOSFET as a function of the

impurity concentration in the channel. At low channel doping, the threshold voltage of

the device remains at a constant value of 0.45 V. The threshold voltage then begins to

increase as the boron concentration in the channel increases to 5.0 x 1016 /cm3 and above.

A threshold voltage of 0.51 V, an ~13% increase over the baseline structure, was

obtained for the MOSFET with a channel doping of 5.0 x 1017 /cm3.

0.55 ) 0.5 ge (V a old Volt h s e

r 0.45 h T

0.4 1.0E+14 1.0E+15 1.0E+16 1.0E+17 1.0E+18 Channel Doping (1/cm^3)

Figure 4.13 Threshold voltage of the MOSFET as a function of channel doping. The VT of the device 16 3 increases, with increasing Nch , for doping concentrations above 10 /cm .

- 128 - Figure 4.14 is a plot of the subthreshold slope of the MOSFET versus the

impurity concentration in the channel region. The subthreshold slope was essentially

unaffected by the changes in the channel doping. It did not deviate more than 1% from

the value of S extracted for the baseline structure.

120

115 ) c de

V/ 110 m e (

105 Slop hold s

e 100 r h bt

Su 95

90 1.0E+14 1.0E+15 1.0E+16 1.0E+17 1.0E+18 Channel Doping (1/cm^3)

Figure 4.14 Subthreshold slope of the device, illustrating almost no dependence on the channel doping.

Figure 4.15 shows the drain induced barrier lowering of the MOSFET as a

function of the channel doping. The overall trend of the DIBL seems to be a slight

16 3 decrease with increasing channel doping. However, at Nch = 1 x 10 /cm , the DIBL peaks at a maximum value of 231.9 mV/V, before decreasing again. The MOSFET with the highest channel doping in this study experienced an approximate 5% reduction in

DIBL compared to the baseline structure.

- 129 - 245

V) 240 V/ m ( g n

i 235 r we 230 Lo ier rr 225 Ba d e c

u 220 d n

ain I 215 Dr

210 1.0E+14 1.0E+15 1.0E+16 1.0E+17 1.0E+18 Channel Doping (1/cm^3)

Figure 4.15 Drain induced barrier lowering of the MOSFET versus the impurity concentration in the channel. The DIBL continuously decreases in the devices with channel doping higher than 1 x 1016 /cm3.

Figure 4.16 shows the peak small signal transconductance of the MOSFET versus

the channel doping. A slight reduction in the peak gm of the device is observed as the

doping in the channel region increases. The peak gm of the baseline structure was

17 3 reduced from ~1602 µS/µm to ~1590 µS/µm by increasing Nch to 5 x 10 /cm . This reduction in the peak gm is very small, less than 1%, and likely due to a reduction of the

carrier mobility in the channel due to increased impurity levels.

- 130 - 1610 ) /um S nce (

1600 ducta anscon l Tr

1590 all Signa m

Peak S 1580 1.0E+14 1.0E+15 1.0E+16 1.0E+17 1.0E+18 Channel Doping (1/cm^3)

Figure 4.16 Peak small signal transconductance of the GOI MOSFET as a function of the channel doping. A decrease in the peak gm of less than 1% is observed as the channel doping is increased to 5 x 1017 /cm3.

Figure 4.17 shows the peak cutoff frequency of the MOSFET as a function of the

impurity concentration in the channel. At low channel doping, the peak fT of the device

remains nearly constant around 252 GHz. The peak cutoff frequency then begins to

slowly decrease as the boron concentration in the channel increases to 5.0 x 1016 /cm3 and above. A peak fT of 243.1 GHz, an ~4% decrease compared to the baseline structure, was obtained for the MOSFET with a channel doping of 5.0 x 1017 /cm3.

- 131 - 260 )

Hz 255 (G y c en equ

r 250 F f f o t Cu

245 eak P

240 1.0E+14 1.0E+15 1.0E+16 1.0E+17 1.0E+18 Channel Doping (1/cm^3)

Figure 4.17 Peak cutoff frequency of the MOSFET as a function of channel doping. The peak fT of 17 3 the device decreases to ~243.1 GHz for Nch = 5 x 10 /cm .

Increasing the channel doping of the baseline GOI MOSFET to 5 x 1017 /cm3 had very little effect on the performance of the device. The threshold voltage of the device increased ~13% while the drain induced barrier lowering and peak cutoff frequency were reduced by 5% and 4%, respectively. The subthreshold slope and peak small signal transconductance remained essentially unchanged with variations of less than 1%. The overall trends in the device performance did, however, reveal that further increases in the channel doping would result in degradation in the performance of the MOSFET by increasing VT, and decreasing both the peak gm and peak fT.

- 132 - 4.4 EFFECTS OF VARIATION IN CHANNEL LENGTH

The channel length (LC) of a MOSFET is arguably the most important parameter in device design, in fact, it is the channel length that defines a particular technology generation. Although it affects nearly every aspect of the device performance, it is the speed of the device that is most directly related to the channel length. The speed of the device is inversely proportional to the length of the channel, thus, downscaling LC will

result in a higher speed device. However, when reducing LC, one must be concerned with the increasing electric fields within the device. These high fields can lead to short channel effects, hot electron effects, or various other problems resulting in degradation of the device’s performance [7]. In this section we will investigate the importance of the channel length of the MOSFET by varying this length and examining the changes in the device’s performance. We will present performance results for GOI MOSFETs with gate lengths of 10, 20, 30, and 60 nm, compared to the 40 nm LC of the baseline structure.

Once again, the parameters of the simulations performed to acquire the following results are the same as those used for the baseline structure presented in section 3.2.

Figure 4.18 is a plot of the threshold voltage of the device as a function of the channel length. As expected, the threshold voltage decreases as the length of the channel becomes shorter, a well known short channel effect. It is shown in the plot that the 60 nm device yields a reasonable VT of 0.51 V, which gradually declines to 0.40 V for the 30 nm device. The VT then rapidly decreases to 0.28 V for the 20 nm device and falls below

0 V for the 10 nm MOSFET. This relationship between the threshold voltage and channel length, i.e., the threshold voltage of the device decreases as the channel length is scaled down, is commonly referred to as a short channel effect and is a result of charge

- 133 - sharing between the source/drain and gate [7]. This creates problems in circuit design

where MOSFETs of various channel lengths are incorporated.

0.6

0.5

0.4 )

ge (V 0.3 a

0.2 old Volt h

s 0.1 e r h T 0

-0.1

-0.2 0 10203040506070 Channel Length (nm)

Figure 4.18 Threshold voltage of the MOSFET as a function of the channel length showing a decrease in VT with decreasing channel length, more commonly known as the short channel effect.

The subthreshold slope versus the channel length of the MOSFET is shown in

Figure 4.19. A subthreshold slope of 78 mV/decade was obtained for the 60 nm device,

which is more than a 25% improvement over the baseline MOSFET. However, this

subthreshold slope continuously increases with decreasing channel length and nearly

doubles for the 30 nm device. Below 30 nanometers, the S of the device increases

extremely fast to an excessively large value of over 700 mV/decade for the 20 nm device.

The subthreshold slope of the 10 nm device could not be extracted due to poor ID –VG characteristics. This degradation in the subthreshold slope is another characteristic short

- 134 - channel effect and is due to the loss of gate in controlling the charge in the channel due to

the close proximity of the source and drain.

750 700 650 )

c 600

de 550 V/

m 500

e ( 450 400 Slop 350 hold

s 300 e r

h 250 bt 200 Su 150 100 50 0 10203040506070 Channel Length (nm)

Figure 4.19 Subthreshold slope of the MOSFET as function of the channel length. Reasonable values of S were obtained for channel lengths of 30, 40, and 60 nm, however, below 30 nm the subthreshold slope drastically increased due to hot electron effects.

Figure 4.20 is a plot of drain induced barrier lowering versus the channel length,

showing that as LC decreases, the DIBL of the device increases dramatically. The

baseline structure reported a DIBL of ~231.9 mV/V with LC of 40 nm, more than two and

a half times larger than the ~92.0 mV/V of the 60 nm device. However, the MOSFET

with LC = 30 nm yielded a DIBL value of ~431.5 mV/V, nearly twice than that of the baseline GOI MOSFET. Due to poor ID –VG characteristics for the devices with channel

lengths less than 30 nm, the DIBL was unable to be extracted. DIBL is due to

undesirable electrostatic interactions between the source and the drain and is another of

- 135 - the short channel effects. Reducing the channel length of a MOSFET can increase these

interactions resulting in an increase in drain induced barrier lowering [8]. For all of these

short channel effects, the addition of a second gate, i.e., a double gate MOSFET, is

known to be needed to adequately control these undesirable effects [10].

500

V) 450 V/

m 400 ( g n i 350 r

we 300 Lo

ier 250 rr

Ba 200 d e c 150 u d n 100 ain I 50 Dr

0 0 10203040506070 Channel Length (nm)

Figure 4.20 Drain induced barrier lowering as a function of channel length showing a drastic increase in DIBL as the channel length is scaled down.

Figure 4.21 shows the peak small signal transconductance of the MOSFET versus

the length of the channel. The peak gm of the device steadily increases with decreasing

channel length as expected since gm is inversely proportional to the gate length.

However, around the 20 nm mark, the peak gm reaches its maximum and then declines by

~4%. The peak gm of ~1528 µS/µm, recorded for the 60 nm device, increased to a maximum value of ~1660 µS/µm for a channel length of 20 nm, and then decreased to

~1599 µS/µm for LC = 10 nm. The initial improvement in the peak small signal

- 136 - transconductance of the MOSFET is likely due to the fact that the transconductance of

the device is inversely related to the channel length, as shown in (4.5).

1700 )

/um 1675 S

nce ( 1650

ducta 1625

1600 anscon l Tr 1575

1550 all Signa m 1525

Peak S 1500 0 10203040506070 Channel Length (nm)

Figure 4.21 Small signal transconductance of the MOSFET as a function of channel length showing a steady increase with decreasing channel length until about the 20 nm mark, where the peak gm reaches a maximum of ~1660 µS/µm and then rapidly declines.

The peak cutoff frequency of the MOSFET steadily increases with decreasing

channel length, as shown in Figure 4.22. Recall that the baseline MOSFET, with LC = 40 nm, yielded a peak fT of 252.6 GHz. This value increased nearly 32% to 332.3 GHz for

the 30 nm device, and more than 80% to 454.7 GHz for the 20 nm device. The drastic

increase in cutoff frequency with decreasing channel length is expected since they are

inversely related. However, the increase in fT is not only a function of the decreasing channel length, but also, of the increasing transconductance of the device, since fT is

proportional to gm. Another way to describe the relationship between the cutoff

- 137 - 1 gm 1 T T m frequency and channel length is that f ∝ 2 since f = and g ∝ and L 2π CGS L

CGS ∝ LW .

800 750 700 ) 650 Hz 600 (G y

c 550

en 500 equ

r 450 F

f 400 f o t 350 Cu 300

eak 250 P 200 150 100 0 10203040506070 Channel Length (nm)

Figure 4.22 Cutoff frequency of the MOSFET versus the length of the channel, showing drastic increases in fT as LC decreases.

Reducing the channel length of the baseline GOI MOSFET just 10 nm resulted in

an ~32% increase in fT, as well as a slight increase in the transconductance of the device.

However, scaling down the channel length of the GOI MOSFET did result in some performance tradeoffs. While shorter channels lengths allowed improvements in the transconductance and cutoff frequency of the device, short channel effects lead to degradation in the subthreshold slope and DIBL. These negative effects of scaling, however, can be minimized with the addition of a second gate to the device.

- 138 - 4.5 SUMMARY AND CONCLUSIONS

In this chapter, the various structural parameters which affect the performance of

the GOI MOSFET have been analyzed. While the performance of this device can be

enhanced, certain performance trade-offs must be considered when designing the

MOSFET.

As a result of increased gate capacitance, nearly all aspects of the performance of

the GOI MOSFET improved with the incorporation of high-κ gate dielectrics. Compared

to the baseline device, the hafnium dioxide (HfO2) device yielded an ~16% improvement in the subthreshold slope, reduced the DIBL by ~43%, and more than tripled the peak gm.

However, the peak fT obtained for the HfO2 device was approximately 21% less than that of the baseline structure. One way to increase the peak cutoff frequency of the device is to increase the thickness of the gate oxide layer. Doubling the gate oxide thickness of the

baseline structure reduced the gate capacitance, which resulted in an ~8% increase in the

peak fT . However, increasing the oxide thickness also resulted in an ~25% higher

subthreshold slope, ~51% higher drain induced barrier lowering, and ~44% lower

transconductance. Therefore, along with minimizing the reduction of fT, the performance

benefits acquired through the incorporation of high-κ dielectrics would be somewhat

overshadowed by increasing the gate insulator thickness.

The effect of variation in the channel doping on device performance was minimal.

Increasing the channel doping of the baseline GOI MOSFET to 5 x 1017 /cm3 increased

VT by ~13% while the DIBL and peak fT experienced reductions of 5% and 4%, respectively. The subthreshold slope and peak gm of the device were nearly unaffected by the change in channel doping. The overall trends in the device performance did,

- 139 - however, reveal that further increases in the channel doping would result in degradation

in the performance of the MOSFET by increasing VT, and decreasing both the peak gm and peak fT.

Scaling down the channel length of the baseline GOI MOSFET resulted in significant increases in the speed of the device. The cutoff frequency of the device increased by nearly 32% and by more than 80% for the MOSFETS with channel lengths of 30 nm and 20 nm, respectively. However, short channel effects lead to serious reduction in the threshold voltage along with degradation in the subthreshold slope and

DIBL. It is important to note that, although, the channel length of the device was scaled down, the rest of the device remained unchanged for this study. Therefore, some of the negative effects discussed above can be minimized by properly scaling the entire device.

As a final note, while this study examined the effects of substituting Ge for Si in the channel for the MOSFET, double gate (FinFETs) are an alternative approach to

MOSFET redesign that enable better control of the short channel effects [10].

Ultimately, a Ge channel FinFET may be a more attractive device that either a Ge channel planar MOSFET or a silicon channel FinFET.

- 140 - BIBLIOGRAPHY

[1] M. Houssa, “High-κ Gate Dielectrics,” Institute of Physics Publishing,

Pennsylvania, USA, 2004.

[2] H. Shang, H. Okorn-Schmidt, J. Ott, P. Kozlowski, S. Steen, E. C. Jones, H.-S. P.

Wong, and W. Hanesch, “Electrical Characterization of Germanium p-Channel

MOSFETs,” IEEE Electron Device Letters, Vol. 24, No. 4, pp. 242-244, April 2003.

[3] Chi On Chui, Hyoungsub Kim, David Chi, Baylor B. Triplett, Paul C. McIntyre, and

Krishna C. Saraswat, “A Sub 400°C Germanium MOSFET Technology with High-κ

Dielectric and Metal Gate,” IEDM Technical Digest, pp. 437-440, December 2002.

[4] A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L.

Kwong, and D. A. Antoniadis, “Epitaxial Strained Germanium p-MOSFETs with

HfO2 Gate Dielectrics and TaN Gate Electrode,” IEDM Technical Digest , pp. 433–

436, December 2003.

[5] ISE TCAD Release 8.5, ISE Integrated Systems Engineering AG, Zurich,

Switzerland, 2003.

[6] A. Khakifirooz, A. Ritenour, and D. A. Antoniadis, “RTP Growth of Germanium

Oxynitride for MOSFET Fabrication,” Massachusetts Institute of Technology,

Microsystems Technology Laboratories, Annual Research Report 2004-2005:

Emerging Technologies, pp. 68, 2004-2005.

[7] Ben G. Streetman and Sanjay Banerjee, “Solid State Electronic Devices,” Prentice

Hall, New Jersey, USA, 2000.

- 141 - [8] Yaun Taur and Tak H. Ning, “Fundamentals of Modern VLSI Devices,” Cambridge

University Press, Cambridge, UK, 1998.

[9] S. M. Sze, “Physics of Semiconductor Devices, Second Edition,” John Wiley &

Sons, Inc., New York, USA, 1981.

[10] Edward J. Nowak, Ingo Aller, Thomas Ludwig, Keunwoo Kim, Rajiv V. Joshi,

Ching-Te Chuang, Kerry Bernstein, and Ruchir Puri, “Turning Silicon On Its

Edge,” IEEE Circuits & Devices Magazine, Vol. 20, No. 1, pp. 20-31,

January/February 2004.

- 142 - CHAPTER 5

CONCLUSIONS AND FUTURE WORK

5.1 CONCLUSIONS

In this study, we have investigated the performance capabilities and scaling behavior of germanium-based n-MOSFETs. Experimental long-channel Ge MOSFETs have shown improvements in the device’s output drain current, effective mobility, and small signal transconductance, compared to similar silicon devices. The simulation results obtained in this study for long channel Ge devices also showed improvements in these areas of the device’s performance, as well as considerable increases in the cutoff frequency and maximum frequency of oscillation. The simulated ID and gm of the long channel Ge MOSFET was nearly twice than those of the Si device, while the fT and fmax of the Ge FET were 2X and 3X those of the Si FET, respectively. The superior performance of the long channel Ge devices, which is primarily due to considerably larger carrier mobilities in Ge, offered promise that short channel Ge MOSFETs would also outperform their Si counterparts. In the simulated short channel devices, however, the baseline germanium-on-insulator MOSFET exhibited performance that was inferior to the SOI device in nearly every aspect. The SOI device exhibited better subthreshold characteristics as well as output drain currents at least 12% larger than those of the GOI

FET. The SOI FET also yielded a 15% larger transconductance and 20% larger cutoff frequency over the Ge device. Both the SOI and GOI MOSFET achieved high lateral

- 143 - electric fields in the saturation region of device operation, causing the electron velocity in

the channel to saturate. As a result, the performance of the Ge device was poorer due to

the smaller saturation velocity of electrons in germanium, relative to silicon.

The structure of the baseline device was then varied in order to optimize the GOI

MOSFET’s performance. The SiO2 gate insulating layer of the baseline device was

replaced by various high-κ materials. The resulting increase in the dielectric constant of

the gate insulator was found to significantly increase the gate capacitance of the GOI

MOSFET, thereby, raising the output drain current and small signal transconductance of

the device, while reducing the subthreshold slope and drain induced barrier lowering.

The device with a HfO2 gate layer achieved a subthreshold slope of ~88 mV/dec and a

transconductance of ~4750 µS/µm, nearly three times that of the baseline device.

However, the increase in the gate capacitance of the device also resulted in a modest reduction in the peak cutoff frequency. Increasing the thickness of the gate insulating layer from 1 nm to 2 nm increased the peak cutoff frequency of the baseline device by

8% to 273.8 GHz. However, the degradation to the DIBL and peak gm overshadowed the

enhancement of the peak fT.

The performance of the MOSFET was also examined as a function of the boron

concentration in the channel. The effect of variation in the channel doping on device

performance was minimal. The DIBL and peak fT of the device experienced reductions of 5% and 4%, respectively, while the subthreshold slope and peak gm were nearly unaffected by the change in channel doping. The overall trends in the device performance did, however, reveal that further increasing the channel doping would result

- 144 - in degradation in the performance of the MOSFET by increasing VT, and decreasing both the peak gm and peak fT.

Finally, the scaling behavior of the GOI MOSFET was examined by reducing the

channel length of the device and studying the effects on the device’s performance.

Reducing the channel length of the baseline GOI MOSFET from 40 nm to 30 nm

increased the peak cutoff frequency from 252.6 GHz to 332.3 GHz. The peak

transconductance of the device also increased with decreasing channel length. However,

scaling down the channel length of the GOI MOSFET did result in some performance

tradeoffs. While shorter channels lengths allowed improvements in the peak gm and fT of the device, short channel effects lead to serious degradation in the subthreshold slope and

DIBL. Although, the channel length of the device was scaled down, the rest of the device remained unchanged for this study. Therefore, the degradation in performance due to short channel effects can be minimized by properly scaling the entire device.

In conclusion, while the preliminary modeling results of this study for long channel devices showed superior performance of the germanium MOSFET when compared to a similar Si device, it was later shown for short channel devices that the performance of the GOI MOSFET did not exceed that for the SOI device due to the smaller saturation velocity for electrons in Ge. The preliminary results regarding the scaling behavior of Ge devices show considerable enhancements in the frequency response of the transistor. However, at present, the GOI MOSFET is not quite ready to replace the SOI MOSFET for CMOS applications due to these velocity saturation effects.

- 145 - 5.2 FUTURE WORK

While the device characteristics and performance results presented in this thesis are reasonable, initial predictions of what can be expected in fabricated structures, a further investigation into the carrier transport properties in germanium could be beneficial by providing a more accurate model of device behavior and operation. In particular, a closer examination of the carrier mobilities and velocities in high electric fields, both lateral and transverse, could provide a more precise description of the physics within the device, enabling a more realistic prediction of the device’s performance.

Additional device modeling needs to be carried out to study the effects of incorporating strain into the channel region of Ge MOSFETs. Strained-germanium may possess significantly better transport properties than silicon and strained-silicon.

Recently, IBM announced that they have discovered a method to fabricate strained- germanium channel MOSFETs that is compatible with conventional CMOS technology.

While a strained-Si device improved the output current of a similar unstrained-Si device by 10 to 30%, these strained-germanium channel devices offered more than a 200% improvement in the output current over the unstrained device [1]. IBM believes that this new technique could help ensure continued performance improvements in chips with circuit sizes of 32 nm and smaller [2]. However, it is not completely understood how the incorporation of strained-germanium will affect other areas of the device or circuit.

Therefore, modeling these devices could provide useful insight into the advantages and challenges of incorporating strain into the channel region of germanium MOSFETs.

- 146 - BIBLIOGRAPHY

[1] Linda Geppert, “Putting Germanium in a Vise,” IEEE Spectrum Online, February

2005. (http://www.spectrum.ieee.org/feb05/2933)

[2] IBM Research, IBM, NY. (http://www.research.ibm.com)

- 147 -