Jack Kilby Dedication

There are few living men whose insights and professional accomplishments have changed the world. Jack Kilby is one of these men. There are few living men whose insights and professional accomplishments have changed the world. Jack Kilby is one of these men. His invention of the integrated circuit — the intellectual property policies by guiding microchip — some 30 years ago at Texas their formulation and participating in their Instruments (TI) provided the conceptual implementation. More recently, he proposed and technical foundation for modern micro- the Landmark Innovation Award the first of electronics. This was the key breakthrough which was presented by Mr. Kilby to Prof. that enabled the high-speed , Farhang Shadman at TECHCON 2000. More large-capacity memories, importantly, Jack has made himself available network appliances, and complex controllers to consult and guide SRC throughout its nine- that characterize today’s information age. teen-year existence. He has been, and is, an On December 10, 2000, Mr. Kilby was important part of the successful development awarded the Nobel Prize in Physics for his of cooperative research in semiconductor pioneering and revolutionary work. technology.

Jack Kilby has been an integral part of SRC’s In recognition of his lifetime of accomplish- evolution. He participated actively in SRC’s ments, of the recognition of his achievements summer studies in which he provided key per- through award of the Nobel Prize, and his spectives in debates on strategic organization contributions to cooperative research in directions and seminal insights on semicon- , the Semiconductor Research ductor technology issues. Jack also played Corporation dedicates this annual report to a key role in the development of SRC’s Jack S. Kilby. SRCTable of Contents 2000 Jack Kilby Dedication ...... inside front cover Message from the President/CEO ...... 2 About SRC ...... 3-4 Research Contributions ...... 5-13 TECHCON 2000 & Awards ...... 14-17 Student Programs ...... 18-19 Industrial Liaison Program ...... 20 2000 Value Delivery ...... 21 SRC Copper IC Design Challenge ...... 22 SRC Web site ...... 23 Industry Assignee Program ...... 24-25 Intellectual Property ...... 26-27 MARCO’s Focus Center Research Program ...... 28 Financial Report ...... 29-35 SRC Member List ...... 36 SRC Board Members & OCE . . . . . inside back cover

Mission SRC’s mission is to cost-effectively exceed members’ expectations by delivering:

Vision • Managed, innovative, semiconductor technology Semiconductor Research research responsive to members’ needs and Corporation (SRC) will provide guided by the ITRS, focusing on universities competitive advantage to its • Relevantly educated university graduates members as the world’s premier • Timely transfer of research results research management consortium in delivering relevant research • Strengthened university semiconductor technology results and relevantly educated capability through partnerships with members technical talent. • Collaboration to enhance commercialization and leveraged research.

The annual report of the Semiconductor Research Corporation is published each year to summarize the directions and results of the SRC research program, present the formal financial report and provide information on activities and events of the SRC community for the previous calendar year. A copy of this report and additional information about SRC are accessible on the World Wide Web at http://www.src.org. Message from the President/CEO

The year 2000 was a great one for SRC, and our June board retreat provided pivotal guidance for SRC as it evolves into a fully We also committed new resources, staff global research management consortium. and priority status to the SRC Education Alliance to help address the projected It seems that each SRC board retreat gets shortfall of talented scientists and engi- better, but last June’s retreat was clearly neers throughout the world. We instituted our best ever. SRC is an organization an undergraduate research program in where its owners are its customers. The cooperation with the Semiconductor Board, to be most effective, needs to Industry Association (SIA) and we recom- examine policy issues from the standpoint mitted our efforts to increase the number of both owners — where the Board is a of SRC-supported graduate students who “steward” of SRC; and as a customer — become employed by member companies. where each Board member wants to see its company receive maximum value for As stewards, our board recognized the each dollar invested in its member fee. necessity for a much stronger SRC to tackle the increasingly complex demands As SRC’s customers, our board reiterated of the International Technology Roadmap the importance of maximizing benefits to for Semiconductors. The board each SRC member company. In that spirit, recognized the importance of not only SRC began to examine new programmatic expanding SRC’s international member- structures and more flexible research ship to increase our research budget and program participation. Our goal is to reduce the “research funding gap” in enable member companies to optimally addressing the major global technology customize their research choices accord- challenges and barrier issues, but also to ing to each company’s interests, while better enable a broader collaboration to maintaining a strong, viable core research include the best researchers in the world. program with high value for all members. Through a broad globalization effort, to include new member companies, university researchers worldwide, enhanced coordi- nation with global consortia, and potential leveraged funding from governments in other regions of the world, the SRC Board of Directors has clearly outlined a broad globalization strategy for SRC. This strategy will not only enable SRC to keep pace with the internationalization efforts of its members but to continue to be a leader among other research consortia throughout the world.

Sincerely,

Larry W. Sumney

2 About SRC PIONEERS IN COLLABORATIVE RESEARCH

needed to maintain the aggressive pace of Moore’s Law. Recent editions of the ITRS point out that the “red” areas — technical challenges for which there are no known solutions — are increasing in number and are encroaching in time. In addition to the technological chal- lenges, the semiconductor industry also faces a potentially critical shortfall in scientists and engineers in the future. These challenges are global and require Pictured left to right during a press conference at UMC: Ralph Cavin, Dinesh collaboration among semiconductor Mehta and Larry Sumney of SRC and Robert Tsao, John Hsuan and Fu-Tai Liou of UMC. companies worldwide. SRC has developed core competencies and a model of collaborative research that More than 18 position the consortium to address years ago, leaders these challenges. In response to these of the semiconductor challenges and based on SRC capabili- industry, decided to ties, the SRC Board decided to expand launch SRC to establish and nurture its membership to non-U.S. companies North American University research starting in the year 2000. At their annual capability in semiconductor technolo- Board Retreat in June 2000, the SRC gies. This was an important decision to Board authorized SRC to expand address several critical issues such as the research performer base to non- the weakened competitive position of North American universities. Thus, we the U.S. semiconductor companies in have begun the process of complete market and technology; inability of globalization of SRC. these companies to invest significantly in long-term research individually; lack In the broader context of a global SRC, of U.S. government support for we have continued to focus on the cre- research in silicon-based technologies; ation of four “products.” These are and resulting lack of university research Research Results, Relevantly Educated capability. Since formation, SRC Talent, Integrated University Research has consistently produced excellent Capability, and Networking. We have research results and trained more also continued to hone processes and than 3000 scientists and engineers who tools associated with the delivery of have helped make the semiconductor SRC value to the member companies. industry a strong and vital part of the Mechanisms and support are also electronic revolution. provided to facilitate our member com- panies’ ability to extract maximum value The semiconductor industry has in a most cost-effective manner. Finally, become global. In addition to we work with the representatives of our establishing distributed marketing and member companies on the Board of manufacturing capability, semicondutor Directors and various advisory boards companies are also creating global to continuously revitalize our products, R&D presence. Semiconductor compa- programs, processes and systems to nies from many regions of the world enhance value for our members. have decided to cooperate in the devel- Several examples of the dynamic nature opment of the International Technology our business and the value that the Roadmap for Semiconductors (ITRS), community of our consortium has which identifies the technologies brought about in the year 2000 are

3 About SRC

presented in various sections of this these awards, the Landmark report. Some of the key accomplish- Innovation Award, presented by ments, major initiatives and important Mr. Jack Kilby, who was selected events of the year 2000 which demon- to receive the Nobel Prize in 2000 strate the value, the strength and agility of (inside front cover). the consortium include: • Culmination of “Cu Design Contest,” conducted in collaboration with • A strong research program which is UMC, Novellus, SpeedFam-IPEC, aimed at addressing major techno- with outstanding results (page 22). logical challenges the industry faces • A very productive set of workshops for technology nodes (pages 5-13). conducted in for the technical • A highly beneficial and productive set community of UMC and Taiwan of student programs and a high rate Universities. of assimilation of the graduates in • Strong participation by the member the year 2000 within the SRC com- companies in the Industry Assignee munity (pages 18-19). Program (page 24-25). • Successful completion of the Pilot • Launching of a completely phase of the first two Focus Centers redesigned Web site which has many managed by MARCO (a subsidiary of more features such as online collabo- SRC) and the decision to initiate two ration capability, etc. (page 23). new Focus Centers in the year 2001 • Creation of a database of the (page 28). Intellectual Property portfolio • A phenomenally successful TECH- (page 26-27). CON 2000, our biennial technical • A set of three new initiatives to conference which showcased the increase the pool of undergraduate best of our research and students engineering students in semiconductor performing the research (page 14-17). technology related disciplines. These • Some of the highly coveted awards initiatives, approved and funded by that recognize the contributions of SIA, are managed through the SRC various constituents of the SRC Education Alliance, an arm of SRC community (pages 16-17). One of (page 18-19).

Robert Tsao, Chairman, UMC (left) and Larry Sumney, President and CEO, SRC at a banquet to celebrate the Taiwanese company’s recently announced SRC membership

4 Research Contributions

SRC’S RESEARCH AGENDA The SRC university research program is focused on the critical technology barriers to the continued exponential performance-cost cadence of Moore’s Law as identified by the 2000 • Develop materials for thin, low- International Technology Roadmap for leakage gate dielectrics; and for Semiconductors (ITRS). In addition, high-conductivity gate electrodes. SRC is conducting several exploratory programs that seek to obtain radical Bulk CMOS may extend to 35 nm solutions to ITRS challenges. In the (physical gate length) with new gate following, perspectives are given on the stack materials and source/drain response of the highly productive process technologies. Non-bulk SRC research program to pacing tech- MOSFET structures may extend CMOS nology challenges. SRC acknowledges to physical gate lengths of 10nm. its excellent partnerships with NSF, DARPA, International SEMATECH and the State of New York in support of some of the programs described herein. EXTENDING CMOS SRC Research is directed toward: • Extensions of bulk and their associated materials and processes; • Continued scaling of non-bulk MOSFETs gate lengths less than Prototypical MOSFET 10 nm; • MOSFET modeling and simulation.

Challenges to the continued scaling of BULK CMOS CMOS transistors include the ability to: Bulk CMOS research focuses on new • Maintain a constant threshold gate stack materials and ultra-shallow voltage as MOSFETs scale to source/drain junction structures that nano-scale dimensions (short extend scaling to the 70 nm technology channel effect); node and beyond. The Front End • Develop hyper-abrupt lateral and Processing Research Center (FEP-RC) vertical doping profiles, with super at North Carolina State University metastable doping concentrations; addresses formation and properties of • Provide extremely shallow ultra-thin high-k gate stack dielectrics source/drain extensions with low and their interfaces, and alternative sheet resistance; high-conductivity gate materials to • Mitigate the effects of channel replace poly-silicon gates and solve dopant fluctuation; the poly-silicon depletion problem related to ultra-thin gate dielectrics.

5 Research Contributions

NANO-SCALE CMOS: MODELING AND SIMULATION The device modeling and simulation research agenda includes: • Quantum confinement and quantum transport in heterostructure channels; • Direct and Fowler-Nordhiem carrier Promising replacements for n+-poly- tunneling through ultra-thin gate silicon include Ta, TaN , and TaSi N , x x y dielectrics; and for p+-poly-silicon, Ru and Ru0 . 2 • Strain effects on band structures; Initial studies at University of California/ • Incorporation of quantum effects Berkeley show that Mo and N implanted into semi-classical models; and Mo are viable gate electrode candidates. • Computational techniques for 3-D NON-BULK CMOS simulators. Complementary non-bulk CMOS Approaches include: approaches to a viable double-gate • 2-D atomic level quantum mechanical MOSFET platform structure are being approaches (Purdue University); investigated to reduce short channel • Efficient 3-D Monte Carlo semi- effects in the 10 nm regime. MIT is classical techniques (University of investigating wafer bonding and self Illinois/Urbana-Champaign); aligned ion-implantation; University of • Combined analytical expressions California/Berkeley uses e-beam litho- for tunneling with a unique numeri- graphic alignment and selective cal 2-D Poisson solver that places processing; and Purdue University, the source, drain and gate on an selective epitaxy and epitaxial lateral equal footing to the channel overgrowth to achieve self alignment. (SUNY/Stony Brook). The potential of strained Si and SiGe (MIT) and graded, strained SiGeC These studies are showing, for example, (University of Texas/Austin) for enhancing that MOSFETs with sub 10 nm physical channel mobility in advanced MOSFET gate lengths provide good performance structures is also being examined. These (if a channel mobility up to 400 cm2/sec different approaches to a double-gate can be realized) and that quantum MOSFET provide very different platform transport along the channel is primarily structures to study experimentally the related to tunneling through the properties of structures and materials. source/drain barrier.

Prototypical double-gate MOSFET

6 Research Contributions

INTERCONNECT SOLUTIONS FOR FUTURE GENERATION IC SYSTEMS The 1997 ITRS identified global inter- connects — where signals often cannot propagate for long distances without TECHNOLOGY SOLUTIONS unacceptable delays, cross-coupling, The Back-End Processes Thrust seeks and/or clock skew as a critical problem. technology solutions to the interconnect At and beyond the 70 nm node, die challenge through innovations in sizes and frequency requirements are copper-low K, and non-contact inter- incompatible with even the most connect using optical or RF/microwave optimistic design, packaging, and tech- links, 3-D devices and chip stacking, nology projections. Radical changes in and radical alternatives such as the approaches to IC design, process- nanotubes and nanowhiskers. These ing and packaging are required. projects are defining fundamental limits for copper-low K technologies DESIGN SOLUTIONS and resolving issues involved in other Near-term approaches include tech- advanced technologies. niques to optimize interconnect routing, minimize crosstalk, and analyze signal and power bussing. Longer-term COST-EFFECTIVE research addresses system and device NANOSCALE PATTERNING design methodology and architectures. SRC supports foundational research in For example, the University of semiconductor patterning to enable: Minnesota is developing hierarchical power network analysis methods • MOSFET scaling at and beyond the for handling power grids with 20 50 nm ITRS technology node; million nodes and the University of • Radical high performance, high California/Los Angeles is focused on throughput, low-cost alternatives to interconnect planning and wire width conventional IC patterning technology; optimization. • Increased functional density both on the chip and within nanostructures. PACKAGING SOLUTIONS Advanced packaging and interconnect Patterning research anticipates future systems using capacitive and RF manufacturing requirements and coupling into the package, reducing addresses strategic technology pin count, and improving system challenges. performance are being investigated at North Carolina State University and the University of California/ Los Angeles. Novel inter-chip and intra-chip communications and signaling protocols are being developed at the Universities of Massachusetts and Toronto for noise reduction, efficient power delivery, and high system throughput.

7 Research Contributions

• EUV Lithography and Actinic Wavefront Metrology: University of California/Berkeley has developed an EUV interferometer with unprecedented accuracy for EUV lithography as well as techniques to OPTICAL LITHOGRAPHY counter carbon contamination SRC research in 193 nm wavelength • Image Formation Modeling and lithography has removed the perceived Verification: barrier at the 100 nm node for optical University of Wisconsin has noted patterning. Today’s challenge is to that thick EUV masks have unique extend optical lithography below the influences on image formation and 65 nm node. Current research were the first to carry out the com- addresses sources, optical compo- plicated modeling of such effects. nents, masks, resists, predictive • E-Beam Lithography: pattern transfer models, and trade- Stanford University research offs for 193 nm, 157 nm, and 127 nm has demonstrated that global wavelengths for patterning beyond 65 space charge effects represent a nm ITRS technology requirements. significant technical challenge for electron projection lithography. NEXT GENERATION LITHOGRAPHY (NGL) MASKLESS AND NON- The current strategy is to replace optical LITHOGRAPHIC PATTERNING lithography for critical layers beyond Increasingly complex mask challenges the 65 nm ITRS node. Two candidates require high throughput, high perform- for the sub-65 nm domain are Extreme- ance, and low-cost patterning options, Ultra Violet (EUV) and Electron such as maskless or step-and-flash Projection Lithography (EPL). patterning. SRC/DARPA cooperative Noteworthy results include: research addresses five maskless pat- • Capillary Discharge: terning options, each requiring delivery University of South Florida has of a tremendous amount of information developed this leading candidate in real time to individual pixels. for future lithography. Consequently, research focuses on managing the flow of data, and enabling delivery of a terabyte of information per second. Step-and-Flash patterning exploits capillary processes that enable nanoscale injection molding.

SRC research is continuing to explore other low-cost enabling material and technology options; functional den- drimers, defect tolerant patterning, heterogeneous self assembly, e.g., controlled directed nanotube growth. Prototype EUV discharge source developed under SRC support. This source was transferred to the EUV LLC.

8 Research Contributions

RESISTS Recent significant resist-related results include: • Molecular Level Simulation of the Lithographic Process: University of Texas/Austin founda- METROLOGY tional research on resist chemistry Advanced Techniques for E-beam is resulting in a potentially com- Metrology: prehensive probabilistic model for University of Tennessee/Knoxville the formation of imaged features researchers are exploring fundamental during development, based on the challenges in ultra-low voltage e-beam design and structure of individual imaging and dynamic charging; and are components. developing a point projection micro- scope for non-destructive nanoscale 3-D metrology. They recently reported the first reconstructed 3-D images of 100 nm features from the nanoscale point projection microscope. HIGH PERFORMANCE, ENVIRONMENTALLY Predictive model of image information based on designed resist components. BENIGN PROCESSES The agenda of the SRC/NSF • Photoresist Material Process: Engineering Research Center (ERC) in University of Wisconsin has investi- Environmentally Benign Semiconductor gated the problem of the collapse Manufacturing is focused on future of high aspect ratio photoresist manufacturing facilities with minimal features, documented the reasons consumables (e.g. water, energy, acids, for collapse, and presented tech- solvents, and gases) and minimum niques for avoiding it. emission of waste materials. The ERC’s • Dendrimer-Based Chemically program currently consists of: Amplified Resist Materials: • Back-End Processes, with empha- University of California/Berkeley sis on replacing perfluorocom- has demonstrated sub-100 pattern- pound chemistries for dielectric ing with novel dendrimer-based wafer etch, PECVD chamber resist materials. cleaning processes, slurry waste from CMP processes, and low-K dielectric technology for interconnect systems with environmentally benign process; • Front-End Processes, with emphasis on benign surface preparation and novel high-K dielectric materials; • Factory facilities, with emphasis on SEM of negative tone lines patterned in a dendrimer based resist. minimization of water and energy usage;

9 Research Contributions

Performance advantages of imaging high aspect ratio features with super- critical CO2 vs. aqueous development.

• Patterning, with emphasis on IMPROVING DESIGN non-solvent lithography and additive processing; and PRODUCTIVITY & TIME- • Education, with emphasis on creat- TO-MARKET IN DESIGNING, ing an engineering curriculum that ANALYZING, AND TESTING includes design for the environment. IC PRODUCTS Four major challenges in the design of Example results from 2000 research electronic circuits and systems are: include: • Increasingly complex circuit design • Reduction of chemical vapor in the deep submicron range; deposition (CVD) effluents by • Exponential growth in the number pulsed plasma excitation (MIT); of circuits; • An electrophoretic cross-flow • Heterogeneous systems; and filtration technique for reducing • Market pressures to reduce design total suspended solids (TSS) and time. copper ions from Chemical- Additional challenges include test cost Mechanical Polishing (CMP) waste and speed, digital/analog mixed-signal streams (University of Arizona); parts, verification, and design reuse. • Using electrodialysis to remove dissolved copper from the TEST AND TESTABILITY dispersion medium of CMP Unit test costs, driven up by increased waste (University of Arizona); numbers of pins, gigahertz speeds, and • Demonstration of 150 nm features inaccessible cores, may soon exceed through e-beam patterning of CVD manufacturing costs. University of fluorocarbon films developed with Texas/Austin is addressing reduced- supercritical CO2 (Cornell cost test techniques for systems-on- University and MIT). Filed chip, extension of self-test techniques provisional patent for non-solvent, to use the power of the processor to run resistless patterning. tests for itself and peripheral cores at- speed, and on tools for test generation and testability insertion for bridging, crosstalk, and delay faults. University of Illinois/Urbana-Champaign has focused

10 Research Contributions

on test data volume reduction, a new scan technique showing significant promise in reducing test application time and test data volume for system-on-chip designs. Testing and diagnosing failures in complex, heterogeneous systems are being POWER ESTIMATION AND investigated at Universities of REDUCTION Texas / Austin, Washington, and Illinois, Tools for the early estimation of power with emphasis on self-test and design and for power reduction are critical in for testability. New failure modes such today’s mobile applications, to avoid as crosstalk disturbances and analog- costly redesign, and to enable design digital noise coupling are the focus at exploration in a design-reuse environ- the University of Southern California ment. Researchers at the University of and University of California/San Diego. Southern California have developed techniques ranging from quasi-synchro- nous, derived clocking schemes and clock gating, to architectural- and oper- ating system-level modeling to investi- gate how power is affected and can be reduced. At the University of Toronto, bottom-up and top-down power mod- els have been used in the difficult task of estimating power early in the process, before the design has even reached the gate level.

Buffers in Global interconnects are one technique used VERIFICATION to eliminate crosstalk glitch effect (University of California Researchers at the University of at San Diego) California/Berkeley, the University of Texas, and Carnegie Mellon University SYNTHESIS are on the forefront of formal verification Traditional synthesis separating tech- work producing tools in use by SRC nology-independent decomposition members. BDD and non-BDD tech- and, technology-dependent library niques, coverage analysis, hybrid for- binding, leads to sub-optimal realiza- mal/simulation methods, model check- tions that cannot be improved ing advances, and counterexample incrementally. Work at the University exposure techniques have been applied of Michigan is focused on carefully to multiprocessor memory protocols, interleaving of these stages. data flow processor arrays, and other Researchers at the Universities of member company designs. These tech- California/Berkeley and Colorado are niques are assisting in locating and addressing synthesis and improve- correcting errors at the design stage ments in quality of results and perform- and are assuring that correct silicon is ance of the VIS and CUDD synthesis shipped to customers. systems now in wide use among SRC members.

11 Research Contributions

HETEROGENEOUS SYSTEMS AND CIRCUITS FOR TOMOR- ROW’S APPLICATIONS Today, there is increasing need to merge not only analog and digital functions on DEEP SUBMICRON EFFECTS the same chip, but also to incorporate Present algorithms for extraction of radio frequency (RF) elements, sensors, parasitic capacitance and inductance and micromechanical components. are inadequate for gigascale and Simultaneously, technologies used to gigahertz designs. Carnegie Mellon manufacture these systems are driving University has demonstrated accurate, toward greater packing density and dra- computationally efficient 3-D extraction matically lower supply voltages. These algorithms to reduce design iterations. trends pose enormous challenges for designers and technologists. SYSTEM LEVEL DESIGN Heterogeneous designs require combi- nations of analog circuits, digital func- tions, mechanical elements, and embedded software in which power, speed, and packing density must be optimized. University of Wisconsin, Princeton University, Virginia Tech, and University of Illinois are investigating advanced processor architectures, power management, and communica- Modeling inductance and capacitance concurrently is tions circuits. New tools for evaluating required to accurately assess potential problems with and refining design options are being on-chip inductance (Carnegie Mellon University) developed.

Noise coupling through the silicon CIRCUIT DESIGN substrate is a particular concern Major research investments are being for mixed-signal circuits. Accurate made in high-performance analog to simulation of noise coupling requires digital conversion circuits. Advanced construction of an equivalent electri- memory architectures that conserve cal network that can then be used in power and dramatically improve per- conjunction with circuit simulation formance are being developed. Novel tools. University of Illinois/Urbane digital logic circuits extending CMOS Champaign is producing accurate and to clock rates of several GHz are computationally-efficient, three-dimen- being developed at the University of sional substrate analysis methods Washington. Advanced circuit designs for use with circuit simulation tools to that take advantage of Silicon-on- effectively attack this problem. Insulator (SOI) technology are being developed at the University of Michigan.

12 Research Contributions

FUTURE SEMICONDUCTOR DEVICES, MATERIALS AND PROCESSES As feature sizes decrease toward the granularity of matter, phenomena, previ- ously of secondary importance, play an increasingly important role in the perform- These initiatives include: ance of MOSFETs. These phenomena, • Integrated nanotubes for future with new materials, such as nanotubes, electronics (Stanford University); offer opportunities for novel information • Integrated molecular RAM and technologies that could displace or, SRAM (Yale University); perhaps, complement existing MOS • Background-charge insensitive technologies. single electron memories (SUNY/ Stony Brook); • Nuclear spin based memory and Carbon logic (Harvard University); Nanotube • Integrated nanosystems with coop- erative assembly of nano-quantum devices and vertical nano MOS (University of California/Los Angeles); • Single-integrated hybrid-chip molecular quantum (University of California/Riverside. SRC published a key document on Research Needs in Basic Science of A network of carbon nanotubes connecting Semiconductors (http://www.src.org/ silicon pillar. (Provided by Professor H. Dai, Stanford University) member/about/srcstaff_pubs.asp). This document seeks to identify and charac- In 2000, SRC continued exploring new terize research needs in the basic phys- nanoelectronic technologies in areas ical sciences that are required to sustain such as molecular electronics, quantum the exponential progress in nanoelec- computing, and spintronics that target tronics. long-term strategic goals, with a possi- bility for nearer-term impact. Examples include projects on quantum cellular automata (Notre Dame University) and on molecular electronics (University of California/Los Angeles).

13 TECHCON 2000

By many accounts, TECHCON 2000 was the best technical conference hosted by SRC to date. The three-day event was packed with student presen- tations, awards ceremonies, and networking opportunities. Industry dignitaries at the conference included Robert Burger, Nobel Prize winner Jack Kilby, and keynote speakers Craig Barrett of Intel and Bijan Davari of IBM.

JobsFair — TECHCON’s networking event — gathered 200 of the top students in microelectronic-related dis- Craig Barrett, President and CEO of Intel Corporation, ciplines and representatives from 21 delivered the keynote address SRC member companies to provide a for the Conference Banquet at rich recruiting opportunity for interns TECHCON 2000. and regular full-time hires. Several job offers were made on the spot as a direct result of JobsFair.

The 2000 Graduate Fellowship Program Annual Conference was held in conjunction with TECHCON 2000. The highlight of the GFP Banquet was the keynote address, which was delivered by Dr. William T. Siegle, AMD Senior Vice President and Chief Scientist.

TECHCON STATS AT A GLANCE

SRC-sponsored student presenters 153 Graduate Fellows and Masters Scholars presenters 44 Total SRC-sponsored student presenters 197

Technical paper sessions 25 Special sessions (Copper Contest & CSR Session) 2 Total Presentation Sessions 27

Faculty & Student attendees 268 Member Company attendees 359 SRC staff & Guest attendees 41 Total Conference Attendees 668

Member companies that participated in JobsFair 21

SRC Awards presented 82

14 TechconBest In Session

2000 199 students presented their research at TECHCON 2000 in five sets of five concurrent technical paper sessions with each set being followed by a TechFair poster session for papers presented in that set. Presentations were judged both on paper and poster presentation and the following “Best in Session” Winners were named for all twenty-five sessions.

SRC-SPONSORED STUDENT PAPER TITLE

Stephen P. Nugent An Ultra-Compact Empirical Model for Throughput Projection for Gigascale Integration Gwang-Soo Kim A Computationally Efficient Feature Scale Model for Copper Electrodeposition in the Presence of Additives Noel Hoilien Physical and Electrical Characterization of Zirconium Dioxide as a Gate Insulator David Tully Evaluation of Novel Hyperbranched Resist Materials for Next Generation Lithography James G. Fiorenza An RF Power LDMOSFET on SOI Noppanunt Utamaphethai Buffer-Oriented Microarchitecture Validation (BMV) Azeez Bhavnagarwala Fluctuation Limits on CMOS SRAM Scaling Brian A. Floyd CMOS Receiver Circuits for On-Chip Wireless Interconnection Francisco Machuca High Brightness III-Nitride Electron Emitters Seongwon Kim An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops Rao Desineni Test Analysis Using Fault Tuples Hendrawan Soeleman VT-Sub-CMOS: Robust Sub-Threshold Digital Logic Zhijiong Luo Temperature Dependence of Gate Current in Thin Ta(2)O(5) and TiO(2) Films Matt Colburn Recent Advancements in Step and Flash Imprint Lithography Jir-Shyr Chen Thermally Reworkable Underfill Materials: Controlled Tuning of Thermo-Mechanical Properties Prakash Gopalakrishnan Direct Transistor-Level Placement Gaolong Jin Uniform and Ordered Self-Assembled Ge Dots on Si-Based Substrates Shyam Gannavaram Ultra-Shallow, Super Abrupt Boron Doped Source/Drain Junctions with Above Equilibrium Dopant Activation for 50 nm and Beyond Using Low Temperature (500 C), In-Situ Boron Doped, Selective Si(x)Ge(1-x) Technology Adam Pawloski Photo-Acid Generation in Chemically Amplified Resist for Next Generation Lithography Maura Jenkins Interface Chemistry and Microstructure in Polymer/Epoxy Underfill Interface Systems Steven A. Vitale Characterization of High Density Plasma Etching of BCB Low-k Dielectric Films for Dual Damascene Integration Atsushi Kawamoto Atomic Scale Effects of Zirconium and Hafnium Incorporation at a Model Silicon/Silicate Interface by First Principles Luca Daniel Interconnect Electromagnetic Modeling Using Conduction Modes as Global Basis Functions Paul Hyden Improved Decision Processes Through Simultaneous Simulation and Time Dilation Hsin-Chiao Luan Germanium Photodetectors Integrated on Si for Si Optical Interconnects Kevin Kidoo Lee The Effect of Size and Roughness on Light Transmission in a Si/SiO(2) Waveguide: Experiments and Model Charles M. Perkins Electrical and Material Properties of ALD ZrO(2) Gate Dielectric (Fellows Award)

15 Techcon 2000 Awards

LANDMARK INNOVATION AWARD Dr. Farhang Shadman, Director of the NSF/SRC-funded Engineering Research Center for Benign Semiconductor Manufacturing at the University of Arizona, received the first-ever SRC Landmark Innovation Award, along with a $10,000 cash prize. Dr. Shadman has provided four patents to SRC members enabling the creation of environmentally-friendly closed manufac- turing systems which reuse gases and ultra-pure water during semiconductor fabrication.

ARISTOTLE AWARD Professor Rafael Reif, of the Mass- achusetts Institute of Technology, was presented the Aristotle Award in recognition of his commitment to the educational experience of SRC students and the profound and continuing impact he has had on their professional careers. This award acknowledges outstanding teaching in its broadest sense, emphasiz- ing student advising and teaching during the research project. Professor Reif has graduated some 40 Master’s students and over 30 PhDs, including three SRC Fellows.

TECHNICAL EXCELLENCE AWARD Lawrence T. Pileggi, professor of electrical and computer engineering at Carnegie Mellon University, received SRC’s Technical Excellence Award in recognition for his work on “Simplified Inductance and Capacitance Extraction Algorithms,” which has had a direct impact on the productivity and competi- tiveness of the semiconductor industry. It is estimated that his research findings may save several months in time-to-market.

The SRC Technical Excellence Award is given annually to researchers who, over a period of years, have demonstrated cre- ative, consistent contributions to the field of semiconductor research, who are ground breakers and leaders in their fields, and who are regarded as model collaborators with their colleagues in the SRC member community.

16 MAHBOOB KHAN MENTOR AWARD The Mahboob Khan Mentor Award, named in memory of a long-time SRC Industrial Liaison program advocate from AMD, is presented to those individuals who have made significant contributions to the SRC community in their roles as an Industrial Liaison. Recipients represent “ideal mentors” whose commitment more than enhances the SRC research program.

Recipients of the 2000 Mahboob Khan Awards, which were presented at TECHCON, include:

Robert Allen, IBM Corporation (not shown) Prashant Sawkar, Intel Corporation (not shown)

Mark Mason David F. Reed Texas Instruments Advanced Micro Devices

INVENTOR RECOGNITION AWARDS In addition to sponsoring the research efforts of many talented SRC university researchers, SRC makes a special effort to recognize and reward those researchers whose efforts lead to patentable inventions. At TECHCON 2000, SRC presented Inventor Recognition Awards to more than 46 university researchers and students.

17 Student MASTER’S SCHOLARSHIP Programs PROGRAM The Master’s Scholarship Program was created in 1995 and targets underrepre- sented minorities and women with outstanding potential in disciplines The SRC community continues to see of interest to the semiconductor indus- an outstanding return on its investment try. This program will be opened to in SRC students. Through internships company-named scholarships in 2001. and permanent hires, students transfer research developed in the university community and build the network of THE UNDERGRADUATE highly qualified researchers both in ENGINEERING PROGRAMS industry and in academia. In June of 2000, the SIA Board of Directors approved funding for the In increasing numbers, students are Undergraduate Engineering Programs forging the links between the individual to be managed by SRC through member companies and the SRC the SRC Education Alliance. Three community by serving as Industrial programs were funded and two were Liaisons and Technical Advisory initiated in 2000. The third program Board Members. Student Programs is scheduled to begin in early 2001. managed by SRC include the Graduate ¥ The Undergraduate Research Fellowship Program, the Master’s Assistants Program targets qualified Scholarship Program and three students early in their undergraduate Undergraduate Engineering Programs. careers and connects them with SRC- sponsored research programs. The GRADUATE FELLOWSHIP program also provides mentoring by PROGRAM graduate students and industry per- sonnel. Fifty-three Assistantships The Graduate Fellowship Program is in were awarded for the 2000-2001 aca- its fifteenth year and continues to be demic year. successful in attracting many of the ¥ MOSIS is an established program best U.S. citizen/permanent resident centered at the University of Southern students to doctoral study in disciplines California, which provides students of interest to the semiconductor industry. with the ability to fabricate their VLSI The number of company-named designs, thereby producing designers Fellowships grew in 2000 to fifteen (12 in with real experience. The MOSIS pro- 1999) as the membership recognized gram serves about 5000 students in the value of this program to the industry. design courses each year. SIA/SRC funding will allow continuation of this Of the 197 technical papers that were program originally funded by DARPA presented at TECHCON 2000, 40 were and NSF. presented by students participating in ¥ The Industry Experience for Faculty the Graduate Fellowship Program. Of Program is scheduled for implemen- those 40, seven won “Best in Session” tation early in 2001 and will target awards. For more about TECHCON faculty at non-SRC-funded schools 2000, see page 14. who do not have connections to the semiconductor industry.

18 STUDENT STATS AT A GLANCE

Total SRC-supported students ...... 1091 (including Graduate Fellows and Masters Scholars)

Total SRC graduates in 2000 ...... 183

Graduate Fellowship Program Stats

Total fellowships in program ...... 64

Company-named fellowships ...... 15 (3 AMD, 2 IBM, 1 Intersil, 3 Motorola, 2 National Semiconductor, 1 NIST, 1 Novellus Systems, 2 Texas Instruments)

Research Fellowships (funded by Hewlett-Packard & AMD) ...... 2

Students to complete program in 2000 ...... 13 (9 joined member companies and 2 joined university faculties)

Graduate Fellows who presented papers at TECHCON 2000 ...... 40

Master’s Scholarship Program Stats

Total scholarships in program ...... 13

Students to complete program in last two years ...... 9 (4 are pursuing Ph.Ds, and 3 have joined SRC member companies)

Master’s Scholars who presented papers at TECHCON 2000 ...... 4

19 Industrial Liaison Program

The SRC Industrial Liaison Program is a ALIGNING RESEARCH powerful partnership that brings togeth- Industrial Liaisons encourage dialogue er the university community and experts and technology exchange between the from the semiconductor industry to pro- university and industrial communities. mote an environment of cooperation. They assist by providing expertise, During 2000 nearly 500 industrial equipment, and feedback about indus- liaisons participated in the Industrial trial needs, as well as guidance and Liaison Program. This major industry material help during all phases of the commitment enabled the best technical research. In the end, research results people to guide, shape, and support are realized faster, are more closely SRC research efforts. The Industrial aligned with real industrial uses, and Liaison Program provides three vital use the most relevant, state of the art functions: technology that can be made available. DEVELOPING THE WORKFORCE TRANSFERRING TECHNOLOGY Industrial Liaisons serve as student Liaisons work with researchers, mem- mentors to provide guidance and inspi- ber companies, and SRC to bring ration to graduate students preparing to knowledge back to industrial sponsors enter the semiconductor industry. They in an expedient, cost-effective way. help the students achieve academic Their focus is on maximizing the return excellence through real-life exposure to for their company. Liaisons work with industrial practices. Liaisons may the researchers during the entire life of a arrange for internships or summer hires; funded task to ensure that results will be they also frequently serve on students’ made available in a form that is of use to thesis advisory committees or final industry. Liaisons are most effectively examination committees. positioned to ensure that exciting new research is actually implemented in a timely manner.

INDUSTRY LIAISONS BY MEMBER COMPANY AMD ...... 42 Conexant ...... 10 Hewlett-Packard ...... 9 IBM ...... 84 Intel ...... 111 LSI Logic ...... 12 Motorola ...... 88 National Institute of Standards Technology ...... 5 National Semiconductor ...... 8 Novellus ...... 5 Texas Instruments ...... 53 Other Companies ...... 26 Total Liaisons that participated in 2000 ...... 453

20 2000 Value Delivery

In the fourth quarter of 1999, SRC formed a directorate, called the Value The Industrial Liaison program, which is Chain to support, service, and satisfy its highly valued by the graduate students members. The Value Chain works to and also provides member companies deliver value by: with valuable, early research results, • Identifying valid member needs; was revitalized under a new program • Developing and managing a manager and reached a record number research portfolio; of industrial liaisons. • Monitoring member satisfaction; • Responding to identified shortcom- The students, perhaps the most valu- ings. able output of the SRC programs, were showcased at TECHCON 2000 where In 2000, all science areas worked with 197 papers were presented by them on the members’ technology advisory their leading-edge research. boards to develop and refine “technol- ogy needs statements” with the A major effort went into identifying mixed signal domain perhaps member needs relative to the getting the most attention. SRC Web site itself. After New, well-received months of intense effort, approaches to the the new Web site reviewing, ranking, framework was rating and select- unveiled at TECH- ing of white papers CON 2000. The and proposals members liked were tested, what they saw, including utilization including the ease of the Internet. of navigation and the Procedures for con- ability to collaborate tract reviews and using the Web site reporting were significant- forums. ly streamlined in order to both simplify the procedures and to In order to improve the monitor- provide more timely technical informa- ing of our members needs, the annual tion to the members via the SRC Web member satisfaction survey was site, and a record number of publica- refined, plus telephone surveys of key tions were placed on the SRC Web site members of both the Board of Directors for member access. and the Executive Technical Advisory Board were conducted in addition to In order to enhance the ability of the their written surveys. The level of Technical Advisory Board (TAB) mem- member satisfaction was measured to bers to effectively deliver value to their increase year over year, as well as members, all of their handbooks were associated measure of value (weighted updated and an Orientation Course for relevance index) to the members. new TAB members was created and implemented.

21 SRC Copper IC Design Challenge Completed

In 2000, SRC completed its first design contest. The “Copper IC Design Challenge” was fully sponsored by members Novellus Systems and UMC The University of Minnesota captured with additional support from first place and a $35,000 award with its SpeedFam/IPEC. Two key objectives for “RF Front-end Design with Copper this contest were to raise the level of Passive Components” concept. The interest and knowledge in the area of IC team, led by Professor Ramesh Harjani, design within the universities and to included members Jonghae Kim, increase interest in designing with Mingta Hsieh and James P. Koeppe. copper interconnects, accelerating the adoption of this relatively new semicon- The topic of the second-place design, ductor copper technology within the submitted by University of Florida, was future design community. The contest “A Wireless Clock Distribution System: was an overwhelming success. Clock Receiver and Transmitter Circuits.” This team received a $25,000 award, was led by Professor Kenneth O and included Brian A. Floyd and Chih- Ming Hung.

The third-place award of $15,000 went to Carnegie Mellon University for its project, “CMOS Micromachined RF 43 teams entered the Contest and over Components.” The team, led by 140 students were involved. Judging Professor Gary Fedder, included Hasnain criteria focused on creativity of design, Lakdawala, Hao Luo and Xu Zhu. The impact of the design on future applica- cash prizes will support integrated circuit tions, design efficiency, test procedures, (IC) design education programs at these correlation of test results to the design universities. In addition, ten other finalist performance predicted in Phase 1 and teams were awarded cash prizes of completeness of the materials submit- $15,000 each for successfully complet- ted. Thirteen teams with over 50 stu- ing both phases of the contest. dents completed Phase 2 involving fab- rication of their designs in copper. Five This contest has provided an excellent Phase 1 winners were recognized at opportunity for the students and faculty ISSCC 2000 in February with $20K to demonstrate their creativity using a going to each of their universities. Three leading-edge copper technology. SRC top teams were selected from among is strongly considering future sponsored the 13 Phase 2 participants. These contests as a way to increase three teams presented their designs at faculty and student interest at both the TECHCON 2000, a student technology graduate and undergraduate levels in conference which was held Sept. 21-23 microelectronics and design, and a way in Phoenix, Ariz. For more on TECHCON to provide increased industry support to 2000, see pages 14-17. student activities in these areas.

22 SRC Web site

The new SRC Web site was designed using one overriding premise: Embrace the latest in web-based technology to better serve the SRC community, but Since its 1996 inception, SRC’s Web DO NO HARM to its success to date. site has evolved at much the same pace Highlights of the new site include: as the Internet. In 2000 alone, site con- tent grew by nearly 30% with a highwa- • A fully redesigned site look-and-feel to ter mark of 22,000 pages of content by simplify navigation and target content; year-end. Site usage increased at the • An integrated News function same pace with over 3800 active users designed to highlight new content. registered by December, 2000. Based This News feature will ultimately on these numbers, SRC has clearly adapt to the identity and interests of established a prominent and successful each user; value delivery mechanism via the Internet. • Redesigned Science Areas pages that are easier to navigate because of their Significant new Web site capabilities consistency; were brought online in 2000, including: • Dynamically-served pages that are ¥ Internationalization: synchronized with SRC’s corporate Early in the year, SRC established database. The goal: more flexible, up- processes, addressed all necessary to-date responses to Members legal issues and brought online the research information needs; appropriate technology to enable the • Discussion forums to facilitate online Web site to effectively serve an collaboration within the SRC commu- International membership. nity. The SRC Forums technology is designed for flexibility and can be ¥ Students Online: easily adapted to meet Member SRC-supported students were company collaboration needs. provided with online accounts so they could be integrated into our web The underlying infrastructure of the new community. site provides a vast opportunity to ¥ New Site Previewed: rapidly deploy new capabilities and A completely redesigned Web site functionality in the coming year with a was previewed at Techcon 2000 particularly strong focus on enhancing in Phoenix, Arizona and received collaboration within the industry. positive feedback on its increased functionality.

www.src.org 23 Industry Assignee Program

The Industry Assignee Assignees use their unique understanding Program was designed to ensure of their company’s and the industy’s R&D that the needs of Member companies interest to have a direct and meaningful play an active role in shaping the day-to- impact on the daily activities at SRC. In day operation of SRC’s global, leading- exchange for that invaluable perspective edge, collaborative research program. and input, Member company employers Through this program, Assignees maintain receive a rebate on their SRC membership their current employment status at their dues. Assignees may work full-time on-site respective Member companies, but work at SRC or split their time between SRC and on-site with SRC staff and management. their regular employer. The 2000 Industry Assignees are:

Lawrence Arledge, Texas Instruments Mr. Arledge served as the Physical Design Thrust Program Manager in Computer Aided Design & Test Sciences and the Circuits Design Thrust Program Manager in Integrated Circuits & Systems Sciences in 2000. He is also a Senior Member of the Technical Staff in the Mixed Signal Products Group at TI.

George Bournioff, Intel Corp. Dr. Bournioff is the Advanced Devices Technologies Thrust Program Manager in Nanostructure & Integration Sciences. He is also a senior program manager in the Strategic Research Group of Intel where he serves as co-chairman of the Semiconductor Technology Committee. He holds BS, MS and P.hD degrees in physics from the University of Texas/ Austin.

Dale Edwards, Advanced Micro Devices Mr. Edwards has been serving as the Circuit Design Thrust Program Manager in Integrated Circuits & Systems Sciences since January 1999.

24 Industry Assignee Program

Jyh-Shyang Jenq, United Microelectronics Corp. Dr. Jenq is the Front-End Processes Thrust Program Manager in Materials & Process Scienc. He is also an EDRAM Process Integration Manager for UMC and holds a BS in Forestry and MS and Ph.D degrees in Materials Science from the University of Wisconsin/Madison.

William H. Joyner, Jr., IBM Corp. Dr. Joyner is the Director of Computer- Aided Design and Test Sciences. Dr. Joyner is also the co-chair of the Design TWG of the International Tehnology Roadmap for Semiconductors [panel chair of the 2001 Design Automation Conference, and associate editor of ACM Transactions on Design Automation of Electronic Systems].

Frank Robertson, Intel Corp. For part of 2000, Mr. Robertson served as the program manager for the Front-End Processes Thrust in Materials and Process Sciences. He later transitioned to become the Factory Systems Program Manager in Nanostructure & Integration Sciences.

Quat T. Vu, Intel Corp. Dr. Vu is a senior staff member of Intel Santa Clara, CA. He is on assignment to SRC as the Packaging and Interconnect Thrust Program Manager in Nanostructure & Integration Sciences. He holds MS and Ph.D degrees in from California Institute of Technology.

25 Intellectual Property

The value of SRC membership is materials and processes, novel device enhanced and protected by providing structures and devices, copper inter- intellectual property assets spanning connect technology, optoelectronics, numerous SRC sponsored university waveguide technology, resists and their research programs. Intellectual property processing, and advanced SOI (silicon- (IP) assets exist to support SRC’s on-insulator) devices. In addition, mission and charter to transfer and several SRC sponsored foreign patents commercialize the results of SRC- issued which were related to previously sponsored research programs to SRC granted U.S. patents. SRC’s significant member companies. SRC’s signifi- patent portfolio supports both U.S. and cant portfolio of intellectual assets global member company operations in serves to minimize the risk of infringe- numerous countries around the world. ment and encumbrances as research For the first time, issued patent informa- results are utilized by industry. tion was added into SRC research Accordingly, SRC member companies catalog web pages so members can are given the freedom to practice, use, appreciate a patent in light of the and commercialize the results of research program from which it arose. research programs funded through SRC Soon, SRC’s new Web site will permit sponsorship. members to submit realtime queries into SRC’s IP database to obtain status on In return for sponsorship, SRC receives pending and issued patents as well as non-exclusive, worldwide, royalty free SRC-sponsored software. licenses to IP resulting from such research programs. Although IP rights In addition, SRC provides over 200 soft- are owned by the university, IP rights are ware programs, software models, and transferred contractually as applicable technical databases to member compa- to SRC member companies. Rights in nies. Software and database IP licenses patents, copyrights, software, databases, from SRC sponsored research programs and other IP, such as mask registrations, represents a growing and complemen- are obtained as required to allow SRC tary IP portfolio. Members are directed members to practice and use the results to the online software directory at of SRC sponsored research. As an www.src.org for further details. SRC additional service to members, access members also receive non-exclusive, to background intellectual property worldwide, royalty free intellectual prop- licenses necessary to practice SRC erty licenses in applicable software pro- research results is provided, whether grams and technical databases. the background IP is from an industry or academic source. While SRC IP exists The Intellectual Property highlight of primarily for defensive purposes, SRC 2000 was the awarding of the inaugural enforces its IP rights as necessary to Landmark Innovation Award to Dr. provide a level playing field for members Farhang Shadman, of the University of by ensuring that those who utilize SRC Arizona, at TECHCON 2000. Jack Kilby, sponsored technologies do so only a recent recipient of the Nobel Prize, within the scope of a valid license. presented the award to Dr. Shadman for his notable and valuable inventions in During 2000, seven SRC-sponsored environmentally friendly semiconductor U.S. patents were issued, bringing the fabrication technologies, which has pro- total U.S. portfolio of SRC patents to vided long term and significant benefits 168. This year’s patents relate to to SRC members.

26 U.S. PATENTS ISSUED IN 2000

Title Inventor(s) Filing Date U.S. Patent University Issue Date Number

Passivated copper Ding Peijun Feb. 10, 1998 6,057,223 SUNY/ conductive layers for W. Lanford May 2, 2000 Albany microelectric applications Wei Wang

Systems, methods and computer Xun Chen May 21, 1998 6,064,486 Stanford program products for detecting May 16, 2000 University the position of a new alignment Amir Ghazanfarian mark on a substrate based on Mark McCord fitting to sample alignment signals R. Fabian Pease

Photoresist compositions com- David Medeiros Mar. 7, 1997 6,103,445 Univ. of Texas/ prising norbornene derivative U. Okoroanyanwu Aug. 15, 2000 Austin polymers with acid labile groups Grant Willson

Optoelectronic integrated circuits A. Agarwal Oct. 13, 1998 6,108,464 M.I.T having polycrystalline silicon Marcie Black Aug. 22, 2000 waveguides therein Jim Foresi Lionel Kimberling Debra Koker

Films for use in microelectronic Jeffry Kelber Apr. 10, 1998 6,114,032 Univ. of devices and methods of Sept. 5, 2000 North Texas producing same

Silicon-On-Insulator Transistors Mansun Chan Sept. 10, 1999 6,121,077 Univ. of having improved current charact- Chenming Hu Sept. 19, 2000 California/ eristics and reduces electrostatic Ping Ko Berkeley discharge susceptibility Hsing-Jen Wann

Methods for decreasing surface G. Reynolds Oct. 6, 1998 6,162,592 Univ. of roughness in novolak-based James Taylor Dec. 19, 2000 Wisconsin resists

27 Focus Center Research Program

DESIGN AND TEST UC/BERKELEY CMU Two years ago, the University of California at Berkeley MIT became the lead university for the Design and Test Penn State Princeton Focus Center (Gigascale Silicon Research Center). Purdue Professor Richard Newton is the center’s director. Stanford SPONSORS: UCLA The Design and Test Center’s research agenda address- UC/San Diego es concepts such as component/communication-based design, UC/Santa Barbara UC/Santa Cruz constructive fabrics, fully programmable systems, calibration of achiev- Univ. of Michigan Semiconductor Industry able design, validation, power and energy. UT Austin Association (SIA): Univ. of Wisconsin Agere Agilent Advanced Micro Devices GEORGIA TECH Analog Devices INTERCONNECT Conexant MIT The Interconnect Focus Center is based at the Georgia Stanford Cypress Institute of Technology. Professor James Meindl has RPI IBM UCLA Intel been the director since the center was established, Univ. of Albany LSI Logic almost two years ago. The center’s research teams Micron examine six major tasks: system architecture and circuit Motorola National Semiconductor innovation, physical design tools, novel communications mechanisms, Texas Instruments integrated input/output interconnects, materials and processing, Xilinx predictive modeling and metrology.

MATERIALS, STRUCTURES AND DEVICES MIT Semiconductor Industry Cornell Supplier Association: Recently, the Massachusetts Institute of Technology was Princeton Air Products designated as the lead university for a new Materials, Purdue Applied Materials Stanford Structures and Devices Focus Center. Professor Dimitri UC/Berkeley Novellus Antoniadis is the director. This center will research UCLA SCP Global sub-10-nanometer silicon-based FETS, silicon-based Univ. of Albany Speed-Fam UT/Austin Teradyne quantum-effect devices, molecular and organic semiconductor elec- UVA Veriflo tronics, nanotube electronics and modeling and simulation.

CIRCUITS, SYSTEMS AND SOFTWARE CMU DUSD (S&T): Columbia Deputy Undersecretary A new Circuits, Systems and Software Focus Center was Cornell of Defense for Science also recently created, with Carnegie Mellon University MIT & Technology Princeton as the lead university. Professor Rob Rutenbar is the RPI director. The center’s research will focus on ana- Stanford log/mixed signal circuit analysis and synthesis, UC/Berkeley UIUC system level technologies and software solutions to CMOS limitations. Univ. of Washington

28 SRC 2000

MEMBERS Advanced Micro Devices, Inc. Conexant Systems, Inc Eastman Kodak Company Hewlett-Packard Company AFFILIATE MEMBERS IBM Corporation Coventor, Inc. Intel Corporation Flip Chip Technologies LSI Logic Corporation Genus, Inc. Lucent Technologies Integrated Systems Engineering, Inc. Motorola, Incorporated Mission Research Corporation National Semiconductor Corporation Neo Linear, Inc. Texas Instruments Incorporated Numerical Technologies, Inc. United Microelectronics Corp. Group PDF Solutions, Inc. Physical Electronics Inc. SCIENCE AREA MEMBERS SILVACO International Axcelis Technologies, Inc Tessera, Inc Cadence Design Systems Testchip Technologies, Inc. Mentor Graphics Corporation Torrex Equipment Corp. Novellus Systems, Inc. Veeco Instruments, Inc. Shipley Company, Inc. Ziptronix, Inc. Synopsys, Inc. ULTRATECH Stepper GOVERNMENT PARTICIPANTS DARPA ADJUNCT MEMBER National Institute of Standards & Compaq Computer Corp. Technology National Science Foundation ASSOCIATE MEMBER The MITRE Corporation STRATEGIC PARTNERS International SEMATECH Semiconductor Industry Association

36 2000 OFFICE OF THE CHIEF EXECUTIVE

2000 BOARD OF DIRECTORS

Larry Sumney Chairman President and CEO Sunlin Chou, Intel Corporation

Dan Casaletto, Compaq Computer Corp. Walter Class, Eaton Corp. Mike Fitzpatrick, Northrop Grumman Corp. Ralph K. Cavin III Vice President, Sherry Gillespie, Motorola, Inc. Research Operations Rick Hill, Novellus Systems, Inc. Michael Jayne, Intersil Corp. Dave Nichols, Eastman Kodak Corp. Yoshio Nishi, Texas Instruments, Inc. Mark Pinto, Lucent Technologies E.D. “Sonny” Maynard* Craig Sander, Advanced Micro Devices Executive Vice President, Rich Schinella, LSI Logic Corp. Government Affairs Hans Stork, Hewlett-Packard Company Larry Sumney, SRC John Warlaumont, IBM Corporation Mohan Yegnashankran, National Semiconductor Dinesh Mehta Vice President, Business Operations and Strategic Initiatives

Peter Verhofstadt* Executive Vice President and Chief Scientist

* Co-Executive Director, MARCO Semiconductor Research Corporation www.src.org

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