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Ez80acclaim! Flash Microcontrollers Ez80f92/F93 Product Brief

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Ez80acclaim! Flash Microcontrollers Ez80f92/F93 Product Brief eZ80Acclaim! Flash Microcontrollers eZ80F92/F93 Product Brief PB010306-0803 Product Block Diagram* • 2 UARTs with independent baud rate generators and providing up to 9 bits of data transmission eZ80F92 MCU • I2C with independent clock rate generator • SPI with independent clock rate generator 128 KB+256 B 8KB SRAM 24-Bit GPIO Flash • Six 16-bit Counter/Timers with prescalers and direct input/output drive capability Infrared • Watch-Dog Timer Encoder/ 2 UART I2C SPI • Real-time clock with on-chip 32KHz oscillator , Decoder selectable 50/60 Hz input, and separate VDD pin for battery backup Real-Time 6 PRT WDT Clock • Glueless external memory interface with 4 Chip Selects, independent WAIT state generators, and ® 4 CS + WSG JTAG ZDI external WAIT input pin; supports eZ80 , Z80, Intel, and Motorola bus-compatible peripherals *eZ80F92 shown. eZ80F93 features 64KB Flash, 4KB SRAM. • JTAG Debug Interface (also supports ZiLOG Features Debug Interface) • Interrupt controller supports internal and exter- The eZ80F92 microcontroller is a member of nal maskable interrupts as well as a non- ZiLOG’s eZ80Acclaim! product family, which maskable interrupt input offers Flash versions of ZiLOG’s eZ80® processor ® core. An additional controller, the eZ80F93 , is • New DMA-like eZ80 instructions intrinsically the same device, but offers smaller • Power management features including SLEEP/ memory sizes. The eZ80F92 and eZ80F93 devices HALT modes and peripheral power-down con- offer the following features: trols • High-performance, pipelined eZ80F92 with sin- • 100-pin LQFP package, pin-compatible with the gle-cycle instruction fetch eZ80L92 microprocessor – eZ80F92—128 KB on-chip Flash program • memory and an extra 256 bytes configuration 3.0–3.6 V supply voltage with 5V tolerant inputs Flash memory; 8 KB on-chip high-speed • Operating Temperature Ranges: SRAM – Standard: 0ºC to +70ºC – eZ80F93—64 KB on-chip Flash program – Extended: –40ºC to +105ºC memory and an extra 256 bytes configuration Flash memory , 4 KB on-chip high-speed • 20MHz versions: SRAM – eZ80F92AZ020SC • 24 General-Purpose I/O pins – eZ80F92AZ020EC – eZ80F93AZ020SC • IrDA™-compatible Infrared Encoder/Decoder – eZ80F93AZ020EC ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com eZ80F92/F93 Product Brief 2 General Description In addition, high-speed relocatable SRAM is avail- able for general application use. The eZ80F92 and eZ80F93 microcontrollers are power-efficient, optimized, pipeline-architecture • eZ80F92: 8KB SRAM microcontrollers operating at 20MHz. They are • eZ80F93: 4KB SRAM new devices in a line of eZ80®-based standard products with integrated Flash memory, and are General-Purpose Input/Output targeted toward industrial, communication, secu- rity, automation, and embedded Internet applica- There are 24 bits of General Purpose Input or Out- tions. put (GPIO) pins. All GPIO pins are individually programmable and support the following I/O eZ80® CPU Core modes: input, output, open-drain, open-source, level-triggered interrupts (High or Low), edge-trig- The eZ80Acclaim! is a Flash version of ZiLOG’ s gered interrupts (High or Low), dual-edge-trig- ® eZ80 processor core, which can operate in Z80- gered interrupts, and alternate function. compatible (64KB) mode or full 24-bit (16 MB) addressing mode. Considering both the increased Infrared Encoder/Decoder clock speed and processor efficiency, the eZ80 ®’s ™ processing power rivals the performance of 16-bit • Supports IrDA SIR format ® microcontrollers. The eZ80 improves on the • Operates seamlessly with the on-chip UART world-famous Z80 architecture. Like the Z80, it ™ features dual bank registers for fast context switch- • Interfaces with IrDA -compliant transceivers ing. • Supports transmit/receive to 115.2 kbps Peripherals Description Universal Asynchronous Receiver/ Transmitter On-Chip Memory Each of the two Universal Asynchronous Receiver/ The eZ80F92 and eZ80F93 microcontrollers o ffer Transmitter (UART) devices contains control reg- integrated Flash program memory. A separate page isters and a Baud Rate Generator (BRG). of 256 bytes Flash memory is available for general device configuration data. • The Baud Rate Generator produces a lower-fre- quency bit clock from the system clock. All • eZ80F92: 128KB Flash standard baud rates up to 115kbps and some • eZ80F93: 64KB Flash rates higher than 115kbps are supported. • Single power supply operation • The UART module implements all of the logic required to support asynchronous communica- • Page erase feature: 1024 bytes/page tions, hardware flow control, and 9-bit character • Fast page erase and byte program operation format. The module also contains separate 16- byte-deep transmit and receive FIFOs. • 60ns maximum access time • Endurance: 20,000 write cycles (typical) Inter-Integrated Circuit • Data retention: greater than 100 years @ room The Inter-Integrated Circuit (I2C) device contains temperature control registers and its own clock rate generator . The I2C operates in four modes: Master Transmit PB010306-0803 eZ80Acclaim! Flash Microcontrollers eZ80F92/F93 Product Brief 3 or Master Receive, Slave Transmit or Sla ve Block Transfer Instructions Receive. Four new block transfer instructions with expanded Serial Peripheral Interface repeat capability are added to the eZ80F92. These provide performance similar to hardware DMAs. The Serial Peripheral Interface (SPI) device con- tains control registers and its own clock rate gener- Chip Select/Wait State Generator ator. The SPI is a synchronous interface allowing and WAIT Pin several SPI-type devices to be interconnected. The SPI may be configured as either a master or a slave. There are four chip selects for external devices. Each chip select may be programmed for either Programmable Reload Timers memory or I/O space. Each memory chip select can be individually programmed on a 64 KB The eZ80F92 features six Programmable Reload- boundary. The I/O chip selects can choose a 256- able Counter Timers (PRT). Each timer is a 16-bit byte section of I/O space. The WAIT input pin down counter and offers a 4-bit clock prescaler facilitates interface with slow peripherals. The chip with four selectable taps for CLK ÷ 4, CLK ÷ 16, selects support eZ80®, Z80-, Intel-, and Motorola- CLK ÷ 64, and CLK ÷ 256. The timers’ two modes style buses. of operation are single-pass and continuous count mode. Four timers can be driven through a GPIO JTAG Debug Interface input pin for external event count. Two other timers have the ability to drive general-purpose output The IEEE1149.1-compatible JTAG debug interf ace pins. supports all of the ZDI functions plus the following features: software break points, 64-word trace Watch-Dog Timer buffer, complex break points using address and data masks, and cascadable triggers. The Watch-Dog Timer (WDT) features four pro- 18 22 25 27 grammable time-out periods: 2 , 2 , 2 , or 2 ZiLOG Debug Interface system clock cycles. It can operate from either the main system clock or the on-chip 32KHz oscillator The ZiLOG Debug Interface (ZDI) incorporates (from RTC). Time-out action of the WDT is user most of the functions of an In-Circuit Emulator on- programmable via hardware reset or nonmaskable chip. ZDI allows the user to single step code, interrupt to the eZ80F92. The source of action change registers, edit programs, and view status of taken after a WDT time-out is indicated by a WDT internal registers. status bit. Power Management Real-Time Clock Several power management features are supported The real-time clock (RTC) allows counting of sec- on the eZ80F92. Peripheral power-down registers onds, minutes, hours, days-of-the-week, day-of- allow independent clock gating of on-chip periph- the-month, month, year, and century. Alarms and erals under software control while operating under interrupts can be set for seconds, minutes, hours, normal conditions. The eZ80F92 can write to these and day-of-the-week. The real-time clock input can control registers to disable the clock from driving be taken from the on-chip 32KHz oscillator or any one of the peripherals when they are inactive. from a 50/60 Hz input. The real-time clock oper- In addition, execution of the HALT instruction sus- ates from an isolated VDD pin to allow constant pends eZ80F92 operation and eliminates clock operation from a battery. power associated with the eZ80F92 core. Normal PB010306-0803 eZ80Acclaim! Flash Microcontrollers eZ80F92/F93 Product Brief 4 operation can be restored via external and periph- Support Tools eral interrupts or HW reset. The following development tools are available to Execution of a SLP (Sleep) instruction provides program and debug applications using the the lowest power consumption. In SLEEP mode, eZ80F92 devices: only the on-chip RTC 32KHz crystal oscillator remains active to drive the RTC and the WDT. All • eZ80F92 and Ethernet compact evaluation mod- other peripherals, the system clock, and the pri- ules mary oscillator are disabled. An RTC alarm, a • eZ80® Development Platform WDT time-out or HW Reset can restart the device. • ZiLOG Development Suite IDE (ZDS) includ- Electrical Features Summary ing assembler, linker, debugger, and simulator • ZiLOG ANSI C-Compiler • Power supply: 3.3V ± 300mV • eZ80F92 Development Kit including: • Standard temperature: 0ºC to +70ºC – One eZ80F92 module • Extended temperature: –40ºC to +105ºC – eZ80® Development Platform • Supply current @ 20MHz: <30mA (typical) – ZP AKII emulator with ZDI • Supply current in HALT
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