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Ez80f91 MCU Product Brief

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Ez80f91 MCU Product Brief eZ80Acclaim!® Flash Microcontrollers eZ80F91 MCU Product Brief PB013507-0412 Product Block Diagram • Inter-integrated circuit (I2C) and serial peripheral interface (SPI) with independent eZ80F91 MCU clock rate generator • Four counter/timers with prescalers supporting 256 KB Flash + 32-Bit GPIO event counting, input capture, output compare, 512 B Flash and Pulse Width Modulator (PWM) modes 10/100 Mbps • Watchdog Timer (WDT) with internal RC 8 KB SRAM Ethernet MAC clocking option 8 KB Frame Buffer • Real time clock (RTC) with on-chip 32 KHz Infrared oscillator, selectable 50/60 Hz input, and sepa- 2 Encoder/ 2 UART I C SPI rate RTC_VDD pin for battery backup Decoder • Glueless external memory interface with 4 Chip-Selects/Wait-State Generators and Real Time 4 PRT WDT Clock external WAIT input pin. It also supports Intel and Motorola buses 4 CS JTAG ZDI PLL • JTAG and Zilog Debug Interface (ZDI) sup- + WSG porting emulation features • Low-power PLL and on-chip oscillator • Programmable-priority vectored interrupts, Key Features non-maskable interrupts, and interrupt The eZ80F91 MCU is a member of Zilog’s controller eZ80Acclaim! product family, which offers on- • New DMA-like eZ80 CPU instructions ® chip Flash versions of Zilog’s eZ80 processor • Power management features supporting core. The eZ80F91 MCU offers the following HALT/SLEEP modes and selective peripheral features: power-down controls • 50 MHz high-performance eZ80 CPU • 144-pin BGA package or 144-pin LQFP • 256 KB Flash Program Memory and extra 512 package B device configuration Flash Memory • 3.0 V to 3.6 V supply voltage with 5 V-tolerant • 32 bits of General-Purpose Input/Output (GPIO) inputs • 16 KB total on-chip high-speed SRAM: • Operating temperature ranges: – 8 KB for general-purpose use – Standard, 0ºC to +70ºC – 8 KB for 10/100 BaseT Ethernet Media – Extended, –40ºC to +105ºC Access Controller (EMAC) high-speed frame buffer General Description • IrDA-compatible infrared encoder/decoder • Two universal asynchronous receiver/ The eZ80F91 MCU is industry’s first MCU transmitter (UARTs) with independent baud featuring a high-performance 8-bit microcontroller rate generators with an integrated 10/100 BaseT EMAC. It is a power-efficient, optimized pipeline architecture Copyright ©2010 by ZiLOG, Inc. All rights reserved. www.zilog.com eZ80F91 MCU Product Brief 2 microcontroller with a maximum operating speed of following I/O modes: input, output, open drain, 50 MHz. Offering on-chip Flash Memory, SRAM, open source, level-triggered interrupts (High or Ethernet MAC, and rich peripherals, the eZ80F91 is Low), edge-triggered interrupts (High or Low), well-suited for industrial, communication, automa- dual edge-triggered interrupts, and alternate tion, security, and embedded Internet applications. function. Eight of the output pins can drive 10 mA each (Port A), while 16 other pins feature eZ80 CPU Core Schmitt-trigger input buffers (Port B and Port C). The eZ80 CPU operates either in Z80-compatible 10/100 BaseT Ethernet MAC (64 KB) mode or full 24-bit (16 MB) addressing mode. Considering both the increased clock speed The eZ80F91 MCU features an integrated IEEE and processor efficiency, the processing power of 802.3 Ethernet controller with 8 KB of the eZ80 CPU competes with the performance of dynamically-configurable Tx/Rx frame buffer. It 16-bit microprocessors. The eZ80 improves on the supports speed of 10 Mbps and 100 Mbps, full world-famous Z80 architecture. Like the Z80, the , duplex operation, and an industry-standard Media eZ80 CPU features dual bank registers for fast con- Independent Interface (MII) for simple connection text switching. to an external Physical Layer interface (PHY) device. The eZ80F91 MCU delivers high perfor- eZ80F91 MCU Peripherals mance and overall cost effectiveness as an embed- Description ded network microcontroller. High performance is achieved by optimizing the The eZ80F91 MCU includes the following periph- internal bus design of the eZ80 CPU with shared eral elements: memories, dedicated Ethernet Tx/Rx DMAs, and On-Chip Memory Tx/Rx FIFOs. This bus design provides the highest data throughput over the Ethernet interface, yet The eZ80F91 device offers 256 KB of Flash requires minimum eZ80 CPU intervention and Program Memory. A separate page of 512 bytes minimizes system loading. Flash memory is available for general device configuration data. Other on-chip memory features Infrared Encoder/Decoder include: • Supports IrDA SIR format • Single power supply operation • Operates seamlessly with on-chip UART • Page erase feature: 2048 bytes/page • Interfaces with IrDA-compliant transceivers • Fast page erase and byte program operation • Supports transmit/receive to 115 Kbps • 78 ns minimum read cycle • Endurance: 10,000 write cycles (typical) Universal Asynchronous Receiver/ Transmitter • Data can be retained for more than 100 years at room temperature Each of the two UART channels contains a transmitter, a receiver, control logic/registers, and In addition, 16 KB of high-speed, relocatable a Baud Rate Generator (BRG). SRAM is available, of which 8 KB is for general- • The BRG produces a lower-frequency bit clock purpose use. Another 8 KB of SRAM is used by the from the system clock. All standard baud rates EMAC for Ethernet operation, but is also user- up to 115 Kbps (and higher) are supported. accessible when Ethernet functionality is not required. • The UART module implements the logic required to support asynchronous communica- General-Purpose Input/Output tions, hardware flow control, and 9-bit charac- There are 32 bits of GPIO. All GPIO pins are ter format. The module also contains separate individually programmable and support the 16-byte-deep transmit and receive FIFOs. PB013507-0412 eZ80Acclaim! Flash Microcontrollers eZ80F91 MCU Product Brief 3 Inter-Integrated Circuit RTC operates from an isolated RTC_VDD pin to The I2C channel contains control registers and a allow constant operation from a battery. 2 clock rate generator. The I C interface operates in Chip-Select/Wait State Generator and four modes: Master Transmit or Receive and Slave WAIT Pin Transmit or Receive. A standard and fast I2C speed of 100 kbps and 400 kbps are supported. Four independent chip selects facilitate glueless interface to system memory and external devices. Serial Peripheral Interface Each chip-select can be configured for up to 7 wait The SPI channel contains control registers and a states and supports either memory or I/O space. clock rate generator. The SPI is a synchronous Memory chip selects can be individually serial interface allowing multiple SPI devices to be programmed on a 64 KB boundary. I/O chip selects interconnected. The SPI interface is configured to can choose a 256-byte section of I/O space. The function either as a master or a slave. WAIT input pin allows interface with slow periph- erals. It also supports Z80, Intel, and Motorola bus Programmable Reload Timers modes. The eZ80F91 MCU provides four independent JTAG Interface Programmable Reloadable Counter Timers (PRT) to handle complex timing functions. Each timer is An IEEE 1149.1-compatible five-pin test access a 16-bit downcounter and offers a 4-bit clock port (TAP) is provided to interface with on-chip prescaler with four selectable taps for CLK ÷ 4, test logic defined by IEEE standard. The TAP also CLK ÷ 16, CLK ÷ 64 and CLK ÷ 256. The timers includes Boundary Scan functions and is used to operates in basic mode supporting SINGLE-PASS control on-chip emulation/debugging capabilities. or CONTINUOUS count. Additional features Some features include software break points, 64- include 4 input captures, 4 output compares, word trace buffer, complex break points using 2 external event counters, and 4 PWMs that can address and data masks, and cascadable triggers. operate independently or in unison. Any one of the PLL and On-Chip Crystal Oscillator input capture pins can be programmed as master PWM power-trip inputs. The eZ80F91 MCU features a low-power, programmable PLL that can be selected to generate Watchdog Timer the system clock. Taking the input from the The WDT features four programmable time-out on-chip crystal oscillator, the PLL generates periods. It operates either from the main system system clock speed up to 50 MHz from low-cost, clock, the on-chip 32 KHz oscillator (from the low-frequency external crystals in the range of RTC), or the internal RC oscillator. The time-out 1 MHz to 10 MHz. action of the WDT is user-programmable for either Zilog Debug Interface a hardware reset or a non-maskable interrupt to the eZ80 CPU. The source of action taken after a WDT The Zilog Debug Interface (ZDI) incorporates the time-out is indicated by a WDT status bit. functions of an in-circuit emulator. ZDI allows you to single-step code, change registers, edit Real Time Clock programs, and view status of the internal registers. The RTC allows counting of seconds, minutes, Block Transfer Instructions hours, day-of-the-week, day-of-the-month, month, year, and century. Alarms and interrupts can be set Block transfer instructions with expanded repeat for seconds, minutes, hours, and day-of-the-week. capability are added to the eZ80 CPU. They The RTC input is taken either from the on-chip provide high-performance data transfer similar to 32 KHz oscillator or from a 50/60 Hz input. The hardware DMAs. PB013507-0412 eZ80Acclaim! Flash Microcontrollers eZ80F91 MCU Product Brief 4 Power Management • Extended temperature, –40ºC to +105ºC • Supply current at 50 MHz; 50 mA (typical) The eZ80F91 MCU supports several power • Supply current in HALT mode with peripherals management features. Two peripheral powered down; <5 mA (typical) Power-Down Registers allow independent clock gating of on-chip peripherals under software • Supply current, SLEEP mode: <50 µA (typical) control while operating under normal conditions. The eZ80 CPU writes to the control registers to Support Tools disable the clock from driving any one of the peripherals while they are inactive.
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