PRINCIPLES OF COMPUTER ARCHITECTURE CLASS TEST EDITION – AUGUST 1999 Miles J. Murdocca Department of Computer Science Rutgers University New Brunswick, NJ 08903 (USA) [email protected] http://www.cs.rutgers.edu/~murdocca/ Vincent P. Heuring Department of Electrical and Computer Engineering University of Colorado Boulder, CO 80309-0425 (USA) [email protected] http://ece-www.colorado.edu/faculty/heuring.html Copyright © 1999 Prentice Hall For Ellen, Alexandra, and Nicole and For Gretchen PREFACE iii PREFACE About the Book Our goal in writing this book is to expose the inner workings of the modern digital computer at a level that demystifies what goes on inside the machine. The only prerequisite to Principles of Computer Architecture is a working knowledge of a high-level programming language. The breadth of material has been chosen to cover topics normally found in a first course in computer architecture or computer organization. The breadth and depth of coverage have been steered to also place the beginning student on a solid track for con- tinuing studies in computer related disciplines. In creating a computer architecture textbook, the technical issues fall into place fairly naturally, and it is the organizational issues that bring important features to fruition. Some of the features that received the greatest attention in Principles of Computer Architecture include the choice of the instruction set architecture (ISA), the use of case studies, and a voluminous use of examples and exercises. THE INSTRUCTIONAL ISA A textbook that covers assembly language programming needs to deal with the issue of which instruction set architecture (ISA) to use: a model architecture, or one of the many commercial architectures. The choice impacts the instruc- tor, who may want an ISA that matches a local platform used for student assembly language programming assignments. To complicate matters, the local platform may change from semester to semester: yesterday the MIPS, today the Pentium, tomorrow the SPARC. The authors opted for having it both ways by adopting a SPARC-subset for an instructional ISA, called “A RISC Computer” (ARC), which is carried through the mainstream of the iv PREFACE book, and complementing it with platform-independent software tools that sim- ulate the ARC ISA as well as the MIPS and x86 (Pentium) ISAs. CASE STUDIES, EXAMPLES, AND EXERCISES Every chapter contains at least one case study as a means for introducing the stu- dent to “real world” examples of the topic being covered. This places the topic in perspective, and in the authors’ opinion, lends an air of reality and interest to the material. We incorporated as many examples and exercises as we practically could, cover- ing the most significant points in the text. Additional examples and solutions are available on-line, at the companion Web site (see below.) Coverage of Topics Our presentation views a computer as an integrated system. If we were to choose a subtitle for the book, it might be “An Integrated Approach,” which reflects high level threads that tie the material together. Each topic is covered in the context of the entire machine of which it is a part, and with a perspective as to how the implementation affects behavior. For example, the finite precision of binary numbers is brought to bear in observing how many 1’s can be added to a floating point number before the error in the representation exceeds 1. (This is one rea- son why floating point numbers should be avoided as loop control variables.) As another example, subroutine linkage is covered with the expectation that the reader may someday be faced with writing C or Java programs that make calls to routines in other high level languages, such as Fortran. As yet another example of the integrated approach, error detection and correc- tion are covered in the context of mass storage and transmission, with the expec- tation that the reader may tackle networking applications (where bit errors and data packet losses are a fact of life) or may have to deal with an unreliable storage medium such as a compact disk read-only memory (CD-ROM.) Computer architecture impacts many of the ordinary things that computer pro- fessionals do, and the emphasis on taking an integrated approach addresses the great diversity of areas in which a computer professional should be educated. This emphasis reflects a transition that is taking place in many computer related undergraduate curricula. As computer architectures become more complex they must be treated at correspondingly higher levels of abstraction, and in some ways PREFACE v they also become more technology-dependent. For this reason, the major portion of the text deals with a high level look at computer architecture, while the appen- dices and case studies cover lower level, technology-dependent aspects. THE CHAPTERS Chapter 1: Introduction introduces the textbook with a brief history of com- puter architecture, and progresses through the basic parts of a computer, leaving the student with a high level view of a computer system. The conventional von Neumann model of a digital computer is introduced, followed by the System Bus Model, followed by a topical exploration of a typical computer. This chapter lays the groundwork for the more detailed discussions in later chapters. Chapter 2: Data Representation covers basic data representation. One’s comple- ment, two’s complement, signed magnitude and excess representations of signed numbers are covered. Binary coded decimal (BCD) representation, which is fre- quently found in calculators, is also covered in Chapter 2. The representation of floating point numbers is covered, including the IEEE 754 floating point stan- dard for binary numbers. The ASCII, EBCDIC, and Unicode character repre- sentations are also covered. Chapter 3: Arithmetic covers computer arithmetic and advanced data represen- tations. Fixed point addition, subtraction, multiplication, and division are cov- ered for signed and unsigned integers. Nine’s complement and ten’s complement representations, used in BCD arithmetic, are covered. BCD and floating point arithmetic are also covered. High performance methods such as carry-lookahead addition, array multiplication, and division by functional iteration are covered. A short discussion of residue arithmetic introduces an unconventional high perfor- mance approach. Chapter 4: The Instruction Set Architecture introduces the basic architectural components involved in program execution. Machine language and the fetch-execute cycle are covered. The organization of a central processing unit is detailed, and the role of the system bus in interconnecting the arithmetic/logic unit, registers, memory, input and output units, and the control unit are dis- cussed. Assembly language programming is covered in the context of the instructional ARC (A RISC Computer), which is loosely based on the commercial SPARC architecture. The instruction names, instruction formats, data formats, and the vi PREFACE suggested assembly language syntax for the SPARC have been retained in the ARC, but a number of simplifications have been made. Only 15 SPARC instruc- tions are used for most of the chapter, and only a 32-bit unsigned integer data type is allowed initially. Instruction formats are covered, as well as addressing modes. Subroutine linkage is explored in a number of styles, with a detailed dis- cussion of parameter passing using a stack. Chapter 5: Languages and the Machine connects the programmer’s view of a computer system with the architecture of the underlying machine. System soft- ware issues are covered with the goal of making the low level machine visible to a programmer. The chapter starts with an explanation of the compilation process, first covering the steps involved in compilation, and then focusing on code gen- eration. The assembly process is described for a two-pass assembler, and examples are given of generating symbol tables. Linking, loading, and macros are also cov- ered. Chapter 6: Datapath and Control provides a step-by-step analysis of a datapath and a control unit. Two methods of control are discussed: microprogrammed and hardwired. The instructor may adopt one method and omit the other, or cover both methods as time permits. The example microprogrammed and hardwired control units implement the ARC subset of the SPARC assembly language intro- duced in Chapter 4. Chapter 7: Memory covers computer memory beginning with the organization of a basic random access memory, and moving to advanced concepts such as cache and virtual memory. The traditional direct, associative, and set associative cache mapping schemes are covered, as well as multilevel caches. Issues such as overlays, replacement policies, segmentation, fragmentation, and the translation lookaside buffer are also discussed. Chapter 8: Input and Output covers bus communication and bus access meth- ods. Bus-to-bus bridging is also described. The chapter covers various I/O devices commonly in use such as disks, keyboards, printers, and displays. Chapter 9: Communication covers network architectures, focusing on modems, local area networks, and wide area networks. The emphasis is primarily on net- work architecture, with accessible discussions of protocols that spotlight key fea- tures of network architecture. Error detection and correction are covered in depth. The TCP/IP protocol suite is introduced in the context of the Internet. PREFACE vii Chapter 10: Trends in Computer Architecture covers advanced architectural features that have either emerged or taken new forms in recent years. The early part of the chapter covers the motivation for reduced instruction set computer (RISC) processors, and the architectural implications of RISC. The latter portion of the chapter covers multiple instruction issue machines, and very large instruc- tion word (VLIW) machines. A case study makes RISC features visible to the programmer in a step-by-step analysis of a C compiler-generated SPARC pro- gram, with explanations of the stack frame usage, register usage, and pipelining. The chapter covers parallel and distributed architectures, and interconnection networks used in parallel and distributed processing.