DOCSLIB.ORG

A Theoretical Framework for Algorithm-Architecture Co-Design

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A Theoretical Framework for Algorithm-Architecture Co-Design Preprint – To appear in the IEEE Int’l. Parallel & Distributed Processing Symp. (IPDPS), May 2013 A theoretical framework for algorithm-architecture co-design Kenneth Czechowski, Richard Vuduc School of Computational Science and Engineering Georgia Institute of Technology, Atlanta, Georgia fkentcz,[email protected] Abstract—We consider the problem of how to en- 28, 44], as well as the classical theory of cir- able computer architects and algorithm designers to cuit models and the area-time trade-offs studied reason directly and analytically about the relationship in models based on very large-scale integration between high-level architectural features and algo- rithm characteristics. We propose a modeling frame- (VLSI) [37, 49]. Our analysis is in many ways work designed to help understand the long-term most similar to several recent theoretical exascale and high-level impacts of algorithmic and technol- modeling studies [22, 47], combined with trends ogy trends. This model connects abstract commu- analysis [34]. However, our specific methods re- nication complexity analysis—with respect to both turn to higher-level I/O-centric complexity analy- the inter-core and inter-processor networks and the memory hierarchy—with current technology proposals sis [4, 5, 10, 13, 21, 54], pushing it further by trying and projections. We illustrate how one might use the to resolve analytical constants, which is necessary framework by instantiating a particular model for a to connect abstract complexity measures with the class of architectures and sample algorithms (three- physical constraints imposed by power and die dimensional fast Fourier transforms, matrix multiply, area. This approach necessarily will not yield cycle- and three-dimensional stencil). Then, as a suggestive demonstration, we analyze a number of what-if sce- accurate performance estimates, and that is not our narios within the model in light of these trends to aim. Rather, our hope is that a principled algorith- suggest broader statements and alternative futures for mic analysis that accounts for major architectural power-constrained architectures and algorithms. parameters will still yield interesting insights and suggest new directions for improving performance I. INTRODUCTION and scalability in the long run. We seek a formal framework that explicitly re- A formal framework. We pose the formal co- lates characteristics of an algorithm, such as its design problem as follows. Let a be an algorithm inherent parallelism or memory behavior, with from a set A of algorithms that all perform the parameters of an architecture, such as the number same computation within the same desired level of cores, structure of the memory hierarchy, or of accuracy. The set A might contain different network topology. Our ultimate goal is to say algorithms, such as “A = ffast Fourier trans- precisely and analytically how high-level changes form, F-cycle multigridg,” for the Poisson model to the architecture might affect the execution problem [17, 41]. Or, A may be a set of tuning time, scalability, accuracy, and power-efficiency parameters for one algorithm, such as the set of of a computation; and, conversely, identify what tile sizes for matrix multiply. Next, let µ be a classes of computation might best match a given machine architecture from a set M, and suppose architecture. Our approach marries abstract al- that each processor of µ has an area of χ(µ). gorithmic complexity analysis with key physical Lastly, let T (n; a; µ) be the time to execute a on constraints, such as caps on power and die area, µ for a problem of size n, while using a maximum that will be critical in the extreme scale systems of instantaneous power of Φ(µ). Then, our goal is to 2018 and beyond [1, 35]. We refer to our approach determine the algorithm a and architecture µ that as one of algorithm-architecture co-design. minimize time subject to constraints on total power We say “algorithm-architecture” rather than and processor die area, e.g., “hardware-software,” so as to evoke a high-level mathematical process that precedes and comple- (a∗; µ∗) = argmin T (n; a; µ) (1) ments traditional methods based on detailed ar- (a2A; µ2M) chitecture simulation of concrete benchmark code subject to artifacts and traces [9, 23, 27, 30, 48, 51]. Our ap- ∗ proach takes inspiration from prior work on high- Φ(µ ) = Φmax (2) ∗ level performance analysis and modeling [3, 26– χ(µ ) = χmax; (3) 1 Preprint – To appear in the IEEE Int’l. Parallel & Distributed Processing Symp. (IPDPS), May 2013 Performance on FFT Power 4.7175 DRAM More DRAM bandwidth 2.3588 $ C C C C C C $ Echelon C C C C C C Memory Bandwidth (TB/s) C C C C C C C C C C C C C C C C C C 0 0 183.5 367 Area Cache Size (MB) Performance on Matrix Multiply 4.7175 More More cores cache DRAM DRAM 2.3588 $ C C C C C C $ Echelon C C C C C C Memory Bandwidth (TB/s) C C C C C C Higher C C C C C C 0 frequency C C C C C C 0 183.5 367 Cache Size (MB) (b) Projected performance for a 3D FFT and matrix (a) A notional power/transistor allocation problem multiply at some problem size (lighter is better) Figure 1: (a) In our framework, a fixed die area (allocated between cores and cache) and a fixed power budget (allocated between core frequency and bandwidth), define a space of possible machines. (b) Different algorithms may perform differently on these machines. The marker is the approximate “location” within this space of the NVIDIA Echelon GPU-like architecture proposed for the year 2017 [32]. In the 3D FFT example, the optimal configuration is 2.6 times faster than Echelon. where Φmax and χmax are caps on power and die get (y-axis) to memory bandwidth, compared to area, respectively. The central research problem matrix multiply. T (n; a; µ) Φ(µ) is to determine the form of , , and However, Figure 1b also suggests an intriguing χ(µ) . The significance and novelty of this analysis possibility. Observe that a die area configuration framework is that it explicitly binds characteristics (x-axis) that is good for matrix multiply will also of algorithms and architectures, Equation (1), with be good for an FFT; to make a system that can physical hardware constraints, Equations (2)–(3). perform “optimally” on both workloads, we would A demonstration. Suppose we wish to design need the ability to dynamically shift power from a manycore processor µ, which we represent by the processor to memory bandwidth, by a large factor of roughly 7×. That is, reconfigurability of the four-tuple (βmem; q; f; Z): βmem is the processor- memory bandwidth (words per unit time), q is processor transistors may be relatively less im- the number of cores per processor, f is the clock portant than extreme power reconfigurability with frequency of each core (cycles per unit time), and respect to bandwidth. Whether one can build such Z is the total size of the aggregate on-chip cache a system is a separate question; this demonstration (in words), assuming just a two-level hierarchy suggests and attempts to quantify the possibility. (cache and main memory). Further suppose that The remainder of this paper formalizes this anal- 2 the χmax = 141 mm of die area can be divided ysis. As a demonstration, we develop an analytical between on-chip cache (Z) and cores (q). Lastly, model of these constraints, Φ(µ) and χ(µ), as well suppose the node power budget is constrained to as performance models, T (n; a; µ). To suggest the Φmax = 173 Watts, which can be used to increase possibilities of the framework, we develop models cycle-frequency (f) or boost off-die memory band- for a full-system configuration, consisting of a dis- width (βmem). Figure 1a is a cartoon that suggests tributed memory machine comprising any number how these parameters and constraints imply a of manycore processors connected by a network, in space of possible designs. Figure 1b shows how, the case of distributed matrix multiply, distributed given a specific model of different algorithms on 3D FFTs, and distributed stencil algorithms. We do this space of machines, we might then solve the op- not view any specific models and projections as the timization problem of Equations 1–3 to identify op- main contribution of our work. Rather, we wish timal systems. Unsurprisingly, a processor tuned to emphasize the basic framework, with the large for a communication-intensive 3D fast Fourier variety of potential detailed modeling strategies, transform will devote more of a fixed power bud- analyses, and projections as possibilities based on 2 Preprint – To appear in the IEEE Int’l. Parallel & Distributed Processing Symp. (IPDPS), May 2013 it. caches and memory systems, and on-chip and off- chip networks [6, 7, 16, 24, 31, 35, 38, 50]. Since II. BACKGROUND AND RELATED WORK our ultimate goal is to consider potential long-term The principal challenge is how to connect power outcomes, we focus on recent projections of scaling (and implicitly, energy) and area constraints with trends [6, 32, 34, 35, 50]. a complexity analysis. There are numerous ap- III. AN EXAMPLE OF INSTANTIATING A MODEL proaches. The most widely-cited come from the WITHIN THE FRAMEWORK computer architecture community [11, 19, 25, 26, 40, 57]. In such approaches, the application or This section explains how one might go about algorithm is typically abstracted away through constructing meaningful cost and constraint mod- an Amdahl’s Law style analysis, which means it els within the framework. In particular, we in- can be difficult to relate high-level algorithmic stantiate specific forms for T (n; a; µ), Φ(µ), and characteristics to architectures precisely.
Load more

Recommended publications
  • Three-Dimensional Integrated Circuit Design: EDA, Design And
    Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change.
    [Show full text]
  • Declustering Spatial Databases on a Multi-Computer Architecture
    Declustering spatial databases on a multi-computer architecture 1 2 ? 3 Nikos Koudas and Christos Faloutsos and Ibrahim Kamel 1 Computer Systems Research Institute University of Toronto 2 AT&T Bell Lab oratories Murray Hill, NJ 3 Matsushita Information Technology Lab oratory Abstract. We present a technique to decluster a spatial access metho d + on a shared-nothing multi-computer architecture [DGS 90]. We prop ose a software architecture with the R-tree as the underlying spatial access metho d, with its non-leaf levels on the `master-server' and its leaf no des distributed across the servers. The ma jor contribution of our work is the study of the optimal capacity of leaf no des, or `chunk size' (or `striping unit'): we express the resp onse time on range queries as a function of the `chunk size', and we show how to optimize it. We implemented our metho d on a network of workstations, using a real dataset, and we compared the exp erimental and the theoretical results. The conclusion is that our formula for the resp onse time is very accurate (the maximum relative error was 29%; the typical error was in the vicinity of 10-15%). We illustrate one of the p ossible ways to exploit such an accurate formula, by examining several `what-if ' scenarios. One ma jor, practical conclusion is that a chunk size of 1 page gives either optimal or close to optimal results, for a wide range of the parameters. Keywords: Parallel data bases, spatial access metho ds, shared nothing ar- chitecture. 1 Intro duction One of the requirements for the database management systems (DBMSs) of the future is the ability to handle spatial data.
    [Show full text]
  • Chap01: Computer Abstractions and Technology
    CHAPTER 1 Computer Abstractions and Technology 1.1 Introduction 3 1.2 Eight Great Ideas in Computer Architecture 11 1.3 Below Your Program 13 1.4 Under the Covers 16 1.5 Technologies for Building Processors and Memory 24 1.6 Performance 28 1.7 The Power Wall 40 1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors 43 1.9 Real Stuff: Benchmarking the Intel Core i7 46 1.10 Fallacies and Pitfalls 49 1.11 Concluding Remarks 52 1.12 Historical Perspective and Further Reading 54 1.13 Exercises 54 CMPS290 Class Notes (Chap01) Page 1 / 24 by Kuo-pao Yang 1.1 Introduction 3 Modern computer technology requires professionals of every computing specialty to understand both hardware and software. Classes of Computing Applications and Their Characteristics Personal computers o A computer designed for use by an individual, usually incorporating a graphics display, a keyboard, and a mouse. o Personal computers emphasize delivery of good performance to single users at low cost and usually execute third-party software. o This class of computing drove the evolution of many computing technologies, which is only about 35 years old! Server computers o A computer used for running larger programs for multiple users, often simultaneously, and typically accessed only via a network. o Servers are built from the same basic technology as desktop computers, but provide for greater computing, storage, and input/output capacity. Supercomputers o A class of computers with the highest performance and cost o Supercomputers consist of tens of thousands of processors and many terabytes of memory, and cost tens to hundreds of millions of dollars.
    [Show full text]
  • Arch2030: a Vision of Computer Architecture Research Over
    Arch2030: A Vision of Computer Architecture Research over the Next 15 Years This material is based upon work supported by the National Science Foundation under Grant No. (1136993). Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation. Arch2030: A Vision of Computer Architecture Research over the Next 15 Years Luis Ceze, Mark D. Hill, Thomas F. Wenisch Sponsored by ARCH2030: A VISION OF COMPUTER ARCHITECTURE RESEARCH OVER THE NEXT 15 YEARS Summary .........................................................................................................................................................................1 The Specialization Gap: Democratizing Hardware Design ..........................................................................................2 The Cloud as an Abstraction for Architecture Innovation ..........................................................................................4 Going Vertical ................................................................................................................................................................5 Architectures “Closer to Physics” ................................................................................................................................5 Machine Learning as a Key Workload ..........................................................................................................................6 About this
    [Show full text]
  • Computer Architecture Techniques for Power-Efficiency
    MOCL005-FM MOCL005-FM.cls June 27, 2008 8:35 COMPUTER ARCHITECTURE TECHNIQUES FOR POWER-EFFICIENCY i MOCL005-FM MOCL005-FM.cls June 27, 2008 8:35 ii MOCL005-FM MOCL005-FM.cls June 27, 2008 8:35 iii Synthesis Lectures on Computer Architecture Editor Mark D. Hill, University of Wisconsin, Madison Synthesis Lectures on Computer Architecture publishes 50 to 150 page publications on topics pertaining to the science and art of designing, analyzing, selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals. Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras and Margaret Martonosi 2008 Chip Mutiprocessor Architecture: Techniques to Improve Throughput and Latency Kunle Olukotun, Lance Hammond, James Laudon 2007 Transactional Memory James R. Larus, Ravi Rajwar 2007 Quantum Computing for Computer Architects Tzvetan S. Metodi, Frederic T. Chong 2006 MOCL005-FM MOCL005-FM.cls June 27, 2008 8:35 Copyright © 2008 by Morgan & Claypool All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means—electronic, mechanical, photocopy, recording, or any other except for brief quotations in printed reviews, without the prior permission of the publisher. Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras and Margaret Martonosi www.morganclaypool.com ISBN: 9781598292084 paper ISBN: 9781598292091 ebook DOI: 10.2200/S00119ED1V01Y200805CAC004 A Publication in the Morgan & Claypool Publishers
    [Show full text]
  • COSC 6385 Computer Architecture - Multi-Processors (IV) Simultaneous Multi-Threading and Multi-Core Processors Edgar Gabriel Spring 2011
    COSC 6385 Computer Architecture - Multi-Processors (IV) Simultaneous multi-threading and multi-core processors Edgar Gabriel Spring 2011 Edgar Gabriel Moore’s Law • Long-term trend on the number of transistor per integrated circuit • Number of transistors double every ~18 month Source: http://en.wikipedia.org/wki/Images:Moores_law.svg COSC 6385 – Computer Architecture Edgar Gabriel 1 What do we do with that many transistors? • Optimizing the execution of a single instruction stream through – Pipelining • Overlap the execution of multiple instructions • Example: all RISC architectures; Intel x86 underneath the hood – Out-of-order execution: • Allow instructions to overtake each other in accordance with code dependencies (RAW, WAW, WAR) • Example: all commercial processors (Intel, AMD, IBM, SUN) – Branch prediction and speculative execution: • Reduce the number of stall cycles due to unresolved branches • Example: (nearly) all commercial processors COSC 6385 – Computer Architecture Edgar Gabriel What do we do with that many transistors? (II) – Multi-issue processors: • Allow multiple instructions to start execution per clock cycle • Superscalar (Intel x86, AMD, …) vs. VLIW architectures – VLIW/EPIC architectures: • Allow compilers to indicate independent instructions per issue packet • Example: Intel Itanium series – Vector units: • Allow for the efficient expression and execution of vector operations • Example: SSE, SSE2, SSE3, SSE4 instructions COSC 6385 – Computer Architecture Edgar Gabriel 2 Limitations of optimizing a single instruction
    [Show full text]
  • Adéquation Algorithme Architecture : Aspects Logiciels, Matériels Et Cognitifs Dominique Ginhac
    Adéquation Algorithme architecture : Aspects logiciels, matériels et cognitifs Dominique Ginhac To cite this version: Dominique Ginhac. Adéquation Algorithme architecture : Aspects logiciels, matériels et cognitifs. Traitement du signal et de l’image [eess.SP]. Université de Bourgogne, 2008. tel-00646480 HAL Id: tel-00646480 https://tel.archives-ouvertes.fr/tel-00646480 Submitted on 30 Nov 2011 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Habilitation à Diriger des Recherches LE2I UMR CNRS 5158 Université de Bourgogne ADÉQUATION ALGORITHME ARCHITECTURE ASPECTS LOGICIELS, MATÉRIELS ET COGNITIFS présentée par DOMINIQUE GINHAC Composition du Jury Pr. PIERRE MAGNAN - Institut Supérieur de l'Aéronautique et de l'Espace - Rapporteur Pr. ALAIN MÉRIGOT - Université Paris Sud - Rapporteur Pr. MICHEL ROBERT - Université Montpellier II - Rapporteur DR AXEL CLEEREMANS - Université Libre de Bruxelles - Examinateur Pr PATRICK MARQUIE - Université de Bourgogne - Examinateur Pr MICHEL PAINDAVOINE - Université de Bourgogne - Directeur de l’HDR Remerciements Sommaire
    [Show full text]
  • A Hybrid-Parallel Architecture for Applications in Bioinformatics
    A Hybrid-parallel Architecture for Applications in Bioinformatics M.Sc. Jan Christian Kässens Dissertation zur Erlangung des akademischen Grades Doktor der Ingenieurwissenschaften (Dr.-Ing.) der Technischen Fakultät der Christian-Albrechts-Universität zu Kiel eingereicht im Jahr 2017 Kiel Computer Science Series (KCSS) 2017/4 dated 2017-11-08 URN:NBN urn:nbn:de:gbv:8:1-zs-00000335-a3 ISSN 2193-6781 (print version) ISSN 2194-6639 (electronic version) Electronic version, updates, errata available via https://www.informatik.uni-kiel.de/kcss The author can be contacted via [email protected] Published by the Department of Computer Science, Kiel University Computer Engineering Group Please cite as: Ź Jan Christian Kässens. A Hybrid-parallel Architecture for Applications in Bioinformatics Num- ber 2017/4 in Kiel Computer Science Series. Department of Computer Science, 2017. Dissertation, Faculty of Engineering, Kiel University. @book{Kaessens17, author = {Jan Christian K\"assens}, title = {A Hybrid-parallel Architecture for Applications in Bioinformatics}, publisher = {Department of Computer Science, CAU Kiel}, year = {2017}, number = {2017/4}, doi = {10.21941/kcss/2017/4}, series = {Kiel Computer Science Series}, note = {Dissertation, Faculty of Engineering, Kiel University.} } © 2017 by Jan Christian Kässens ii About this Series The Kiel Computer Science Series (KCSS) covers dissertations, habilitation theses, lecture notes, textbooks, surveys, collections, handbooks, etc. written at the Department of Computer Science at Kiel University. It was initiated in 2011 to support authors in the dissemination of their work in electronic and printed form, without restricting their rights to their work. The series provides a unified appearance and aims at high-quality typography. The KCSS is an open access series; all series titles are electronically available free of charge at the department’s website.
    [Show full text]
  • CHAPTER 1 Introduction
    CHAPTER 1 Introduction 1.1 Overview 1 1.2 The Main Components of a Computer 3 1.3 An Example System: Wading through the Jargon 4 1.4 Standards Organizations 15 1.5 Historical Development 16 1.5.1 Generation Zero: Mechanical Calculating Machines (1642–1945) 17 1.5.2 The First Generation: Vacuum Tube Computers (1945–1953) 19 1.5.3 The Second Generation: Transistorized Computers (1954–1965) 23 1.5.4 The Third Generation: Integrated Circuit Computers (1965–1980) 26 1.5.5 The Fourth Generation: VLSI Computers (1980–????) 26 1.5.6 Moore’s Law 30 1.6 The Computer Level Hierarchy 31 1.7 The von Neumann Model 34 1.8 Non-von Neumann Models 37 Chapter Summary 40 CMPS375 Class Notes (Chap01) Page 1 / 11 by Kuo-pao Yang 1.1 Overview 1 • Computer Organization o We must become familiar with how various circuits and components fit together to create working computer system. o How does a computer work? • Computer Architecture: o It focuses on the structure and behavior of the computer and refers to the logical aspects of system implementation as seen by the programmer. o Computer architecture includes many elements such as instruction sets and formats, operation code, data types, the number and types of registers, addressing modes, main memory access methods, and various I/O mechanisms. o How do I design a computer? • The computer architecture for a given machine is the combination of its hardware components plus its instruction set architecture (ISA). • The ISA is the agreed-upon interface between all the software that runs on the machine and the hardware that executes it.
    [Show full text]
  • An Unprivileged OS Kernel for General Purpose Distributed Computing
    Graduate School ETD Form 9 (Revised 12/07) PURDUE UNIVERSITY GRADUATE SCHOOL Thesis/Dissertation Acceptance This is to certify that the thesis/dissertation prepared By Jeffrey A. Turkstra Entitled Metachory: An Unprivileged OS Kernel for General Purpose Distributed Computing For the degree of Doctor of Philosophy Is approved by the final examining committee: DAVID G. MEYER SAMUEL P. MIDKIFF Chair CHARLIE HU MARK C. JOHNSON RICHARD L. KENNELL To the best of my knowledge and as understood by the student in the Research Integrity and Copyright Disclaimer (Graduate School Form 20), this thesis/dissertation adheres to the provisions of Purdue University’s “Policy on Integrity in Research” and the use of copyrighted material. Approved by Major Professor(s): ____________________________________DAVID G. MEYER ____________________________________ Approved by: V. Balakrishnan 04-17-2013 Head of the Graduate Program Date METACHORY: AN UNPRIVILEGED OS KERNEL FOR GENERAL PURPOSE DISTRIBUTED COMPUTING A Dissertation Submitted to the Faculty of Purdue University by Jeffrey A. Turkstra In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy May 2013 Purdue University West Lafayette, Indiana ii I dedicate this dissertation to... my wife, Shelley L. Turkstra. I would have given up long ago were it not for her|you are the love of my life and my strength; my son, Jefferson E. Turkstra, the joy of my life and hope for the future; my grandmother, Aleatha J. Turkstra, my connection to the past and source of limitless endurance. iii ACKNOWLEDGMENTS It is impossible to enumerate all of the people that have made this dissertation possible|my memory is just not that good.
    [Show full text]
  • Integral Estimation in Quantum Physics
    INTEGRAL ESTIMATION IN QUANTUM PHYSICS by Jane Doe A dissertation submitted to the faculty of The University of Utah in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Mathematical Physics Department of Mathematics The University of Utah May 2016 Copyright c Jane Doe 2016 All Rights Reserved The University of Utah Graduate School STATEMENT OF DISSERTATION APPROVAL The dissertation of Jane Doe has been approved by the following supervisory committee members: Cornelius L´anczos , Chair(s) 17 Feb 2016 Date Approved Hans Bethe , Member 17 Feb 2016 Date Approved Niels Bohr , Member 17 Feb 2016 Date Approved Max Born , Member 17 Feb 2016 Date Approved Paul A. M. Dirac , Member 17 Feb 2016 Date Approved by Petrus Marcus Aurelius Featherstone-Hough , Chair/Dean of the Department/College/School of Mathematics and by Alice B. Toklas , Dean of The Graduate School. ABSTRACT Blah blah blah blah blah blah blah blah blah blah blah blah blah blah blah. Blah blah blah blah blah blah blah blah blah blah blah blah blah blah blah. Blah blah blah blah blah blah blah blah blah blah blah blah blah blah blah. Blah blah blah blah blah blah blah blah blah blah blah blah blah blah blah. Blah blah blah blah blah blah blah blah blah blah blah blah blah blah blah. Blah blah blah blah blah blah blah blah blah blah blah blah blah blah blah. Blah blah blah blah blah blah blah blah blah blah blah blah blah blah blah. Blah blah blah blah blah blah blah blah blah blah blah blah blah blah blah.
    [Show full text]
  • Operating Systems and Middleware: Supporting Controlled Interaction
    Operating Systems and Middleware: Supporting Controlled Interaction Max Hailperin Gustavus Adolphus College Revised Edition 1.1 July 27, 2011 Copyright c 2011 by Max Hailperin. This work is licensed under the Creative Commons Attribution-ShareAlike 3.0 Unported License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/3.0/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California, 94105, USA. Bibliography [1] Atul Adya, Barbara Liskov, and Patrick E. O’Neil. Generalized iso- lation level definitions. In Proceedings of the 16th International Con- ference on Data Engineering, pages 67–78. IEEE Computer Society, 2000. [2] Alfred V. Aho, Peter J. Denning, and Jeffrey D. Ullman. Principles of optimal page replacement. Journal of the ACM, 18(1):80–93, 1971. [3] AMD. AMD64 Architecture Programmer’s Manual Volume 2: System Programming, 3.09 edition, September 2003. Publication 24593. [4] Dave Anderson. You don’t know jack about disks. Queue, 1(4):20–30, 2003. [5] Dave Anderson, Jim Dykes, and Erik Riedel. More than an interface— SCSI vs. ATA. In Proceedings of the 2nd Annual Conference on File and Storage Technology (FAST). USENIX, March 2003. [6] Ross Anderson. Security Engineering: A Guide to Building Depend- able Distributed Systems. Wiley, 2nd edition, 2008. [7] Apple Computer, Inc. Kernel Programming, 2003. Inside Mac OS X. [8] Apple Computer, Inc. HFS Plus volume format. Technical Note TN1150, Apple Computer, Inc., March 2004. [9] Ozalp Babaoglu and William Joy. Converting a swap-based system to do paging in an architecture lacking page-referenced bits.
    [Show full text]