Processor Design
1 / Professors
●José María Arnau –Office: C6-115 –Email: [email protected] –Office hours: agreed through email ●Leonidas Kosmidis –Office: Nexus II Building, 1A 124 –Email: [email protected] –Office hours: agreed through email
2 / Course Materials
●http://jarnau.site.ac.upc.edu/PD/ –Course Information –Slides –Lab documentation
3 / High Performance Computing
4 / Course Structure
●Theory lectures (once a week) –Friday 10-12, A6104 –Thursday, Oct 31st ●Lab lectures –Tuesday 12-14, A5S109 ●Assignments –6 lab sessions –2 reviews –1 final project
5 / Evaluation
●Final mark will be based on performance of: –The lab sessions (Lab) –Presentation of a research topic (T) ●Final mark computed as: –0.8 x Lab + 0.2 x T
6 / What will I be able to do after the course?
●Understand and implement a simple pipelined processor ●Program skillfully in a hardware description language ●Understand the intricacies of advanced IC design and development
7 / Contents
1. Moore’s Law and Dennard Scaling 2. Hardware Design Cycle 3. Functional Verification 4. Circuit Design 5. Physical Design
8 / Lab Schedule
Lab Session Session Dates Deliverable Due Date Lab 1. Infrastructure setup and test. 10/09 01/10 Microprocessor selection 17/09 Lab2. Module definition and 01/10 15/10 specification. Workplan 08/10 Lab3. Module implementation 15/10 12/11 22/10 29/10 05/11 (No lab) Lab4. Module review Week of 11-15/11 Interview Lab5. Insertion in pipelined CPU 12/11 10/12 19/11 (No lab) 26/11 03/12 Lab6. CPU review 17/12 Interview Extension of original module 10/12 21/01 17/12
7 or 14/1 9 / Lab Sessions - Module
●Each group will choose one of the following modules to extend their baseline processor 1. Associative cache 2. Branch predictor 3. Store forwarding queue 4. Error detection and correction codes in the memory 5. High performance functional units (i.e. adder, subtracter…) 6. Accelerators (cryptography, neural nets...)
10 / Lab Sessions - Module
●Each group will choose one of the following modules to extend their baseline processor 7. Multi-issue / superscalar 8. Vector extensions 9. Coherent cache for a multiprocessor 10. Random placement cache 11. Lockstep functionality 12. Floating point Unit subset 13.Other modules possible upon agreement with the instructor and the background of the students
11 / Lab Sessions – Baseline Processor
●Can be the processor from PA or different
●Can be in Verilog, VHDL or a higher level HDL language such as Chisel or Bluespec
●Can be an open source or commercial CPU core or GPU
●Must not include the selected module
12 / Lab Sessions – Baseline Processor Examples of Available Options
●Open Source or Commercial Open Sourced CPU Cores: –RISC-V: Ariane (Verilog), Rocket (Chisel), SHAKTI (BlueSpec) –SPARC: LEON3/LEON4 (VHDL), OpenPiton(Verilog), OpenSPARC T1/T2 (Verilog) –Power: OpenPower Microwatt (VHDL) –X86: Zet (Verilog)
●Commercial CPU Cores: – ARM, MIPS
●GPU/Accelerator Cores: –Commercial: ARM Mali-400, ThinkSilicon Nema Pico –Open Source: NVIDIA NVDLA (Verilog)
13 / Bibliography
●Weste, N. H., & Harris, D. “CMOS VLSI Design : A Circuits and Systems Perspective”. 4th Edition, 2010. ●Kahng AB, Lienig J, Markov IL, Hu J. “VLSI Physical Design: from Graph Partitioning to Timing Closure”. Springer Science & Business Media; 2011 Jan 27. ●Mead, C., & Conway, L. Introduction to VLSI systems (Vol. 1080). Reading, MA: Addison-Wesley, 1980
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