Brigham Young University BYU ScholarsArchive Theses and Dissertations 2015-07-01 An Evaluation of Soft Processors as a Reliable Computing Platform Michael Robert Gardiner Brigham Young University - Provo Follow this and additional works at: https://scholarsarchive.byu.edu/etd Part of the Electrical and Computer Engineering Commons BYU ScholarsArchive Citation Gardiner, Michael Robert, "An Evaluation of Soft Processors as a Reliable Computing Platform" (2015). Theses and Dissertations. 5509. https://scholarsarchive.byu.edu/etd/5509 This Thesis is brought to you for free and open access by BYU ScholarsArchive. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of BYU ScholarsArchive. For more information, please contact [email protected], [email protected]. An Evaluation of Soft Processors as a Reliable Computing Platform Michael Robert Gardiner A thesis submitted to the faculty of Brigham Young University in partial fulfillment of the requirements for the degree of Master of Science Michael J. Wirthlin, Chair Brad L. Hutchings Brent E. Nelson Department of Electrical and Computer Engineering Brigham Young University July 2015 Copyright © 2015 Michael Robert Gardiner All Rights Reserved ABSTRACT An Evaluation of Soft Processors as a Reliable Computing Platform Michael Robert Gardiner Department of Electrical and Computer Engineering, BYU Master of Science This study evaluates the benefits and limitations of soft processors operating in a radiation-hardened FPGA, focusing primarily on the performance and reliability of these systems. FPGAs designs for four popular soft processors, the MicroBlaze, LEON3, Cortex- M0 DesignStart, and OpenRISC 1200 are developed for a Virtex-5 FPGA. The performance of these soft processor designs is then compared on ten widely-used benchmark programs. Benchmarking results indicate that the MicroBlaze has the best integer performance of the soft processors, with at least 2.23X better performance on average than the other three processors. However, the LEON3 has the best floating-point performance, with benchmark scores 8.9X higher on average than its competitors. The soft processors' performance is also compared against estimated benchmark scores for a radiation-hardened processor, the RAD750. We find the average performance of the RAD750 to be 2.58X better than the best soft processor scores on each benchmark, although the best soft processor scores were higher on two benchmarks. The soft proces- sors' inability to compete with the performance of the decade-old RAD750 illustrates the substantial performance gap between hard and soft processor architectures. Although soft processors are not capable of competing with rad-hard processors in performance, the flexi- bility they provide nevertheless makes them a desirable option for space systems where speed is not the key issue. Fault injection experiments are also completed on three of the soft processors to eval- uate their configuration memory sensitivity. Our results demonstrate that the MicroBlaze is less sensitive than the LEON3 and the Cortex-M0 DesignStart, but that the LEON3 has lower sensitivity per FPGA slice than the other processors. A combined metric for soft pro- cessor performance and configuration sensitivity is then developed to aid future researchers in evaluating the trade-offs between these two distinct processor attributes. Keywords: soft processor, radiation-hardened processor, benchmarking, fault injection ACKNOWLEDGMENTS This thesis and the research it presents would not have been possible without the help of many to whom I offer sincere thanks. I would like to thank my advisor, Dr. Mike Wirthlin, for guiding me toward this research topic and helping me see this work through to completion. His insight and suggestions have been invaluable. As well, I am grateful for my other committee members, Dr. Brent Nelson and Dr. Brad Hutchings, for their support for me in pursuing this research. A number of students in our lab have also been instrumental in helping me carry out my research. I would like to thank Jae Lee for his diligent work in helping me prepare and run benchmarking tests and assisting in many other ways. Nathan Harward and Luke Hsiao have also been an incredible resource for me in completing fault injection experiments. Not only has their work greatly improved and simplified the fault injection system, but their assistance in debugging and helping to run the experiments has been a major support. Others have also made major contributions to this work. I owe a special thanks to John Fenly for providing me with his iMac G3, allowing me to perform the PowerPC 750 benchmarking experiments included in this thesis. I would also like to thank Tim Gallagher and the others I have worked with at Lockheed Martin for helping to fund this research and providing suggestions on where to focus our research efforts. Finally, I would like to recognize my family, particularly my parents, for their unwa- vering support for me in pursuing a master's degree and my other academic goals. Their love and encouragement have been constants throughout my life, and I consider my close relationship with them one of my choicest blessings. This work was supported by the I/UCRC Program of the National Science Foundation under Grant No. 1265957. I also acknowledge the Xilinx Radiation Test Consortium (XRTC) and members for support and use of XRTC test hardware. TABLE OF CONTENTS LIST OF TABLES. viii LIST OF FIGURES . xii 1 Introduction. 1 1.1 Contributions . 3 1.2 Related Work . 5 1.3 Outline . 9 2 Radiation Effects and Radiation-Hardened Electronics . 10 2.1 Radiation Effects on Semiconductor Devices . 10 2.2 Radiation-Hardened Processors . 11 2.3 Radiation-Hardened FPGAs . 13 3 Processor Architectures . 15 3.1 Soft Processor Selection . 15 3.2 Introduction to the Processors . 16 3.3 FPGA Boards . 23 3.4 Soft Processor System-on-Chip Designs . 26 3.4.1 Base System-on-Chip Design . 26 3.4.2 Final Designs . 29 3.5 Accounting for Processor Maximum Frequencies . 31 3.6 Estimating Soft Processor Performance on the V5QV . 34 4 Benchmark Programs. 39 4.1 Criteria for Benchmark Selection . 39 iv 4.2 Introduction to the Benchmark Programs . 41 4.2.1 Dhrystone . 41 4.2.2 Whetstone . 42 4.2.3 CoreMark . 43 4.2.4 MiBench Benchmark Suite . 43 4.3 Porting the Benchmarks to the Processors . 45 4.3.1 Benchmark Timing for the Soft Processors . 45 4.3.2 Benchmark Timing for the PowerPC 750 . 47 4.3.3 Other Code Changes . 48 4.4 Benchmark Verification . 50 4.5 Running the Benchmarks . 51 5 Benchmarking Results . 53 5.1 Soft Processor Performance Comparison . 53 5.1.1 Benchmark Scores . 56 5.1.2 Performance per Slice . 71 5.2 Performance Comparison with the RAD750 . 78 6 Fault Injection Experiments . 83 6.1 Introduction to Fault Injection . 84 6.2 Hardware Designs . 85 6.3 Benchmark Programs . 90 6.4 Fault Injection Results . 91 6.4.1 Number of Sensitive Bits . 92 6.4.2 Normalized Sensitivity per Slice . 94 6.4.3 Combining Performance and Radiation Sensitivity . 95 v 7 Conclusion . 101 REFERENCES. 104 Appendix A Soft Processor Configurable Options . 111 A.1 MicroBlaze Options . 112 A.2 LEON3 Options . 115 A.3 Cortex-M0 DesignStart Options . 125 A.4 OpenRISC Options . 127 Appendix B Architectural Comparison of the Processors . 133 B.1 Instruction Pipeline . 133 B.2 Integer Unit . 133 B.3 Floating-Point Unit . 134 B.4 Branch Predictor . 135 B.5 Caches . 136 B.6 System Bus . 136 Appendix C Benchmark Execution Timing . 138 Appendix D Software Tools and Settings . 144 D.1 Software Development Tools . 144 D.2 Compiler Settings . 145 D.2.1 MicroBlaze . 146 D.2.2 LEON3 . 149 D.2.3 Cortex-M0 DesignStart . 151 D.2.4 OpenRISC . 156 vi D.2.5 PowerPC 750 . 158 Appendix E Verifying the Benchmarks . 161 Appendix F Soft Processor Raw Benchmark Scores . 163 Appendix G Benchmark Code Changes . 171 Appendix H Soft Processor Setup . 175 H.1 MicroBlaze Setup . 175 H.2 LEON3 Setup . 176 H.3 Cortex-M0 DesignStart Setup . 176 H.4 OpenRISC Setup . 177 Appendix I Details of the Base System-on-Chip Designs . 178 Appendix J Implementing Soft Processors.