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Find the BAE Systems RAD750 at our website: Click HERE RAD750 Board
Hardware Specification
Document Number 234A524 Release Date
August 1, 2000
Copyright by BAE SYSTEMS
All Rights Reserved Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Notices
Before using this information and the product it supports, be sure to read the general information on the back cover of this book.
Trademarks
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM IBM Logo PowerPC PowerPC 750
The following are trademarks of BAE SYSTEMS in the United States, or other countries, or both: RAD750
The following are registered trademarks of PCI Industrial Computer Manufacturing Group in the United States, or other countries, or both: PICMG CompactPCI
Other company, product, and service names may be trademarks or service marks of others.
Preliminary Edition (Version 4.0, 8/1/2000) This unpublished document is the preliminary edition of RAD750 3U CompactPCI board Hardware Specification. Make sure you are using the correct edition for the level of the product.
This document contains information on a new product under development by BAE SYSTEMS. BAE SYSTEMS reserves the right to change or discontinue this product without notice.
© BAE SYSTEMS 2000. All rights reserved.
i Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Preface
This is the preliminary version of the document and includes all sections planned for the final version. Items marked TBA or TBD are not yet known as of this publication. Many of these will require the actual hardware prior to their resolution. Items marked (TBR) represent estimates that will also require the real hardware to verify and adjust. All such items may change in future versions of this document.
ii Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Revision History
REVISION REVISION HISTORY DATE 1.0 Draft for Internal Review 08/13/99 2.0 Preliminary Version Delivery Date 08/30/99 2.1 Minor rewording of capabilities, updates to registers, general clean-up 03/20/00 4.0 Release to web 08/01/00
iii Document Number: 234A524 RAD750 CompactPCI Hardware Specification
TABLE OF CONTENTS SECTION 1 INTRODUCTION...... 1
1.1 SCOPE ...... 1
1.2 APPLICABLE AND RELATED DOCUMENTS ...... 1
1.3 CONVENTIONS / NOMENCLATURE...... 4
1.4 TERMINOLOGY AND ACRONYMS ...... 4
SECTION 2 OVERVIEW...... 10
2.1 RAD750 3U COMPACTPCI BOARD MODULE FUNCTIONS ...... 10
2.2 EMBEDDED SOFTWARE ...... 14
2.3 POWER MANAGEMENT ...... 14
2.4 PERFORMANCE ...... 15
2.5 GENERAL PARAMETERS ...... 15
SECTION 3 EXTERNAL ELECTRICAL INTERFACE ...... 16
3.1 COMPACTPCI DEFINED SIGNALS ...... 16
3.2 NON-PCI INTERFACES ...... 27
3.3 POWER INTERFACES ...... 40
SECTION 4 ELECTRICAL AND THERMAL CHARACTERISTICS ...... 42
4.1 DC ELECTRICAL CONDITIONS ...... 42
4.2 AC ELECTRICAL CHARACTERISTICS ...... 44
SECTION 5 MECHANICAL INTERFACE ...... 52
5.1 RAD750 3U COMPACTPCI BOARD MODULE ASSEMBLY...... 52
5.2 GROUNDING REQUIREMENTS...... 54
5.3 RAD750 3U COMPACTPCI BOARD ELECTRICAL CONNECTORS ...... 55
5.4 NAME PLATE AND PRODUCT MARKINGS ...... 62
5.5 LIFETIME...... 62
SECTION 6 ENVIRONMENTAL CONDITIONS...... 63
6.1 TEMPERATURE...... 63
6.2 LAUNCH ATMOSPHERIC ENVIRONMENT...... 63
6.3 GROUND HANDLING ...... 63
6.4 LAUNCH DYNAMIC ENVIRONMENTS ...... 64 6.5 THERMAL...... 66
6.6 ELECTROMAGNETIC COMPATIBILITY ...... 67
6.7 RADIATION...... 71
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SECTION 7 FUNCTIONAL INTERFACE ...... 73
7.1 RAD750 PROGRAMMING INTERFACE ...... 73
7.2 EXTERNAL PCI BUS INTERFACE...... 77
7.3 EMBEDDED MICRO-CONTROLLER PROGRAMMING INTERFACES ...... 79
7.4 EXTERNAL JTAG INTERFACES...... 80
7.5 MODULE INITIALIZATION...... 80
SECTION 8 RAD750 3U COMPACTPCI BOARD REGISTER DEFINITION...... 81
8.1 RAD750 REGISTER MAP ...... 81
8.2 POWER PCI ASIC REGISTER MAP ...... 82
SECTION 9 ORDERING INFORMATION ...... 93
SECTION 10 COMMENTS...... 94
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LIST OF FIGURES FIGURE 1. NOTIONAL C&DH ARCHITECTURE USING A RAD750 BOARD ...... 10
FIGURE 2. RAD750 3U COMPACTPCI BOARD FUNCTIONAL BLOCK DIAGRAM ...... 11
FIGURE 3. RAD750 3U COMPACTPCI BOARD CLOCKING...... 14
FIGURE 4. RAD750 3U COMPACTPCI BOARD INTERFACE DIAGRAM ...... 16
FIGURE 5. JTAG BACKPANEL INTERFACE I/O ...... 32
FIGURE 6. JTAG RAD750 INTERFACE I/O ...... 34
FIGURE 7. JTAG SLAVE INTERFACE I/O ...... 35
FIGURE 8. PERIPHERAL DEVICE INTERFACE I/O ...... 36
FIGURE 9. PCI CLOCKED LOGIC TIMING DIAGRAMS ...... 46
FIGURE 10. SYS CLOCKED LOGIC TIMING DIAGRAMS ...... 47
FIGURE 11. RTC CLOCKED LOGIC TIMING DIAGRAMS ...... 48
FIGURE 12. JTAG CLOCKED LOGIC TIMING DIAGRAMS ...... 51
FIGURE 13. RAD750 3U COMPACTPCI BOARD MODULE VIEWS ...... 53
FIGURE 14. RAD750 3U COMPACTPCI BOARD MODULE VIEWS ...... 54
FIGURE 15. J1 CONNECTOR SIDE VIEW...... 56
FIGURE 16. J1 CONNECTOR BOTTOM VIEW ...... 56
FIGURE 17. J2 CONNECTOR SIDE VIEW...... 59
FIGURE 18. J2 CONNECTOR BOTTOM VIEW ...... 59
FIGURE 19. NANONICS DUALOBE CONNECTOR WITH 25 CONTACTS AND B=.431, C=.500 AND L=.300...... 61
FIGURE 20. 25 PIN NANONICS DUALOBE CONNECTOR PAD LAYOUT ...... 61
FIGURE 21. RAD750 3U COMPACTPCI BOARD PYROSHOCK DESIGN AND TEST REQUIREMENTS ...... 66
FIGURE 22. POWER BUS RIPPLE CONDUCTED EMISSIONS...... 68
FIGURE 23. POWER LINE TRANSIENTS CONDUCTED EMISSIONS ...... 68
FIGURE 24. E-FIELD RADIATED EMISSIONS...... 69
FIGURE 25. LOW FREQUENCY H-FIELD RADIATED EMISSIONS...... 69
FIGURE 26. LOW FREQUENCY E-FIELD RADIATED EMISSIONS ...... 70
FIGURE 27. E-FIELD RADIATED SUSCEPTIBILITY ...... 71
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LIST OF TABLES TABLE 1. RAD750 3U COMPACTPCI BOARD PCI INTERFACE SIGNALS ...... 17
TABLE 2. RAD750 3U COMPACTPCI BOARD NON-PCI SIGNALS ...... 27
TABLE 3. PID DEFINITION TABLE...... 38
TABLE 4. ABSOLUTE MAXIMUM RATINGS...... 42
TABLE 5. RECOMMENDED OPERATING CONDITIONS ...... 42
TABLE 6. CARD THERMAL CHARACTERISTICS...... 43 ± ≤ O TABLE 7. DC ELECTRICAL CHARACTERISTICS WITH VCC = 3.3 5% VDC, GND = 0 VDC, -55 TJ < 125 C... 43 ± TABLE 8. RAD750 3U COMPACTPCI BOARD MAXIMUM POWER CONSUMPTION WITH VCC = 3.3 5% VDC, GND ≤ O = 0 VDC, -55 TJ < 125 C ...... 44
TABLE 9. RAD750 3U COMPACTPCI BOARD TYPICAL POWER CONSUMPTION WITH VCC = 3.3 VDC, GND = 0 O VDC, TMR = 25 C...... 44
O TABLE 10. PCI INPUT CLOCK AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C ...... 45
O TABLE 11. PCI OUTPUT CLOCK AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C ...... 45
O TABLE 12. PCI INPUT AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C ...... 45
O TABLE 13. PCI OUTPUT AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C...... 46
O TABLE 14. SYS CLOCKED INPUTS AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C..... 47
O TABLE 15. SYS CLOCKED OUTPUTS AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C.47
O TABLE 16. RTC CLOCKED INPUTS AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C..... 48
O TABLE 17. RTC CLOCKED OUTPUTS AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C.48
O TABLE 18. RAD750 JTAG AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C ...... 49
O TABLE 19. POWER PCI JTAG AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C...... 50
O TABLE 20. BACKPANEL JTAG SLAVE AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C. 50
O TABLE 21. BACKPANEL JTAG MASTER AC TIMING SPECIFICATIONS WITH VCC=3.3±5% V DC, 0 ≤ TJ < 125 C51
TABLE 22. COMPACTPCI J1 CONNECTOR SIGNALS ...... 57
TABLE 23. COMPACTPCI J2 CONNECTOR PINOUTS...... 60
TABLE 24. FRONT PANEL CONNECTOR J7 PIN ASSIGNMENTS...... 61
TABLE 25. RANGE OF EXPLOSIVE ATMOSPHERE PHYSICAL CHARACTERISTICS ...... 63
TABLE 26. RAD750 3U COMPACTPCI BOARD RANDOM VIBRATION REQUIREMENTS...... 64
TABLE 27. RAD750 3U COMPACTPCI BOARD RANDOM VIBRATION FORCE SPECTRUM ...... 64
TABLE 28. RAD750 3U COMPACTPCI BOARD ACOUSTIC NOISE DESIGN REQUIREMENTS...... 65
TABLE 29. REQUIREMENT SOURCES OF RADIATED SUSCEPTIBILITY ...... 71
TABLE 30. RAD750 3U COMPACTPCI BOARD INDUCED SEU RATE REQUIREMENTS ...... 72
TABLE 31. RAD750 3U COMPACTPCI BOARD MEMORY MAP SEEN FROM THE RAD750 CPU, JTAG SLAVE OR EMBEDDED MICRO-CONTROLLER...... 73
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TABLE 32. RAD750 EXCEPTIONS ...... 75
TABLE 33. RAD750 3U COMPACTPCI BOARD MEMORY MAP SEEN FROM THE EXTERNAL PCI BUS...... 77
TABLE 34. PCI BUS INTERRUPTS ...... 79
TABLE 35. EMC INTERRUPTS IN PRIORITY ORDER...... 79
TABLE 36. RAD750 ARCHITECTURE DEFINED REGISTERS ...... 81
TABLE 37. RAD750 SPECIAL PURPOSE REGISTERS ...... 81
TABLE 38. POWER PCI ASIC PCI CONFIGURATION REGISTERS ...... 83
TABLE 39. POWER PCI ASIC MEMORY CONTROLLER REGISTER MAP...... 84
TABLE 40. POWER PCI ASIC 60X INTERFACE REGISTER MAP ...... 86
TABLE 41. POWER PCI ASIC UART REGISTER MAP ...... 87
TABLE 42. POWER PCI ASIC JTAG MASTER REGISTER MAP...... 88
TABLE 43. POWER PCI ASIC MICRO-CONTROLLER REGISTER MAP...... 88
TABLE 44. POWER PCI ASIC INTERRUPTS, TIMERS AND DISCRETES REGISTER MAP...... 89
TABLE 45. POWER PCI ASIC CLOCKS AND TEST REGISTER MAP ...... 91
TABLE 46. POWER PCI ASIC JTAG SLAVE REGISTER MAP ...... 92
TABLE 47. RAD750 3U COMPACTPCI BOARD PART NUMBER LISTING ...... 93
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Section 1 Introduction
1.1 Scope This hardware specification defines the interface and form, fit and functional requirements of the RAD750 3U CompactPCI board.
1.2 Applicable and Related Documents The following documents are referenced in the specification or were used in the creation of this specification and should be useful to someone reading this document.
1.2.1 Specifications PCI Local Bus Specification Peripheral Component Interface (PCI) Local Bus Specification, Rev 2.2. December 18, 1998. PCI Special Interest Group, 2575 NE Kathryn St. #17, Hillsboro, OR, 97124, Telephone: (800) 433-5177 (inside the U.S.), or (503) 693-6232 (outside the U.S.), FAX: (503) 693- 8344, http://www.pcisig.com/
CompactPCI Specification CompactPCI Specification, PICMG 2.0 R2.1, September 2, 1997, PCI Industrial Manufacturers Group (PICMG), 401 Edgewater Place, Suite 500, Wakefield, MA 01880, Telephone: 781-246-9318, Fax: 781-224- 1239, http://www.picmg.com/
On Chip Bus (OCB) Spec On-Chip Bus Specification, July 8, 1999, Rev. 1.1
234A525 RAD750 3U CompactPCI Board Software Specification, August 1999.
234A526 RAD750 3U CompactPCI Board Support Equipment Specification, August 1999.
1.2.2 Standards IEEE Standard 1149.1a- Standard Test Access Port and Boundary Scan Architecture (JTAG), 1993 October 21, 1993, Institute of Electrical and Electronics Engineers, Inc., Publication and Sales Department, 345 East 47th Street, New York, New York 10017-21633, Telephone: 1-800-678-4333, http://standards.ieee.org/
IEEE Standard 1101.1-1991 Mechanical Core specifications for Microcomputers Using IEC 603-2 Connectors, Institute of Electrical and Electronics Engineers, Inc., Publication and Sales Department, 345 East 47th Street, New York, New York 10017-21633, Telephone: 1-800-678-4333, http://standards.ieee.org/
JEDEC Standard No. 21-C SDRAM Architectural and Operational Features (section 3.11.5), Release 7, http://www.jedec.org/menu.htm
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ANSI/EIA/TIA-232-E Interface Between Data Terminal Equipment and Data Circuit- Terminating Equipment Employing Serial Binary Data Interchange, July 1991, Electronic Industries Association, Engineering Department, 2001 Eye Street, NW, Washington, DC 20006, http://www.eia.org/, or http://www.tiaonline.org/standards/search_n_order.html
ANSI/TIA/EIA-422-B-94 Electrical Characteristics of Balanced Voltage Digital Interface Circuits, May 1994, Electronic Industries Association, Engineering Department, 2001 Eye Street, NW, Washington, DC 20006, http://www.eia.org/, or http://www.tiaonline.org/standards/search_n_order.html
1.2.3 BAE SYSTEMS Documents BAE SYSTEMS has reference documentation available for the RAD750 family of products. Visit the RAD750 web site http://www.rad750.com/ or contact your BAE SYSTEMS sales representative to obtain copies. • RAD750 Fact Sheet • Power PCI Fact Sheet • Power PCI Specification • RAD750 Datasheet • RAD750 Software Users Guide • RAD750 Frequently Asked Questions (FAQ) • RAD750 Board Hardware User Manual • RAD750 Board Software User Manual
1.2.4 External Documents In addition to the documentation from BAE SYSTEMS, PowerPC documentation (i.e., Datasheets, User Manuals, Application Notes, etc.) is also available from • IBM at http://www.chips.ibm.com/products/powerpc/index.html, and • Motorola at http://www.mot.com/SPS/PowerPC/. This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture.
1.2.4.1 General PowerPC Information The following documentation provides useful information about the PowerPC architecture and computer architecture in general: Useful documents on probing the PowerPC include: 1. Passively Probing a Motorola/IBM PowerPC 740/750 Target System with HP E5346A High Density Termination Adapters, Product Note, Hewlett Packard, 1998. 2. MICTOR Connectors for Surface Mount Technology (SMT) Printed Circuit (PC) Board Applications, Application Specification 114-11004, AMP Incorporated, Harrisburg, PA, 17105, February 5, 1997. 3. Emulation and Analysis Solutions for Motorola/IBM PowerPC 740/750 Microprocessors, Product Overview, 1998. The following books are available from the Morgan-Kaufmann Publishers, 340 Pine Street, Sixth Floor, San Francisco, CA 94104; Tel. (800) 745-7323 (USA), (415) 392-2665 (International); Internet address: [email protected].
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1. The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, by International Business Machines, Inc. Updates to the architecture specification are accessible via the worldwide web at http://www.austin.ibm.com/tech/ppc-chg.html. 2. PowerPC Programming for Intel Programmers, by Kip McClanahan; IDG Books Worldwide, Inc., 919 East Hillsdale Boulevard, Suite 400, Foster City, CA, 94404; Tel. (800) 434-3422 (USA), (415) 655-3022 (International). 3. PowerPC System Architecture, by Tom Shanley; Mindshare, Inc., 2202 Buttercup Drive, Richardson, TX 75082; Tel. (214) 231-2216 (USA), 021-706 6000 (United Kingdom), (800) 420- 2677 (International).
1.2.4.2 IBM PowerPC Documentation The PowerPC documentation is available from the links indicated above; the document order numbers are included in parentheses for ease in ordering: • Embedded Market Solutions - Publications: SC09-3032 - This is a CD-ROM containing documentation on all the PowerPC family of products from IBM. The CD-ROM is updated quarterly. • Programming environment manuals - This book provides information about resources defined by the PowerPC architecture that are common to PowerPC processors. 1. PowerPC Microprocessor Family: The Programming Environments G522-0290-00 • Implementation Variances Relative to Rev. 1 of The Programming Environments Manual is available via the worldwide web at http://www.chips.ibm.com/. • Hardware specifications—Hardware specifications provide specific data regarding bus timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations for each PowerPC implementation. This include the following: 1. PowerPC 740 and PowerPC 750 Embedded RISC Microprocessor: Hardware Specifications is available via the worldwide web at http://www.chips.ibm.com/. 2. PowerPC 750 SCM RISC Microprocessor: Hardware Specification G522-0324-00 • Technical Summaries—Each PowerPC implementation has a technical summary that provides an overview of its features. This document is roughly the equivalent to the overview (Chapter 1) of an implementation’s user’s manual. 1. PowerPC 750 RISC Microprocessor Technical Summary is available via the worldwide web at http://www.chips.ibm.com/. 2. PowerPC Microprocessor Family: 60x Bus Interface for 32-Bit Microprocessors, G522-0291-00, provides a detailed functional description of the 60x bus interface, as implemented on the 601, 603, 604 and 740/750 family of PowerPC microprocessors. This document is intended to help system and chip set developers by providing a centralized reference source to identify the bus interface presented by the 60x family of PowerPC microprocessors. • PowerPC Microprocessor Family: The Programmer’s Reference Guide, MPRPPCPRG-01, is a concise reference that includes the register summary, memory control model, exception vectors, and the PowerPC instruction set. • PowerPC Microprocessor Family: The Programmer’s Pocket Reference Guide, SA14-2093-00 This foldout card provides an overview of the PowerPC registers, instructions, and exceptions for 32-bit implementations. • Application notes—These short documents contain useful information about specific design issues useful to programmers and engineers working with PowerPC processors.
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Additional literature on PowerPC implementations is being released as new processors become available. For a current list of PowerPC documentation, refer to the web sites listed at the beginning of this section.
1.3 Conventions / Nomenclature The following conventions apply except were specifically noted. • In PowerPC terminology, multiple bit fields are numbered from 0 to n, where 0 is the MSB and n is the LSB. • PCI terminology follows the convention that bit 0 is the LSB and n is the MSB. • When counting N elements, the first element is designated element 0 and the last element is designated element N-1. • Information of particular importance is in bold typeface and is further highlighted by the NOTE reference. • Signal names are fully capitalized and use a bold font: SIGNAL1 • Active low PCI I/O signals are suffixed with the ‘#’ symbol to be consistent with the PCI specification. All other active low signals are suffixed with ‘_L’. Note that this does not supersede the coding requirement that all active low signal names are coded using the ‘_L’ suffix: FRAME#, SIGNAL2_L • Internal register names have leading caps and use a bold font: Device ID, Status • Register field or bit names have leading caps and use a bold and italicized font: Bus Master • All numbers are expressed in decimal, except addresses and memory or register data, which are expressed in hexadecimal: 0x0F; or binary: 0b0110 or ‘1’, following the 'C' programming language convention. • An ‘n’ denotes bit definitions. • An ‘xnnnn’ denotes word definitions. • The multipliers 'k', 'M' and 'G' have their conventional scientific and engineering meanings of *103, *106 and *109, respectively. The only exception to this is in the description of the size of memory areas, when 'K', 'M' and 'G' mean *210, *220 and *230, respectively. • When describing transfer rates, ‘k’, ‘M’ and ‘G’ mean *103, *106 and *109, not *210, *220 and *230, respectively. • Names of external core signals which have a single destination are of the form
Term Description
Active Bank A physical bank (or sub-bank) of SDRAM which has already received a “Bank Activate” command, thereby selecting a row. Once a bank is active, the bank must be pre-charged before another “Bank Activate” command can be issued to select a different row.
Active Scrubbing A memory scrubbing process in which the memory controller inserts extra memory read operations during idle cycles to detect and correct data errors.
ASIC Application Specific Integrated Circuit
Bank A memory part (or, more typically, a group of memory parts) which provides a
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Term Description complete data vector. A complete data vector typically contains 64-bits of data and 8, 16 or 24 ECC bits.
Bank Miss A memory operation that does not address an open bank.
BAR Base Address register BDODIL A bi-directional, open drain, inverted logic input/output pin, with an external pull- up resistor, allowing multiple devices to concurrently drive the signal in a “wired- OR” configuration. Drivers assert the bus (i.e. sink current) to indicate a logic “1” state or release the bus (i.e. tri-state) to indicate a logic “0” state.
BDSTS A bi-directional, sustained tri-state. This is an active low tri-state signal owned and driven by one, and only one, agent at a time. The agent that drives an STS pin low must drive it high for at least one clock cycle before letting it float. A new agent cannot start driving any sooner than one clock cycle after the previous owner tri-states it. An external pull-up resistor is required to sustain the inactive state until another agent drives it.
BDTS A bi-directional, tri-state input/output pin (only one direction at a time).
Big Endian The ordering of data such that the most significant byte is stored at the lowest order address.
BIST Built-in Self Test
Byte An 8-bit value.
Byte-Enabled Write A write in which some bytes of a data beat are not stored to memory.
Cache Line A cache line consists of 4 double words (32 bytes).
Character In this document a character refers to a byte of data that is stored into a FIFO.
Column In the context of internal SDRAM layout, the column is used in conjunction with the SDRAM row to select a single bit (per data output bit) from the SDRAM memory matrix.
CS Cold Spareable - A term indicating that a device input is designed so as not to provide a sneak path for powering that device when the device's power inputs have no voltage on them.
Data Beat A single unit of data, usually a data beat is a double word.
Double word A 64-bit value.
Doze Mode A power management mode that consumes more power than Sleep Mode, but less power than Normal Mode. . See also Nap, Normal and Sleep Modes.
DRAM Dynamic Random Access Memory. On the RAD750 3U CompactPCI board, this is implemented using SDRAM
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Term Description
DWORD 32-bit block of data (4 bytes)
EDAC Error Detection and Correction
EEPROM Electrically Erasable Programmable Read Only Memory - a non volatile memory device used on the RAD750 3U CompactPCI board to store startup and recovery code. See SUROM.
EM Engineering Model - form fit and function compatible with flight units and able to withstand qualification environments
EMC Embedded Micro-Controller - error handling core within the Power PCI chip
ESD Electrostatic Discharge
FIFO First In First Out. Bank of registers that store data, such that the first set of data stored is the first data that is read out.
FM Flight Model - version of the RAD750 3U CompactPCI board that will be used in space
Half word A 16-bit value.
HDL Hardware Description Language – A language for describing digital electronic systems.
I/O Input / Output
ISA Instruction Set Architecture - usually refers to instructions used by a CPU
JTAG Joint Test Action Group Interface. Refers to the test interface standardized in IEEE 1149.1a
JTAG Master A TAP Controller and associated logic that controls JTAG Slave(s) located outside the function.
Little Endian The ordering of data such that the most significant byte is stored at the highest order address. The endian ordering of data never extends beyond an 8-byte group of storage. lsb least-significant bit
LSB Least-Significant Byte
Marking State Logic ‘1’.
Mbps Millions of bits per second - a measure of communications throughput
MBps Millions of bytes per second - a measure of communications throughput
Memory Scrubbing The process of writing memory to correct a data error in the memory.
Memory Sparing The process of using extra (or spare) columns of memory to replace failed
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Term Description columns.
MIPS Millions of Instructions per second - a measure of CPU throughput msb Most-significant bit
MSB Most-Significant Byte
Munging A transformation of the address to convert between endian modes.
Nap Mode A power management mode of the RAD750 or Power PCI, which consumes more power than Sleep Mode, but less power than Normal Mode. See also Normal, Doze and Sleep Modes.
Normal Mode The typical (full-power) operational mode of the RAD750 or Power PCI. See also Doze, Nap and Sleep Modes.
NVM Non volatile memory - a memory that does not lose its state when power is withdrawn
OCB On Chip Bus - internal interconnect between functions within the Power PCI ASIC as defined in On-Chip Bus Specification.
OD An Open Drain output with external pull-up resistor allowing multiple devices to share as a wire-OR.
One-hot State Each state of the state machine has its own register bit. Machine
Open Bank Same as Active Bank.
OTS A tri-state output
Parity Can be odd or even. Even Parity indicates that the number of ones in the data and parity bit is even, and likewise odd parity indicates that the number of ones is odd.
Passive Scrubbing A memory scrubbing process in which the Power PCI memory controller only looks for and corrects data errors at memory locations that the Power PCI has read.
PCB Printed Circuit Board
PCI Peripheral Component Interconnect. Refers to the PCI Local Bus as defined in the PCI Local Bus Specification. Version 1.0 of the PCI specification was developed by Intel Corporation and released on 6/22/92. The PCI Special Interest Group (SIG) currently manages the specification.
PID Programmable Interrupt and Discrete - general purpose I/O
PLL Phase Locked Loop - used to run the RAD750 at a speed higher than the input frequency
POR Power on Reset
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Term Description
PowerPC A high performance CPU family developed jointly by IBM, Motorola and Apple
Pre-charge An SDRAM command that closes an open bank.
RAD750 A radiation hardened version of the PowerPC 750
Record A VHDL construct that can contain many signals of different types.
Row In the context of internal SDRAM layout, a single bit-line selected by the Bank Activate command. When used in conjunction with an SDRAM column, a single bit (per data output bit) is selected from an SDRAM memory matrix.
RTC Real Time Clock - used by the UART and Timers on the RAD750 3U CompactPCI board
RTL Register Transfer Level. Refers to a HDL coding style that is characterized by the explicit definition of all register to register transfers within the device being described.
SDRAM Synchronous DRAM - This is implemented on the RAD750 3U CompactPCI board.
SEU Single Event Upset - an error in the hardware caused by radiation
Sleep Mode The lowest power operational mode of the RAD750 or Power PCI. See also Normal, Doze and Nap Modes.
SP or SPU Soft Pull-up - resistor embedded in logic chip providing default value on input
Spacing State Logic ‘0’.
SPR Special Purpose Register
SRS Software Requirements Spec
Sub-bank A single internal bank in an SDRAM part with multiple internal banks.
SUROM Start Up Read Only Memory - this non-volatile memory is implemented out of EEPROM on the RAD750 3U CompactPCI board
TAP Test Access Port - main state machine in the JTAG slave logic found in an 1149.1 compliant device
TID Total Ionizing Doze - usually measured in rads (Si)
UART Universal Asynchronous Receiver / Transmitter - main software interface on the RAD750 3U CompactPCI board
VHDL VHSIC Hardware Description Language – standardized in IEEE standard 1076
VHSIC Very High Speed Integrated Circuit
Word A 32-bit value.
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Term Description
106 Mode Behavior that matches the operation of a Motorola MPC106 PowerPC bridge device
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Section 2 Overview The RAD750 3U CompactPCI board is designed to provide the main computational capability for a spacecraft. Figure 1 shows the RAD750 3U CompactPCI Board combined with other I/O and memory boards to form the main processing elements of an spacecraft avionics command and data handling (C&DH) system.
SpacecraftSpacecraft BulkBulk Memory Memory RAD750RAD750 PayloadPayload I/O I/O I/OI/O and and TT&C TT&C
PCI and JTAG Buses
Figure 1. Notional C&DH Architecture using a RAD750 board
2.1 RAD750 3U CompactPCI board Module Functions As shown in Figure 2, the RAD750 3U CompactPCI board consists of the following major functions: • RAD750 PowerPC processor, • Power PCI Bridge function and its oscillators and transceivers, • SUROM, • And Local Memory. All requirements in this specification apply to the Flight Model (FM) of the RAD750 3U CompactPCI board unless specifically applied only to the less-stringent Engineering Model version of the RAD750 3U CompactPCI board that will also be built. The RAD750 3U CompactPCI board Engineering Model (EM) is identical to the FM, except that it uses a commercial PowerPC 750 instead of a RAD750 CPU. The remaining parts will be identical between the two versions, except that EM parts may be less fully screened. The following section is divided into subsections corresponding to the top-level capabilities of each of these major functions.
10 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
2.5V 2.5V 3.3V RAD750 CPU Regulator
RAD750 6xx Clocks, JTAG Port Address 6xx Interrupts & Control Data and Controls SUROM Slave JTAG Port Memory Control UART Port Memory Address Local Memory Memory Data
PCI Bus Power PCI Bridge Master Clock JTAG Port OSC Reset,Interrupts & Discretes Configuration
Figure 2. RAD750 3U CompactPCI board Functional Block Diagram
2.1.1 RAD750 PowerPC Processor The RAD750 is functionally and pin-for-pin compatible with a commercial PowerPC 750. The RAD750 PowerPC processor provides the RAD750 3U CompactPCI board with the following functions: • PowerPC 750 Instruction Set Architecture (ISA), • Floating Point Unit which implements the IEEE-754 floating point standard • 32 Kbytes of instruction cache, • 32 Kbytes of data cache, • Software-controlled power savings modes, and • An L2 cache interface supporting at least 1 Mbytes of cache addressability. This interface is internal to the RAD750 3U CompactPCI board. No L2 cache is implemented on the RAD750 3U CompactPCI board.
2.1.2 Power PCI Bridge Function The primary function of the Power PCI Bridge is to provide a bridge between the native RAD750 6xx bus and a Version 2.1 compatible PCI bus. The Power PCI Bridge provides the RAD750 3U CompactPCI board a: • Version 2.1 compatible PCI bus interface, • The Power PCI Bridge is generally fully compliant with the requirements set forth in the PCI Local Bus Specification, Rev 2.2, however, at this time, only full version 2.1 compliance is guaranteed. • PCI burst mode with contiguous data transfers, • PCI arbitration and resource control, • Memory data and address interface, • Memory error detection and correction (EDAC),
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• Auto memory scrub, • Cache snooping on system memory accesses, • 16550 compatible UART interface, • RAD750, PCI and JTAG clock control, • Three programmable timers which may be used to provide operating system tick and cycle start interrupts, • A watchdog timer, • Interrupts and discretes, • Embedded micro-controller that may control complex DMA operations, • Power saving modes to match the RAD750, • Dual JTAG master interfaces, and a • JTAG tap controller. The Power PCI provides enhanced features over the most used COTS PowerPC bridge chip (Motorola MPC106) and thus is not pin compatible with any COTS bridge chip. The Power PCI provides the ability to enable and disable the local and SUROM memory EDAC mechanisms on the RAD750 3U CompactPCI board. The local and SUROM memory EDAC mechanisms are enabled upon reset. Visibility is provided into the number of memory corrections and address of the correction. Single bit or nibble errors are counted. Multiple bit or nibble errors that are uncorrectable generate a maskable interrupt to the RAD750. The ability to program different access times for the SUROM and DRAM is provided. The RAD750 3U CompactPCI board provides the capability to restrict a block of adjustable size (8K byte granularity) from external PCI access. All interrupts not listed as non-maskable are maskable by software. A UART is provided by the Power PCI, which will be initialized to a known usable state for external communication.
2.1.3 SUROM The SUROM on the RAD750 3U CompactPCI board consists of 256 Kbytes of nonvolatile EEPROM memory and provides nonvolatile program store for the initial program load of the RAD750. The SUROM is organized as 128K x 24 with 16 bits of data and 8 bits of error correction code. The error correction code provides single bit error correction and double bit error detection. All SUROM memory can be directly addressed by the RAD750 and by any internal master function of the Power PCI. This includes the internal EMC, an external JTAG master connected through the backpanel or Power PCI JTAG port to the RAD750 3U CompactPCI board, or any PCI initiator device connected to the RAD750 3U CompactPCI board. The ability to enable and disable the SUROM EDAC mechanism is provided in the Power PCI ASIC. The SUROM EDAC mechanism will be enabled upon reset.
2.1.4 Local Memory 128 Mbytes of Synchronous DRAM is provided on the RAD750 3U CompactPCI board to provide processor program and data store. This local memory is directly addressable by the RAD750 and by any internal master function of the Power PCI. The local memory is organized as 16M x 80 with 64 bits of data and 16 bits of error correction code. The error correction coding can provide single nibble error correction and double nibble error detection so that cluster SEU events in a single part can be corrected. The Local Memory can be placed into a self-refresh mode by software to allow its memory contents to be retained during a reset of any duration, provided RAD750 3U CompactPCI board power input is not
12 Document Number: 234A524 RAD750 CompactPCI Hardware Specification interrupted. However, the SDRAM will not be scrubbed while it is in self-refresh mode and thus SEU errors may start accumulating in memory depending on the operational environment.
2.1.5 Clocking The RAD750 3U CompactPCI board uses a single 33 MHz Oscillator to derive the PCI Clocks, Processor Clocks, JTAG Master Clocks and Real Time Clocks as shown in Figure 3. For test purposes, an external clock input is also provided to override the on-board oscillator. In Figure 3, R represents a receiver, D represents driver, and SEL represents a selection block on a chip. DELAYs are for matching clock skews and will normally never be adjusted. All blocks are part of the Power PCI ASIC except those in blue. Specifically, the RAD750 Logic and RAD750 JTAG and their respective receivers are part of the RAD750. The 33 MHz Oscillator is a standalone component and the SDRAM Memory and its receiver is part of each SDRAM component on the RAD750 3U CompactPCI board. Heavy arrows are clock signals and light arrows are discrete or control signals. Black or blue arrows represent connections internal to the components. Red arrows represent connections on the RAD750 3U CompactPCI board that are not accessible. Green arrows represent signals that are brought to either functional or test pins and are accessible externally. The left side of this figure shows the input oscillator signals being divided and passed to the logic areas. The right side of the figure focuses mainly on the JTAG clocks including potential external sources. The RAD750 3U CompactPCI board is configurable to use the 33 MHz Oscillator to run the RAD750 at the following speeds: • 132 MHz using a 4x Tap (Full Speed Mode) • 99 MHz using a 3x Tap • 66 MHz using a 2x Tap • 33 MHz using no PLL (High Speed Mode) • 16.5 MHz using no PLL and a divide by 2 (Half Speed Mode) • 8.25 MHz using no PLL and a divide by 4, and (Quarter Speed Mode) • 4.125 MHz using no PLL and a divide by 8. (Eighth Speed Mode) The RAD750 3U CompactPCI board is configurable to use the 33 MHz Oscillator to run the PCI Bus at the following speeds: • 33 MHz • 16.5 MHz • 8.25 MHz • 4.125 MHz The RAD750 3U CompactPCI board is configurable to use the 33 MHz Oscillator to run the real time clock at the following speeds: • 8.25 MHz • 4.125 MHz • 2.0625 MHz • 1.03125 MHz
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SDRAM EXT_OSC_SEL DELAY D R R MEMORY
EXT_OSC PROBE R R 33 MHz SEL POWER PCI JTS_TCLK SEL R OSC R JTAG R
DIV BY DIV BY 1/2/4/8 D R D DELAY 2/4/8/…/256 JTB_TCLK
DELAY SYS_CLK JTB_ME D R POWER PCI RAD750 D R LOGIC JT7_ME R LOGIC PCI_CLK(1:6) D DIV BY 2/4/8/…/256 D PCI_CLK(7) DIV BY 1/2/4/8 D RAD750 JT7_TCLK PCI_CLK JTAG R D
R R Color Key: PCI_SYSEN# POWER PCI R SEL PCI LOGIC Black - Power PCI ASIC Blue - Other Board Comp Green - External Signal POWER PCI D R Red - Board Wiring DIV BY 4/8/16/32 UART & TIMERS RTC_CLK D
Figure 3. RAD750 3U CompactPCI board Clocking. The RAD750 3U CompactPCI board defaults after reset to the lowest speed mode on all clocks with the PLL Disabled in the CPU.
2.1.6 Power Regulation The RAD750 3U CompactPCI board draws all required power from an external 3.3V supply. The power source must be regulated to 3.3V ± 5% and a maximum ripple of 60 mV p-p with a power converter switching frequency of 1 MHz. The 2.5V power required by the internal CPU logic on the RAD750 3U CompactPCI board is generated on card from the 3.3V input. The RAD750 3U CompactPCI board does not contain fuses or circuit breakers.
2.2 Embedded Software The RAD750 3U CompactPCI board contains embedded software for initial board checkout and program load. This code, which is stored in SUROM, is run by the Power PCI Embedded Microcontroller (EMC) and the RAD750. Details on this code can be found in the RAD750 3U CompactPCI board Software Specification.
2.3 Power management Because power management is such a key attribute for space missions, the RAD750 3U CompactPCI board provides a number of power saving modes of operation. First, the RAD750 3U CompactPCI board supports the following Power PC standard power management modes: Full-on, Doze, Nap and Sleep.
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In addition, the Power PCI bridge chip is also capable of operating the RAD750 3U CompactPCI board with the CPU PLL bypassed, which allows further power savings by allowing the CPU to run at lower rates (33MHz, 16.5MHz, 8.25MHz, and 4.125MHz). The change between these four clock frequencies can be done glitch free, however and power mode switch that involves either enabling or disabling the PLL will require the Power PCI bridge to initiate a reset of the CPU chip.
2.4 Performance The RAD750PowerPC processor provides performance of 240 Dhrystone 2.1 MIPS or TBD SPECint95, TBD SPECfp95 when run at 132 MHz. The RAD750PowerPC processor shall provide performance of TBD Dhrystone 2.1 MIPS or TBD SPECint95, TBD SPECfp95 when run at 132 MHz with an external device continually performing DMA activity at 66 MBps. The RAD750 3U CompactPCI board external interrupt latencies while running from local memory at 132MHz will be 10us or less. The latencies for other power savings mode and CPU frequency settings are TBD. Latencies are measured from interrupt signal transition to first instruction execution of the interrupt handler.
2.5 General Parameters The RAD750 3U CompactPCI board meets the following general parameters. Board Size 160 x 100 mm Board Form Factor CompactPCI 3U x 160 Connectors J1: Amp CompactPCI IEC-1076-2-101 J2: Amp CompactPCI IEC-1076-4-101 J7: Nanonics N10138/250 Dualobe 2 Row 25 Pin Connector Power Supply 3.3V ± 5% V dc
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Section 3 External Electrical Interface The external electrical interfaces of the RAD750 3U CompactPCI board are shown in Figure 4.
PCI Bus Version 2.2 UART
Backpanel JTAG Functional RAD750 PowerPCI Debug / Test Discretes & JTAG Interfaces Interrupts Board Interfaces
Clocks & Reset RAD750 JTAG Configuration
Power 3.3 V Power Supply Interfaces
Figure 4. RAD750 3U CompactPCI Board Interface Diagram The RAD750 3U CompactPCI board contains functional, debug/test, and power interfaces. Individual signals from each interface shall be as shown in Table 1 and Table 2 in the sections that follow.
3.1 CompactPCI Defined Signals Table Heading Notes: • In the Signal Type column: • BDTS indicates a bi-directional, tri-state input/output pin (only one direction at a time). • BDODIL indicates a bi-directional, open drain, inverted logic input/output pin, with an external pullup resistor, allowing multiple devices to concurrently drive the signal in a “wired-OR” configuration. Drivers assert the bus (i.e. sink current) to indicate a logic “1” state or release the bus (i.e. tri-state) to indicate a logic “0” state. • OTS indicates a tri-state output. • OD indicates open drain output with external pull-up resistor allowing multiple devices to share as a wire-OR. • BDOD indicates a bi-directional, open drain input/output pin. • BDSTS indicates a bi-directional, sustained tri-state. This is an active low tri-state signal owned and driven by one, and only one, agent at a time. The agent that drives an STS pin low must drive it high for at least one clock cycle before letting it float. A new agent cannot start driving any sooner than one clock cycle after the previous owner tri-states it. An external pull-up resistor is required to sustain the inactive state until another agent drives it. • CS indicates cold-spareable. • SP indicates internal soft pull-up on an input.
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• The I/O Pin identifies which connector (first two characters) and which pin (last three characters) the signal is wired to. See section 5.3 for more details on the connectors. • The Voltage/Technology column indicates the type of I/O assumed for signals at the card boundary. Included here are external non-VLSI elements and terminations. • In the POR Value column, the value shown is the state of the signal after a POR is issued. If a second value is shown, this is for when the card is being used as a PCI Resource Controller. • In the BIST Value column, the value shown is the state of the signal during a BIST of the Power PCI chip. • In the PCI Reset column, the value shown is the state of the signal after a PCI Reset is issued. If a second value is shown, this is for when the card is being used as a PCI Resource Controller. • The RAD750 3U CompactPCI board must be able to operate as a system controller or a peripheral board without change of hardware. This does not seem to be accounted for in the CompactPCI spec, at least in the area of required resistors. The table shows what is required by the spec. Further analysis and communication with the spec owners are needed to determine if any of these may be omitted on a dual-purpose board such as the RAD750 3U CompactPCI board. Table 1. RAD750 3U CompactPCI board PCI Interface Signals
SIGNAL NAME Signal I/O Voltage/ POR PCI Reset Comment Type Pin Technology Value Value PCI Bus PCI_AD_0 BDTS J1D24 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_1 BDTS J1A24 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_2 BDTS J1E23 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_3 BDTS J1C23 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_4 BDTS J1B23 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_5 BDTS J1E22 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_6 BDTS J1D22 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_7 BDTS J1A22 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_8 BDTS J1C21 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub
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SIGNAL NAME Signal I/O Voltage/ POR PCI Reset Comment Type Pin Technology Value Value PCI_AD_9 BDTS J1B21 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_10 BDTS J1E20 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_11 BDTS J1D20 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_12 BDTS J1A20 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_13 BDTS J1E19 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_14 BDTS J1C19 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_15 BDTS J1B19 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_16 BDTS J1C11 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_17 BDTS J1B11 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_18 BDTS J1A11 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_19 BDTS J1E10 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_20 BDTS J1D10 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_21 BDTS J1A10 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_22 BDTS J1E09 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_23 BDTS J1C09 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub
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SIGNAL NAME Signal I/O Voltage/ POR PCI Reset Comment Type Pin Technology Value Value PCI_AD_24 BDTS J1E08 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_25 BDTS J1D08 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_26 BDTS J1A08 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_27 BDTS J1E07 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_28 BDTS J1C07 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_29 BDTS J1B07 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_30 BDTS J1A07 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_AD_31 BDTS J1E06 3.3V PCI 3-State 3-State / 0 PCI Address/Data Bus 5V PCI Toler. 10 Ohm Stub PCI_C/BE0# BDTS J1E21 3.3V PCI 3-State 3-State / 0 PCI Cmd/Byte Enable 5V PCI Toler. 10 Ohm Stub PCI_C/BE1# BDTS J1E18 3.3V PCI 3-State 3-State / 0 PCI Cmd/Byte Enable 5V PCI Toler. 10 Ohm Stub PCI_C/BE2# BDTS J1E11 3.3V PCI 3-State 3-State / 0 PCI Cmd/Byte Enable 5V PCI Toler. 10 Ohm Stub PCI_C/BE3# BDTS J1A09 3.3V PCI 3-State 3-State / 0 PCI Cmd/Byte Enable 5V PCI Toler. 10 Ohm Stub PCI_PAR BDTS J1D18 3.3V PCI 3-State 3-State / 0 Even Parity over AD and 5V PCI Toler. C/BE(0:3)# 10 Ohm Stub PCI_FRAME# BDSTS J1B15 3.3V PCI 3-State 3-State Master Start / Stop 5V PCI Toler. 10 Ohm Stub 8.2K Pull-up
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SIGNAL NAME Signal I/O Voltage/ POR PCI Reset Comment Type Pin Technology Value Value PCI_IRDY# BDSTS J1C15 3.3V PCI 3-State 3-State Initiator Ready 5V PCI Toler. 10 Ohm Stub 8.2K Pull-up PCI_TRDY# BDSTS J1E15 3.3V PCI 3-State 3-State Target Ready 5V PCI Toler. 10 Ohm Stub 8.2K Pull-up PCI_STOP# BDSTS J1D16 3.3V PCI 3-State 3-State Target Stop 5V PCI Toler. 10 Ohm Stub 8.2K Pull-up PCI_DEVSEL# BDSTS J1A16 3.3V PCI 3-State 3-State Device select 5V PCI Toler. 10 Ohm Stub 8.2K Pull-up PCI_IDSEL Input J1B09 3.3V PCI N/A N/A Chip select for device 5V PCI Toler. configuration space 10 Ohm Stub PCI_PERR# BDSTS J1E17 3.3V PCI 3-State 3-State Parity Error 5V PCI Toler. 10 Ohm Stub 8.2K Pull-up PCI_SERR# BDOD1 J1A18 3.3V PCI Floated Floated System Error 5V PCI Toler. 10 Ohm Stub 8.2K Pull-up PCI_REQ# BDTS1 J1A06 3.3V PCI 3-State 3-State Bus Request 5V PCI Toler. Series Term. PCI_GNT# BDTS2 J1E05 3.3V PCI N/A / N/A / Bus Grant 5V PCI Toler. 3-State 3-State Series Term. 100K Pull-up PCI_RST# BDTS2 J1C05 3.3V PCI N/A / 0 N/A / 0 Reset 5V PCI Toler. PCI_RDY_PAR BDTS2 J1B05 3.3V PCI N/A / N/A / Ready Parity 5V PCI Toler. 3-State 3-State 10 Ohm Stub 8.2K Pull-up PCI_CLK BDTS2 J1D06 3.3V PCI N/A / N/A / Bus Clock 5V PCI Toler. Active Active Series Term. PCI_SDONE N/A J1B17 None Unused PCI_SBO# N/A J1C17 None Unused PCI_LOCK# N/A J1E16 10 Ohm Stub N/A N/A Unused
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SIGNAL NAME Signal I/O Voltage/ POR PCI Reset Comment Type Pin Technology Value Value PCI Central Resource PCI_SYSEN# Input J2C02 3.3V PCI N/A N/A System Slot Enable 5V PCI Toler. 8.2K Pull-up PCI_REQ1# Input J2C01 3.3V PCI N/A N/A Arbitration Request 5V PCI Toler. PCI_REQ2# Input J2E01 3.3V PCI N/A N/A Arbitration Request 5V PCI Toler. PCI_REQ3# Input J2E02 3.3V PCI N/A N/A Arbitration Request 5V PCI Toler. PCI_REQ4# Input J2D03 3.3V PCI N/A N/A Arbitration Request 5V PCI Toler. PCI_REQ5# Input J2D15 3.3V PCI N/A N/A Arbitration Request 5V PCI Toler. PCI_REQ6# Input J2D17 3.3V PCI N/A N/A Arbitration Request 5V PCI Toler. PCI_GNT1# OTS J2D01 3.3V PCI 3-State 3-State Arbitration Grant Series Term. PCI_GNT2# OTS J2D02 3.3V PCI 3-State 3-State Arbitration Grant Series Term. PCI_GNT3# OTS J2C03 3.3V PCI 3-State 3-State Arbitration Grant Series Term. PCI_GNT4# OTS J2E03 3.3V PCI 3-State 3-State Arbitration Grant Series Term. PCI_GNT5# OTS J2E15 3.3V PCI 3-State 3-State Arbitration Grant Series Term. PCI_GNT6# OTS J2E17 3.3V PCI 3-State 3-State Arbitration Grant Series Term. PCI_CLK1 OTS J2A01 3.3V PCI 3-State 3-State / Clock Distribution Series Term. / Active Active PCI_CLK2 OTS J2A02 3.3V PCI 3-State 3-State / Clock Distribution Series Term. / Active Active PCI_CLK3 OTS J2B02 3.3V PCI 3-State 3-State / Clock Distribution Series Term. / Active Active PCI_CLK4 OTS J2A03 3.3V PCI 3-State 3-State / Clock Distribution Series Term. / Active Active PCI_CLK5 OTS J2A20 3.3V PCI 3-State 3-State / Clock Distribution Series Term. / Active Active PCI_CLK6 OTS J2A21 3.3V PCI 3-State 3-State / Clock Distribution Series Term. / Active Active PCI_CLK7 OTS J2C21 3.3V PCI 3-State 3-State / Clock Distribution Series Term. / Active Active PCI Miscellaneous Signals PCI_REQ64# Pull-up J1B25 8.2K Pull-up High High 64 Bit Bus Request, Unused
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SIGNAL NAME Signal I/O Voltage/ POR PCI Reset Comment Type Pin Technology Value Value PCI_ACK64# Pull-up J1E24 8.2K Pull-up High High 64 Bit Bus Acknowledge, Unused PCI_PRST# Pull-up J2C17 8.2K Pull-up N/A N/A Push Button Reset Unused PCI_DEG# Input, J2C16 3.3V CMOS N/A N/A Power Degrading CS 5V TTL Tol. 8.2K Pull-up PCI_FAL# Input, J2C15 3.3V CMOS N/A N/A Power Failed CS 5V TTL Tol. 8.2K Pull-up PCI_ENUM# Input, J1C25 3.3V CMOS N/A N/A Module Added or about CS 5V TTL Tol. to be Dropped 8.2K Pull-up Table 1 Content Notes: Signal will be input only when the card is operating as the PCI central resource. This is indicated by the input signal PCI_SYSEN# being active. Signal will be an OTS when the card is operating as the PCI central resource. This is indicated by the input signal PCI_SYSEN# being active. The RAD750 3U CompactPCI board contains a fully compliant target and initiator I/O interface to the PCI local bus. Additionally, when PCI_SYSEN# is active, the RAD750 3U CompactPCI board provides the clock, request and grant I/O signals required for a PCI central resource. The PCI I/O signals are discussed thoroughly in chapter 2 of the PCI Specification, so this section mostly serves to specify optional PCI I/O features the RAD750 3U CompactPCI board must support, as well as to provide a PCI I/O summary for ease of reference. Note the special requirements on PCI_RST#, PCI_SERR#, and on the added PCI sideband signal PCI_RDY_PAR. PCI_RDY_PAR was added to provide additional fault tolerance.
3.1.1 PCI Interface I/O The RAD750 3U CompactPCI board shall be designed to allow multiple RAD750 3U CompactPCI boards on the same PCI Bus. The RAD750 3U CompactPCI board supports the following PCI interface I/O on the main backpanel connectors (J1 and J2). The RAD750 3U CompactPCI board is designed to permit operation from any CompactPCI slot without requiring physical reconfiguration of the RAD750 3U CompactPCI board. Multiple RAD750 3U CompactPCI board’s can be placed on the same PCI bus backpanel, with the PCI_SYSEN# signal from the backpanel being used by the RAD750 3U CompactPCI board to determine if it is to act as the PCI Central Resource.
3.1.1.1 PCI_AD(31:0) The RAD750 3U CompactPCI board supports a 32-bit PCI AD bus as described in the PCI Specification. PCI address and data are multiplexed onto the PCI_AD(31:0) I/O signals. A bus transaction consists of an address phase (the RAD750 3U CompactPCI board does not support Dual-Address Cycles) followed by one or more data phases. The RAD750 3U CompactPCI board supports burst accesses as both target and initiator on the PCI bus. When acting as the PCI central resource (PCI_SYSEN# is active), the PCI_AD(31:0) signals are driven to 0x0000 0000 during PCI reset to prevent the PCI bus from floating, provided the board is not in test or POR mode, which will override the OCD control and tri-state the driver. PCI_AD(31:0) are held in tri-state during PCI reset when the RAD750 3U CompactPCI board is not selected as the PCI central resource. There is a 10 Ohm stub termination on each signal.
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3.1.1.2 PCI_C/BE(3:0)# PCI_C/BE(3:0)# provide multiplexed command and byte enables on the PCI bus. During the address phase of a transaction, the PCI command is valid. During each data phase of a transaction, the byte enables are valid. The byte enables are free to change between data phases, but are valid on the clock that starts each data phase and stay valid for the entire data phase (regardless of the state of PCI_IRDY#). PCI_C/BE(3:0)# is always driven by the transaction master. Similar to PCI_AD(31:0), when acting as the PCI central resource, the RAD750 3U CompactPCI board drives PCI_C/BE(3:0)# to 0b0000 during PCI reset provided the board is not in test or POR mode, which will override the OCD control and tri-state the driver. PCI_C/BE(3:0)# are tri-state during PCI reset when the it is not the central resource. There is a 10 Ohm stub termination on each signal.
3.1.1.3 PCI_PAR The PCI_PAR signal provides even parity over PCI_AD(31:0) and PCI_C/BE(3:0)#. (The number of ‘1’s on PCI_AD(31:0), PCI_C/BE(3:0)#, and PCI_PAR equals an even number.) Parity is calculated the same for all PCI transactions regardless of the type. PCI_PAR is valid for address phases one clock after the address phase completes. For data phases, parity is valid one clock after PCI_IRDY# is asserted on a write, or one clock after PCI_TRDY# is asserted on a read and remains valid until once clock after the data phase completes. The transaction master drives PCI_PAR on writes; the target drives PCI_PAR on reads. Similar to PCI_AD(31:0) and PCI_C/BE(3:0)#, the RAD750 3U CompactPCI board, when acting as the PCI central resource, drives PCI_PAR to ‘0’ during PCI reset, provided the board is not in test or POR mode, which will override the OCD control and tri-state the driver. When not acting as the PCI central resource, the RAD750 3U CompactPCI board tri-states PCI_PAR during PCI reset. There is a 10 Ohm stub termination on this signal.
3.1.1.4 PCI_FRAME# PCI_FRAME# is asserted by the PCI entity who is granted mastership of the PCI bus to claim the bus and begin a transaction. While PCI_FRAME# is asserted, data transfers continue. When PCI_FRAME# is deasserted, the transaction is in its final data phase or has completed. There is a 10 Ohm stub termination on this signal and an 8.2K pull-up to 3.3V.
3.1.1.5 PCI_IRDY# Initiator Ready is driven by the initiator (bus master) and is asserted to indicate that the master is able to complete the current data phase of a transaction. During a write, PCI_IRDY# indicates that valid data is present on PCI_AD(31:0). During a read, PCI_IRDY# indicates the master is ready to accept data. Data is transferred (and a data phase is completed) whenever PCI_IRDY# and PCI_TRDY# are both asserted. Wait cycles are inserted into data phases until both PCI_IRDY# and PCI_TRDY# are asserted. There is a 10 Ohm stub termination on this signal and an 8.2K pull-up to 3.3V.
3.1.1.6 PCI_TRDY# Target Ready is driven by the bus target and is asserted to indicate that the target is able to complete the current data phase of a transaction with data being transferred. During a read, PCI_TRDY# indicates that valid data is present on PCI_AD(31:0). During a write, PCI_TRDY# indicates the target is ready to accept data. Data is transferred (and a data phase is completed) whenever PCI_TRDY# and PCI_IRDY# are both asserted. Wait cycles are inserted into data phases until both PCI_TRDY# and PCI_IRDY# are asserted. There is a 10 Ohm stub termination on this signal and an 8.2K pull-up to 3.3V.
23 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
3.1.1.7 PCI_STOP# PCI_STOP# is driven by the bus target and is asserted to indicate that the target is requesting to terminate the current transaction. The RAD750 3U CompactPCI board supports all types of target termination. There is a 10 Ohm stub termination on this signal and an 8.2K pull-up to 3.3V.
3.1.1.8 PCI_DEVSEL# A PCI bus target will drive PCI_DEVSEL# active when it determines it has been selected as the target for the current transaction. The transaction master uses PCI_DEVSEL# as an input to signify that a target has claimed the transaction the master has started. Once asserted, PCI_DEVSEL# remains active throughout a transaction, unless to signify a target abort. The RAD750 3U CompactPCI board only supports Medium speed PCI_DEVSEL# as a target, but supports all valid PCI_DEVSEL# timings as a master. There is a 10 Ohm stub termination on this signal and an 8.2K pull-up to 3.3V.
3.1.1.9 PCI_IDSEL Initialization Device Select is used as a chip select during configuration read and write cycles. As a target, the RAD750 3U CompactPCI board only responds to "multi-function" Type 0 configuration cycles. A device that supports multi-function Type 0 configuration cycles will assert PCI_DEVSEL# in response to a configuration read or write command only if its PCI_IDSEL is active, PCI_AD(1:0) is 0b00, and PCI_AD(10:8) match a function that is implemented in the device. The RAD750 3U CompactPCI board only has function 0 defined. (A single-function Type 0 configuration cycle decode does not include a decode of AD(10:8).) There is a 10 Ohm stub termination on this signal.
3.1.1.10 PCI_PERR# Parity Error is used for the reporting of data parity errors during all PCI transactions except a Special Cycle. (Data parity errors during Special Cycle commands and address parity errors are reported using PCI_SERR# if enabled.) Refer to the PCI Specification for details on the operation of PCI_PERR#. There is a 10 Ohm stub termination on this signal and an 8.2K pull-up to 3.3V.
3.1.1.11 PCI_SERR# System Error is defined in the PCI Specification as an open drain output only signal. However, the RAD750 3U CompactPCI board, when operating as the PCI central resource will additionally receive PCI_SERR# as an input, therefore the RAD750 3U CompactPCI board redefines this signal as a bi- directional open drain I/O (BDOD). The PCI Specification (chapter 3.10 Special Design Considerations) states ‘devices cannot drive and receive signals at the same time’. In order to meet this requirement, the RAD750 3U CompactPCI board wraps its PCI_SERR# output internally (i.e. prior to the I/O cell in the Power PCI chip). The RAD750 3U CompactPCI board ignores the PCI_SERR# receiver input when it is not the PCI central resource. There is a 10 Ohm stub termination on this signal and an 8.2K pull-up to 3.3V.
3.1.1.12 PCI_REQ# The RAD750 3U CompactPCI board asserts PCI_REQ# only when it is not the PCI central resource, it requires mastership of the PCI bus and is capable of sending or receiving data as soon as PCI_FRAME# is asserted. PCI_REQ# is an output only signal that istri-stated during PCI reset. A series termination resistor is placed on the RAD750 3U CompactPCI board close to the drive pin for this signal.
3.1.1.13 PCI_GNT# Grant is defined by the PCI Specification as a type t/s (tri-state) signal. The RAD750 3U CompactPCI board only uses this signal as a chip input. GNT# is asserted by a bus arbiter to indicate that the device
24 Document Number: 234A524 RAD750 CompactPCI Hardware Specification receiving GNT# can assert FRAME# on the next clock to claim mastership of the bus. The RAD750 3U CompactPCI board ignores this input when it is the PCI central resource. A 100K pull-up resistor to 3.3V is connected to this signal. NOTE: To support a PCI board that can be configured as either a System Board or a Peripheral Board in a Compact PCI environment, two PCI request/grant pairs are provided at the Power PCI ASIC periphery. One that is used when in a System Board slot (central resource active), and one that is used when in a Peripheral Board slot (central resource inactive). REQ#/GNT# function normally when the PCI Core is not the central resource, and are held tri-state (REQ#) and ignored (GNT#) when the PCI Core is configured as the central resource. CR_REQ#/CR_GNT#, function normally when the PCI Core is the central resource, and shall be held tri-state (CR_REQ#) and ignored (CR_GNT#) when the PCI Core is not configured as the central resource. CR_REQ#/CR_GNT# are connected on card to PCI_REQ#7/PCI_GNT7# so internal RAD750 3U CompactPCI board requests for the PCI bus can be routed back to the arbiter when the card is acting as the central resource.
3.1.1.14 PCI_RST# PCI Reset is used to bring PCI specific registers, sequencers, and signals to a consistent state. When the RAD750 3U CompactPCI board is the PCI central resource it drives PCI_RST# as an output. The PCI Specification requires that PCI_RST# be driven active ‘as soon as possible’ during power up and that it remains active for at least 1ms. Additionally, the PCI Specification requires that PCI_RST# be active for a minimum of 100us after PCI_CLK is stable. The RAD750 3U CompactPCI board relies on software to meet the PCI_RST# length requirements. While PCI_RST# is being driven active by the RAD750 3U CompactPCI board, it tri-states the following signals: PCI_FRAME#, PCI_IRDY#, PCI_TRDY#, PCI_STOP#, PCI_DEVSEL#, PCI_PERR#, PCI_REQ#, PCI_RDY_PAR, and PCI_GNT(6:1)#. At the same time, PCI_SERR# is floated and PCI_AD(31:0), PCI_C/BE(3:0)#, and PCI_PAR is driven to 0’s. When the RAD750 3U CompactPCI board is not the PCI central resource, it receives PCI_RST# as an input. In this mode, the RAD750 3U CompactPCI board tri-states/floats all PCI outputs asynchronously to meet the 40ns maximum T_rst-off requirement. (This includes PCI_AD(31:0), PCI_C/BE(3:0)#, and PCI_PAR.) There is a 10 Ohm stub termination on this signal.
3.1.1.15 PCI_RDY_PAR Ready Parity is a PCI sideband signal that reflects odd parity across itself, PCI_IRDY#, and PCI_TRDY#. The RAD750 3U CompactPCI board drives this signal when it is acting as the PCI central resource, and receives this signal otherwise. PCI_RDY_PAR is delayed one clock cycle from the values of PCI_IRDY# and PCI_TRDY# and is always valid regardless of their states. PCI_RDY_PAR checking is enabled by the Ready Parity Enable bit in the Error Checking register and the Parity Error Response bit in the Command register. If Ready Parity Enable and Parity Error Response are both asserted, and the RAD750 3U CompactPCI board detects a ready parity error while it is master of a PCI transaction, it signals PCI_SERR# (if enabled), reports the error in the PCI Initiator Ready Parity Error bit of the Status 2 register, and terminates the transfer. If Ready Parity Enable and Parity Error Response are both asserted, and the PCI Core detects a ready parity error while it is the target of a PCI transaction, it signals PCI_SERR# (if enabled), report the error in the PCI Target Ready Parity Error bit of the Status 2 register and target abort. There is a 10 Ohm stub termination on this signal and an 8.2K pull-up to 3.3V.
25 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
3.1.1.16 PCI_CLK The PCI_CLK must be from 0 to 33 MHz and is used for all PCI clock domain functions. PCI_CLK is a rising edge active clock and originates with the PCI central resource. When the RAD750 3U CompactPCI board is the PCI central resource, PCI_CLK drives a buffered copy of the PCI_CLK through a series terminating resistor. When the RAD750 3U CompactPCI board is not the PCI central resource, PCI_CLK is used to directly receive this signal and clock the PCI function on the RAD750 3U CompactPCI board.
3.1.2 PCI Central Resource I/O (external) The RAD750 3U CompactPCI board provides a PCI central resource function that, when enabled, uses the following external I/O signals in addition to ones described above. The RAD750 3U CompactPCI board provides the capability to disable the central resource function through hard wired or register controls.
3.1.2.1 PCI_SYSEN# The RAD750 3U CompactPCI board uses this input signal to enable/disable the PCI central resource. When PCI_SYSEN# is active (low), the RAD750 3U CompactPCI board enables the PCI central resource function. When PCI_SYSEN# is inactive (low), the RAD750 3U CompactPCI board disables the PCI central resource function. This signal is pulled up through a 8.2K resistor to V(I/O).
3.1.2.2 PCI_REQ(6:1)# When configured as the PCI central resource, the RAD750 3U CompactPCI board uses these inputs and PCI_REQ# to receive PCI requests from up to seven external devices. Each PCI_REQ(6:1)# and PCI_REQ# input is paired with its corresponding PCI_GNT(6:1)# and PCI_GNT# output signal. An eighth set of request and grant signals is used for the internal Power PCI requests. The RAD750 3U CompactPCI board supports all eight of these PCI_REQ# inputs being active at the same time.
3.1.2.3 PCI_GNT(6:1)# When configured as the PCI central resource, the RAD750 3U CompactPCI board uses these outputs to grant one of up to six external requesting devices mastership of the PCI bus. PCI_GNT(7)# is used internally on the RAD750 3U CompactPCI board to wrap the internal grant to the Power PCI when acting as the PCI central resource board. Only one of these PCI_GNT# outputs is active at any one time. All of these PCI_GNT# outputs are tri-stated while the RAD750 3U CompactPCI board is generating PCI reset. When the Power PCI is not acting as PCI central resource, PCI_GNT(6:1)# are tri-state. Each of these signals is series terminated close to its driver pin.
3.1.2.4 PCI_CLK(7:1) When the RAD750 3U CompactPCI board is the PCI central resource, PCI_CLK(7:1) are used to drive buffered copies of the PCI_CLK through series terminating resistors. PCI_CLK_7 is wrapped to the PCI clock input signal on the RAD750 3U CompactPCI board Power PCI ASIC.
3.1.3 PCI Miscellaneous Interface This section covers signals not part of the main PCI Data Bus or the PCI central resource but defined in the PCI bus or CompactPCI specifications.
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3.1.3.1 PCI_REQ64# The 64 bit transfer request signal, PCI_REQ64#, is not used by the RAD750 3U CompactPCI board. It is pulled up through a 8.2K Ohm resistor to 3.3V so that when used as the PCI central resource, the bus will default to 32 bits after reset.
3.1.3.2 PCI_ACK64# The 64 bit transfer acknowledge signal, PCI_REQ64#, is not used by the RAD750 3U CompactPCI board. It is pulled up through a 8.2K Ohm resistor to 3.3V so that when used as the PCI central resource, the bus will default to 32 bits after reset.
3.1.3.3 PCI_PRST# This optional push button reset signal is not implemented on the RAD750 3U CompactPCI board.
3.1.3.4 PCI_DEG# The PCI power degrading signal, PCI_DEG#, is available for use by the RAD750 3U CompactPCI board to signal an interrupt when power from the 3.3V power supplies begins to degrade. This signal is pulled up to 3.3V through an 8.2K Ohm resistor.
3.1.3.5 PCI_FAL# The PCI power failed signal, PCI_FAL#, is available to be used by the RAD750 3U CompactPCI board to signal an interrupt when power from the 3.3V power supplies has failed. This signal is pulled up to 3.3V through an 8.2K Ohm resistor.
3.1.3.6 PCI_ENUM# The PCI enumerate signal, PCI_ENUM#, is available to be used by the RAD750 3U CompactPCI board to signal an interrupt when one or more modules are added or about to be removed. This signal is pulled up to 3.3V through an 8.2K Ohm resistor.
3.2 Non-PCI Interfaces The signals listed in Table 2 are implemented on the indicated main (J1 or J2) or front panel connector (J7).
Table 2. RAD750 3U CompactPCI board Non-PCI Signals
SIGNAL NAME Signal I/O Pin Reset BIST Voltage/ Comment Type Value Value Technology (Normal Op.) BACKPANEL JTAG MASTER/SLAVE INTERFACE JTMS_TMS BDTS1, J1C02 3-State 3-State 3.3V CMOS JTAG Test Mode CS 5V TTL Tol. Select 8.2K Pull-up JTMS_TCLK BDTS1, J1A02 3-State 3-State 3.3V CMOS JTAG Test Clock CS 5V TTL Tol. 8.2K Pull-up JTMS_TDO OTS J1D02 3-State 3-State 3.3V CMOS, JTAG Test Data Out 8.2K Pull-up
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SIGNAL NAME Signal I/O Pin Reset BIST Voltage/ Comment Type Value Value Technology (Normal Op.) JTMS_TRST_L BDTS1, J1C01 3-State 3-State 3.3V CMOS JTAG Test Reset CS 5V TTL Tol. 1K Pull-down JTMSB_TDI Input, CS J1E02 N/A N/A 3.3V CMOS JTAG Test Data In 5V TTL Tol. 8.2K Pull-up JTMSB_MSTR_EN_IN Input, CS J2E21 N/A N/A 3.3V CMOS JTAG Master Enable 5V TTL Tol. 8.2K Pull-up RAD750 JTAG (COP) INTERFACE JTM_TMS Input, J7A07 3-State 3-State 3.3V CMOS JTAG Test Mode OTS2 5V TTL Tol. Select 1K Pull-up JTM_TCLK Input, J7A05 3-State 3-State 3.3V CMOS JTAG Test Clock OTS2 5V TTL Tol. 1K Pull-up JTM_TDO OTS J7A01 3-State 3-State 3.3V CMOS JTAG Test Data Out JTM_TRST_L Input J7A02 N/A N/A 3.3V CMOS JTAG Test Reset 5V TTL Tol. 1K Pull-up JTM_TDI Input J7A03 N/A N/A 3.3V CMOS JTAG Test Data In 5V TTL Tol. 1K Pull-down JTM_SRESET_L Input J7A06 N/A N/A 3.3V CMOS RAD750 Soft Reset 1K Pull-up JTM_RESET_L Input J7A08 N/A N/A 3.3V CMOS RAD750 3U 1K Pull-up CompactPCI board Hard Reset CPU_CKSTP_L OTS J7A09 3-state 3-state 3.3V CMOS RAD750 Checkstop 1K Pull-up Out JTM_MSTR_EN_IN Input, SP J7A10 N/A N/A 3.3V CMOS JTAG Master Enable / 5V TTL Tol. Probe Present 1K Pull-up JTM_POWER Output J7A04 Active Active 3.3V through Power Sense by Probe 1K Series Resistor POWER PCI ASIC JTAG INTERFACE JTS_TMS Input J7A17 N/A N/A 3.3V CMOS JTAG Test Mode 5V TTL Tol. Select 8.2K Pull-up JTS_TCLK Input J7A19 N/A N/A 3.3V CMOS JTAG Test Clock 5V TTL Tol. 8.2K Pull-up JTS_TDI Input J7A13 N/A N/A 3.3V CMOS JTAG Test Data In 5V TTL Tol. 8.2K Pull-up
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SIGNAL NAME Signal I/O Pin Reset BIST Voltage/ Comment Type Value Value Technology (Normal Op.) JTS_TRST_L Input J7A22 N/A N/A 3.3V CMOS JTAG Test Reset 5V TTL Tol. 1K Pull-down JTS_TDO Output J7A15 3-State 3-State 3.3V CMOS, JTAG Test Data Out 8.2K Pull-up JTS_PROBE_PRESENT_L Input, SP J7A21 N/A N/A 3.3V CMOS Control for external 5V TTL Tol. JTAG probe support UART INTERFACE UART_TX_DATA Output J2E19 ‘1’ ‘1’ 3.3V CMOS Serial Data Out J7A16 UART_RX_DATA Input J2D19 N/A N/A 3.3V CMOS Serial Data In J7A14 5V TTL Tol. UART_CTS_L Input J2E20 N/A N/A 3.3V CMOS Clear to Send (CTS) J7A20 5V TTL Tol. UART_RTS_L OD J2C20 3-State 3-State 3.3V CMOS Request to Send J7A18 (RTS) INTERRUPTS AND DISCRETES MISC_PID0 BDTS J2E13 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID1 BDTS J2E12 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID2 BDTS J2E11 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID3 BDTS J2E10 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID4 BDTS J2E09 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID5 BDTS J2E08 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID6 BDTS J2E07 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID7 BDTS J2E06 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID8 BDTS J2D13 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID9 BDTS J2D11 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID10 BDTS J2D09 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID11 BDTS J2D07 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID12 BDTS J2E05 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID13 BDTS J2E04 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID14 BDTS J1D04 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes
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SIGNAL NAME Signal I/O Pin Reset BIST Voltage/ Comment Type Value Value Technology (Normal Op.) MISC_PID15 BDTS J1E04 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID21 BDTS J2B08 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID22 BDTS J2B06 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID23 BDTS J2C04 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID24 BDTS J2C06 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID25 BDTS J2C12 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID26 BDTS J2C10 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID27 BDTS J2C08 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID30 BDTS J2E14 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes MISC_PID31 BDTS J2C14 3-State 3-State 3.3V CMOS Programmable I/O 5V TTL Tol. Discretes UART_OUT1_L OD J2A12 3-State 3-State 3.3V CMOS Output 1 (OUT1) 8.2K Pull-up MISC_NMI_L Input, J2E18 N/A N/A 3.3V CMOS Non-maskable CS, SPU 5V TTL Tol. interrupt PCI_INTA# - MISC_PID16 - BDTS, J1A03 3-State 3-State 3.3V CMOS System PCI Interrupt UART_OUT_2_L OD 5V TTL Tol. Input 10 Ohm Stub 8.2K Pull-up PCI_INTB# - MISC_PID17 BDTS J1B03 3-State 3-State 3.3V CMOS System PCI Interrupt 5V TTL Tol. Input 10 Ohm Stub 8.2K Pull-up PCI_INTC# - MISC_PID28 BDTS J1C03 3-State 3-State 3.3V CMOS System PCI Interrupt 5V TTL Tol. Input 10 Ohm Stub 8.2K Pull-up PCI_INTD# - MISC_PID 29 BDTS J1E03 3-State 3-State 3.3V CMOS System PCI Interrupt 5V TTL Tol. Input 10 Ohm Stub 8.2K Pull-up RESET AND CLOCKS MISC_POR_L Input, J2B04 N/A N/A 3.3V CMOS Power On Reset CS, SP 5V TTL Tol.
CLK_EXT_SYS_OSC Input, CS J7A25 N/A N/A 3.3V CMOS External System 5V TTL Tol. Oscillator for Test
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SIGNAL NAME Signal I/O Pin Reset BIST Voltage/ Comment Type Value Value Technology (Normal Op.) CLK_EXT_SYS_OSC_SEL_L Input, CS J7A24 N/A N/A 3.3V CMOS External System 5V TTL Tol. Oscillator Select 8.2K Pull-up CONFIGURATION INTERFACE PCI_GA0 Unused J2E22 N/A N/A Unused Geographical Address PCI_GA1 Unused J2D22 N/A N/A Unused Geographical Address PCI_GA2 Unused J2C22 N/A N/A Unused Geographical Address PCI_GA3 Unused J2B22 N/A N/A Unused Geographical Address PCI_GA4 Unused J2A22 N/A N/A Unused Geographical Address PCI_GAP Unused J2D21 N/A N/A Unused Geographical Address Parity MISC_I2C_0 Unused J2C18 N/A N/A Unused I2C Interface MISC_I2C_1 Unused J2B18 N/A N/A Unused I2C Interface MISC_ROM_ON_PCI Input, CS J2A16 N/A N/A 3.3V CMOS Indicates ROM is 5V TTL Tol. located on PCI 8.2K Pull-up CHASSIS_GRND_0 Unused J2B16 N/A N/A Tied to 5 M Chassis Grounding ohm Pull- down CHASSIS_GRND_1 Unused J2E16 N/A N/A Tied to 5 M Chassis Grounding ohm Pull- down Notes on Table 2: This port operates as either a JTAG Master or Slave depending on the state of various signals. When the JTAG Power PCI Probe is present, that is JTS_PROBE_PRESENT_L is grounded, this interface shall not include the Power PCI JTAG Slave in this JTAG string. If JTB_MASTER_ENABLE_IN is active, then this port shall control the JTAG interface; otherwise, this port acts as a slave port on the JTAG interface if JTS_PROBE_PRESENT_L is not grounded. When the Probe is not present that is JT7_MSTR_EN_IN is not grounded, these signals may be driven as OTS by the RAD750 3U CompactPCI board in order to obtain online access to the RAD750's JTAG Interface Port
3.2.1 JTAG Interfaces The RAD750 3U CompactPCI board provides three JTAG (IEEE 1149.1a) ports. Taken together, these RAD750 3U CompactPCI board interfaces provide external or internal Power PCI access to the RAD750 slave port, external access to the Power PCI ASIC slave port either from the front panel or the backpanel, and external control of the backpanel JTAG interface by the Power PCI ASIC.
3.2.1.1 Backpanel JTAG Master/Slave Interface The Backpanel JTAG Master/Slave Interface port supports either a slave JTAG interface to an external master or control the interface through the Power PCI ASIC. If JTS_PROBE_PRESENT_L is high and either the Master En bit of the JTAG Control/Status Port A register in the Power PCI ASIC is low or the JTB_MSTR_EN_IN input is low, the port responds solely as a JTAG slave to an external backpanel master.
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If JTS_PROBE_PRESENT_L is low and either the Master En bit of the JTAG Control/Status Port A register in the Power PCI ASIC is low or the JTB_MSTR_EN_IN input is low, this port will not respond to any external backpanel master or control any external backpanel slave. If JTS_PROBE_PRESENT_L is low and both the Master En bit of the JTAG Control/Status Port A register in the Power PCI ASIC is high and the JTB_MSTR_EN_IN input is high, this port will control the external backpanel JTAG interface through the JTAG Control/Status Port A registers but not include the Power PCI ASIC slave JTAG port in this JTAG string. If JTS_PROBE_PRESENT_L is high and both the Master En bit of the JTAG Control/Status Port A register in the Power PCI ASIC is high and the JTB_MSTR_EN_IN input is high, this port will control the external backpanel JTAG interface through the JTAG Control/Status Port A registers and include the Power PCI ASIC slave JTAG port in this JTAG string. This port uses the set of signals listed below as described in the JTAG IEEE 1149.1a Standard. Figure 5 shows the signals that make up this interface.
JTMS_TDO JTMS_TCLK JTAG JTMS_TRST_ Backpanel JTMS_TMS Interface JTMS_TDI JTMS_MSTR_EN_IN
Figure 5. JTAG Backpanel Interface I/O
3.2.1.1.1 JTMS_TMS JTAG Test Mode Select is used to control the state of the Test Access Port (TAP) in devices connected to the backpanel JTAG interface. This signal is tied to the JTM_A_TMS(0) pin of the Power PCI ASIC. When the RAD750 3U CompactPCI board is controlling this JTAG interface, JTMS_TMS is an output. When the RAD750 3U CompactPCI board is responding solely as a JTAG slave, it is an input. Otherwise, this signal is tri-stated. This signal is tied to a 8.2K ohm pull-up resistor.
3.2.1.1.2 JTMS_TCLK JTAG Test Clock is used to clock state information and test data into and out of the devices connected to the backpanel JTAG interface during TAP operation. When the RAD750 3U CompactPCI board is controlling this JTAG interface, JTMS_TCLK is an output. When the RAD750 3U CompactPCI board is responding solely as a JTAG slave, it is an input. Otherwise, this signal is tri-stated. This signal is tied to a 8.2K ohm pull-up resistor.
3.2.1.1.3 JTMS_TDO JTAG Test Data Out is used to serially shift test data and test instructions into devices connected to the backpanel JTAG interface in a string during TAP operations. When the RAD750 3U CompactPCI board is controlling this JTAG interface, JTMS_TDO is an output from the JTAG Master Port A in the Power PCI ASIC. When the RAD750 3U CompactPCI board is
32 Document Number: 234A524 RAD750 CompactPCI Hardware Specification responding solely as a JTAG slave, it is an output from the JTAG Slave Port in the Power PCI ASIC. Otherwise, this signal is tri-stated.
3.2.1.1.4 JTMS_TRST_L JTAG Test Reset is driven active to initialize the TAP controllers in devices connected to the backpanel JTAG interface. When the RAD750 3U CompactPCI board is controlling this JTAG interface, JTMS_TRST_L is an output. When the RAD750 3U CompactPCI board is responding solely as a JTAG slave, it is an input. Otherwise, this signal is tri-stated. This signal is tied to a 1K ohm pull-down resistor.
3.2.1.1.5 JTMS_TDI The RAD750 3U CompactPCI board receives serially shifted test data from other devices on the backpanel JTAG interface via the JTAG Test Data In during TAP operations. This signal is always an input. When the RAD750 3U CompactPCI board is controlling this JTAG interface, JTMS_TDI is an input to either JTAG Master Port A or the JTAG slave port in the Power PCI ASIC depending on whether the slave port is included in the JTAG string. When the RAD750 3U CompactPCI board is responding solely as a JTAG slave, it is an input to the JTAG Slave Port in the Power PCI ASIC. This signal is tied to a 8.2K ohm pull-up resistor.
3.2.1.1.6 JTMS_MSTR_EN_IN The JTAG Backpanel Interface Master Enable signal controls whether the JTAG backpanel interface may be controlled by this RAD750 3U CompactPCI board. When low, all primary non-data outputs are tri- stated and used solely as inputs. Typically, this signal is allowed to float high for a card in the system slot and tied low for a card in a peripheral slot. For fault tolerance reasons, multiple cards may be configured as possible masters and multiple positions may be floated high relying on the internal Master En bit of the JTAG Control/Status Port A register in each Power PCI ASIC to enable the appropriate slot as master of the JTAG interface. This signal is tied to a 8.2K ohm pull-up resistor.
3.2.1.2 RAD750 JTAG (COP) Interface The RAD750 JTAG (COP) Interface primarily functions as a slave JTAG interface port on the RAD750 to an external processor emulator probe for hardware / software debug. When this interface is not connected to such a probe, the RAD750 port allows internal RAD750 3U CompactPCI board access through the Power PCI ASIC JTAG Master Port B. If either the Master En bit of the JTAG Control/Status Port B register in the Power PCI ASIC is low or the JT7_MSTR_EN_IN input is low, the RAD750 port will respond solely as a JTAG slave to an external probe. If both the Master En bit of the JTAG Control/Status Port B register in the Power PCI ASIC is high and the JT7_MSTR_EN_IN input is high, the RAD750 port will be controlled through the JTAG Control/Status Port B registers in the Power PCI ASIC and must not be controlled externally. This port supports the set of signals listed below as described in the JTAG IEEE 1149.1a Standard. Figure 6 shows the signals that make up this interface.
33 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
JTM_TDO JTM_TCLK JTAG JTM_TRST_L RAD750 JTM_TMS Interface JTM_TDI JTM_MSTR_EN_IN JTM_RESET_L JTM_SRESET_L CPU_CHKSTP_L JTM_POWER
Figure 6. JTAG RAD750 Interface I/O
3.2.1.2.1 JTM_TMS JTAG Test Mode Select is used to control the state of the Test Access Port (TAP) in the RAD750. This signal is tied to the JTM_B_TMS(0) pin of the Power PCI ASIC. When the RAD750 3U CompactPCI board is controlling this JTAG interface, JTM_TMS is an output. When the RAD750 3U CompactPCI board is responding solely as a JTAG slave, it is an input. Otherwise, this signal is tri-stated.
3.2.1.2.2 JTM_TCLK JTAG Test Clock is used to clock state information and test data into and out of the RAD750 during TAP operation. When the RAD750 3U CompactPCI board is controlling this JTAG interface, JTM_TCLK is an output. When the RAD750 3U CompactPCI board is responding solely as a JTAG slave, it is an input. Otherwise, this signal is tri-stated.
3.2.1.2.3 JTM_TDO JTAG Test Data Out is used to serially shift test data and test instructions into the RAD750 during TAP operations. This signal is always an output from the RAD750 during JTAG operations. Otherwise, this signal is tri-stated.
3.2.1.2.4 JTM_TRST_L JTAG Test Reset is driven active to initialize the TAP controller in the RAD750. It is always an input.
3.2.1.2.5 JTM_TDI The RAD750 receives serially shifted test data from either the external emulator probe or the internal Power PCI ASIC during TAP operations. This signal is always an input.
3.2.1.2.6 JTM_MSTR_EN_IN The RAD750 JTAG Interface Master Enable signal controls whether the RAD750 JTAG slave port may be controlled by this RAD750 3U CompactPCI board. When low, all primary non-data outputs are tri- stated and used solely as inputs. This signal should be tied low when an emulator probe is attached to the RAD750 3U CompactPCI board to prevent any chance of both the probe and Power PCI ASIC trying to control this port at the same time.
34 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
However, if this is impossible, then software must solely control this through the internal Master En bit of the JTAG Control/Status Port B register in the Power PCI ASIC.
3.2.1.2.7 JTM_SRESET_L This signal causes a soft reset of the RAD750.
3.2.1.2.8 JTM_RESET_L This signal causes a hard reset to the RAD750 3U CompactPCI board. It shall have the same effect as MISC_POR_L.
3.2.1.2.9 CPU_CKSTP_L This signal, when low indicates the RAD750 has detected a Checkstop condition and is entering checkstop mode where it is gating off all clocks and tri-stating all outputs. When high, this signal indicates the RAD750 is running normally.
3.2.1.2.10 JTM_POWER This signal provides a sensing output of the 3.3V power of the RAD750 3U CompactPCI board. 3.3V is connected to this pin through a 1K ohm series resistor.
3.2.1.3 Power PCI JTAG Slave Interface The Power PCI JTAG slave interface supports the control of the Power PCI ASIC JTAG slave port through an external JTAG connection. If JTS_PROBE_PRESENT_L is tied low, the external signals are connected to the Power PCI ASIC JTAG slave port. Otherwise, the slave port is connected to the Backpanel JTAG Interface string. The set of signals listed below as described in the JTAG 1149.1a Standard. All signals must be synchronous to the JTS_TCLK except JTS_TRST_L. Figure 7 shows all the signals in this interface.
JTS_TMS JTAG JTS_TCLK Power JTS_TDI PCI JTS_TDO Interface JTS_TRST_L JTS_PRO_PRE_L
Figure 7. JTAG Slave Interface I/O
3.2.1.3.1 JTS_TMS JTAG Test Mode Select is used to control the state of the Test Access Port (TAP) in the Power PCI ASIC JTAG Slave Core.
3.2.1.3.2 JTS_TCLK JTAG Test Clock is used to clock state information and test data into and out of the Power PCI ASIC JTAG Slave Core during TAP operation.
3.2.1.3.3 JTS_TDI JTAG Test Data In is used to serially receive test data and test instructions from the JTAG Master during TAP operations.
35 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
3.2.1.3.4 JTS_TDO JTAG Test Data Out is used to serially shift test data and test instructions into the external probe connected to JTAG in a string during TAP operations.
3.2.1.3.5 JTS_TRST_L When JTAG Test Reset is driven active, the TAP controller in the Power PCI JTAG core shall be initialized.
3.2.2 UART Interface The UART interface on the RAD750 3U CompactPCI board sends and receives signals external to the chip. These signals include the serial data and MODEM control signals. The RAD750 3U CompactPCI board uses no separate transceivers for this interface. Users must convert this to RS-232 or RS-422 external to the RAD750 3U CompactPCI board. Because this is the primary software debug interface for the RAD750 3U CompactPCI board, these signals are routed to both a set of user backpanel signals (J2) and the front panel connector (J7). Users must connect to no more than one of these two interfaces at a time. A picture of this Interface and its signals is shown in Figure 8.
UART_TX_DATA
UART_RX_DATA
UART Interface
UART_CTS_L
UART_RTS_L
Figure 8. Peripheral Device Interface I/O
3.2.2.1 UART_TX_DATA This signal is the serial data output to the communications link. This value is driven to a ‘1’ on reset.
3.2.2.2 UART_RX_DATA This port is the serial data input from the communications link.
3.2.2.3 UART_CTS_L Clear to Send is an active low signal that indicates the MODEM or data set is ready to exchange data. The compliment of this signal is stored in bit 4 of the MODEM Status Register. Bit 0 of the MODEM Status Register indicates whether this signal has changed since the last time the MODEM Status Register was read. Whenever bit 4 of the MODEM Status Register changes state an interrupt is sent if the MODEM Status interrupt is enabled.
36 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
3.2.2.4 UART_RTS_L Request to Send is an active low output signal that informs the MODEM or data set that the UART is ready to exchange data. Bit 1 of the MODEM Control Register controls the output of this signal. A reset sets this signal to an inactive (high) state.
3.2.3 Interrupts and Discretes The RAD750 3U CompactPCI board provides the following interrupts and discretes on the main backpanel connectors (J1 and J2).
3.2.3.1 MISC _PID(31:0) The 32 Programmable Interrupt/Discrete lines are individually configurable via software to be enabled as inputs or outputs or to be disabled. The RAD750 3U CompactPCI board allows software to use PIDs configured as inputs to provide controls for the internal chip timers, discrete inputs, and interrupts (both vector interrupts to be handled by the internal EMC and normal interrupts handled by the embedded interrupt controller). Table 3 shows the configurations for each pin that is supported by the RAD750 3U CompactPCI board. As an input, when a PID is configured to set the PID Input Register in the Power PCI ASIC, it can be configured so that the PID In Register bit will be set to a one either when a level of 1 is seen on the pin or on a falling edge transition. The values in the PID In Register can also be configured via software to generate interrupts or to be simply used as discretes. MISC_PID16 is connected on the RAD750 3U CompactPCI board to PCI_INTA#. This must be configured as an input only because PCI requires that any output be open drain. It may be configured as interrupt input if this is the Resource Controller slot. It may be configured as an output only if the system is not implementing PCI interrupts. See Section 3.2.3.5 for more details on PCI_INTA#. MISC_PID17 is connected on the RAD750 3U CompactPCI board to PCI_INTB#. This must be configured as an input only because PCI requires that any output be open drain. It may be configured as interrupt input if this is the Resource Controller slot. It may be configured as an output only if the system is not implementing PCI interrupts. See Section 3.2.3.6 for more details on PCI_INTB#. MISC_PID18 is connected on the RAD750 3U CompactPCI board to PCI_DEG#. This must be configured as an input only because PCI requires that this be sourced by a power supply. It may be configured as interrupt input in any slot position. It may be configured as an output only if the system is not implementing this power signal. MISC_PID19 is connected on the RAD750 3U CompactPCI board to PCI_FAL#. This must be configured as an input only because PCI requires that this be sourced by a power supply. It may be configured as interrupt input in any slot position. It may be configured as an output only if the system is not implementing this power signal. MISC_PID20 is connected on the RAD750 3U CompactPCI board to PCI_ENUM#. This must be configured as an input only because PCI requires that any output be open drain. It may be configured as interrupt input if this is the Resource Controller slot. MISC_PID28 is connected on the RAD750 3U CompactPCI board to PCI_INTC#. This must be configured as an input only because PCI requires that any output be open drain. It may be configured as interrupt input if this is the Resource Controller slot. It may be configured as an output only if the system is not implementing PCI interrupts. This can be used as interrupt to the RAD750 or a vector interrupt to the EMC in the Power PCI ASIC. See Section 3.2.3.7 for more details on PCI_INTC#. MISC_PID29 is connected on the RAD750 3U CompactPCI board to PCI_INTD#. This must be configured as an input only because PCI requires that any output be open drain. It may be configured as interrupt input if this is the Resource Controller slot. It may be configured as an output only if the system
37 Document Number: 234A524 RAD750 CompactPCI Hardware Specification is not implementing PCI interrupts. This can be used as interrupt to the RAD750 or a vector interrupt to the EMC in the Power PCI ASIC. See Section 3.2.3.8 for more details on PCI_INTD#.
Table 3. PID Definition Table
Signal Name PID Input Power PCI Input PID Output Power PCI External Function Function Function ASIC Function Output Function MISC_PID31 PID In Reg 31 Vector Interrupt 5 PID Out Reg 31 MISC_PID30 PID In Reg 30 Vector Interrupt 4 PID Out Reg 30 MISC_PID29 PID In Reg 29 Vector Interrupt 3 PID Out Reg 29* PCI_INTD# MISC_PID28 PID In Reg 28 Vector Interrupt 2 PID Out Reg 28* PCI_INTC# MISC_PID27 PID In Reg 27 Vector Interrupt 1 PID Out Reg 27 MISC_PID26 PID In Reg 26 Vector Interrupt 0 PID Out Reg 26 MISC_PID25 PID In Reg 25 PID Out Reg 25 MISC_PID24 PID In Reg 24 PID Out Reg 24 MISC_PID23 PID In Reg 23 PID Out Reg 23 MISC_PID22 PID In Reg 22 PID Out Reg 22 MISC_PID21 PID In Reg 21 PID Out Reg 21 MISC_PID20 PID In Reg 20 PID Out Reg PCI_ENUM# 20*** MISC_PID19 PID In Reg 19 PID Out Reg PCI_FAL# 19** MISC_PID18 PID In Reg 18 PID Out Reg PCI_DEG# 18** MISC_PID17 PID In Reg 17 PID Out Reg 17* PCI_INTB# MISC_PID16 PID In Reg 16 PID Out Reg 16* PCI_INTA# MISC_PID15 PID In Reg 15 PID Out Reg 15 MISC_PID14 PID In Reg 14 PID Out Reg 14 MISC_PID13 PID In Reg 13 PTIM3 Clear PID Out Reg 13 MISC_PID12 PID In Reg 12 PTIM3 Snapshot PID Out Reg 12 MISC_PID11 PID In Reg 11 PTIM3 Clock PID Out Reg 11 MISC_PID10 PID In Reg 10 PTIM2 Clear PID Out Reg 10 MISC_PID09 PID In Reg 09 PTIM2 Snapshot PID Out Reg 09 MISC_PID08 PID In Reg 08 PTIM2 Clock PID Out Reg 08 MISC_PID07 PID In Reg 07 PTIM1 Clear PID Out Reg 07 MISC_PID06 PID In Reg 06 PTIM1 Snapshot PID Out Reg 06 MISC_PID05 PID In Reg 05 PTIM 1 Clock PID Out Reg 05 MISC_PID04 PID In Reg 04 PID Out Reg 04 WD Timer Heartbeat MISC_PID03 PID In Reg 03 PID Out Reg 03 WD Timer Expired MISC_PID02 PID In Reg 02 PID Out Reg 02 PTIM 3 Output MISC_PID01 PID In Reg 01 PID Out Reg 01 PTIM 2 Output MISC_PID00 PID In Reg 00 PID Out Reg 00 PTIM 1 Output * PID may be output only if PCI interrupts not implemented in system.
38 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
** PID may be output only if CompactPCI power signals not implemented in system. ***PID may never be output.
3.2.3.2 UART_IO_OUT1_L This programmable output signal will be an active low signal that is user-designated. Bit 2 of the MODEM Control Register in the Power PCI ASIC controls the output of this signal. This signal resets to its inactive high state.
3.2.3.3 UART_IO_OUT2_L This programmable output signal will be an active low output signal. Bit 3 of the MODEM Control Register of the Power PCI ASIC controls the output of this signal. This signal resets to its inactive high state. This signal is connected on the RAD750 3U CompactPCI board to PCI_INTA# in order to provide an open drain driver for this signal on cards needing to generate a PCI interrupt.
3.2.3.4 MISC_NMI_L The non-maskable interrupt input causes a machine check interrupt to be posted to the RAD750. This signal shall be NOR'd through logic with any non-maskable interrupt conditions in the Power PCI ASIC to generate the Machine Check Interrupt (MCP) to the RAD750.
3.2.3.5 PCI_INTA# This active low interrupt signal causes an interrupt to be seen by RAD750 when the RAD750 3U CompactPCI board is configured to process interrupts on this pin. Externally generated interrupts must conform to the requirements in the PCI Specification. The RAD750 3U CompactPCI board can be configured to generate a single function PCI interrupt on this pin using the Open Drain output from UART_OUT2_L. This would typically be used when the RAD750 3U CompactPCI board is not the Resource Controller for its processor subsystem.
3.2.3.6 PCI_INTB# This active low interrupt signal causes an interrupt to be seen by RAD750 when the RAD750 3U CompactPCI board is configured to process interrupts on this pin. Externally generated interrupts must conform to the requirements in the PCI Specification. The RAD750 3U CompactPCI board should not be configured to generate an output on this pin unless no card in the subsystem supports PCI Interrupts.
3.2.3.7 PCI_INTC# This active low interrupt signal causes an interrupt to be seen by RAD750 when the RAD750 3U CompactPCI board is configured to process interrupts on this pin. Externally generated interrupts must conform to the requirements in the PCI Specification. The RAD750 3U CompactPCI board should not be configured to generate an output on this pin unless no card in the subsystem supports PCI Interrupts.
3.2.3.8 PCI_INTD# This active low interrupt signal causes an interrupt to be seen by RAD750 when the RAD750 3U CompactPCI board is configured to process interrupts on this pin. Externally generated interrupts must conform to the requirements in the PCI Specification. The RAD750 3U CompactPCI board should not be configured to generate an output on this pin unless no card in the subsystem supports PCI Interrupts.
3.2.4 Resets and Clocks The RAD750 3U CompactPCI board provides the following general reset and clock signals.
39 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
3.2.4.1 MISC_POR_L The RAD750 3U CompactPCI board receives and processes the MISC_POR_L as an asynchronous reset for the entire board. This signal causes the Power PCI ASIC and RAD750 to be changed to their default states. It also causes all signals to be placed in their Reset states.
3.2.4.2 CLK_EXT_SYS_OSC When CLK_EXT_SYS_OSC_SEL_L is active, this signal is used by the RAD750 3U CompactPCI board as an alternate clock signal (instead of the onboard oscillator) from which all other internally generated system, PCI, real-time, and JTAG clock signals are generated. It must have a maximum frequency of 33MHz with no minimum frequency. The duty cycle of this signal must be between 40% (TBR) and 60% (TBR).
3.2.4.3 CLK_EXT_SYS_OSC_SEL_L This signal is used to select whether the RAD750 3U CompactPCI board should use the onboard oscillator or the input CLK_EXT_SYS_OSC as an the clock signal from which all other internally generated system, PCI, real-time, and JTAG clock signals are generated. This signal shall be tied to a 8.2K ohm pull-up resistor.
3.2.5 Configuration Inputs The RAD750 3U CompactPCI board provides the following configuration input signals.
3.2.5.1 PCI_GA(4:0,P) The PCI Geographical Address bits are provided for boards that require a unique slot address for each board in a subsystem. These pins are unused on the RAD750 3U CompactPCI board.
3.2.5.2 I2C(1:0) The I2C interface is used as a configuration and status interface in some systems. These pins are unused on the RAD750 3U CompactPCI board.
3.2.5.3 MISC_ROM_ON_PCI This active high signal indicates that there is ROM in the upper 16 MB of the PCI Memory Address space. When this signal is high, the RAD750 3U CompactPCI board maps memory accesses in the upper 8 or 16 MB (depending on Power PCI ASIC memory control registers) from the RAD750 to PCI Memory bus. Otherwise, such accesses are mapped to on-card EEPROM or treated as non-existent memory. This signal is tied to a 8.2K ohm pull-up resistor.
3.2.5.4 CHASSIS_GRND(0:1) These pins are attached to 5 M Ohm resistors to ground on the RAD750 3U CompactPCI board. They may be utilized for chassis to signal isolation verification and redundant chassis grounding.
3.3 Power Interfaces The RAD750 3U CompactPCI board operates on a single 3.3V supply connected through the main connector (J1). At least one 0.1 µF ceramic capacitor suitable for high speed decoupling is provided for each voltage (+5, +3.3V, +12, -12, V(I/O)) close to the connector to decouple every 10 power pins.
40 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
10 µF tantalum capacitors are located close to the connector and 3.3V pins. The RAD750 3U CompactPCI board does not utilize power from the +5V, -12V or +12V inputs on the main connector (J1). Other than required pull-ups, the RAD750 3U CompactPCI board does not utilize the V(I/O) pins on the main connector (J2).
41 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Section 4 Electrical and Thermal Characteristics The tables in this section describe the AC and DC electrical specifications and thermal characteristics for the RAD750 3U CompactPCI board.
4.1 DC Electrical Conditions This section describes the DC electrical operating conditions for the RAD750 3U CompactPCI board.
4.1.1 Absolute Maximum Ratings The RAD750 3U CompactPCI board is designed to survive up to the ratings listed in Table 4. Stresses above the absolute maximum rating may cause permanent damage to the RAD750 3U CompactPCI board. Extended operation at the maximum levels may degrade performance and affect reliability. See Section 6 for the full set of environmental requirements.
Table 4. Absolute Maximum Ratings
Applied Condition Symbol Minimum Maximum Unit Value Value
RAD750 3U CompactPCI board Supply Voltage Vcc 3.0 3.6 V
Input Voltage Vin -0.5 Vcc +0.5 V o Operating Temperature Range Top - 55 + 70 C o Ambient Storage Temperature Range Tstg - 55 + 150 C Electrostatic Discharge Sensitivity as defined in Class 1 MIL-STD-883, Method 3015
4.1.2 Recommended Operating Conditions The RAD750 3U CompactPCI board shall be designed to operate at full performance under the recommended operating conditions shown in Table 5.
Table 5. Recommended Operating Conditions
Applied Condition Symbol Minimum Maximum Unit Value Value
RAD750 3U CompactPCI board Supply Voltage Vcc + 3.135 + 3.465 V Supply Voltage Reference GND + 0 + 0 V
Input Voltage Vin + 0 + 3.3 V o Card Mounting Rails Temperature TMR - 55 + 70 C
4.1.3 Card Thermal Characteristics The RAD750 3U CompactPCI board shall provide thermal resistance characteristics within the limits shown in Table 6. Due to the non-linearity of these measurements, this table may be expanded when the actual hardware has been designed and built. The RAD750 running at full speed is expected to be the hottest component.
42 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Table 6. Card Thermal Characteristics
Characteristic Symbol Maximum Unit Value o RAD750 3U CompactPCI board Board Thermal θRP TBA C/W Resistance (Rail to Printed Wiring Board) o RAD750 3U CompactPCI board Component θJP TBA C/W Thermal Resistance (Die Junction to Printed Wiring Board)
4.1.4 DC Electrical Specifications The RAD750 3U CompactPCI board shall meet the electrical characteristics shown in Table 7.
o Table 7. DC Electrical Characteristics with Vcc = 3.3r 5% VDC, GND = 0 VDC, -55 d Tj < 125 C Characteristic Symbol Minimum Maximum Unit Value Value
High Level Input Voltage VIH + 2.3 (TBR) TBA V
Low Level Input Voltage VIL TBA + 0.5 (TBR) V
High Level Output Voltage, IOH = - 4 mA VOH + 2.4 (TBR) TBA V
Low Level Output Voltage, IOL = 4 mA VOL TBA + 0.4 (TBR) V
PCI Signal High Level Input Voltage PVIH + 1.65 (TBR) TBA V
PCI Signal Low Level Input Voltage PVIL TBA + 1.0 (TBR) V
PCI Signal High Level Output Voltage PVOH + 3.0 (TBR) TBA V
PCI Signal Low Level Output Voltage PVOL TBA + 0.3 (TBR) V
Input Leakage Current, VCC = 3.465 V, 0 ≤ VIN ≤ IIH, IIL - 20 (TBR) + 20 (TBR) µA 3.465 V
+5V Tolerant Input Leakage Current, VCC = 3.465 IIH, IIL - 20 (TBR) + 20 (TBR) µA V, VIN ≤ 5.25 V
Cold Spare Input Leakage Current, VCC = 3.465 V, IIH, IIL - 20 (TBR) + 20 (TBR) µA VIN ≤ 3.465 V
PCI Signal Input Leakage Current, VCC = 3.465 V, PIIH, PIIL - 20 (TBR) + 20 (TBR) µA 0 ≤ VIN ≤ 3.465 V
PCI Signal +5V Tolerant Input Leakage Current, PIIH, PIIL - 20 (TBR) + 20 (TBR) µA VCC = 3.465 V, VIN ≤ 5.25 V
Capacitance In, VIN = 0 V CIN 10 (TBR) pF
Capacitance Out, VIN = 0 V COUT 10 (TBR) pF
43 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
4.1.5 Power Consumption The RAD750 3U CompactPCI board shall operate below the maximum power consumption requirements of Table 8. Maximum power includes worst case temperature, voltage, and post-radiation exposure. The RAD750 3U CompactPCI board shall operate at or below the typical power numbers shown in Table 9 while executing the SPECint_base95 or SPECfp_base95 benchmarks.
Table 8. RAD750 3U CompactPCI board Maximum Power Consumption with Vcc = 3.3r 5% VDC, o GND = 0 VDC, -55 d Tj < 125 C Mode 132 MHz 33 MHz 16.5 MHz 8.25 MHz 4.125 MHz
Full-On (W) TBA TBA TBA TBA TBA
Doze (W) TBA TBA TBA TBA TBA
Nap (W) TBA TBA TBA TBA TBA
Sleep (W) TBA TBA TBA TBA TBA
Reset Held Active (W) TBA TBA TBA TBA TBA
Table 9. RAD750 3U CompactPCI board Typical Power Consumption with Vcc = 3.3 VDC, GND = 0 o VDC, TMR = 25 C Mode 132 MHz 33 MHz 16.5 MHz 8.25 MHz 4.125 MHz Full-On (W) 11.5 (TBR) 7.5 (TBR) 7.0 (TBR) 6.5 (TBR) 6.0 (TBR)
Doze (W) TBA TBA TBA TBA TBA
Nap (W) TBA TBA TBA TBA TBA
Sleep (W) TBA TBA TBA TBA TBA
Reset Held Active (W) TBA TBA TBA TBA TBA
4.2 AC Electrical Characteristics This section provides the AC electrical characteristics for the RAD750 3U CompactPCI board. As shown in Figure 3, the RAD750 3U CompactPCI board has seven major timing regions: PCI Clocked logic (Backpanel and Power PCI), SYS Clocked logic (RAD750 and Power PCI), SDRAM memory, RTC clocked logic (UART and Timers), RAD750 JTAG logic, Power PCI JTAG logic and Backpanel JTAG logic (this may include Power PCI JTAG logic). Values marked by ? are placeholders for the real values once they are obtained from the Power PCI design.
4.2.1 PCI Clocked Logic AC Specifications This section covers signals in the PCI Clock domain of the RAD750 3U CompactPCI board. The number column indicates the line in the referenced timing diagram. See Figure 9 for the PCI clocked timing diagrams. The RAD750 3U CompactPCI board is designed to accept a PCI_CLK signal when PCI_SYSEN# is inactive as defined in Table 10.
44 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
o Table 10. PCI Input Clock AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value PCI_CLK frequency 0 33 MHz 1 PCI_CLK cycle time 30 ns
2 PCI_CLK rise time measured from 0.3 to 3.0 V TBA ns
3 PCI_CLK fall time measured from 3.0 to 0.3 V TBA ns
4 PCI_CLK duty cycle measured at 1.4 V 40 (TBR) 60 (TBR) % PCI_CLK jitter TBA ps
The RAD750 3U CompactPCI board is designed to generate any combination of the eight PCI_CLK(0:7) signals when PCI_SYSEN# is active as defined in Table 11. When PCI_SYSEN# is active, the RAD750 3U CompactPCI board uses PCI_CLK(7) to clock internal PCI logic.
o Table 11. PCI Output Clock AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value PCI_CLK frequency 0 33 MHz 1 PCI_CLK cycle time 30 ns
2 PCI_CLK rise time measured from 0.3 to 3.0 V TBA ns with a load of CL = 50 pF (TBR) 3 PCI_CLK fall time measured from 3.0 to 0.3 V TBA ns with a load of CL = 50 pF (TBR) 4 PCI_CLK duty cycle measured at 1.4 V with a 40 (TBR) 60 (TBR) % load of CL = 50 pF (TBR) PCI_CLK jitter TBA ps
The RAD750 3U CompactPCI board meets the input timing specifications given in Table 12. These specifications are for operation of the RAD750 3U CompactPCI board PCI Logic at 33 MHz using either PCI_CLK or PCI_CLK(7) depending on the state of PCI_SYSEN#.
o Table 12. PCI Input AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value 5a PCI bussed signals valid to PCI_CLK (input TBA ns setup) measured from 1.65 V (Vcc / 2) on the rising edge of PCI_CLK to VOH = 3.0 V or VOL = 0.3 V
45 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Number Characteristic Minimum Maximum Unit Value Value 5b PCI point to point signals valid to PCI_CLK TBA ns (input setup) measured from 1.65 V (Vcc / 2) on the rising edge of PCI_CLK to VOH = 3.0 V or VOL = 0.3 V 6a PCI_CLK to input signals valid (input hold) TBA ns
PCI_RST# pulse width TBA
5c Mode select inputs (GNT#) valid to PCI_RST# TBA ns
6b PCI_RST# to mode select input (GNT#) valid TBA ns (input hold) The RAD750 3U CompactPCI board meets the output timing specifications given in Table 13. These specifications are for operation of the RAD750 3U CompactPCI board PCI Logic at 33 MHz using either PCI_CLK or PCI_CLK(7) depending on the state of PCI_SYSEN#.
o Table 13. PCI Output AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value 7 PCI_CLK rising edge to output driven (output TBA TBA ns enable time) 8a PCI_CLK to non PCI signaling output valid TBA TBA ns measured at the pin from 1.4V on the rising edge of PCI_CLK to the TTL level (0.8 V or 2.0 V) of the signal in question with a load of CL = 50 pF 8b PCI_CLK to PCI signaling output valid TBA TBA ns measured at the pin from 1.65 V (Vcc / 2) on the rising edge of PCI_CLK to VOH = 3.0 V or VOL = 0.3 V of the signal in question with a load of CL = 50 pF 9 PCI_CLK rising edge to output valid (output TBA TBA ns hold) with a load of CL = 50 pF
Figure 9. PCI Clocked Logic Timing Diagrams TBA
4.2.2 SYS Clocked Logic AC Specifications This section deals with signals that are referenced to the SYS_CLK on the RAD750 3U CompactPCI board. This signal is used to drive SYS clocked logic on the RAD750 and Power PCI. No RAD750 signals in this clocking region are brought to RAD750 3U CompactPCI board outputs, so these are not included in this specification. This clocking region may be asynchronous to the PCI clocked region, depending on the source of the PCI Clock. SYS_CLK, which is only brought to a test point on the RAD750 3U CompactPCI board, is generated by the Power PCI during normal operation from the on-card oscillator. The EXT_OSC input to the RAD750 3U CompactPCI board is included for test and
46 Document Number: 234A524 RAD750 CompactPCI Hardware Specification characterization only and is also not specified in this section. The only external SYS clocked signals covered in this section are the MISC_PIDs and various mode inputs. See Figure 10 for the SYS Clocked timing diagrams. The RAD750 3U CompactPCI board meets the input timing specifications given in Table 14. These specifications are for operation of the RAD750 3U CompactPCI board SYS Logic at 33 MHz using an internally delayed and wrapped SYS_CLK.
o Table 14. SYS Clocked Inputs AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value 10a MISC_PID signals valid to SYS_CLK (input TBA ns setup) measured from 1.4 V on the rising edge of SYS_CLK to VOH = 2.4 V or VOL = 0.4 V 11a SYS_CLK to input signals valid (input hold) TBA ns
MISC_POR_L pulse width TBA
10b Mode select inputs valid to MISC_POR_L TBA ns
11b MISC_POR_L to mode select input valid (input TBA ns hold) The RAD750 3U CompactPCI board meets the output timing specifications given in Table 15. These specifications are for operation of the RAD750 3U CompactPCI board SYS clocked logic at 33 MHz using an internally delayed and wrapped SYS_CLK.
o Table 15. SYS Clocked Outputs AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value 7 SYS_CLK rising edge to output driven (output TBA ns enable time) 8 SYS_CLK to output valid measured at the pin TBA ns from 1.4V on the rising edge of SYS_CLK to the TTL level (0.8 V or 2.0 V) of the signal in question 9 SYS_CLK rising edge to output valid (output TBA ns hold) with a load of CL = 50 pF
Figure 10. SYS Clocked Logic Timing Diagrams TBA
4.2.3 SDRAM Clocked Memory AC Specifications The SDRAM clocked region is controlled by an internally delayed and wrapped version of the SYS_CLK developed in the Power PCI. Parts of the memory interface and the memory devices in the RAD750 3U CompactPCI board are included. The SDRAM interface is entirely internal to the RAD750 3U
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CompactPCI board and none of the signals involved are brought to external I/O. Thus this interface is not specified in this document.
4.2.4 RTC Clocked Logic AC Specifications This section deals with signals that are referenced to the RTC_CLK on the RAD750 3U CompactPCI board. This signal is used to drive RTC clocked logic (timers and the UART) on the Power PCI. This clocking region may be asynchronous to the PCI clocked region, depending on the source of the PCI Clock. RTC_CLK, which is only brought to a test point on the RAD750 3U CompactPCI board, is generated by the Power PCI during normal operation from the on-card oscillator. The EXT_OSC input to the RAD750 3U CompactPCI board is included for test and characterization only and is also not specified in this section. Timers utilizing this region are fed back through the SYS clocked region before reaching an external I/O. The only external RTC clocked signals covered in this section are the UART signals. The RAD750 3U CompactPCI board meets the input timing specifications given in Table 16. These specifications are for operation of the RAD750 3U CompactPCI board RTC Logic at 8.25 MHz using an internally divided and wrapped RTC_CLK. See Figure 11 for the RTC timing diagrams.
o Table 16. RTC Clocked Inputs AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value 10a UART signals valid to RTC_CLK (input setup) TBA ns measured from 1.4 V on the rising edge of RTC_CLK to VOH = 2.4 V or VOL = 0.4 V 11a RTC_CLK to input signals valid (input hold) TBA ns
The RAD750 3U CompactPCI board meets the output timing specifications given in Table 17. These specifications are for operation of the RAD750 3U CompactPCI board RTC clocked logic at 8.25 MHz using an internally divided and wrapped RTC_CLK.
o Table 17. RTC Clocked Outputs AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value 7 RTC_CLK rising edge to output driven (output TBA ns enable time) 8 RTC_CLK to output valid measured at the pin TBA ns from 1.4V on the rising edge of RTC_CLK to the TTL level (0.8 V or 2.0 V) of the signal in question 9 RTC_CLK rising edge to output valid (output TBA ns hold) with a load of CL = 50 pF
Figure 11. RTC Clocked Logic Timing Diagrams TBA
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4.2.5 RAD750 JTAG Clocked Logic AC Specifications The RAD750 JTAG port may be accessed either internally by the Power PCI or externally by a hardware debug probe. When the internal connection is active, there should be no activity on the external probe (except perhaps a passive monitoring). Thus this section only deals with the external probe connection to the RAD750 JTAG interface. The RAD750 3U CompactPCI board meets the RAD750 JTAG AC timing specifications given in Table 18. It is assumed that JTM_TCLK is independent of all RAD750 3U CompactPCI board clocking regions. See Figure 12 for the JTAG timing diagrams.
o Table 18. RAD750 JTAG AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value JTM_TCLK frequency of operation 0 25 MHz 1 JTM_TCLK cycle time 40 ns
2 JTM_TCLK clock pulse width measured at 1.4V TBA ns
3 JTM_TCLK rise and fall times TBA TBA ns 4 JTM_TRST_L setup time to JTM_TCLK rising TBA ns edge (test purposes only) 5 JTM_TRST_L assert time TBA ns
6 Boundary scan non-test input data setup time TBA ns
7 Boundary scan non-test input data hold time TBA ns
8 JTM_TCLK to non-test output data valid TBA TBA ns 9 JTM_TCLK to output high impedance TBA TBA ns 10 JTM_TMS, JTM_TDI data setup time TBA ns
11 JTM_TMS, JTM_TDI data hold time TBA ns
12 JTM_TCLK to JTM_TDO data valid TBA TBA ns 13 JTM_TCLK to JTM_TDO high impedance TBA TBA ns
4.2.6 Power PCI JTAG Clocked Logic AC Specifications The Power PCI JTAG port is one of two access points to the Power PCI JTAG core. This port is dedicated to a connection to an external JTAG probe. When the external probe is active (as indicated by the PROBE_PRESENT_L signal, the Power PCI will always connect its JTAG core to this port. Thus this port behaves as a standalone slave port to the external world. The RAD750 3U CompactPCI board meets the Power PCI JTAG AC timing specifications given in Table 19. It is assumed that JTS_TCLK is independent of all RAD750 3U CompactPCI board clocking regions. See Figure 12 for the JTAG timing diagrams.
49 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
o Table 19. Power PCI JTAG AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value JTS_TCLK frequency of operation 0 25 MHz 1 JTS_TCLK cycle time 40 ns
2 JTS_TCLK clock pulse width measured at 1.4V TBA ns
3 JTS_TCLK rise and fall times TBA TBA ns 4 JTS_TRST_L setup time to JTS_TCLK rising TBA ns edge (test purposes only) 5 JTS_TRST_L assert time TBA ns
6 Boundary scan non-test input data setup time TBA ns
7 Boundary scan non-test input data hold time TBA ns
8 JTS_TCLK to non-test output data valid TBA TBA ns 9 JTS_TCLK to output high impedance TBA TBA ns 10 JTS_TMS, JTS_TDI data setup time TBA ns
11 JTS_TMS, JTS_TDI data hold time TBA ns
12 JTS_TCLK to JTS_TDO data valid TBA TBA ns 13 JTS_TCLK to JTS_TDO high impedance TBA TBA ns
4.2.7 Backpanel JTAG Clocked Logic AC Specifications The Backpanel JTAG port is the second of two access points to the Power PCI JTAG core. This port is dedicated to a connection to the JTAG interface through the CompactPCI backpanel. This may either be controlled by the RAD750 3U CompactPCI board or a slave to some other CompactPCI card depending on the state of JTMSMASTER_ENABLE_IN and whether the Power PCI probe is present. The RAD750 3U CompactPCI board meets the Backpanel JTAG AC timing specifications given in Table 20 whenever it is configured as a slave port only and no Power PCI probe is present. It is assumed that JTMS_TCLK is independent of all RAD750 3U CompactPCI board clocking regions. See Figure 12 for the JTAG timing diagrams.
o Table 20. Backpanel JTAG Slave AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value JTMS_TCLK frequency of operation 0 25 MHz 1 JTMS_TCLK cycle time 40 Ns
2 JTMS_TCLK clock pulse width measured at TBA Ns 1.4V 3 JTMS_TCLK rise and fall times TBA TBA Ns
50 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Number Characteristic Minimum Maximum Unit Value Value 4 JTMS_TRST_L setup time to JTMS_TCLK TBA Ns rising edge (test purposes only) 5 JTMS_TRST_L assert time TBA Ns
6 Boundary scan non-test input data setup time TBA Ns
7 Boundary scan non-test input data hold time TBA Ns
8 JTMS_TCLK to non-test output data valid TBA TBA ns 9 JTMS_TCLK to output high impedance TBA TBA ns 10 JTMS_TMS, JTMS_TDI data setup time TBA ns
11 JTMS_TMS, JTMS_TDI data hold time TBA ns
12 JTMS_TCLK to JTMS_TDO data valid TBA TBA ns 13 JTMS_TCLK to JTMS_TDO high impedance TBA TBA ns The RAD750 3U CompactPCI board meetS the Backpanel JTAG AC timing specifications given in Table 21 whenever it is configured as a master port. These specifications are for operation at 16.5 MHz using an internally wrapped, delayed and divided JTB_TCLK.
o Table 21. Backpanel JTAG Master AC Timing Specifications with Vcc=3.3r5% V DC, 0 d TJ < 125 C Number Characteristic Minimum Maximum Unit Value Value 5 JTMS_TRST_L assert time TBA ns
6 Boundary scan non-test input data setup time TBA ns
7 Boundary scan non-test input data hold time TBA ns
8 JTMS_TCLK to non-test output data valid TBA TBA ns 9 JTMS_TCLK to output high impedance TBA TBA ns 10 JTMS_TDI data setup time TBA ns
11 JTMS_TDI data hold time TBA ns
12 JTMS_TCLK to JTMS_TDO, JTMS_TMS data TBA TBA ns valid 13 JTMS_TCLK to JTMS_TDO, JTMS_TMS high TBA TBA ns impedance
Figure 12. JTAG Clocked Logic Timing Diagrams TBA
51 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Section 5 Mechanical Interface
5.1 RAD750 3U CompactPCI board Module Assembly The RAD750 3U CompactPCI board mass is estimated to be less than 0.53 Kg. The design and fabrication of the RAD750 3U CompactPCI board uses accepted space industry standard requirements and practices. It is constructed using Polyimide material and has PCB trace characteristic impedance of 65 ± 10 ohms. Both the EM and FM versions of the RAD750 3U CompactPCI board are conformal coated.
5.1.1 Module Parameters Signal length for 32-bit PCI signals on J1 is designed to be less than or equal to 38.1 mm. This length is measured from the connector pin through the stub or series termination resistor to the Power PCI ASIC pin. The RAD750 3U CompactPCI board provides a front panel compliant with IEEE 1101.10. The Front Panel I/O plate is assumed to be connected to chassis ground and isolated from logic ground. The RAD750 3U CompactPCI board does not connect chassis ground through a low impedance path to logic ground used on the board. The RAD750 3U CompactPCI board provides a single ejector/injector handle using jack screws compliant with IEEE 1101.10 for insertion and removal.
5.1.2 Module Drawing The RAD750 3U CompactPCI board shall conform to the drawings in Figure 13 and Figure 14.
52 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
*Components and Associated Circuitry within this area Both Sides
*Components and Associated Circuitry within this area Both Sides
Figure 13. RAD750 3U CompactPCI board Module Views
53 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Max Allowable Component Height 6.0MM [0.236 IN]
Max Allowable Component Height 10.0MM [0.393 IN]
Figure 14. RAD750 3U CompactPCI board Module Views
5.2 Grounding Requirements
5.2.1 Structural Grounding Preparation of metal-to-metal surfaces on the RAD750 3U CompactPCI board for electrical bonding purposes is made in accordance with MIL-B-5087B, paragraph 3.1.4.
5.2.2 Circuit Grounding, General Generally, all RAD750 3U CompactPCI board electronic interface circuitry is referenced to the System Reference Plane with the lowest practicable impedance. All circuitry interconnecting integrated circuits, semiconductors, discrete devices, transformers, and other electronic components is provided with an electrical path to structure, at all times. This reference point is called the Circuit Common. The single point grounding method must be used for all Circuit Commons. The Circuit Common must have a low resistance, low inductance path to structure (the System Reference Plane). Comment: The maximum required ground path resistance ranges from milliohms for low level electronic circuits, to kilo-ohms for circuits with current-limiting resistance for fault conditions, to megohms for circuits only requiring electrostatic discharge paths. The single point grounding method requires that there be no more than one path from any circuit or group of circuits to structure but does not require the use of only one ground tree
5.2.3 ESD Grounding All metallic elements, including wires, unused conductors of cable, connectors, circuit board traces, spot shields, and other conductive elements greater than 3 cm2 in surface area or longer than 25 cm, shall have a conductive path to structure with a resistance <1E8 ohms when measured in air or <1E12 ohms when measured in vacuum. Every effort will be made to also provide ESD grounding to all surface areas greater than 0.3 cm2 in surface area.
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5.3 RAD750 3U CompactPCI board Electrical Connectors The J1 and J2 connectors shall load a shield at row F on the board. This shield covers the top of the IEC-1076 connector and help to provide a low impedance return path for ground between the board and the CompactPCI backpanel. The lower shield option that is provided for in IEC-1076 is not required and shall not be loaded if it protrudes into the interboard separation plane.
5.3.1 J1 Connector The J1 connector is the primary bus interface for the RAD750 3U CompactPCI board to the assembly it resides in. The main PCI and backpanel JTAG signals are mostly routed on this connector. The RAD750 3U CompactPCI board shall use AMP 352068-1 or the equivalent for the J1 connector. Representative drawings from AMP are shown in Figure 15 and Figure 16.
55 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
5.3.1.1 J1 Connector Diagrams
Figure 15. J1 Connector Side View
Figure 16. J1 Connector Bottom View
5.3.1.2 J1 Pin Assignment
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The following color coding is used in Table 22 and Table 23: Black - Power and Ground Assignments Red - Base CompactPCI 32 bit System Mappings Blue - Mapping to 64-bit Bussed System Signals or Connections to PCI Signals Green - Mapping onto Non-Bussed Reserved Signals Light Green - Mapping onto Bussed Reserved System Signals Purple - Unused Signals - RSV (non-bussed reserved), BRSV (bussed reserved), B64 (bussed 64-bit)
Table 22. CompactPCI J1 Connector Signals PIN A B C D E
25 5V REQ64# ENUM# - PID20 3.3V 5V
24 AD1 5V V(I/O) AD0 ACK64#
23 3.3V AD4 AD3 5V AD2
22 AD7 GND 3.3V AD6 AD5
21 3.3V AD9 AD8 GND C/BE0#
20 AD12 GND V(I/O) AD11 AD10
19 3.3V AD15 AD14 GND AD13
18 SERR# GND 3.3V PAR C/BE1#
17 3.3V SDONE SBO# GND PERR#
16 DEVSEL# GND V(I/O) STOP# LOCK#
15 3.3V FRAME# IRDY# GND TRDY#
12-14 KEY AREA
11 AD18 AD17 AD16 GND C/BE2#
10 AD21 GND 3.3V AD20 AD19
9 C/BE3# IDSEL AD23 GND AD22
8 AD26 GND V(I/O) AD25 AD24
7 AD30 AD29 AD28 GND AD27
6 REQ# GND 3.3V CLK AD31
5 BRSV RDY_PARITY RST# GND GNT#
4 BRSV GND V(I/O) INTP-PID14 INTS-PID15
3 INTA# - PID16 - INTB# - PID17 INTC# - PID28 5V INTD# - PID29 UART_OUT2
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PIN A B C D E
2 TCK 5V TMS TDO TDI
1 5V -12V TRST_L +12V 5V
5.3.1.3 Keying The RAD750 3U CompactPCI board operates in any CompactPCI system or peripheral slot in a 3.3V backpanel. The RAD750 3U CompactPCI board shall be keyed as a 3.3V signaling I/O board. The RAD750 3U CompactPCI board shall not be keyed for either system or peripheral slots.
5.3.2 J2 Connector The J2 connector provides the additional PCI signals for the resource controller and all user-defined pins to the backpanel. The RAD750 3U CompactPCI board shall use AMP 352152-1 or the equivalent for the J2 connector. Representative drawings from AMP are shown in Figure 17 and Figure 18.
58 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
5.3.2.1 J2 Connector Diagrams
Figure 17. J2 Connector Side View
Figure 18. J2 Connector Bottom View
59 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
5.3.2.2 J2 Pin Assignments
Table 23. CompactPCI J2 Connector Pinouts PIN A B C D E
22 GA4 GA3 GA2 GA1 GA0
21 CLK6 GND CLK7 GAP JTMS_MSTR_E N
20 CLK5 GND UART_RTS_L GND UART_CTS_L
19 GND GND RSV UART_RX_DAT UART_TX_DAT
18 BRSV I2C_1 I2C_0 GND NMI
17 BRSV GND PRST# REQ6# GNT6#
16 ROM_ON_PCI CHAS_GND_0 DEG# - PID18 GND CHAS_GND_1
15 BRSV GND FAL# - PID19 REQ5# GNT5#
14 B64 B64 PID31 GND PID30
13 B64 GND V(I/O) PID08 PID00
12 UART_OUT1 B64 PID25 GND PID01
11 B64 GND V(I/O) PID09 PID02
10 B64 B64 PID26 GND PID03
9 B64 GND V(I/O) PID10 PID04
8 B64 PID21 PID27 GND PID05
7 B64 GND V(I/O) PID11 PID06
6 B64 PID22 PID24 GND PID07
5 B64 GND V(I/O) B64 PID12
4 V(I/O) POR_N PID23 GND PID13
3 CLK4 GND GNT3 REQ4# GNT4#
2 CLK2 CLK3 SYSEN# GNT2# REQ3#
1 CLK1 GND REQ1# GNT1# REQ2#
5.3.3 J7 Front Panel Connector The J7 connector provides all external UART, debug and test signals that are brought out to the front panel except for the second set of UART interface pins on the backpanel. J7 shall be wired as shown in Table 24.
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5.3.3.1 J7 Connector Diagrams The J7 connector shall use a Nanonics Dualobe two row 25 pin connector with pin through hole mounting or the equivalent. Pad layout is shown in Figure 20 and portions of a representative Nanonics connector drawing are shown in Figure 19.
Figure 19. Nanonics Dualobe Connector with 25 Contacts and B=.431, C=.500 and L=.300
Figure 20. 25 Pin Nanonics Dualobe Connector Pad Layout
5.3.3.2 J7 Pin Assignments
Table 24. Front Panel Connector J7 Pin Assignments
PIN Signal PIN Signal 1 JTM_TDO 2 JTM_TRST_L
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PIN Signal PIN Signal 3 JTM_TDI 4 JTM_POWER 5 JTM_TCLK 6 JTM_SRESET_L 7 JTM_TMS 8 JTM_RESET_L 9 CPU_CKSTP_L 10 JT7_MSTR_EN_IN 11 GND 12 GND 13 JTS_TDI 14 UART_RX_DATA 15 JTS_TDO 16 UART_TX_DATA 17 JTS_TMS 18 UART_RTS_L 19 JTS_TCLK 20 UART_CTS_L 21 JTS_PROBE_PR_L 22 JTS_TRST_L 23 GND 24 X_SYS_OSC_SEL_L 25 X_SYS_OSC
5.3.4 Mating Force The RAD750 3U CompactPCI board requires no more than TBA pounds of force to be installed in a CompactPCI chassis and no more than TBA pounds of force to be extracted from a CompactPCI chassis.
5.3.5 Module Cooling The RAD750 3U CompactPCI board uses industry standard, multiple segment, wedgelock retainers and stiffeners for conduction cooling. The RAD750 3U CompactPCI board may be operated without the wedgelocks and stiffeners and plugged into any commercial CompactPCI rack.
5.4 Name Plate and Product Markings Each RAD750 3U CompactPCI board EM is uniquely marked sequentially beginning with E001. Each RAD750 3U CompactPCI board FM is uniquely marked sequentially beginning with F001.
5.5 Lifetime The RAD750 3U CompactPCI board is designed for a lifetime of up to two years after pre-launch integration and test and 14 years of powered mission operation in the worst case environment. During this lifetime, the RAD750 3U CompactPCI board is capable of operating within specification.
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Section 6 Environmental Conditions This section provides the initial environmental design specifications for the RAD750 3U CompactPCI board. Further analysis must be performed to verify proper operation for conditions outside the ranges specified in this section.
6.1 Temperature The RAD750 3U CompactPCI board shall operate within specification in a vacuum over a cold plate temperature range of -55 oC to +70 oC as measured at the rails on the card.
6.2 Launch Atmospheric Environment The launch environments are those the hardware encounters during launch and ascent phases.
6.2.1 Launch Pressure Profile The RAD750 3U CompactPCI board, while integrated in a spacecraft during launch, is designed to withstand a maximum atmospheric pressure decay rate of 4 kPa/sec (30 Torr/sec).
6.2.2 Explosive Atmosphere The RAD750 3U CompactPCI board is designed to not ignite an explosive atmosphere within the pressure and temperature ranges and the minimum auto-ignition temperature specified in Table 25.
Table 25. Range of Explosive Atmosphere Physical Characteristics
Explosive Atmosphere Physical Range Characteristics Pressure 1.33x101 kPa (100 torr) to 1.06x102 kPa (800 torr)
Temperature 5 to 45°C Minimum Auto-ignition Temperature 350°C Chemical Constituents MMH, Hydrogen (reference fuel) and air (oxidizer) combined in any potentially explosive ratio.
6.2.3 Vacuum The RAD750 3U CompactPCI board is designed for pressure to decrease from 100 kPa (760 torr) on Earth to 1.3x10-15 kPa (10-14 torr) in space.
6.3 Ground Handling Flight hardware will be handled, transported, and stored in handling and shipping containers designed and qualified in accordance with JPL 8208, section 3.18.
63 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
6.3.1 Particulate Contamination All RAD750 3U CompactPCI board external surfaces shall allow cleaning with isopropyl and/or ethyl alcohol without damage.
6.3.2 Temperature and Pressure Environment The RAD750 3U CompactPCI board ground-handling temperature and pressure environment shall be restricted between 5 oC to 45 oC and 68.4 kPa (520 Torr) to 100 kPa (760 Torr).
6.3.3 Humidity Environment The RAD750 3U CompactPCI board ground-handling relative humidity environment shall be restricted between 40 and 70%. While in a shipping container, the RAD750 3U CompactPCI board must be wrapped in a non-ESD-generating vapor barrier with redundant maximum humidity indicators.
6.4 Launch Dynamic Environments The following are the launch dynamics requirements for the RAD750 3U CompactPCI board. The specifications are design and test levels to be input at the mounting location of the hardware. The RAD750 3U CompactPCI board will typically be mounted on Integrated Avionics Structure (IAS) panels, and the input to the structure and electronic CompactPCI boards is based on the predicted response of the panels at the location of the electronic hardware.
6.4.1 Random Vibration The RAD750 3U CompactPCI board is designed to meet the random vibration requirements shown in Table 26 These acceleration spectra shall be applied in each of the three orthogonal axes at the mounting points of the associated hardware. Force Limiting as specified in Table 27 may be used to notch the acceleration input spectrum.
Table 26. RAD750 3U CompactPCI board Random Vibration Requirements
Frequency (Hz) Design/Qual, PF Test FA Test 20-50 +9dB/Oct. +9dB/Oct 50-250 0.20 g2/Hz 0.10 g2/Hz 250-350 -6dB/Oct. -6dB/Oct. 350-1000 0.10 g2/Hz .05g2/Hz 1000-2000 -12dB/Oct. –12dB/Oct.XXgrms
Overall 12.3 grms 8.7 grms
Duration: Design/Qual 3 minutes in each of 3 orthogonal axes PF, FA 1 minute in each of 3 orthogonal axes
Table 27. RAD750 3U CompactPCI board Random Vibration Force Spectrum
Frequency (Hz) Force Spectral Level
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Frequency (Hz) Force Spectral Level Qual and PF FA 20-250 5 F lb2/Hz 5 F lb2/Hz 250-2000 -9 dB/octave -9 dB/octave The factor, F, is the product of the acceleration spectrum times the square of the total mass of the assembly in pounds. 6.4.2 Acoustic Noise The RAD750 3U CompactPCI board is designed to meet the acoustic noise requirements shown in the Table 28. Test qualification is not required for the acoustic environment.
Table 28. RAD750 3U CompactPCI board Acoustic Noise Design Requirements
1/3 Oct. Band FA SPL (dB) Qual, PF SPL (dB) Test Tolerances * Ctr. Freq. (Hz) ref. 20µ Pascal ref. 20µ Pascal (dB)
31.5 127.5 130.5 +5, -3 40. 128.5 131.5 +5, -3 50. 129. 132. +5, -3 63. 130. 133. ± 3 80. 130.5 133.5 ± 3 100. 131 134. ± 3 125. 131. 134. ± 3 160. 131.5 134. ± 3 200. 131. 134. ± 3 250. 131. 134. ± 3 315. 130.5 133.5 ± 3 400. 130. 133. ±3 500. 129. 132. ± 3 630. 128. 131. ± 3 800. 126.5 129.5 ± 3 1000. 1245 127.5 ± 3 1250. 123. 126. ± 3 1600. 121. 124. ± 3 2000. 119.5 122.5 ± 3 2500. 118. 121. ± 3 3150. 117. 120. ± 3 4000. 115.5 118.5 ± 3 5000. 114.5 117.5 ± 3 6300. 114. 117. ± 3 8000. 113.5. 116.5. ± 3 10,000. 113.5 116.5 ± 3 ± 3 ± 3 Overall 141.9 144.9 ± 1 Design Duration: 3 minutes 6.4.3 Pyroshock The RAD750 3U CompactPCI board shall meet the pyroshock design and test requirement given in Figure 21. Three shock pulses, with the SRS level specified below, shall be applied for design and
65 Document Number: 234A524 RAD750 CompactPCI Hardware Specification qualification at the hardware mounting interface in each of the three orthogonal axes. Flight acceptance pyroshock tests are not required. The shock waveform shall satisfy both of the following criterion: A) The pulse shall be oscillatory in nature, and B) The pulse shall decay to less than 10% of its peak value within 50 milliseconds.
10000
1000 RS Acceleration Response (g) Response RS Acceleration
S (Q=10) 100
JPF 07/99 10 10 100 1000 10000 Natural Frequency (Hz)
Figure 21. RAD750 3U CompactPCI board Pyroshock Design and Test Requirements
6.5 THERMAL
6.5.1 LAUNCH THERMAL ENVIRONMENT During ascent, the spacecraft and assemblies will be designed to maintain allowable assembly flight temperatures (including analytic uncertainties).
6.5.2 ASSEMBLY TEMPERATURES The RAD750 3U CompactPCI board is designed to operate within specification over the temperature range of -55 to +70°C measured at the mounting rails, and to survive unpowered over the same range. During test, a ramp rate not to exceed 5oC per minute will be used. Dwell times at the high and low temperatures will be a minimum amount of time to reach thermal stability and run functional tests. TEMPERATURE (°C) ITEM Design/QUAL/PF OP Non-OP min max min max
66 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
AVIONICS RAD750 3U CompactPCI board -55 70 -55 70 Assembly
DEFINITIONS. Terms used herein for thermal design are defined as follows:
Design Temperature Limits: Temperature limits to which all assemblies shall be designed to meet all functional and performance specifications.
Operating Allowable Flight Temperatures: The temperature ranges of assemblies when powered-on in a worst case operational mode (hot or cold) that will be maintained during all expected mission environments.
Non-Operating Allowable Flight Temperatures: The temperature ranges of assemblies when the powered-off in a worst case non-operational mode (hot or cold).
6.6 Electromagnetic Compatibility The RAD750 3U CompactPCI board is designed to be compatible with the requirements presented in this section. LFE/LFH testing will be performed on an RAD750 3U CompactPCI board assembly. Remaining EMC testing must be performed at a higher assembly level.
6.6.1 Electrostatic Discharge Requirements All metallic elements used in association with the RAD750 3U CompactPCI board assembly (e.g. component cans or lids, wires, unused conductors, connectors, and circuit board traces) shall have a conductive path to RAD750 3U CompactPCI board chassis ground with a resistance less than 10E8 ohms when measured in air and less than 10E12 ohms when measured in vacuum. Confirmation of meeting this requirement may be made through test or analysis. Analysis is achieved in accordance with design rules as described in NASA-HDBK-4002 (Internal Charging Effects Avoidance, Preliminary soon to be published) and NASA-HDBK-2361 (Surface Charging Avoidance).
6.6.2 Magnetic Field Constraints The RAD750 3U CompactPCI board shall operate within a magnetic field requirement of 1nT at 1 meter. This is due to the fact that the Solar Probe mission will be flying a magnetometer.
6.6.3 Electromagnetic Compatibility (EMC) The RAD750 3U CompactPCI board is designed to meet the EMC/EMI requirements that follow, when installed in a suitable next higher assembly.
6.6.3.1 Emissions Limits
6.6.3.1.1 Conducted Emissions, Power Line Ripple. The RAD750 3U CompactPCI board, when mounted in a CompactPCI assembly, shall not produce noise on the Spacecraft DC power bus in excess of the levels depicted in Figure 22 below.
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150
100 120 dBuA, 30-2000 Hz
dBuA 50 50 dBuA, 2-50 MHz 0 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
Frequency
Figure 22. Power Bus Ripple Conducted Emissions
6.6.3.1.2 Conducted Emissions, Power Line Transients. The RAD750 3U CompactPCI board, when mounted in a CompactPCI assembly, shall not produce transient voltage spikes on the spacecraft DC-power bus in excess of the limits specified in Figure 23. Power Line Transients
100 10 +/- 14 Volts +/- 1 Volts 1 0.1 1 us 10 us 100us 1 ms 10 ms 100 ms 1 s
0-Peak Transient Voltage Transient 0-Peak Time
Figure 23. Power Line Transients Conducted Emissions
6.6.3.1.3 Radiated Emissions, E-Fields. The RAD750 3U CompactPCI board, when mounted in a CompactPCI assembly, shall not radiate electric fields in excess of those described in Figure 24. Figure 24 includes the launch vehicle receiver frequency, and it should be noted that more frequencies might be added to accommodate science instruments.
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80 70 60 50 40 30 dBuV/m 20 7171059413 Hz to 7174731143 Hz 10 @ 10 dBuV/m 0 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09 1.0E+10 1.0E+11 Frequency (Hertz)
Figure 24. E-Field Radiated Emissions
6.6.3.1.4 Radiated Emissions, Low Frequency H Fields. The RAD750 3U CompactPCI board, when mounted in a CompactPCI assembly, shall have Low Frequency H-Field Emissions no greater than the levels indicated in Figure 25.
0 -10 -20 50 Hz -30 -40 150kHz
T/root Hertz @ 1 meter 1 @ Hertz T/root -50 p -60 dB 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz Frequency
Figure 25. Low Frequency H-field Radiated Emissions
6.6.3.1.5 Radiated Emissions, Low Frequency E Fields. The RAD750 3U CompactPCI board, when mounted in a CompactPCI assembly, shall have Low frequency E-Field Emissions no greater than the levels indicated in Figure 26.
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50 40 meter 30 50 Hz 20 10 150 kHz 0 -10 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz dBuV/m @ 1 Frequency
Figure 26. Low Frequency E-Field Radiated Emissions
6.6.3.2 Susceptibility Limits.
6.6.3.2.1 Radiated Susceptibility, E-Fields. The RAD750 3U CompactPCI board shall perform within specification when subjected to the electric (E)
100
10
Amplitude (Volts/meter 1 10000 100000 1000000 1E+07 1E+08 1E+09 1E+10 1E+11 fields defined in Frequency (Hz) Figure 27 and under the stated conditions. Above 1 MHz, the applied field must be modulated with a 1 kHz AM square wave, 100% depth as default unless otherwise specified. The applied field must be 10 V/m from 14 kHz to 18 GHz. Sources of these emissions are shown in Table 29. The larger field strengths and bandwidths are associated with the range radar and launch vehicle transmitter. Note that more frequencies may be added once additional spacecraft transmitter and radar requirements are known.
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100
10
Amplitude (Volts/meter 1 10000 100000 1000000 1E+07 1E+08 1E+09 1E+10 1E+11 Frequency (Hz)
Figure 27. E-Field Radiated Susceptibility
Table 29. Requirement Sources of Radiated Susceptibility Facility Emitter Name Center Frequency Theoretical Intensity (V/m) (MHz) SLC 41/37 FPS-66 1265 &1345 16 SLC 41/37 WSR-74C 5625 20 SLC 41/37 WSR-88D 2879 20 SLC 41/37 C-Band Range 5690 & 5800 40 Radar Delta IV/Atlas V Sec. Stage Trans 2241.5 10 Delta IV/ Atlas V Sec. C-band Trans 5765 80 Spacecraft 8425364198 8429080247 20 Transmitter Note: 1 MHz of Bandwidth should be used around the center frequencies to account for modulation. Note: The RAD750 3U CompactPCI board, which is not powered on during launch, only has to survive exposure to the Launch Site radar sources. These requirements do not include any shielding provided by the L/V fairing.
6.6.4 Electrical Isolation If any of the RAD750 3U CompactPCI board signals are used for isolated interface circuits in the spacecraft, the electrical isolation of these power line, command, data, and telemetry signals shall exceed 1 M ohm DC and coupling capacitance shall be less than 400 picofarads.
6.7 Radiation The following radiation environments assume approximately a 6 year mission. The data presented are for general guidance only; the actual radiation exposure of an assembly will depend upon its configuration on the spacecraft and will require a radiation transport analysis.
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6.7.1 Total Ionizing Dose (TID) The RAD750 3U CompactPCI board flight units operate within post-irradiation specification of Test Requirements document, JPL D-15517. These devices at a packaged part level are limited to 100 Krad TID.
6.7.2 Single Event Effects (SEE) Single event effects are caused by solar heavy ions and protons and by Galactic Cosmic Rays (GCR), which are primarily heavy ions. The RAD750 3U CompactPCI board (including all of its flight interfaces and memory) is designed so that the number of “intrusive events”, while operating under the Heinrich Flux Spectra is less than or equal to the values indicated in Table 30. An “intrusive event” is defined as an SEU induced behavior that disrupts the operation of the RAD750 3U CompactPCI board or the operation of the software executing on the RAD750 3U CompactPCI board. A disruption is defined as an event which prevents the normal execution of the software for a period greater than one millisecond or that requires a reset and initialization to restore the RAD750 3U CompactPCI board to the operational state prior to the SEU. The RAD750 3U CompactPCI board (including all of its flight interfaces and memory) is designed so that recovery or correction for SEU induced errors, in the worst case environment, does not require more than 1% of the CPU performance at any given clock speed.
Table 30. RAD750 3U CompactPCI board Induced SEU Rate Requirements
Time Period SEU Rate Event
Any 90 minutes period 1E10-5 Probability of an intrusive within the mission lifetime event occurring in the RAD750 3U CompactPCI board Bit errors per day 1E10-10 Probability of an SEU event occurring in an ASIC
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Section 7 Functional Interface The RAD750 3U CompactPCI board provides the following functional interfaces to the user. For more detail behind these summarized requirements, see the RAD750 Board User Manuals. The RAD750 3U CompactPCI board provides four separate functional interfaces to a potential user: RAD750 Programming, External PCI Bus Master, EMC Programming, and External JTAG.
7.1 RAD750 Programming Interface The RAD750 Programming Interface includes the RAD750 registers (see subsection 8.1), RAD750 address map, and RAD750 interrupts.
7.1.1 RAD750 Address Map The RAD750 3U CompactPCI board implements the RAD750 60X Address Map shown in Table 31. The RAD750 3U CompactPCI board permits RAD750 access to all internal memory and the entire 4 GB PCI I/O and Memory address spaces.
Table 31. RAD750 3U CompactPCI board Memory Map seen from the RAD750 CPU, JTAG Slave or Embedded Micro-Controller
RAD750 Physical Size Destination Actual Destination Address Notes Address 0000 0000 – 07FF FFFF 128 MB System Memory 0000 0000 – 07FF FFFF 128 MB DRAM 0800 0000 - 7FFF FFFF 1.875 System Memory 0800 0000 - 7FFF FFFF Unimplemented GB on RAD750 3U CompactPCI board 8000 0000 – 8000 0CF7 3220 B PCI Bus I/O 0000 0000 – 0000 0CF7 Mapped to PCI Bus I/O 8000 0CF8 – 8000 0CFB 4 B Power PCI ASIC PCI Config Address Register PCI PCI Register in Power PCI ASIC Configuration Address Port 8000 0CFC – 8000 0CFF 4 B PCI Bus PCI Config ADDRESS PCI Configuration Configuration Space, Or Data access Power PCI ASIC PCI Register -- See Table 38 8000 0D00 – BF7F FFFF 1 GB PCI Bus I/O 0000 0D00 – 3F7F FFFF 106 Mode - Mapped to PCI - 8 MB or Bus I/O - 3228 B (1 of 8) I/O Base Address or Regs[0:10]||A[11:31] PCI Bus I/O Paging Mode
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RAD750 Physical Size Destination Actual Destination Address Notes Address BF80 0000 – BF80 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 39 System Memory Registers BF81 0000 – BF81 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 40 60x Registers BF82 0000 – BF82 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 41 UART Registers BF83 0000 – BF83 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 42 JTAG(A) Registers BF84 0000 – BF84 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 42 JTAG(B) Registers BF85 0000 – BF85 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 43 Micro-controller Registers BF86 0000 – BF86 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 45 Clocks and Test Registers BF87 0000 – BF87 FFFF 64 KB Power PCI ASIC 0000- FFFF See Table 38 PCI Registers BF88 0000 – BF88 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 44 Interrupts / Timers / Discretes Registers BF89 0000 – BFFF FFFF 7616 KB Reserved Unimplemented in RAD750 3U CompactPCI board C000 0000 – FEFF FFFF 1 GB PCI Bus Memory 0000 0000 – 3EFF FFFF 106 Mode - Mapped to PCI - 16 MB or Bus Memory (1 of 8) Memory Base or Address Regs[0:4]||A[5:31] PCI Bus Memory Paging Mode
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RAD750 Physical Size Destination Actual Destination Address Notes Address FF00 0000 – FF7F FFFF 8 MB System Memory FF00 0000 – FF7F FFFF Unimplemented on RAD750 3U Or CompactPCI PCI Bus Memory board Or ROM on PCI Bus Memory FF80 0000 - FFEF FFFF 7 MB System Memory FF80 0000 - FFEF FFFF Unimplemented on RAD750 3U Or CompactPCI PCI Bus Memory board Or ROM on PCI Bus Memory FFF0 0000 - FFF3 FFFF 256 KB SUROM FFF0 0000 - FFF3 FFFF 256 KB SUROM Or Or PCI Bus Memory ROM on PCI Bus Memory FFF4 0000 – FFFF FFFF 768 KB System Memory FFF4 0000 – FFFF FFFF Unimplemented on RAD750 3U Or CompactPCI PCI Bus Memory board Or ROM on PCI Bus Memory
7.1.2 RAD750 Interrupts and Exceptions The RAD750 3U CompactPCI board wires and supports the exceptions to the RAD750 shown in Table 32.
Table 32. RAD750 Exceptions
Exception Offset Name RAD750 3U Description / Comments / Type CompactPCI Cause board Source System 00100 HRESET_L Power PCI Register Caused by External Condition or Reset or JTAG Wire Internal / External Write System 00100 SRESET_L JTAG Wire Generated by Test Equipment Reset
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Exception Offset Name RAD750 3U Description / Comments / Type CompactPCI Cause board Source Machine 00200 MCP_L External Input, External NMI, Internally detected Check Power PCI 60x interface Error DSI 00300 Data Storage Interrupt RAD750 Data Memory Access Cannot be Performed ISI 00400 Instruction Storage RAD750 Instruction Fetch Cannot be Interrupt Performed Ext. 00500 Multiprocessor Signal Power PCI Register Internal / External Write Interrupt 0:31 Ext. 00500 PCI_INTA# PCI Bus Signal Wired to Power PCI PID 16 Interrupt Ext. 00500 PCI_INTB# PCI Bus Signal Wired to Power PCI PID 17 Interrupt Ext. 00500 PCI_INTC# PCI Bus Signal Wired to Power PCI PID 28 Interrupt Ext. 00500 PCI_INTD# PCI Bus Signal Wired to Power PCI PID 29 Interrupt Ext. 00500 PCI_DEG# PCI Bus Signal Wired to Power PCI PID 18 Interrupt Ext. 00500 PCI_FAL# PCI Bus Signal Wired to Power PCI PID 19 Interrupt Ext. 00500 PCI_ENUM# PCI Bus Signal Wired to Power PCI PID 20 Interrupt Ext. 00500 Discrete Input 0:31 External Inputs Wired to Power PCI PID 0:31 Interrupt Ext. 00500 PCI Interface Power PCI Register Internal Interrupt Ext. 00500 60X Interface Power PCI Register Internal Interrupt Ext. 00500 Memory High Priority Power PCI Register Internal Interrupt Ext. 00500 Memory Low Priority Power PCI Register Internal Interrupt Ext. 00500 UART Interface Power PCI Register Internal Interrupt Ext. 00500 Embedded Power PCI Register Internal Interrupt Microcontroller Ext. 00500 Miscellaneous Sources Power PCI Register Internal Interrupt
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Exception Offset Name RAD750 3U Description / Comments / Type CompactPCI Cause board Source Alignment 00600 Alignment Error RAD750 Alignment or Endian Problem with Access Program 00700 Program Error RAD750 Software Execution Floating 00800 Floating Point RAD750 Attempt to Run Floating Point Point Unavailable Instruction when not Available Unavailable Decremente 00900 Decrementer Rollover RAD750 Decrement Changes to all 1's r System Call 00C00 System Call RAD750 System Call Instruction Trace 00D00 Trace RAD750 Software Monitor Performance 00F00 Performance Monitor RAD750 Software Monitor - PowerPC 750 Monitor Only Instruction 01300 Instruction Address RAD750 Software Monitor - PowerPC 750 Address Breakpoint Only Breakpoint System 01400 SMI_L RAD750 Not Used Managemnt Interrupt Thermal 01700 Thermal Management RAD750 Junction Temperature Exceeds Managemnt Interrupt Threshold - PowerPC 750 Only Interrupt
7.2 External PCI Bus Interface The RAD750 3U CompactPCI board provides the following programming interfaces from the External PCI Bus Initiator's point of view. This point of view assumes an external PCI Initiator or System Controller is attempting to access the RAD750 3U CompactPCI board.
7.2.1 PCI Address Map The RAD750 3U CompactPCI board does not respond to any external accesses in the PCI I/O address space. The RAD750 3U CompactPCI board does respond to PCI accesses according to Table 33.
Table 33. RAD750 3U CompactPCI board Memory Map seen from the External PCI Bus
PCI Bus Address Size Destination Destination Address Notes BAR1 => X 128 MB System Memory 0000 0000 – 07FF FFFF 128 MB DRAM X000 0000 - X7FF FFFF PCI Memory Address Space
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PCI Bus Address Size Destination Destination Address Notes X800 0000 - XFFF FFFF 128 MB System Memory 0800 0000 - 0FFF FFFF Unimplemented Interface BAR2 => YYY 64 KB Power PCI ASIC 0000 – FFFF See Table 39 System Memory YYY0 0000 - YYY0 FFFF Registers PCI Memory Address Space YYY1 0000 – YYY1 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 40 60x Registers YYY2 0000 – YYY2 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 41 UART Registers YYY3 0000 – YYY3 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 42 JTAG(A) Registers YYY4 0000 – YYY4 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 42 JTAG(B) Registers YYY5 0000 – YYY5 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 43 Micro-controller Registers YYY6 0000 – YYY6 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 45 Clocks and Test Registers YYY7 0000 – YYY7 FFFF 64 KB Power PCI ASIC 0000 - FFFF See Table 38 PCI Registers YYY8 0000 – YYY8 FFFF 64 KB Power PCI ASIC 0000 – FFFF See Table 44 Interrupts / Timers / Discretes Registers YYY9 0000 – YYYF FFFF 448 KB Reserved Unimplemented in RAD750 3U CompactPCI board Configuration Cycle 256 B PCI Core 00 – FF PCI Core Configuration PCI Configuration Registers in Registers Address Space Power PCI ASIC See first 256 bytes of Table 38
7.2.2 PCI Interrupts The RAD750 3U CompactPCI board wires and supports the PCI Bus interrupts shown in Table 34.
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Table 34. PCI Bus Interrupts
Name RAD750 3U CompactPCI Cause Sensing board Source PCI_INTA# UART_DATA_OUT2_L Write to RAD750 3U May be monitored / cause CompactPCI board RAD750 interrupt through UART Register in Power Power PCI PID 16 PCI will change this signal. PCI_INTB# None - single function External Device May be monitored / cause device RAD750 interrupt through Power PCI PID 17 PCI_INTC# None - single function External Device May be monitored / cause device RAD750 interrupt through Power PCI PID 28 PCI_INTD# None - single function External Device May be monitored / cause device RAD750 interrupt through Power PCI PID 29 PCI_DEG# None - not power supply External Power Supply May be monitored / cause RAD750 interrupt through Power PCI PID 18 PCI_FAL# None - not power supply External Power Supply May be monitored / cause RAD750 interrupt through Power PCI PID 19 PCI_ENUM# None - not hot swappable External Hot Swappable May be monitored / cause Board RAD750 interrupt through Power PCI PID 20
7.3 Embedded Micro-Controller Programming Interfaces The Embedded Micro-Controller (EMC), which is embedded in the Power PCI ASIC has a more limited programming interface than the RAD750.
7.3.1 EMC Address Map The RAD750 3U CompactPCI board provides an EMC address memory map identical to Table 31 accessed through any EMC indirect address access. This includes all EMC internal registers.
7.3.2 EMC Interrupts The RAD750 3U CompactPCI board wires and supports the EMC interrupts shown in Table 35.
Table 35. EMC Interrupts in Priority Order
Vector # Offset RAD750 3U CompactPCI board Sources Comments 7 001C Power PCI Critical Errors Non-Maskable Watchdog Timer Expired
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Vector # Offset RAD750 3U CompactPCI board Sources Comments 6 0018 Power PCI EMC Instruction Error Non-Maskable
5 0014 RAD750 Checkstop PID 31 Power PCI EMC Register Write 4 0010 Power PCI Programmable Timer 1 PID 30 Power PCI EMC Register Write 3 000C Power PCI Programmable Timer 2 PCI_INTD# (PID 29) Power PCI EMC Register Write 2 0008 Power PCI Programmable Timer 3 PCI_INTC# (PID 28) Power PCI EMC Register Write 1 0004 RAD750_INT_L signal PID 27 Power PCI EMC Register Write 0 0000 PID 26 Power PCI EMC Register Write
7.4 External JTAG Interfaces The RAD750 3U CompactPCI board provides to an external JTAG Master a JTAG slave address memory map identical to Table 31. This memory map may be accessed through any JTAG slave OCB read or write by the Power PCI JTAG Probe or a Backpanel JTAG Interface Master using the Slave JTAG registers given in Table 46. Since the JTAG slave interface is fully synchronous, there are no interrupts.
7.5 Module Initialization The RAD750 3U CompactPCI board is configured in the following default modes through hardware. The INTR_PIN_VALUE signal of the Power PCI ASIC is wired to a value of '1" to match the connection of PCI_INTA# to the output of UART_OUT2_L. The IO_MCTL_SU_WIDTH signal of the Power PCI ASIC is pulled high to enable a 16 bit interface for the EEPROM connected to row 0 of the Power PCI ASIC memory control interface. The Power PCI ASIC shall be hardwired to set BAR1 at its minimum size of 256 Mbytes in the PCI Memory address space. The Power PCI ASIC shall be hardwired to set BAR2 at its normal size of 1 Mbyte in the PCI Memory address space.
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Section 8 RAD750 3U CompactPCI board Register Definition The RAD750 3U CompactPCI board contains registers that reside in the RAD750 and the Power PCI ASIC. These are summarized below. Full definition may be found in the PowerPC 750 User Manual.
8.1 RAD750 Register Map The RAD750 3U CompactPCI board provides the following register interfaces through the RAD750.
8.1.1 RAD750 General Registers The RAD750 3U CompactPCI board contains the PowerPC general registers shown in Table 36 within the RAD750.
Table 36. RAD750 Architecture Defined Registers
Register(s) Level Function CR User Condition Register FPR0-FPR31 User 64-bit Floating Point Registers FPSCR User Floating Point Status and Control Register GPR0-GPR31 User General Purpose Registers MSR Supervisor Machine State Register SR0-15 Supervisor Segment Registers
8.1.2 RAD750 Special Purpose Registers The RAD750 3U CompactPCI board contains the PowerPC Special Purpose Registers (SPR) shown in Table 37 within the RAD750.
Table 37. RAD750 Special Purpose Registers
Register(s) Level SPR Function Address XER User 1 Miscellaneous Condition and Index Register LR User 8 Link Register CTR User 9 Count Register DSISR User 18 Data Storage Interrupt Status Register DAR User 19 Data Address Register DEC Supervisor 22 Decrementer Register SDR1 Supervisor 25 Specifies page table format used in virtual to physical page translation SRR0-1 Supervisor 26-27 Machine Save / Restore Registers
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Register(s) Level SPR Function Address SPRG0-3 Supervisor 272-275 For Operating System Use EAR Supervisor 282 External Address Register TB (L:U) User: Read 284-285 Time Base Register. Used in Lower / Upper pair. Supervisor: R/W PVR Supervisor 287 Processor Version Register IBAT0-3 (U:L) Supervisor 528-535 Instruction Block Address Translation Registers. Used In Upper / Lower pairs DBAT0-3 (U:L) Supervisor 536-543 Data Block Address Translation Registers. Used in Upper / Lower pairs UMMCR0 User 936 User Monitor Mode Control Register 0 UPMC1-2 User 937-938 User Performance Monitor Counter Registers 1-2 USIA User 939 User Sampled Instruction Address Register UMMCR1 User 940 User Monitor Mode Control Register 1 UPMC3-4 User 941-942 User Performance Monitor Counter Registers 3-4 MMCR0 Supervisor 952 Monitor Mode Control Register 0 PMC1-2 Supervisor 953-954 Performance Monitor Counter Registers 1-2 SIA Supervisor 955 Sampled Instruction Address Register MMCR1 Supervisor 956 Monitor Mode Control Register 1 PMC3-4 Supervisor 957-958 Performance Monitor Counter Registers 3-4 HID0-1 Supervisor 1008-1009 Hardware Implementation Dependent Registers IABR Supervisor 1010 Instruction Address Breakpoint Register DABR Supervisor 1013 Data Address Breakpoint Register L2CR Supervisor 1017 L2 Cache Control Register ICTC Supervisor 1019 Instruction Cache-Throttling Control Register THRM1-2 Supervisor 1020-1021 Thermal Management Registers 1-2 THRM3 Supervisor 1022 Thermal Management Register 3
8.2 Power PCI ASIC Register Map The RAD750 3U CompactPCI board contains registers grouped by function or core within the Power PCI ASIC. These are shown in the tables in the subsections that follow. Full definition of the registers may be found in the RAD750 Board Hardware User Manual.
8.2.1 PCI Configuration Registers The RAD750 3U CompactPCI board contains PCI configuration registers shown in Table 38 within the Power PCI ASIC.
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The base address for these registers is either xBF87 0000 when accessed by the RAD750, EMC or an external JTAG master (see Table 31) or xYYY7 0000 when accessed by an external PCI Bus Initiator with YYY representing the high order 12 bits of BAR2 (see Table 33). The first 256 bytes are also accessible through PCI configuration space accesses.
Table 38. Power PCI ASIC PCI Configuration Registers
Register Name Address Access Reset State Bits Expected Use Offset Rights Vendor ID 0x0000 R 0x11D0 16 Information Device ID 0x0002 R 0x0000 16 Information Command 0x0004 R/W – R 0x0000 16 Configuration Status 0x0006 R/WC - R 0x0280 16 Status Revision ID 0x0008 R 0x00 8 Information Class Code 0x000A R 0x060000 24 Information Cache Line Size 0x000C R/W 0x00 8 Configuration Latency Timer 0x000D R/W 0x00 8 Configuration Header Type 0x000E R 0x00 8 Information Base Address 1 0x0010 R/W – R 0x0000_0008 32 Configuration Base Address 2 0x0018 R/W – R 0x0000_0000 32 Configuration Subsystem Vendor ID 0x002C R1 0x0000 16 Information Subsystem ID 0x002E R1 0x0000 16 Information Interrupt Line 0x003C R/W 0x00 8 Information Interrupt Pin 0x003D R X2 8 Information MIN_GNT 0x003E R 0x00 8 Information MAX_LAT 0x003F R 0x00 8 Information Status 2 0x0050 R/WC - R 0x0200_0000 32 Status Status 2 Mask 0x0054 R/W 0x0000_0000 32 Intr. Disables BAR1 Size Adjust 0x0058 R/W 0x000000 24 Configuration PCI Core Configuration 0x005C R/W 0x0000_0000 32 Configuration Arbitration Priority 0x0060 R/W 0x0000 16 Configuration Error Checking 0x0062 R/W 0x0000 16 Configuration Error Injection 0x0064 R/W 0x00 8 Action Bus Reset 0x0065 R/W - R 0x012 8 Action PCI Core Revision ID 0x0066 R 0x3001 16 Information User Defined A Register 0x0070 R/W 0’s 32 User Defined
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Register Name Address Access Reset State Bits Expected Use Offset Rights O2P I/O Paging 0 0x0080 R/W 0x0000 16 Configuration O2P I/O Paging 1 0x0082 R/W 0x0000 16 Configuration O2P I/O Paging 2 0x0084 R/W 0x0000 16 Configuration O2P I/O Paging 3 0x0086 R/W 0x0000 16 Configuration O2P I/O Paging 4 0x0088 R/W 0x0000 16 Configuration O2P I/O Paging 5 0x008A R/W 0x0000 16 Configuration O2P I/O Paging 6 0x008C R/W 0x0000 16 Configuration O2P I/O Paging 7 0x008E R/W 0x0000 16 Configuration O2P Memory Paging 0 0x0090 R/W 0x0000 16 Configuration O2P Memory Paging 1 0x0092 R/W 0x0000 16 Configuration O2P Memory Paging 2 0x0094 R/W 0x0000 16 Configuration O2P Memory Paging 3 0x0096 R/W 0x0000 16 Configuration O2P Memory Paging 4 0x0098 R/W 0x0000 16 Configuration O2P Memory Paging 5 0x009A R/W 0x0000 16 Configuration O2P Memory Paging 6 0x009C R/W 0x0000 16 Configuration O2P Memory Paging 7 0x009E R/W 0x0000 16 Configuration User Defined B Register 0x00A8 R/W 0’s 32 User Defined User Defined C Register 0x00AC R/W 0’s 32 User Defined PCI Bus Error Status 0x00C6 R 0x0000 16 Status PCI Error Address 0x00C8 R 0’s 32 Status
1 This register is always read only from the PCI bus, but may be read/write from the OCB bus depending on the setting of the SUBSYSTEM_ID_RW VHDL constant. 2 The reset value of the Interrupt Pin register is dependent on the INTR_PIN_VALUE I/O signal. The reset value of the Bus Reset register is dependent on the CENTRAL_RSRC_L I/O signal.
8.2.2 System Memory Configuration Registers The RAD750 3U CompactPCI board contains the Memory Controller configuration registers shown in Table 39 within the Power PCI ASIC. The base address for these registers is either xBF80 0000 when accessed by the RAD750, EMC or an external JTAG master (see Table 31) or xYYY0 0000 when accessed by an external PCI Bus Initiator with YYY representing the high order 12 bits of BAR2 (see Table 33).
Table 39. Power PCI ASIC Memory Controller Register Map
Memory Controller Core Register/Resource Map Register/Array/Command Address Access Reset State Expected Use
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Memory Controller Core Register/Resource Map Register/Array/Command Address Access Reset State Expected Use General Purpose Registers Vendor ID/ Revision Register ’0000’X RO ’0000 1801’X Diagnostics Enter SDRAM Self-Refresh Command ‘0008’X WO N/A Operational Exit SDRAM Self-Refresh Command 000C’X WO N/A Operational Initialization Registers Initialization Data High Register ’0010’X R/W ’0000 0000’X Initialization Initialization Data Low Register ‘0014’X R/W ‘0000 0000’X Initialization Initialization Starting Address Register ’0018’X R/W ’0000 0000’X Initialization Initialization Ending Address Register ’001C’X R/W ’0000 0000’X Initialization Memory Addressing Registers Memory Bank 0 Address Register ‘0020’X R/W ‘FFF0 FFFF’X Configuration Memory Bank 1 Address Register ‘0024’X R/W ‘8001 8000’X Configuration Memory Bank 2 Address Register ‘0028’X R/W ‘8001 8000’X Configuration Memory Bank 3 Address Register ‘002C’X R/W ‘8001 8000’X Configuration Memory Bank 4 Address Register ‘0030’X R/W ‘8001 8000’X Configuration Memory Bank 5 Address Register ‘0034’X R/W ‘8001 8000’X Configuration Memory Bank 6 Address Register ‘0038’X R/W ‘8001 8000’X Configuration Memory Bank 7 Address Register ‘003C’X R/W ‘8001 8000’X Configuration Memory Type Register ‘0060’X R/W ‘0000 0000’X1 Configuration Memory Address Mode Register ‘0064’X R/W ‘0000 0000’X Configuration Memory Bank Enable Register ‘0068’X R/W ‘0000 0001’X1 Configuration Memory Bank Write Enable Register ‘006C’X R/W ‘0000 0000’X Configuration Error Correction/Detection Registers Correction Type Register ‘0070’X R/W ‘0000 FFFD’X Configuration ECC Error Injection Register ‘0074’X R/W ‘0000 0000’X Configuration Memory Scrubbing Mode Register ‘0078’X R/W ‘0000 0000’X Configuration Memory Scrubbing Parameters ‘007C’X R/W ‘0000 0000’X Configuration Register Memory Bank 0 Sparing Register ‘0080’X R/W ‘00FF FF00’X Configuration Memory Bank 1 Sparing Register ‘0084’X R/W ‘00FF FF00’X Configuration Memory Bank 2 Sparing Register ‘0088’X R/W ‘00FF FF00’X Configuration Memory Bank 3 Sparing Register ‘008C’X R/W ‘00FF FF00’X Configuration Memory Bank 4 Sparing Register ‘0090’X R/W ‘00FF FF00’X Configuration Memory Bank 5 Sparing Register ‘0094’X R/W ‘00FF FF00’X Configuration Memory Bank 6 Sparing Register ‘0098’X R/W ‘00FF FF00’X Configuration Memory Bank 7 Sparing Register ‘009C’X R/W ‘00FF FF00’X Configuration Error Reporting Registers
85 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Memory Controller Core Register/Resource Map Register/Array/Command Address Access Reset State Expected Use Status Register ‘00C0’X R & W ‘0000 0000’X Status Clear Interrupt Enable Register ‘00C4’X R/W ‘0000 0000’X Configuration Error Counter ‘00D0’X RO & ‘0000 0000’X Status Clear Error Log Word 1 ‘00D8’X RO & ‘0000 0000’X Status Clear Error Log Word 2 ‘00DC’X RO & ‘0000 0000’X Status Clear SDRAM Access Registers SDRAM Configuration Register ‘00E0’X R/W ‘0022 0000’X Configuration SDRAM Timing Parameters Register 1 ‘00E8’X R/W ‘0000 0000’X Configuration SDRAM Timing Parameters Register 2 ‘00EC’X R/W ‘600F 01FF’X Configuration SRAM/ROM Access Registers ROM Timing Parameters Register ‘00F0’X R/W ‘000F FFFF’X Configuration SRAM Timing Parameters Register ‘00F4’X R/W ‘0000 FFFF’X Configuration 8.2.3 60X Interface Configuration Registers The RAD750 3U CompactPCI board contains the 60X Interface configuration registers shown in Table 40 within the Power PCI ASIC. The base address for these registers is either xBF81 0000 when accessed by the RAD750, EMC or an external JTAG master (see Table 31) or xYYY1 0000 when accessed by an external PCI Bus Initiator with YYY representing the high order 12 bits of BAR2 (see Table 33).
Table 40. Power PCI ASIC 60x Interface Register Map
Register/ Physical OCB Reset State SEU or Expected Use Array/ Address Access non- Command Rights SEU Vendor ID/ Revision ’BF81 0000’X RO ’0000 1001’X SEU Lab Diagnostics Register 60x Bus Error Status ’BF81 0008’X RO ’0000 0000’X SEU Error Analysis Register 60x Bus Error Address ’BF81 000C’X RO ’0000 0000’X SEU Error Analysis Register Error Status Register ’BF81 0010’X R/W ’0000 0000’X SEU Error Analysis Error Status Mask ’BF81 0014’X R/W ’0000 0000’X SEU Error Analysis Register Error Injection ‘BF81 0018’X R/W ‘0000 0000’X SEU Error Analysis Register
86 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
8.2.4 UART Configuration Registers The RAD750 3U CompactPCI board contains the UART configuration registers shown in Table 41 within the Power PCI ASIC. The base address for these registers is either xBF82 0000 when accessed by the RAD750, EMC or an external JTAG master (see Table 31) or xYYY2 0000 when accessed by an external PCI Bus Initiator with YYY representing the high order 12 bits of BAR2 (see Table 33).
Table 41. Power PCI ASIC UART Register Map
Register/ Physical OCB Reset State Expected Use Array/ Address Access Command Rights UART Receiver Buffer ’0000 0000’X RO ’0000 0000’ Read FIFO Register *DLAB = 0 UART Transmitter ’0000 0000’X WO ’0000 0000’ Write FIFO Holding Register *DLAB = 0 UART Interrupt Enable ’0000 0001’X R/W ’0000 0000’ Configuration Register *DLAB = 0 UART Divisor Low ’0000 0000’X R/W ’0000 0000’ Configuration Register *DLAB = 1 UART Divisor High ’0000 0001’X R/W ’0000 0000’ Configuration Register *DLAB = 1 UART Interrupt ’0000 0002’X RO ’0000 0001’ Configuration Identification Register UART FIFO Control ’0000 0002’X WO ’0000 0000’ Configuration Register UART Line Control ’0000 0003’X R/W ’0000 0000’ Configuration Register UART MODEM Control ’0000 0004’X R/W ’0000 0000’ Configuration Register UART Line Status ’0000 0005’X RO ’0110 0000’ Status Register UART MODEM Status ’0000 0006’X RO ’0000 0000’ Status Register UART Scratch Register ’0000 0007’X R/W ’0000 0000’ Status UART Error Status ’0000 0008’X RO ’0000 1000’ Status Register UART Core ID Register ’0000 0009’X RO CORE_ID Status UART Revision # ’0000 000A’X RO REV_NUM Status Register
87 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Register/ Physical OCB Reset State Expected Use Array/ Address Access Command Rights Reserved ’0000 000B’X- RO ’0000 0000’ Status ‘FFFF FFFF’X
*DLAB = Line Control Register bit(7)
8.2.5 JTAG Master Configuration Registers The RAD750 3U CompactPCI board contains two sets (A) and (B) of the JTAG Master configuration registers shown in Table 42 within the Power PCI ASIC. The base address for set A of these registers is either xBF83 0000 when accessed by the RAD750, EMC or an external JTAG master (see Table 31) or xYYY3 0000 when accessed by an external PCI Bus Initiator with YYY representing the high order 12 bits of BAR2 (see Table 33). The base address for set B of these registers is either xBF84 0000 when accessed by the RAD750, EMC or an external JTAG master (see Table 31) or xYYY4 0000 when accessed by an external PCI Bus Initiator with YYY representing the high order 12 bits of BAR2 (see Table 33).
Table 42. Power PCI ASIC JTAG Master Register Map
Register/ Physical OCB Reset State Expected Use Array/ Address Access Command Rights JTAG Control/Status Register ‘0000’X R/W ’0000 0000’X Control/Status JTAG Bit Count Register ‘0004’X R/W ’0000 0000’X Control JTAG TDI Register ‘0008’X R/W ’0000 0000’X Read data JTAG TDO Register ‘000C’X R/W ’0000 0000’X Write data JTAG TCLK Divide Register ’0010’X R/W ’0000 0003’X Configuration JTAG Core ID ‘0014’X R Hard-coded Configuration Reserved ‘0018’X – R ‘0000 0000’X Padding to end of ‘001C’X cache line Illegal Addresses ‘0020’X – None N/A N/A ‘FFFC’X 8.2.6 Micro-Controller Configuration Registers The RAD750 3U CompactPCI board contains the Micro-controller configuration registers shown in Table 43 within the Power PCI ASIC. The base address for these registers is either xBF85 0000 when accessed by the RAD750, EMC or an external JTAG master (see Table 31) or xYYY5 0000 when accessed by an external PCI Bus Initiator with YYY representing the high order 12 bits of BAR2 (see Table 33).
Table 43. Power PCI ASIC Micro-Controller Register Map
Register Physical OCB Reset State Expected Use Address Access Rights
88 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Register Physical OCB Reset State Expected Use Address Access Rights GPR 0 ’0000’X R/W1 ’0000 0000’X Operation GPR 1 ’0004’X R/W1 ’0000 0000’X Operation GPR 2 ’0008’X R/W1 ’0000 0000’X Operation GPR 3 ’000C’X R/W1 ’0000 0000’X Operation GPR 4 ‘0010’X R/W1 ‘0000 0000’X Operation GPR 5 ‘0014’X R/W1 ‘0000 0000’X Operation GPR 6 ‘0018’X R/W1 ‘0000 0000’X Operation GPR 7 ‘001C’X R/W1 ‘0000 0000’X Operation GPR 8 ‘0020’X R/W1 ‘0000 0000’X Operation GPR 9 ‘0024’X R/W1 ‘0000 0000’X Operation GPR 10 ‘0028’X R/W1 ‘0000 0000’X Operation Condition/Status Register ‘002C’X R/W1 ‘0000 0000’X Operation Vector Interrupt Address ‘0030’X R/W1 ‘0000 0000’X Operation Vector Control Register ‘0034’X R/W ‘0000 0000’X Operation Vector Anchor Register ‘0038’X R/W1 ‘FFF0 0000’X Operation Watchdog Timer Register ‘003C’X R/W1 ‘0000 FFFF’X Operation Program Counter ‘0040’X R/W1 ‘FFF0 0020’X Operation Breakpoint Address ‘0044’X R/W1 ‘0000 0000’X Debug Debug Command/Status ‘0048’X R/W ‘0000 0000’X Debug Error Interrupt Status ‘004C’X R/W ‘0000 0000’X Operation Revision ID ‘0050’X R Hard Wired Configuration Zero Pad ‘0054’ – R ‘0000 0000’ N/A ‘005C’X Reserved ‘0060’ – N/A N/A N/A ‘FFFC’ 1 Writable only while in the Stop state.
8.2.7 Interrupt, Timers and Discretes Configuration Registers The RAD750 3U CompactPCI board contains the Interrupt, Timers and Discretes configuration registers shown in Table 44 within the Power PCI ASIC. The base address for these registers is either xBF88 0000 when accessed by the RAD750, EMC or an external JTAG master (see Table 31) or xYYY8 0000 when accessed by an external PCI Bus Initiator with YYY representing the high order 12 bits of BAR2 (see Table 33).
Table 44. Power PCI ASIC Interrupts, Timers and Discretes Register Map
Register Physical RAD750 Reset State Expected Use Address Access Rights Interrupt Collection ’0000’X R ’0000 0000’X Status
89 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
Register Physical RAD750 Reset State Expected Use Address Access Rights Interrupt Enable ’0004’X R/W ’0000 0000’X Configuration PID Output Enable ’0008’X R/W ’0000 0000’X Configuration PID Output Select ’000C’X R/W ’0000 0000’X Configuration PID Output ‘0010’X R/W ‘0000 0000’X Operation PID Input Enable ‘0014’X R/W ‘0000 0000’X Configuration PID Input Select ‘0018’X R/W ‘0000 0000’X Configuration PID Interrupt Enable ‘001C’X R/W ‘0000 0000’X Configuration PID Vector Enable ‘0020’X R/W ‘0000 0000’X Configuration PID Input ‘0024’X R/W ‘0000 0000’X Operation CPU Discretes ‘0028’X R/W ‘0000 0001’X Operation MCP Collection ‘002C’X R ‘0000 0000’X Status MCP Enable ‘0030’X R/W ‘0000 0000’X Configuration PTIM 1 Configuration ‘0034’X R/W ‘0000 0000’X Configuration PTIM 1 Timer ‘0038’X R/W ‘0000 0000’X Timer PTIM 1 Reload ‘003C’X R/W ‘0000 0000’X Configuration PTIM 2 Configuration ‘0040’X R/W ‘0000 0000’X Configuration PTIM 2 Timer ‘0044’X R/W ‘0000 0000’X Timer PTIM 2 Reload ‘0048’X R/W ‘0000 0000’X Configuration PTIM 3 Configuration ‘004C’X R/W ‘0000 0000’X Configuration PTIM 3 Timer ‘0050’X R/W ‘0000 0000’X Timer PTIM 3 Reload ‘0054’X R/W ‘0000 0000’X Configuration Watchdog Timer ‘0058’X R/W ‘FFFF FFFF’X Timer Semaphore ‘005C’X R ‘0000 0000’X Communication SemTake/SemGive ‘0060 – R/W ‘0000 0000’X Communication 007C’X Multiprocessor Signaling ‘0080 – R/W ‘0000 0000’X Communication 0084’X Signaling Enable ‘0088’X R/W ‘0000 0000’X Configuration Vector Interrupt Status ‘008C’X R/W ‘0000 0000’X Status Vector Interrupt Enable ‘0090’X R/W ‘0000 0000’X Configuration Misc Interrupt Status ‘0094’X R/W ‘0000 0000’X Status Misc Interrupt Enable ‘0098’X R/W ‘0000 0000’X Configuration Revision ID ‘009C’X R Hard Wired ID Reserved ‘00A0’ – N/A N/A N/A ‘FFFC’
90 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
8.2.8 Clocks and Test Configuration Registers The RAD750 3U CompactPCI board contains the Clocks and Test configuration registers shown in Table 45 within the Power PCI ASIC. The base address for these registers is either xBF86 0000 when accessed by the RAD750, EMC or an external JTAG master (see Table 31) or xYYY6 0000 when accessed by an external PCI Bus Initiator with YYY representing the high order 12 bits of BAR2 (see Table 33).
Table 45. Power PCI ASIC Clocks and Test Register Map
Register Physical RAD750 Reset State Expected Use Address Access Rights Clock Control ’0000’X R/W ’0000 003F’X Configuration PLL Setup '0004'X R/W '0000 0000'X Configuration PLL Configuration '0008'X R/W '0000 0000'X Configuration PM Control '000C'X R/W '0000 0000'X Configuration Error Interrupt Status '0010'X R/W '0000 0000'X Status Revision ID '0014'X R '0000 0000'X ID Zero Pad '0018'X R '0000 0000'X N/A Zero Pad '001C'X R '0000 0000'X N/A BIST Core MISR ‘0020 - R/W N/A BIST 0024’X BIST Core Control ‘0028’X R/W ‘0000 0000’X BIST BIST Core Status ‘002C’X R/W N/A BIST/RESET BIST Core ID ‘0030’X R N/A ID Zero Pad ‘0034 – R ‘0000 0000’X N/A 003C’X BIST Core Soft Reset ‘0040’X W N/A RESET BIST Core Stop Clocks ‘0044’X W N/A TEST BIST Core Start Clocks ‘0048’X W N/A TEST BIST Core Single Cycle ‘004C’X W N/A TEST BIST Core Start LBIST ‘0050’X W N/A BIST BIST Core Start ABIST ‘0054’X W N/A BIST BIST Core Start Labscan ‘0058’X W N/A TEST BIST Core Cycle Count ‘005C’X R/W ‘0000 0000’X BIST Reserved '0060'X to N/A N/A N/A 'FFFC'X 8.2.9 JTAG Slave Configuration Registers The RAD750 3U CompactPCI board contains the JTAG Slave configuration registers shown in Table 46 within the Power PCI ASIC. Since these are only accessible through an external JTAG master, there are no base registers as position in the external string is the only "address" required to access these registers.
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Table 46. Power PCI ASIC JTAG Slave Register Map
Register/ JTAG Instruction JTAG Reset State Expected Array/ Address Register Access Use Command Opcode Rights JTAG Tap Instruction N/A N/A Scan Write Test Logic Reset JTAG Register Instruction Opcode and Address JTAG TAP Status N/A N/A Scan Read ’X00 0000 0001’ Status Register JTAG ID Register N/A ’100’ Scan Read ’0000 0000’ JTAG ID JTAG Data Staging N/A N/A Scan ’0000 0000’ Read and Register Read/Write write data JTAG Bypass N/A ’111’ Scan ’0’ JTAG string Register Read/Write bypass OCB Address ’00000’ ’101’ or R/W ’0000 0000’ OCB Address Register ’110’ OCB Data Register ‘00001’ ’101’ or R/W ’0000 0000’ OCB Data ’110’ Control/Status ‘00010’ ’101’ or R/W ‘X 0000 0000 0000’ Control and Register ’110’ Status Revision ID ‘00011’ ’101’ R N/A Chip rev level Discrete Registers ’00100’ – ’101’ or R/W ‘0000 0000’ User defined ’00111’ ’110’
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Section 9 Ordering Information This section provides the part numbering nomenclature for the RAD750 3U CompactPCI board. Note that the individual part numbers correspond to combinations of processor core frequencies, populated memory, and environmental levels. For availability of RAD750 3U CompactPCI board variations, contact BAE SYSTEMS in Manassas, Virginia or visit our web site at www.rad750.com. Table 47 shows the designed part numbers that meet this hardware specification.
Table 47. RAD750 3U CompactPCI board Part Number Listing
Part Number Processor SDRAM SUROM Mechanical Environmental Available / Type & Designation Maximum Frequency TBD COTS 128 MB 256 KB 3U Equivalent to 2000 PowerPC EEPROM CompactPC Flight - no burn- RAD750 3U 750 I w/ Front in or screening; CompactPCI Panel board 132 MHz Parts Selected Engineering for Qualification Model w/ Front Panel TBD COTS 128 MB 256 KB 3U Equivalent to 2000 PowerPC EEPROM CompactPC Flight - no burn- RAD750 3U 750 I w/o Front in or screening; CompactPCI Panel board 132 MHz Parts Selected Engineering for Qualification Model w/o Front Panel TBD LMSE&C 128 MB 256 KB 3U Space Qualified 2001 RAD750 EEPROM CompactPC RAD750 3U I w/ Front CompactPCI 132 MHz Panel board Flight Model w/ Front Panel TBD LMSE&C 128 MB 256 KB 3U Space Qualified 2001 RAD750 EEPROM CompactPC RAD750 3U I w/o Front CompactPCI 132 MHz Panel board Flight Model w/o Front Panel
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Section 10 Comments Document Title: RAD750 3U CompactPCI board Revision / Date: 4.0 August 1, 2000 Hardware Specification Document number: 234A524 Originator: Company: Point of Contact: Telephone: e-mail Address: Address:
Problem Description:
Please send this report to the BAE SYSTEMS address listed on the documentation page, or back cover.
If you require a written or electronic reply, please furnish your address in the form above.
94 Document Number: 234A524 RAD750 CompactPCI Hardware Specification
© BAE SYSTEMS Corporation 2000 Printed in the United States of America 08/00 All Rights Reserved
The information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change BAE SYSTEMS’ product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of BAE SYSTEMS or third parties. All information contained in this document was obtained in specific environments, and is presented as illustration. The results obtained in other operating environments may vary.
While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will BAE SYSTEMS be liable for any damages arising directly or indirectly from any use of the information contained in this document.
BAE SYSTEMS 9300 Wellington Road Manassas, Va 20110-4122
The RAD750 home page can be found at http://www.rad750.com/
The BAE SYSTEMS - Manassas, Va home page can be found at http://www.baesystems- iews.com/space
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