Power Everywhere POWER5 Processor Update

Mark Papermaster VP, Technology Development IBM Systems and Technology Group

PPC 970FX PPC 750GX top Deskt PPC 750FX es PPC 750 PPC 750CXe Gam PPC 603e

PPC 440GX PPC 440GP edded PPC 405GP Emb PPC 401

►PowerPC is at the heart of the BAE Systems RAD6000 Single Board Computer, a specialized system enabling the Mars Rovers — Spirit and Opportunity — to explore, examine and even photograph the surface of Mars. ►In fact, a new generation of PowerPC based space computers is ready for the next trip to another planet. The RAD750, also built by BAE Systems, is powered by a licensed radiation-hardened PowerPC 750 microprocessor that will power space exploration and Department of Defense applications in the years to come.

© 2004 IBM Corporation POWER4 Recognition --- January 2002 “… considering system scalability, bandwidth, chip-level multiprocessing, fault tolerance, and performance --- it is impossible to ignore the accomplishments of the IBM POWER4 architecture … “It has … actually met shipment schedules publicized 2 years ago; and generally lived up to the promise.”

--- Kevin Krewell Senior Analyst, Microprocessor Report

POWER4 High-end

First dual-core microprocessor Mid-range, Low-end

2001-2 2002-3 2004-5 2005-6 2006-7 POWER4 POWER4+ POWER5 POWER5+ POWER6

90 nm 65 nm 130 nm 130 nm Ultra high 180 nm >> GHz >> GHz frequency cores Core Core 1.2-1.9 1.2-1.9 GHz > GHz > GHz L2 caches GHz Core Core 1.0-1.3 1.0-1.3 Core Core Shared L2 Advanced GHz Core GHz Core Distributed Switch System Features Shared L2 Shared L2

Distributed Switch Distributed Switch Shared L2 Simultaneous multi-threading Distributed Switch Sub-processor partitioning Reduced size Dynamic firmware updates Chip Multi Processing Lower power Enhanced scalability, parallelism - Distributed Switch Larger L2 High throughput performance - Shared L2 More LPARs (32) Enhanced memory subsystem Dynamic LPARs (16) Autonomic Computing Enhancements

Build on POWER4 base ►Maintain binary and structural compatibility ►Enhance and extend multiprocessor scalability ►Continue superior performance ►Provide breakthrough virtualization server flexibility ►Deliver power efficient design ►Enhance reliability, availability, serviceability attributes

AIX 5L AIX 5L Linux Linux OS/400 ► Second generation dual core chip AIX 5L AIX 5L Linux Linux OS/400 Integrated xSeriesIntegrated Server AIX AIX Linux Linux SLIC ► Intelligent 2-way SMT xSeries Server kernelAIX kernelAIX kernelLinux kernelLinux (IXA) SLIC (IXA) kernel kernel kernel kernelVirtual I/O Virtual I/O Virtual I/O Virtual LAN Virtual I/O Virtual I/O Virtual I/O ► Power management with no Virtual Virtual I/O LAN Virtual I/O POWER Hypervisor performance impact POWER Hypervisor Hardware LAN IOA IOA LAN IOA Hardware IOA IOALAN IOALAN Management IOA IOA IOA IOA ► 130 nm lithography ManagementConsole IOA IOA (HMC)Console LAN (HMC) LAN 276M transistors 8 layers of metal ► Micropartitioning ► Up to 64 physical processors,1280 virtual processors per system ► Virtual I/O ► Eight way SMP looks like 16-way to ► Virtual LAN software ► All that’s needed is DIMMs and I/O ► 95 mm on a side ► Performance equivalent to >4 p690 MCMs

L2 L2 LargerLarger SMPsSMPs Fab Ctl Fab Ctl

L3 L3 Cntrl Cntrl Number of chips cut in half L3 Faster L3 access to Mem Ctl memory Mem Ctl

Memory Memory

►Each chip appears as a 4-way SMP Simultaneous Multi-Threading to software FX0 ►Processor resources dynamically FX1 optimized for enhanced FP0 multithreading performance FP1 LS0 ►Dynamic switching between single LS1 and multithreaded mode BRX CRL

Thread 0 active Thread 1 active

Reduces power automatically – no program intervention required and no performance impact

Two components: switching power and leakage power

►Switching power reduction: Extensive fine-grain, dynamic clock-gating ►Leakage power reduction Minimal use of low Vt devices

Single Thread

Simultaneous Photos taken with thermal sensitive Multi-threading camera while prototype POWER5 chip was undergoing tests

Simultaneous Multi-threading with dynamic power management reduces power consumption below standard, single threaded level

►POWER4 drove unscheduled outages to near zero ►POWER5 designed to significantly reduce scheduled outages Adds dynamic firmware upgrades Allows for concurrent CEC maintenance … while at the same time enhancing basic reliability Full ECC on chip interconnections including address and tag Additional centralized resource redundancy

Highest Value / Lowest Risk

Lower Superior Superior Higher TCO Availability Flexibility Performance

Leading Technology