2010 IEEE Radiation Effects Data Workshop

Proceedings

Denver, Colorado 19-23 July 2010

IEEE Catalog Number: CFP10422-PRT ISBN: 978-1-4244-8402-7

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The Radiation Effects Data Workshop (REDW) is a session of the Nuclear and Space Radiation Effect Conference (NSREC) Technical Program. The workshop is held as a poster session that is documented by this Workshop Record Publication, which serves as a permanent archive of the REDW. Posters were presented during the 2010 NSREC held at the Sheraton Denver Downtown Hotel, Denver, Colorado, on July 21. The purpose of the REDW is to publish high quality radiation effects data to the radiation effects community. The data includes but is not limited to radiation effects test facilities, standards, and environments, as well as radiation effects on microelectronic devices.

The 2010 Workshop Record has twenty eight papers covering a broad range of topics including: total ionizing dose, displacement damage, and single particle effects on a large number of electronic devices, integrated circuits and detectors; test methodologies; environments and facilities. In addition, like the rest of the conference’s content, there is substantial international participation by contributors from Canada, France, Germany, as well as the United States.

The high quality of this year’s Workshop Record is due to the contribution of the REDW authors. We thank them for their efforts. We also thank the session reviewers for their time and the valuable feedback they provided (reviewers are listed on the following page). All contributed to a very successful 2010 REDW.

Although the Workshop Record provides a cumulative index that can be used to locate papers based on author and title, it is difficult to search for response data on a particular part number, type, or radiation effect. To simplify this activity, searchable tables covering the Workshop Records 1992-2009 are available on the NSREC website at http://www.nsrec.com/redw/

Each year the NSREC Awards Committee selects a paper as the Outstanding REDW Paper. The selection is based on relevance, technical content, innovation and overall quality. This year the Awards Committee selected “Current Single Event Effects Compendium of Candidate Spacecraft Electronics for NASA,” by Martha V. O'Bryan, Dakai Chen, Hak S. Kim, Anthony M. Phan, and Melanie Berg of MEI Technologies; Kenneth A. LaBel, Jonathan A. Pellish, Jean- Marie Lauenstein, Cheryl Marshall, Ray L. Ladbury, Martin A. Carts, Anthony B. Sanders, and Michael A. Xapsos of NASA/GSFC; Timothy R. Oldham of Perot Systems Government Services, Inc; Stephen P. Buchner of Global Defense Technology and Systems; Paul Marshall; Farokh Irom of JPL; Larry G. Pearce, Eric T. Thomson, Theju M. Bernard, Harold W. Satterfield, Alan P. Williams, and Nick W. van Vonno, of Intersil Corporation; and Sam Burns, Rafi S. Albarian of Linear Technology. The authors will receive their awards at the 2011 NSREC in Las Vegas, Nevada.

Leif Scheick 2010 REDW Chair Jeffery Black 2010 NSREC Technical Chair

REDW 2010 Reviewers

Larry McGee Susan H Crain Peter Miraglia Hafer, Craig Nick van Vonno Jean Marie Lauenstein Dave Hiemstra Chuck Foster Mayrant Simons, Raymond L.Ladbury Allan Johnston Aurore Luu Christian Poivey Marta Bagatin Joe Benedetto 2010 REDW Table of Contents

Guide to the 2009 IEEE Radiation Effects ...... 1 D. M Hiemstra, MDA Corporation

Recent Results for PowerPC Processor and Bridge Chip Testing...... 5 S. M. Guertin, Farokh Irom, NASA/JPL

Single Event Upset Characterization of the Virtex-5 Field Programmable Gate Array Using Proton Irradiation ...... 13 D. M. Hiemstra, G. Battiston, P. Gill, MDA Corporation

Sensitivity of 2 Gb DDR2 SDRAMs to Protons and Heavy Ions ...... 17 R. Koga, P. Yu, J. George, S. Bielat, The Aerospace Corporation

90-nm Digital Single Event Transient Pulsewidth Measurements ...... 23 R. K. Lawrence, J. F. Ross, N. E. Wood, BAE Systems

SEE Results for a 4-Port SpaceWire Router ...... 28 C. Hafer, B. Baranski, J. Larsen, F. Sievert, A. Jordan, Aeroflex Colorado Springs

Current Single Event Effects Compendium of Candidate Spacecraft Electronics for NASA ...... 32 M. V. O'Bryan, D. Chen , H. S. Kim, A. M. Phan, M. D. Berg, MEI Technologies Inc. ; K. A. LaBel, J. A. Pellish, J.-M. Lauenstein, C. J. Marshall, R. L. Ladbury, M. A. Carts, A. B. Sanders, M. A. Xapsos, NASA GSFC; T. R. Oldham, Perot Systems Government Services, Inc.; S. P. Buchner, Global Defense Technology and Systems, Inc.; P. W. Marshall, Consultant; F. Irom, NASA JPL; L. G. Pearce, E. T. Thomson, T. M. Bernard, H. W. Satterfield, A. P. Williams, N. W. van Vonno, Intersil Corporation; J. F. Salzman, Texas Instruments; S. Burns, R. S. Albarian, Linear Technology

Compendium of Test Results of Recent Single Event Effect Tests Conducted by the Jet Propulsion Laboratory ...... 44 S. S. McClure, G. R. Allen, F. Irom, L. Z. Scheick, P. C. Adell, T. F. Miyahira, Jet Propulsion Laboratory

Cross Comparison Guide for Results of Neutron SEE Testing of Microelectronics Applicable to Avionics .... 50 E. Normand, Boeing; L. Dominik, Honeywell

Commercially Designed and Manufactured SDRAM SEE Data ...... 58 C. Hafer, M. Von Thun, M. Leslie, F. Sievert, A. Jordan, Aeroflex

SEE Testing of National Semiconductor's LM98640QML System on a Chip for Focal Plane Arrays and Other Imaging Systems ...... 63 K. Kruckmeyer, R. Eddy, A. Szczapa, B. Brown, T. Santiago, National Semiconductor

Single Event Latchup (SEL) and Total Ionizing Dose (TID) of a 1 Mbit Magnetoresistive Random Access Memory (MRAM) ...... 71 J. Heidecker, G. Allen, D. Sheldon, Jet Propulsion Laboratory, California Institute of Technology

TID and SEE Responses of Rad-Hardened A/D Converters ...... 75 G. Chaumont, A. Uguen, C. Prugne, STMicroelectronics; F. Malou, CNES

Total Dose and Single Event Testing of a Hardened Point of Load Regulator ...... 80 N. W. van Vonno, L. G. Pearce, J. S. Gill, H. W. Satterfield, E. T. Thomson, T. E. Fobes, A. P. Williams, P. J. Chesley, Intersil Total Dose and Single Event Testing of a Hardened Single-Ended Current Mode PWM Controller ...... 88 N. W. van Vonno, L. G. Pearce, G. M. Wood, J. D. White, E. J. Thomson, T. M. Bernard, P. J. Chesley, R. Hood, Intersil

Single Event and Low Dose-Rate TID Effects in the DS16F95 RS-485 Transceiver ...... 94 A. T. Kelly, P. R. Fleming, R. D. Brown, BAE Systems; F. Wong, Space Systems Loral

Radiation Test of 8 Bit Microcontrollers ATmega128 & AT90CAN128 ...... 100 A. Schüttauf, S. Rakers, C. Daniel, EADS ASTRIUM-ST

ELDRS Characterization for a Very High Dose Mission ...... 104 R. D. Harris, S. S. McClure, B. G. Rax, D. O. Thornbourn, K. B. Clark, T.-Y. Yan, Jet Propulsion Laboratory; A. J. Kenna, Northrop Grumman Space Technology

The Effects of ELDRS at Ultra-Low Dose Rates ...... 111 D. Chen, J. D. Forney, A. M. Phan, M. A. Carts, MEI/NASA-GSFC; R. L. Pease, RLP Research; S. R. Cox, K. LaBel , NASA-GSFC; K. Kruckmeyer, National Semiconductor; S. Burns, R. Albarian, Linear Technology; B. Holcombe, B. Little, J. Salzman, Texas Instruments; G. Chaumont, H. Duperray, A. Ouellet, ST Microelectronics

Total Ionizing Dose and Displacement Damage Compendium of Candidate Spacecraft Electronics for NASA ...... 117 D. J. Cochran, D. Chen, H. S. Kim, M. J. Campola, M. V. O'Bryan, MEI Technologies, Inc.; T. R. Oldham, Dell Perot Systems ; A. B. Sanders, K. A. LaBel, C. J. Marshall, J. A. Pellish, M. A. Carts, NASA/GSFC; S. P. Buchner, Global Defense Technology and Systems, Inc.

Comparison of TID Response of Micron Technology Single-Level Cell High Density NAND Flash Memories ...... 125 D. N. Nguyen, F. Irom, NASA/CalTech/Jet Propulsion Lab

Performance of Commercial Off-the-Shelf Microelectromechanical Systems Sensors in a Pulsed Reactor Environment ...... 129 K. E. Holbert, Arizona State University; A. Sharif Heger, S. S. McCready, Los Alamos National Laboratory

Radiation Hardness Characterization of a 130nm ASIC Library Technology ...... 137 R. Dumitru, C. Hafer, T.-W. Wu, R. Rominger, H. Gardner, P. Milliken, K. Bruno, T. Farris, Aeroflex Colorado Springs

Radiation Performance of Commercial SiGe HBT BiCMOS High Speed Operational Amplifiers ...... 142 D. Chen, A. Phan, H. Kim, MEI/NASA-GSFC; J. Pellish, K. LaBel , NASA-GSFC; S. Burns, R. Albarian, Linear Technology; B. Holcombe, B. Little, J. Salzman, Texas Instruments; P. Marshall, Consultant

Radiation Testing a Very Low-Noise RHBD ASIC Electrometer ...... 147 A. R. Jones, D. O'Connor, E. Thiemann, V. A. Drake, G. Newcomb, N. White, S. Dooley, S. Finkelstein, P. Haskins, V. Wei Hsu, B. Kirby, T. Reese and P. Soto Hoffmann, University of Colorado; D. D. Aalami, Space Instruments; H. L. Clark, Texas A&M University; R. L. Ladbury, NASA; B. von Przewoski, Indiana University

Hardening of Texas Instruments' VC33 DSP ...... 153 R. Fuller, W. Morris, D. Gifford, R. Lowther, J. Gwin, Silicon Space Technology; J. Salzman, Texas Instruments; D. Alexander, K. Hunt, AFRL SEU Testing of SiGe Bipolar and BiCMOS Circuits ...... 158 D. L. Hansen, A. Le, K. Chesnut, E. Miller, S. Pong, S. Sung, J. Truong, Boeing

Single Event Transient and ELDRS Characterization Test Results for LM4050QML 2.5V Precision Reference...... 164 K. Kruckmeyer, E. Morozumi, R. Eddy, T. Trinh, T. Santiago, National Semiconductor; P. Maillard, Vanderbilt University

Cummulative Index ...... 171

Author Index ...... 191

Guide to the 2009 IEEE Radiation Effects Data Workshop Record

David M. Hiemstra, Senior Member, IEEE

Single Event Latchup (SEL) Abstract-- The 2009 Workshop Record has been reviewed and Single Event Burnout (SEB) a table prepared to facilitate the search for radiation response Single Event Gate Rupture data by part number, type, or effect. (SEGR) − Dose rate I. INTRODUCTION − Displacement Damage N this paper a Guide to the 2009 Radiation Effects Data Protons I Workshop (REDW) Record is provided [1]. The Neutrons Workshop Record (WR) published each year is a permanent • Facilities archive of the REDW. It serves as a key source of radiation • Standard response data for the radiation effects community (REC). It • Environment also provides descriptions of radiation effects test facilities, • Shielding standards, and environments. Although the record provides a cumulative index that can be used to locate papers based on II. RESPONSE DATA SEARCH author and title it is difficult to search for response data on a This paper contains the Table for REDW 2009 in Table I. particular part number, type, or radiation effect. To simplify Tables for all WR’s are available on the NSREC website this search as an ongoing effort each year a table is prepared for that year’s WR [2-5]. In this table the following http://www.nsrec.com/redw/. The tables are provided in information is provided for each paper: Portable Document Format (pdf) and a search can simply be • Cumulative Index Number performed using capabilities built into the Adobe Acrobat • Page number in Workshop Record software. Once the paper(s) with the response data required • Name of first author has been located it is the radiation effects engineer’s • Part Number(s) responsibility to perform a detailed review to establish applicability of the response data. Individual copies of the • Part Type(s) ® • Manufacture(s) full papers are available online at IEEE Xplore . • Data − Terrestrial or Flight III. 2009 WORKSHOP RECORD SUMMARY • Radiation Effect(s) Evaluated The 2009 Workshop Record has thirty high quality papers. − Total Ionizing Dose It provides: radiation response data on a wide range of Co60 High Dose Rate devices, circuits, and systems, test facilities descriptions, and Co60 Low Dose Rate (ELDRS) dosimetry. x-ray pions IV. CONCLUSIONS Protons The Guide to the 2009 IEEE Radiation Effects Data Electrons Workshop provides an efficient way to search for response − Single Event Effects due to: heavy ions, data on a particular part number, type, or radiation effect. protons, neutrons, and laser Single Event Upset (SEU) V. REFERENCES Single Event Transient (SET) Single Event Functional Interupt [1] 2009 IEEE Radiation Effects Data Workshop Record, S. Armstrong, Editor, New Jersey, IEEE, 2009. (SEFI) [2] D. Hiemstra, “Guide to the IEEE Radiation Effects Data Workshop Record,” IEEE REDW, pp. 1-5, 2006. [3] D. Hiemstra, “Guide to the 2006 IEEE Radiation Effects Data Manuscript received July 19, 2010. The author gratefully acknowledges Workshop Record,” IEEE REDW, pp. 211-214, 2007. the financial support of MDA Space Missions to attend NSREC. [4] D. Hiemstra, “Guide to the 2007 IEEE Radiation Effects Data D. M. Hiemstra is with MDA Space Missions, Brampton, Ontario L6S4J3 Workshop Record,” IEEE REDW, pp. 1-4, 2008. Canada (telephone: 905-790-2800, e-mail: [5] D. Hiemstra, “Guide to the 2008 IEEE Radiation Effects Data [email protected]). Workshop Record,” IEEE REDW, pp. 1-5, 2009.

TABLE I REDW 2009 REDW2009 Revision 1.0, Jan. 10/2010 Prepared by: David M. Hiemstra [email protected] Data Total Ionizing Dose, X-xray, P-pions Single Event Effects, H-heavy ion, P-proton, L-laser, N-neutrons Displacement Damage Facilities Standard Environment Shielding Paper No., Page Terrestrial Flight Co60 ProtonsElectrons SEU SET SEFI SEL SEB SEGR Dose Rate Protons Neutrons No. First Author Part No. Type Manufacture ELDRS 1, pp. 1-5 D. Hiemstra Guide to the Radiation Effects Data Workshop 2009 2, pp. 5-11 J. Bird 4N55 Optocoupler Avago √√ LM119 Voltage Comparator National Semiconductor √√√ LM158 Operational Amplifier National Semiconductor √√√ LM158A Operational Amplifier National Semiconductor √√√ AD620 Instrumentation Amplifier Analog Devices √√ AD580LH Voltage Reference Analog Devices √√ AD588TQ Voltage Reference Analog Devices √√ AD1671 12 bit DAC Analog Devices √√ OM1850 Low Dropout Voltage Regulator International Rectifier √√ EL7457 Quad CMOS Driver Intersil √√ OP400 Operational Amplifier Analog Devices √√ AD630 Balanced Modulator/Demodulator Analog Devices √√ 2N3019 NPN Transistor Microsemi √√ 3, pp. 12-14 J. Bird PA07 Power Operational Amplifier Apex √ √H REF02 Voltage Reference Analog Devices √√H IS-2981 8-Channel Source Driver Intersil √√H EL7457 Quad CMOS Driver Intersil √ √H 4. pp. 15-24 M. O'Bryan MAX997 Voltage Comparator Maxim √√H √H DG390 Analog Switch Maxim √√H √H SG1845 Pulse Width Modulator Microsemi √√H √H SG1846 Pulse Width Modulator Microsemi √√H √H AD822 Operational Amplifier Analog Devices √√H LM124 Operational Amplifier National Semiconductor √√H LM139 Operational Amplifier Texas Instruments √√H ADG526A Analog Multiplexer Analog Devices √√H √H UC1708 Power MOSFET Driver Texas Instruments √√H RH1086 Voltage Regulator Linear Technology √√H √H RI1773 Power MOSFET Driver International Rectifier √√H √H APT50M38PLL Power MOSFET Microsemi √ √H IRH7250 Power MOSFET International Rectifier √ √H AFL12028 DC-DC Converter International Rectifier √√H √H ADC14155W-MLS 14 bit ADC National Semiconductor √√H √H ADS5424 14 bit ADC Texas Instruments √√H,P √H √H MT29F4G08AAAWP 4 Gbit Flash Micron √√H √H K9F4G08U0A 4 Gbit Flash Samsung √√H √H EDS5108ABTA SDRAM Eplidia √√H √H √H Test Structure SRAM IBM √√H √H Test Structure SRAM IBM √√H,P Test Structure SRAM Texas Instruments √√H,P √H XC4VLX25-10FF668 FPGA Xilinx √√H,P √H MAX367 Oscillator Circuit Protector √√H HMP1-155TRX Fiber Optic Transceiver Space Photonics √√P ISC9803 and QWIP ROIC Indigo and GSFC √√P 5. pp. 25-31 D. Cochran AFL12028SX/CH DC-DC Converter International Rectifier √√ AD822 Operational Amplifier Analog Devices √√ RM158 Operational Amplifier National Semiconductor √√ ADG526A Analog Multiplexer Analog Devices √√ K9F8G08U0A 8 Gbit Flash Samsung √√ MT29F4G08AAAWP 4 Gbit Flash Micron √√ K9F8G08U0M 8 Gbit Flash Samsung √√ MT29F4G08AAA 4 Gbit Flash Micron √√ HY27UF084G2M 4 Gbit Flash Hynix √√ MT29F4G08AAAWP 4 Gbit Flash Micron √√ EDE1104AB-50-E 1 Gbit SDRAM Eplidia √√ K4T1G044QA-ZCD5 1 Gbit SDRAM Samsung √√ K9K8G08U0A 8 Gbit Flash Samsung √√ UC1875JQMLV PWM Controller Texas Instruments √√ CD54HCT4046A Phase Locked Loop Texas Instruments √√ XPA-11 Prototype AMIS √√ APT50M38JLL Power MOSFET Microsemi √√ 2N5157 NPN Bipolar Transistor Microsemi √√ Test Structure SIRF Test Transistor Xilinx √√ 2N2907 PNP Bipolar Transistor Microsemi √√ 2N2222 NPN Bipolar Transistor Microsemi √√ RadFET NMRC √√ LM139 Voltage Comparator National Semiconductor √√ TPS5420 Switching Regulator Texas Instruments √√ RH1021CMH-5 Voltage Reference Linear Technology √√ RH1021CMW-5 Linear Technology Linear Technology √√ LP2951 Low Dropout Regulator National Semiconductor √√ TPS79133 Low Dropout Regulator Texas Instruments √√ MT9T001P12STC CMOS Imager Micron √√ KAC9628 CMOS Imager Kodak √√

TABLE I (CONTINUED) REDW 2009 Data Total Ionizing Dose, X-xray, P-pions Single Event Effects, H-heavy ion, P-proton, L-laser, N-neutrons Displacement Damage Facilities Standard Environment Shielding Paper No., Page Terrestrial Flight Co60 Protons Electrons SEU SET SEFI SEL SEB SEGR Dose Rate Protons Neutrons No. First Author Part No. Type Manufacture ELDRS 6. pp. 32-38 A. Aaron AD5670 8 bit ADC Analog Devices √√√ AD670 8 bit ADC Analog Devices √√√ AD574 12 bit ADC Analog Devices √√√ LTC1417 14 bit ADC Linear Technology √√√ LTC1419 14 bit ADC Linear Technology √√ LTC1604 16 bit ADC Linear Technology √√ LTC1608 16 bit ADC Linear Technology √√ AD8138 Differential ADC Driver Analog Devices √√√ AD7714 24 bit ADC Analog Devices √√ LS2812D DC-DC Converter International Rectifier √√√ LS2805S DC-DC Converter International Rectifier √√√ LS2803R3S DC-DC Converter International Rectifier √√√ LS2805R3S DC-DC Converter International Rectifier √√ LS2805S DC-DC Converter International Rectifier √√ LS2812D DC-DC Converter International Rectifier √√ LF198 Sample and Hold National Semiconductor √√√ 2N3700 NPN Bipolar Transistor Semicoa √√ 2N3700 NPN Bipolar Transistor ST Microelectronics √√ 2N3700 NPN Bipolar Transistor New England Micro √√ AD832 Operational Amplifier Analog Devices √√ LT1211 Operational Amplifier Linear Technology √√ LM124 Operational Amplifier National Semiconductor √√√ OP97 Operational Amplifier Analog Devices √√ OP484 Operational Amplifier GD √√ AD648 Operational Amplifier Analog Devices √√√ OP400 Operational Amplifier Analog Devices √√ RH1498 Operational Amplifier Linear Technology √√ RH1078 Operational Amplifier Analog Devices √√ MC350272 Operational Amplifier Motorola √√ RH1814 Operational Amplifier Linear Technology √√ AD829 Operational Amplifier Linear Technology √√ EDS5104ABTA-75 512 Mbit SDRAM ELPIDA √√ RH119 Voltage Comparator Linear Technology √√√ LM193 Voltage Comparator National Semiconductor √√√ PM139 Voltage Comparator Analog Devices √√ LP2951 Low Dropout Regulator National Semiconductor √√ LP2953 Low Dropout Regulator National Semiconductor √√√ LM2941 Low Dropout Regulator National Semiconductor √√√√ RH117 Voltage Regulator Linear Technology √√√ RH137 Voltage Regulator Linear Technology √√√ RH117 Voltage Regulator Linear Technology √√ LM1577K Switching Regulator National Semiconductor √√√ LP2953 Low Dropout Regulator National Semiconductor √√ MAX708 Power Supply Supervisor Maxim √√ UC1845 Pulse Width Modulator Controller Texas Instruments √√ FZT458 NPN Bipolar Transistor Zetex √√ FZT958 PNP Bipolar Transistor Zetex √√ MRF901 NPN Bipolar Transistor Motorola √√ √ LS401 JFET Linear Systems √√ LSK398 JFET Linear Systems √√ 2N918 NPN Bipolar Transistor AEI √√ 2N3251A PNP Bipolar Transistor Microsemi √√ 2N4391 JFET Linear Systems √√ 2N4393 JFET Linear Systems √√ AD667 12 bit ADC Analog Devices √√√ DAC8413 12 bit DAC Analog Devices √√ OMH3040 Hall Effect Switch Optek √√√ AD537 Voltage to Frequency Converter Analog Devices √√√ RTSX72SU FPGA Actel √√ IDTQS4A210 Multiplexer/DeMultiplexer Integrated Device Technology √√ MAX306 Analog Multiplexer Maxwell √√ AD590 Temperature Sensor Analog Devices √√√ LT1019 Voltage Reference Linear Technology √√√ LM113 Voltage Reference National Semiconductor √√√ LM136 Voltage Reference National Semiconductor √√ AD652 Voltage to Frequency Converter Analog Devices √√√ AD606 Logarithmic Amplifier Analog Devices √√√ LMD18200 Full Bridge Driver National Semiconductor √√√ TC4423 Power MOSFET Driver Microchip √√ 7. pp. 39-41 A. Tipton AD7943 12 bit DAC Analog Devices √ √H √H AD9740 10 bit DAC Analog Devices √√ √H AD9705 10 bit DAC Analog Devices √√ √H √H AD9763 10 bit DAC Analog Devices √√ AD9911 Frequency Synhesizer Analog Devices √√ √H AD4252 Frequency Synhesizer Analog Devices √√ √H √H 8. pp. 42-46 G. Chaumont RHF43B Operational Amplifier ST Microelectronics √√√ √H RHF310 Operational Amplifier ST Microelectronics √√√ √H

TABLE I (CONTINUED) REDW 2009 Data Total Ionizing Dose, X-xray, P-pions Single Event Effects, H-heavy ion, P-proton, L-laser, N-neutrons Displacement Damage Facilities Standard Environment Shielding Paper No., Page Terrestrial Flight Co60 Protons Electrons SEU SET SEFI SEL SEB SEGR Dose Rate Protons Neutrons No. First Author Part No. Type Manufacture ELDRS 9. pp. 47-50 K. Kruckmeyer LM136-2.5 Voltage Reference National Semiconductor √√√ 10. pp. 51-58 M. Alvarez LM4132AMF-3.3 Voltage Reference National Semiconductor √√ LM4128AMF-3.3 Voltage Reference National Semiconductor √√√ LM4129AIM5-3.3 Voltage Reference National Semiconductor √√√ LM4120AI5-1.8 Voltage Reference National Semiconductor √√√ 11. pp. 59-64 K. Kruckmeyer LM2941WGRLQMLV Voltage Reference National Semiconductor √√√ 12. pp. 65-70 K. Kruckmeyer LM139AxLQMLV Voltage Comparator National Semiconductor √√H,L 13. pp. 71-75 R. Lawrence Test Structure Trench Oxide Capacitor 90nm √ √H 14. pp. 76-81 L. Selva 2SK4217 Power MOSFET Fuji Electric Drive Co. √ √H √H 2SK4152 Power MOSFET Fuji Electric Drive Co. √ √H √H 2SK4155 Power MOSFET Fuji Electric Drive Co. √ √H √H 2SK4158 Power MOSFET Fuji Electric Drive Co. √ √H √H 2SK4217 Power MOSFET Fuji Electric Drive Co. √ √H √H 2SK4152 Power MOSFET Fuji Electric Drive Co. √ √H √H 2SK4155 Power MOSFET Fuji Electric Drive Co. √ √H √H 2SK4158 Power MOSFET Fuji Electric Drive Co. √ √H √H 15. pp. 82-93 L. Scheick IRHNJ597130 Power MOSFET International Rectifier √ √H √H IRHLF77110 Power MOSFET International Rectifier √ √H √H IRHNJ57133SE Power MOSFET International Rectifier √ √H √H JANSR2N7498T2 Power MOSFET International Rectifier √ √H √H IRHMB57260SE Power MOSFET International Rectifier √ √H √H IRHF7230 Power MOSFET International Rectifier √ √H √H IRHNJ57230 Power MOSFET International Rectifier √ √H √H IRHNA57264SE Power MOSFET International Rectifier √ √H √H IRF9530PBF-ND Power MOSFET International Rectifier √ √H √H IRF3315PBF-ND Power MOSFET International Rectifier √ √H √H 497-4339-5-ND Power MOSFET ST Microelectronics √ √H √H IRHF7430SE Power MOSFET International Rectifier √ √H √H 16. pp. 94-98 C. Oudea MS8002 MEMS Accelerometer Colybris √√√H, P 17. pp. 99-102 C. Poivey SOIS Optical Transceiver 1 Mbps DAS Photonics √√ √ √ P SOIS Optical Transceiver 1 Mbps DAS Photonics √√ √ √P 18. pp. 103-105 R. Katti 1 Mb MRAM Honeywell √√ √H 19. pp. 106-113 J. Schaefer KM44V16004AK-6 64Mb DRAM Samsung √√√√H, P KM44V16004BK-6 64Mb DRAM Samsung √√√√H, P KM44V16004DK-6 64Mb DRAM Samsung √√√√H, P KM44S32030AT-GL 128M DRAM Samsung √√√√H, P HM5225405BTT75 256M DRAM Hitachi √√√√H, P 20. pp. 114-122 T. Oldham K9F4G08U0APCB0 4Gb Flash Samsung √√ √H √H √H MT29F4G08AAWP 4Gb Flash Micron √√ √H √H √H 21. pp. 123-126 R. Lawrence Test Structure 512 kb SRAM BAE Systems √√H, P 22. pp. 127-132 R. Koga uPD4382322 8 Mb SRAM NEC √√ √H, P √H, P √H, P IDT71V67603 9 Mb SRAM Integrated Device Technology √√ √H, P √H, P √H, P CY7C1360A 9 Mb SRAM Cypress √√ √H, P √H, P √H, P 23. pp, 133-135 D. Hiemstra TMD320C6713 Digital Signal Processor Texas Instruments √√√P 24. pp. 136-139 D. Admas W28C0108 128KB EEPROM Northrop Grumman Corp √√ √H √H √√ 25. pp. 140-147 J. George RTAX-2000S-CQ352E FPGA Actel √√√H, P √H 26. pp. 148-151 C. Hafer LEON 3FT Microprocessor Aeroflex Gaisler √√H 27. pp. 152-156 M. Campola RadFET NMRC √√ Test Structure SiRF Test Transistor Xilinx √√ LM317 Voltage Regulator Texas Instruments √√ 28. pp. 157-160 E. Blackmore Large Area Neutron Beam TRIUMF √ 29. pp. 161-165 E. Cascio Farady Cup Francis H. Burr Proton Therapy √ 30. pp. 166-173 A. Prokofiev ANITA Neutron Source The Svedlerg Laboratory √ Once the paper with the response data required has been located it is the radiation effects engineer’s responsibility to perform a detailed review to establish applicability.

Recent Results for PowerPC Processor and Bridge Chip Testing

Steven M. Guertin and Farokh Irom, Member, IEEE

interrupts (SEFI). This paper identifies the leading radiation Abstract-- Recent single event effect (SEE) test results for the sensitivities for the tested devices and provides the cross Freescale 7447A and IBM 750FX microprocessors, and Marvell sections for the SEEs causing them. It is up to an application 64460 bridge chips are reported. The 7447A and 750FX results to interpret the impact of each type of SEE on a given design. are compared to earlier work. The 64460 represents unique For this work, the 7447A data represents first data on this data. The data extraction methods for each test type are described. The 7447A and 750FX were found to have a single device, though other devices in its family have been reported event upset (SEU) threshold of about 1 MeV-cm2/mg and on before [9]. The IBM 750FX has been tested previously saturated cross section of 2x10-9 cm2/bit. Both devices have [10]. This work focuses on a more recently produced 750FX proton cross sections of about 10-14cm2/bit and proton thresholds and includes detailed testing of the error detection and below 20 MeV. The 64460 was shown to have functional correction (EDAC) protection of the device’s L2 cache. The interrupts similar to single event latchup with threshold below 1 750FX L2 cache has no user registers to monitor its MeV-cm2/g and saturated cross section around 1 cm2. correction capabilities – this requires special analysis methods to extract test data. The Marvell 64460 bridge chip I. INTRODUCTION has not been reported on for radiation effects previously. In owerPC processors are used in spacecraft, are available the particular case of the bridge chip, it was not possible to Pin preconfigured radiation-hardened computer systems, gain access to the manufacturer’s data sheet, so the data and are under consideration for new flight projects [1-4]. presented is that which can be gained through testing of This work includes data taken for the Space Technology 8 publicly documented interfaces. (ST8) project and Orion program. When used in space This paper continues with a description of the test applications, the sensitivity of these devices to single event effects (SEEs) must be understood to a degree consistent with approach for the three devices. General information about the application. how testing was performed follows. A brief section on For this work we concentrate on test methods for radiation extraction of data from fault tolerant structures is presented. evaluation of the processors and one of their potential bridge Test results are then presented for heavy ions and protons. chips. The methods discussed here are then used to develop Following this, the workshop discusses key findings and SEE data on the target devices. Most of the other supporting details of the testing including unexpected frequency devices for computer systems are tested and reported in other dependence observed in the 750FX, and single event function places and are periodically reported in compendia [5-8]. interrupts (SEFIs). For these devices, the SEEs involve data bit errors, changes in configuration, loss of internal machine state, and II. TEST APPROACH possibly single event latchup (SEL). Most upsets in the test SEE data taken on the devices under consideration seek to devices manifest as bits with corrupt values (single big upsets provide potential users with the information necessary to – or SBU). This holds for both direct upset of a bi-stable calculate rates for the most common events a system will see. element, and also for single event transient (SET)-induced Similarly, it is important to verify operation of the test upsets. Because some bits in these devices control the devices’ fault tolerance (FT) features. Cross sections for FT operating state of the device, it is also true that SBUs may be events are not of direct importance and testing must continue indistinguishable form more intrusive single event functional in invasiveness to find the next level of faults exhibited by the test devices. Once the FT mechanisms are shown to work Manuscript received July 16, 2010. The research in this paper was carried care must be taken to ensure that the non-space-like out by the Jet Propulsion Laboratory, California Institute of Technology, laboratory event rates do not overload the FT elements and under contract with the National Aeronautics and Space Administration. This work was supported in part by the Orion and ST8 Programs. contribute erroneously to other error measurements. Steven M. Guertin is with the Jet Propulsion Laboratory, California The general approach is then to do the following: Verify Institute of Technology, Pasadena, CA 91109 (USA), phone: 818-393-6895, operation of FT systems on the devices. Measure the cross e-mail: steven.m.guertin@jpl.nasa.gov. Farokh Irom is with the Jet Propulsion Laboratory, California Institute of section for non-FT bit elements such as processor registers Technology, Pasadena, CA 91109 (USA), phone: 818-354-7463, e-mail: and configuration bits. Measure the cross section for errors [email protected]. during operation of devices and compare those to the bit- © 2010 California Institute of Technology. Government sponsorship acknowledged. element event rates (this allows identifying the type of upset

that is most likely to occur in an operating system). And Indiana University Cyclotron Facility (IUCF). Table 1 gives finally provide cross section information for general an overview of test devices exposed at these facilities. All execution failure (SEFI) in the devices. Because SEFIs may testing was performed at normal incidence (multiple LETs be caused by bit upsets in “important” bits, often SEFI and energies are due to degraders and tuning). information cannot be separated from background bit upsets. TABLE I The devices discussed in this workshop are similar in that BEAMS USED ON THE TEST DEVICES their complexity necessitates test circuits that are essentially full computers. Due to constraints on the test campaign, it was determined the data could best be taken using commercially-available single board computers. The computer is used to test itself by running algorithms designed to sensitize target internal structures. This is essentially the approach developed by JPL under the Remote Exploration and Experimentation program and is closely related to the method used in [11]. There are several other test methods that may prove adequate, in the event that custom test circuits are built [12-15]. All of the devices reported here have some degree of error protection. In error protection scenarios, some of the alternative approaches will significantly overestimate rates of systems with built-in error protection. The test methods that are the most rigorous (such as test-vector [12,13] or lock-step tests [14]) will overestimate upset rates because FT recovery does not match the test vectors. However, system-level testing for impact of upsets is at risk to find the problems with the test code more than the test device. For these reasons, and standard project constraints, the test approach used was to obtain a commercial board employing the test device, and run targeted custom test code on it. Use of the data, however, may require analyzing fault recovery effects.

III. TEST SETUP

Fig. 2. An Xpedite6031 board is shown in position at UCD. In this image the Freescale 7447A is exposed by a hole cut in the aluminum heat sink. For runs using the Marvell 64460 another heat sink was used.

For the Freescale 7447A and Marvell MV64460, the test Fig. 1. A schematic of the operation of the Xpedite6031 is shown. The processor test devices are sensitized and monitored by applications running board was the Xpedite6031 single board computer (SBC) on the 6031. An ATX power supply was used for board power. A similar [16]. For the IBM 750FX, the test board used was the system was used for testing the IBM 750FX. Advanet ADVME7509A [17]. The implementation of the

Testing was conducted with heavy ions at the Texas A&M Xpedite6031 can be seen in Fig. 1. A photo of the University cyclotron (TAMU). Testing with protons was Xpedite6031 in place for testing at UCD is shown in Fig. 2. conducted at University of California, Davis (UCD), and The ADVME7509A implementation is similar. A picture of

an ADVME7509 is given in Fig. 3. The processor is under For the IBM 750FX there are a few things to point out. the heat sink on the left side of the image. The bit upset testing is essentially identical to the 7447A except that other register bits were used to take the place of the Altivec registers since the 750FX does not have Altivec. Also during bit upset testing of the 750FX the L2 cache was tested. The test code and analysis was designed to work with the parity in the L1 cache and EDAC in the L2 cache in order to collect data. The 750FX’s dual PLL system was also used for on-the-fly switching for testing at 667, 600, and 400MHz. Finally, the 750FX testing also included a special test for the floating point unit (FPU) that deserves comment. Most algorithms to test FPU operation include only a few percent FPU instructions. For the operational testing of the 750FX an FPU algorithm was selected with greater than 98% FPU

Fig. 3. An ADVME7509A board is shown. The IBM750FX is under the instructions. During the testing the processor calculated the heat sink on the left side of the image. The heat sink is removed for elements of a Mandelbrot sequence xn = xn-12 + C, where C = irradiation. -0.525 - 0.5i. (The floating point representations are C = RE For this work, only the MV64460 was delidded. The 0xbfe0_cccc_cccc_cccd, CIM = 0xbfe0_0000_0000_0000.) positioning of the microprocessors on the test boards proved The calculation was carried out 16 times per loop, with to not allow thinning. Thus backside irradiation was limited 524288 cycles of the loop. The real part of the final value, to ions that could fully penetrate the 900 micron thick die. x8388609 is compared to 0xbfe6_901a_78d1_c4d1. Although originally delidded, the MV64460 proved to be impossible to test above LET = 8 MeV-cm2/mg, which could IV. FT DATA EXTRACTION be accomplished by irradiating through the packaging. Thus A. Parity the device was tested both through the package and delidded. In order to verify parity protection systems during this Testing was accomplished by loading special test programs testing we took the following approach. The test plan was into the test board. These test programs were designed to test “two-stage”. The first stage was to disable the parity some specific operations or bits in the target device. They are protection and collect upset data. The second stage was to optimized for radiation testing to limit the risk of general enable the parity protection while running a test program, and software problems during testing. observe the parity exception rate. Test applications generally fall into one of two categories. This approach was partially used on the 7447A and fully The first is the bit upset test. In this type of test a specific set used on the 750FX L1 data and instruction caches. Testing of of bits is prepared with known values, the device is exposed the 750FX showed that all parity events led to recoverable to radiation, then the bits are interrogated to identify bits operations (provided the parity handler was able to recover whose values have changed. The second type of test is an the test operation – which it was designed to do). In real operational test. In this test the processor is conFig.d to systems, the impact of a parity event is undefined at the perform some operation. The output of that operation is machine state, but it is possible to design software such that it verified periodically to identify functional errors. can be rolled back to a known machine state in the event of a For the Freescale 7447A only bit upset testing was parity event. performed. The data cache, floating point, and Altivec registers were loaded with known values before irradiation. B. EDAC The processor was then irradiated. After irradiation the Since there was no available telemetry on the operation known values were interrogated for bit upsets. of the ECC system during single bit upsets, and the L2 cache For the Marvell 64460 two types of testing were performed seemingly becomes unstable in attempts to continue access simultaneously. First, the configuration space of the bridge following an ECC uncorrectable event, the cross section for chip was recorded (recall the datasheet was unavailable). single bit upsets was determined by the address at which the This region was monitored without beam to determine those first double-bit error occurred. That is, the address where the regions that change so that a test mask could be made. Then first double-bit upset is observed gives an estimate for the changes to the normally unchanged bits provided a basis for error density in the part. The formula for the cross section, observing changes in the configuration. The second test was based on the address of the first double bit error is given to monitor for bit upsets in the SRAM that is in the bridge below in Equation 1 chip. The SRAM is written to a known pattern before 1 irradiation. Following irradiation it is read to identify upsets. σ = (1) bit Φ 1/ 2 The SRAM is single bit correction double bit protection 18 2 ADDRECC (SECDED) protected. There are counters in the 64460 to monitor actions of this EDAC but we were not able to read them due to lack of datasheet.

where σbit is the per-bit cross section, Φ is the fluence, and ADDRECC is the address of the ECC/EDAC uncorrectable (in bytes). Using this formula we were able to compare cross sections for L1 and L2 cache bits in the 750FX. The results agreed within 25%, which is within the statistical significance due to the limited number of EDAC events observed.

V. RESULTS A. General Results During this testing several key observations were made. This section summarizes those observations. The saturation cross section for all types of testing occurred at LETs below 14 MeV-cm2/mg. The general behavior was similar to earlier testing of PowerPC processors and enabled us to perform testing without thinning devices. Fig. 4. L1 Data Cache heavy ion upset sensitivity for the 7447A. The ‘1’ The Marvell 64460 had a obtrusive SEFI whose cross section to ‘0’ upset data is shifted by 0.2 in LET for readability. The curve represents the 2006 results for the Motorola 7457. was so large at LET = 8 that it was not possible to perform test runs without triggering. Cross sections for the Freescale 7447A and IBM 750FX were collected while in sleep mode and while operating a simple loop. The cross sections were found to be the same. When running the simple test programs used here, which have built-in fault tolerance, there was no significant SEFI risk observed on the microprocessors. This is consistent with earlier testing of PowerPCs which found that the test board and circuit construction were important to real SEFI observation. It should be noted that real applications will get SEFI-like observations due to configuration SBUs. The test programs did see a handful of crashes (defined by having to reset the processor) but these generally only occurred after the register bits show dozens of bit errors, meaning the executing program was at risk for corruption. FT systems worked on these devices. The parity Fig. 5. L1 Data Cache proton upset sensitivity for the 7447A. The data is operations of the 7447A and 750FX L1 caches were observed averaged between ‘0’ to ‘1’ due to low number of counts. to work correctly. The EDAC operation of the 750FX L2 cache and the Marvell 64460 worked well (the 64460 SRAM data showed virtually no upsets and the few events where there were upsets often included two bit upsets at a time). B. Freescale 7447A Results Using the bit upset test methods described above, the 7447A was tested for register and L1 bit upsets. The testing was performed using heavy ions at Texas A&M University (TAMU), and with protons at UC Davis (UCD) and the Indiana University Cyclotron Facility (IUCF). Due to the flip-chip construction of the 7447A, heavy ion irradiations were limited to linear energy transfer (LET) below 20 MeV- cm2/mg.

Fig. 6. Register bit heavy ion upset sensitivity for the 7447A. The ‘1’ to ‘0’ upset data is shifted by 0.2 in LET for readability. Points with no marker are only an upper bound.

Fig. 8. L1 Data Cache heavy ion upset sensitivity for the IBM 750FX. The 2002 results are shown as dotted lines.

Fig. 7. Register bit proton upset sensitivity for the 7447A. Points with no marker are only an upper bound. Most data points represent only a few counts.

The 7447A is probably most comparable to the Motorola 7457, in regards to existing radiation data [11]. Fig. 4 shows the L1 data cache test results for the 7447A, and compares the data to the 2006 7457 results. Fig. 5 shows the proton sensitivity for the L1 data cache. Fig. 6 shows the register test results, again compared to the 7457 results. It should be noted that this device continues the asymmetry between ‘0’ to ‘1’ and ‘1’ to ‘0’ error sensitivity. The final data for the 7447A is in Fig. 7 where the register proton sensitivity is shown. There are several energies where no proton upsets Fig. 9. L1 Data Cache proton upset sensitivity for the IBM 750FX. The were seen. These are represented by lines with no data 2002 results are shown as dotted lines. points. During testing any single event functional interrupts (SEFIs) were noted. There were fewer than 7 SEFIs over about 250 test runs, and these could not be separated from potential register bit upsets. The SEFIs corresponded to a heavy ion cross section of 3x10-7 cm2/dev, and a limiting proton cross section of 3x10-11cm2/dev (no SEFIs observed with protons). C. IBM 750FX Results Using the bit upset test methods described above, the 750FX was tested for register, L1 and L2 bit upsets. The testing was performed using heavy ions at TAMU, and with protons at UCD and IUCF. Due to the flip-chip construction of the 750FX, heavy ion irradiations were limited to linear 2 Fig. 10. Register heavy ion upset sensitivity for the IBM 750FX. ‘0’ to energy transfer (LET) below 20 MeV-cm /mg. ‘1’ were found to be about 8 times lower than ‘1’ to ‘0’, which is consistent The 750FX was tested in 2002 [9]. Fig. 8 shows the L1 with 2002 findings, and opposite of the data for the 7447A. data cache heavy ion test results for the 750FX, and compares the data to the 2002 results. Fig. 9 shows the L1 data cache proton test results. After careful extraction of L2 data, the cross section for L2 bit upsets was the same as L1. Fig. 9 shows the register test results, again compared to the 2002 results. This device also continues the asymmetry between ‘0’ to ‘1’ and ‘1’ to ‘0’ error sensitivity. The asymmetry observed in the 750FX is in the opposite direction to that observed in the 7447A.

Fig. 11. Register proton upset sensitivity for the IBM 750FX. The observed asymmetry from the heavy ion results continues. These data are Fig. 13. Register proton upset sensitivity for the MV64460 is shown. consistent with 2002 findings.

During heavy ion testing there were 3 observed SEFIs which corresponded to an upper bound for cross section of about 3x10-8cm2/dev. And during proton testing there were no SEFIs, corresponding to a limiting cross section of about 3x10-14cm2/dev. D. Marvell 64460 Results The Marvell 64460 was tested primarily with the bit upset approach, however due to a significant high current effect risk; this device was also monitored for a high-current mode related to SEFI. The device is memory-mapped in application computer systems, and a test application can target the device’s registers and SRAM cells easily. Results Fig. 14. High current heavy ion upset sensitivity for the MV64460 is for register testing are given in Figs. 12 and 13. The high- shown. The error bars on LET = 8.2 MeV-cm2/mg include fluence current mode related SEFI results are given in Figs. 14 and uncertainty since the beam could not be cycled quickly enough to produce no high current event. 15.

Fig. 12. Register heavy ion upset sensitivity for the MV64460 is shown. Fig. 15. High current proton upset sensitivity for the MV64460 is shown. Although the data could be merged, the full data set enables other groups to interpret the impact of ion range since all of the data on this plot comes from Testing of the SRAM in the 64460 was essentially degraded Ne. impossible without access to the manufacturer’s datasheet. This is because the SRAM is EDAC protected and no control bits for checking the EDAC system are documented. The SRAM did encounter events and occasionally double-bit upsets would be seen in the data stream. Unfortunately, the high current mode swamped this signal, so we can only state that it was observed.

VI. SEFI RESULTS recovery routine. It should be noted, however, that at 600 or SEFIs are often caused by basic cell upsets that happen to 667 MHz, this parity handler change had no effect. have extreme significance in the software and hardware configuration at the time of the upset. For this reason, they VIII. CONCLUSION are application dependent, and may approach device cross This workshop has presented SEE results for the IBM sections significantly higher than individual cell upsets. 750FX, Freescale 7447A, and Marvell 64460. The 750FX SEFIs not related to basic cell upsets do not carry this and 7447A are PowerPC processors and are similar to caveat, but are sometimes more invasive. We have shown previously reported devices. The 7447A is most closely SEFIs for the Marvell 64460 which are very similar to SEL, related to the 7457 and the data here is consistent with but cannot be proven as classical SEL under the available test previous results. The 750FX was also tested in 2002 and the data. These SEFIs are not likely due to cell upsets, and results presented here are similar to the previous results. The therefore may be applied independent of application. results for the 64460 are the first data on a device of this type. However, they swamp out any other SEE in this device. The 7447A and 750FX were found to have an SEU SEFIs in the IBM 750FX and Freescale 7447A were threshold of about 1 MeV-cm2/mg and saturated cross section almost nonexistent (only a few over the entire data taking of 2x10-9 cm2/bit. Both devices have proton cross sections of effort). This is because the software used during testing is about 10-14cm2/bit and proton thresholds below 20 MeV. The very simple, and streamlined to handle radiation-induced 64460 was shown to have functional interrupts similar to states. Real applications will include software structures that single event latchup with threshold below 1 MeV-cm2/g and are not robust to upsets, and unlike the test software used saturated cross section around 1 cm2. here, will not be debugged in an SEE environment. The 750FX and 64460 required new test methods. In It is recommended, especially for the processors, that flight the case of the former, specific test methods were developed projects consider the device cross section for all the bits to extract data from the L2 cache. The 64460 was tested for sensitive in their design and apply a use factor to account for register sensitivity. However, on the 64460 test data the average sensitivity of their applications to upsets. collection was severely limited by high current SEFI modes that generally required board power cycling to recover. VII. FREQUENCY RESULTS The 750FX has a run-time configurable PLL system, and IX. ACKNOWLEDGMENT using this system with 600 and 667MHz settings resulted in The authors acknowledge assistance from Sherry Akins, the SEFI results above. Other SEFIs were observed while Matthew Smith, and Lee Hoffman of Honeywell, Clearwater using this alternate PLL system. Those SEFIs are discussed FL. here. The research was carried out at the Jet Propulsion In order to correctly test the PLL system we used the Laboratory, California Institute of Technology, under a operation test of the FPU system. Using a 400MHz PLL contract with the National Aeronautics and Space setting resulted in SEFI rates increasing by a factor of 10 Administration. Project support is also acknowledged. however the statistical impact of the data is very small because the observed number of events is so small. X. REFERENCES This observation led to a campaign to determine the source [1] D.Rea, D.Bayles, P.Kapcio, S.Doyle, D.Stanley, “The RAD750- A of the increased upset sensitivity. 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David M. Hiemstra, Senior Member IEEE, George Battiston, and Prab Gill

Proton irradiation was performed at the TRIUMF Proton Abstract-- Proton induced SEU cross-sections of the SRAM Irradiation Facility (PIF), located on the campus of the which stores the logic configuration and certain functional blocks University of British Columbia (UBC), British Columbia, of the Virtex-5 FPGA are presented. Upset rates in the space Canada. Beamline 2C of the PIF was used for characterization radiation environment are estimated. of the Virtex-5 using 120 MeV [2]. The outcome of this research was the single event effects (SEE) characterization of Keywords--single event upset; SRAM FPGA; proton the Virtex-5. irradiation II. DEVICES UNDER TEST OVERVIEW I. INTRODUCTION The Virtex-5 device tested was the XC5VLX50T- N this paper, the approach followed to characterize the 1FFG1136. It is fabricated on a 65 nm copper CMOS process Istatic SEU susceptibility of the static random access run at a core voltage of 1.0V. It includes flexible logic memory (SRAM) which stores the logic configuration and the dynamic single event upset (SEU) susceptibility of certain resources (configurable logic blocks (CLBs) and flip-flops functional blocks of the Virtex-5 field programmable gate (FFs)), dedicated multipliers, dual ported block RAM array (FPGA) are presented. The experimental test setups, test (BRAM), programmable I/O, clock management circuitry, and results obtained, and analysis of these results, are described. extensive routing resources. Additional details can be found in Based on the test results obtained and using the Figure of the manufacturer’s datasheets [3]. Merit (FOM) technique [1], SEU rates are determined for a typical low earth orbit mission. Single event latchup (SEL) and III. TEST: METHODOLOGY, SETUP, AND PROCEDURE total dose effects are discussed. SEU performance comparisons to Xilinx Virtex-4 and Virtex-II devices A. SEU Test Approach previously tested are discussed. Two types of test were performed to evaluate the SEU The Virtex-5 is a re-programmable logic device where the performance of the Virtex-5 XC5VLX50T. In the first type of logic configuration is stored in SRAM. They have advantages test the device was configured with a known pattern in the over ASIC designs such as: reduced cost and lead-time, faster SRAM which stores the logic configuration and irradiated in prototyping, allow for on-orbit design changes, and hardware steps. No clock was applied to the device for this test. At the re-use (multiple functions from the same hardware). These end of each step the SRAM was read back via the JTAG benefits however result in an additional upset risk over fixed interface using the iMPACT console [4], the number of upsets logic. An upset in the SRAM storing the logic configuration and total fluence recorded, and the known pattern re-loaded. can result in single event functionality upset (SEFU). User This test established the SEU cross-section for the SRAM logic can also upset in the same manner as fixed logic. which stores the logic configuration. The Virtex-5 Therefore, SEU testing and analyses are undertaken to XC5VLX50T contains 12547968 bits of logic configuration evaluate the performance of these devices in the space SRAM. This test is named Virtex-5 SRAM Logic radiation environment. Configuration. In the second type of tests the Virtex-5 XC5VLX50T was Manuscript received July 19, 2010. This work was supported by MDA configured with various dynamic test designs to evaluate the internal research and development. SEU performance of certain functional blocks of the device: D. M. Hiemstra is with MDA, Brampton, Ontario L6S 4J3 Canada CLBs and FFs, multipliers, and BRAM. These tests are named (telephone: 905-790-2800, e-mail: [email protected]). G. Battiston is with MDA, Brampton, Ontario L6S 4J3 Canada (telephone: Virtex-5 CLBs and FFs, Virtex-5 Multipliers, and Virtex-5 905-790-2800, e-mail: [email protected]). BRAM, respectively. These tests do not distinguish between P. Gill is with MDA, Brampton, Ontario L6S 4J3 Canada (telephone: 905- upsets in the SRAM storing the logic configuration and user 790-2800, e-mail: [email protected]).

logic. The test designs included monitoring and self checking method were recorded. The device’s power rails were features which allowed SEUs to be monitored during monitored using a current probe, current amplifier, and irradiation via the LED’s included on the Virtex-5LXT FPGA oscilloscope. ML505 Evaluation Platform (EP) for CLBs and FFs, E. Test Facility multipliers. Xilinx ChipScope [5] was used to monitor BRAM. Testing was performed at the TRIUMF PIF located on the The number of errors accumulated during irradiation in the UBC campus. This general purpose proton irradiation facility SRAM storing the logic configuration was also monitored. consists of two beam lines located in the same room. Beam B. SEU Test Setup line 1B provides protons with energies ranging from 180 to The Virtex-5 XC5VLX50T was installed on the Virtex- 520 MeV. Beam line 2C provides proton energies up to 120 5LXT FPGA ML505 EP with part number HW-V5-ML505- MeV. Beam line 2C is also used for proton therapy. The beam line characteristics are described in Table I [2]. Beam line 2C UNI-G [6]. was used in this test campaign. The layout of the PIF is shown The setup for both types of test consisted of the EP with the in Figure 1 [7]. Virtex-5 XC5VLX50T installed, a lab power supply, current probe, current amplifier, oscilloscope, communication cable, TABLE I and personal computer. The LED’s were monitored remotely TRIUMF PROTON IRRADIATION FACILITY SPECIFICATION [2]. via a camera in the beam line. Beam Line 1B Beam Line 2C C. Dynamic Functional Block Tests Energy (MeV) 180-520 65-120 The Virtex-5 CLBs and FFs dynamic test design consists of 120-180 by degrader 20-65 by degrader 2 5 7 5 8 twenty four 376-bit counters running in parallel at 27 MHz. Intensity (protons/cm /s) 10 - 4x10 10 - 10 These counters are arranged in groups of three where each Field Size Square (cm2) 4- 225 1 - 49 counter spans a complete column of CLBs from the top to the bottom of the device. The outputs of each triplet of counters were compared every clock cycle and if the results did not match a corresponding on board LED was turned on. This resulted in eight separate failure signatures that could be detected representing eight independent groups of triple counters connected to the eight on board LEDs. The Virtex-5 Multipliers dynamic test design consists of a total of thirty six 25x18 DSP48 blocks running in parallel at 27 MHz. These multiply accumulate blocks were arranged in groups of two with each group consisting of six chained DSP48 blocks. The output of the first group was compared to the second one on every clock cycle and if the results did not match an on board LED was turned on. The Virtex-5 BRAM dynamic test design consisted of a total of sixteen 10 kbit segement of BRAM. The BRAM was written with a known pattern at the start of the test. The BRAM was readback continuously. Xilinx Chipscope [5] was Fig. 1. Layout TRIUMF Proton Irradiation Facility [7]. used to monitor errors in each 10 kbit segement of BRAM. D. SEU Test Procedures IV. TEST OBJECTIVES AND RESULTS For the first type of test each run began by re-programming A. Objectives the Virtex-5 XC5VLX50T, once executing the proton beam was applied to the Virtex-5 XC5VLX50T for a fixed total The objectives of these tests were: (1) to establish the upset fluence. After the irradiation was complete the number of bit cross-section of certain functional blocks of the Virtex-5 flips in SRAM storing the logic configuration were recorded. XC5VLX50T, (2) to investigate possible latchup sensitivity, The device’s power rails were monitored using a current and (3) to establish the total dose (protons) performance. This probe, current amplifier, and oscilloscope. proof of principle testing was performed on one Virtex-5 For the second type of tests each run began by re- XC5VLX50T device. Additional samples of the devices would programming the Virtex-5 XC5VLX50T, once executing the need to be tested to establish bounded radiation performance. proton beam was applied to the Virtex-5 XC5VLX50T. B. Single Event Upset Results Whenever an SEU was detected the beam was halted, fluence The SEU test results for Virtex-5 SRAM storing logic to upset, number of errors observed, upset signature, number configuration is shown in Table II. of bit flips in SRAM storing logic configuration, and recovery

The SEU test results for Virtex-5 CLBs and FF, Multipliers, TABLE V and BRAM, are shown in Tables III, IV, and V, respectively. VIRTEX-5 BRAM FLUENCE TO UPSET In these tables the fluence to upset, number of errors observed, Fluence to # of Upset Signature Recovery Method upset signature, number of bit flips in SRAM storing logic Upset Errors configuration, and recovery method are recorded. (p/cm2) TABLE II 1.85x109 2 Single bit flip, Re-program FPGA VIRTEX-5 SRAM STORING LOGIC CONFIGURATION UPSETS PER FLUENCE separate BRAM blocks Fluence # of 9 2 2.56x10 1 Single bit flip Re-program FPGA (p/cm ) Upsets 9 10 6.19x10 1 Single bit flip Re-program FPGA 1.1x10 2710 1.1x1010 2722 1.1x1010 2751 V. ANALYSIS AND DISCUSSION 1.1x1010 2672 1.1x1010 2701 1.1x1010 2596 A. SEU Cross-sections 1.1x1010 2719 The proton SEU cross-section of the Virtex-5 SRAM Storing 1.1x1010 2720 Logic Configuration, CLBs and FFs, Multipliers, BRAM and 10 1.1x10 2598 RocketI/OTM are 1.95x10-14 cm2/bit, 0.48x10-9 cm2/device, 10 1.1x10 2671 0.48x10-9 cm2/device, and 5.4 x10-9 cm2/device, respectively (per device cross-sections were determined by scaling TABLE III measured results to full utilization of CLBs and FFs, VIRTEX-5 CLBS AND FFS FLUENCE TO UPSET Multipliers, and BRAM). Fluence # of Upset # of Bit Recovery Method B. Single Event Latchup to Upset Errors Signature Flips (p/cm2) No SEL due to protons was observed. Advanced micro- 4.3x109 1 LED 2 1029 Re-program FPGA circuits, have shown SEL to protons [11]. Devices susceptible partially to proton SEL are considered unacceptable for space missions. On The Virtex-5 XC5VLX50T was irradiated with the equivalent 9.1x109 1 LED 6 On 1177 Re-program FPGA of at least 53 years heavy ion fluence up to a LET of 6.4x109 1 LED 7 On 1542 Re-program FPGA approximately 10 MeVcm2/mg [12], with no SEL observed. 9 8.2x10 1 LED 2 303 Based on this work and that of O’Neill et al., this suggests the partially probability of heavy ion SEL is low if these devices were used On on the Space Shuttle or any other low earth orbit short duration 1.1x109 1 LED 2 On 701 Re-program FPGA 1.2x109 1 LED 3 On 280 Re-program FPGA mission [13]. 9 1.7x10 1 LED 3 On 1135 Re-program FPGA C. Total Dose 1.7x109 1 LED 4 On 133 Re-program FPGA 2.0x109 1 LED 5 On 580 Re-program FPGA The Virtex-5 XC5VLX50T received a total fluence of 10 2 2.2x109 1 LED 2 On 486 Re-program FPGA 26.5x10 p/cm at 120 MeV, equivalent to a total dose of 23.8 krad(Si). No change in post irradiation supply current was TABLE IV observed. This total dose tolerance is suitable for many low VIRTEX-5 MULTIPLIERS FLUENCE TO UPSET earth orbit missions. Fluence # of Upset # of Bit Recovery Method D. Virtex-5 SEU Cross-section Comparison with Virtex-4 to Upset Errors Signature Flips and Virtex-II (p/cm2) 2.7x109 1 LED 5 586 Re-program FPGA The per unit proton SEU cross-section of the Virtex-II 4.8x109 1 LED 2 1103 Re-program FPGA XC2V1000 SRAM Storing Logic Configuration, CLBs and 4.4x109 1 LED 3 1056 Re-program FPGA FFs, Multipliers, and BRAM were 3.36x10-14 cm2/bit, 8.3x10- 1.9x109 1 LED 0 430 Re-program FPGA 14 cm2/FF, 7.8x10-11 cm2/multiplier, and 4.7 x10-15 cm2/bit, 1.0x109 1 LED 4 226 Re-program FPGA 9 respectively [8,9]. The Virtex-II XC2V1000 was fabricated on 6.8x10 1 LED 4 164 Re-program FPGA a 150nm / 120 nm CMOS process run at a core voltage of 2.1x109 1 LED 3 556 Re-program FPGA 1.5V. 2.2x109 1 LED 1 515 Re-program FPGA 2.4x109 1 LED 2 592 Re-program FPGA The proton SEU cross-section of the Virtex-4 XC4VLX25 0.4 x109 1 LED 3 98 Re-program FPGA SRAM Storing Logic Configuration, CLBs and FFs, Multipliers, and BRAM were 1.56x10-14 cm2/bit, 6.6x10-14

cm2/FF, 1.0x10-11 cm2/multiplier, and 4.2 x10-15 cm2/bit, programmablegate arrays using proton irradiation,” IEEE REDW, pp. respectively [10]. The Virtex-4 XC4VLX25 was fabricated on 79-84, 2004. [9] D. Hiemstra and F. Chayab, “Part II: Dynamic Single Event Upset a 90 nm CMOS process run at a core voltage of 1.2V. Characterization of the Virtex-II Field Programmable Gate Array Using The proton SEU cross-section of the Virtex-5 XC5VLX50T Proton Irradiation,” IEEE REDW, pp.46-50, 2005. SRAM Storing Logic Configuration, CLBs and FFs, [10] D. Hiemstra, F. Chayab, and Z. Mohammed, “Single event upset Multipliers, BRAM and were 1.95x10-14 cm2/bit, 1.7x10-14 characterization of the Virtex-4 field programmable gate array using 2 -11 2 -15 2 proton irradiation,” IEEE REDW, pp. 105-108, 2006. cm /FF, 1.0x10 cm /multiplier, and 2.44x10 cm /bit, [11] A. Johnston, G. Swift, and L. Edmonds, “Latchup in integrated circuits respectively. The Virtex-5 XC5VLX50T is fabricated on a 65 from energetic protons,”IEEE Transactions on Nuclear Science,” Vol. nm CMOS process run at a core voltage of 1.0V The per unit 44, No. 6, pp. 2367-2377, Dec., 1997. cross-sections for SRAM Storing Logic Configuration, CLBs [12] P. O’Neill, G. Badhwar, and W. Culpepper, “Risk Assessment for Heavy Ions of Parts Tested with Protons,” IEEE Transactions on and FFs, Multipliers, and BRAM are decreasing or leveling Nuclear Science, Vol. 44, No. 6, pp. 2311-2314 , Dec., 1997. off with feature size and core voltage reduction a surprising [13] P. O’Neill, G. Badhwar, and W. Culpepper, “Internuclear cascade- result. evaporation model for LET spectra of 200 MeV protons used for parts The proton SEU cross-section of the Virtex-5 testing,” IEEE Transactions on Nuclear Science, Vol. 45, No. 6, pp. XC5VLX50T and Virtex-4 XC4VLX25 with the same logic 2467-2474, Dec., 1998. resource utilization as the Virtex-II Full Functionality design on a Virtex-II XC2V1000 reported in [6] are estimated to be 0.43x10-9 cm2 and 0.73x10-9 cm2 at 120 MeV, respectively. These cross-sections are nearly a factor of 6 and 4 lower, respectively, than the same design on the Virtex-II which had a cross-section of 2.64x10-9 cm2/device. Using the FOM [1] technique on the Space Shuttle, assuming 2.5” Al shielding, in a space station orbit (57°, 555.6 km, circular), the upset rate for the Virtex-5 XC5VLX50T is estimated to be (protons and heavy ions) 0.00042/day. This device with the appropriate mitigation scheme could be used on the Space Shuttle or other short duration demonstration missions.

VI. CONCLUSIONS The Virtex-5 provides considerable advantages over ASIC solutions for logic circuitry in space applications as previously described. It’s SEE and total dose performance are acceptable for many low earth orbit short duration missions. Also, it’s SEU performance is dramatically better than the Virtex-II XC2V1000 and similar to the Virtex-4 XC4VLX25.

VII. ACKNOWLEDGMENT We gratefully acknowledge the technical support with respect to proton irradiation of Dr. Ewart Blackmore, TRIUMF. Also, the authors gratefully acknowledge the financial support of MDA internal research and development.

VIII. REFERENCES [1] E. Petersen, “The SEU Figure of Merit and Proton Upset Rate Calculations,” IEEE Transactions on Nuclear Science, Vol. 45, No. 6, pp. 2550-2562, Dec., 1998. [2] E. Blackmore, “Operation of the TRIUMF (20-500MeV) proton irradiation facility,” IEEE REDW, pp. 1-5, 2000. [3] http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf [4] http://www.xilinx.com/products/design_tools/logic_design/design_entry /impact.htm [5] http://www.xilinx.com/tools/cspro.htm [6] http://www.xilinx.com/products/devkits/HW-V5-ML505-UNI-G.htm [7] http://www.triumf.ca/pif. [8] D. Hiemstra, F. Chayab, and L. Szajek, “Dynamic single event upset characterization of the Virtex-II and Spartan-3 SRAM field

Sensitivity of 2 Gb DDR2 SDRAMs to Protons and Heavy Ions

R. Koga, Member, IEEE, P. Yu, J. George, and S. Bielat

memory. That is, we can write bits, store and read them. If a Abstract-- SEE sensitivity to protons and heavy ions is device is not functional, it is possible to “power cycle”, which examined with several 2 Gb DDR2 SDRAM device types. Upsets is equivalent to carrying out (1) power-up and (2) software in memory elements as well as in control circuit sections have conditioning sequentially. This may restore the functionality. been measured. In some cases the software conditioning alone (without resorting to power-up) is effective in restoring full I. INTRODUCTION functionality. These considerations are important because YNCHRONOUS Dynamic Random Access Memories events such as single event functional interrupt (SEFI) have S(SDRAMs) have been successfully utilized in various great relevance to the operations of these devices. space applications [1]. Over the years the SDRAM technology has been evolving to encompass ever-higher CKE Row Refresh CK Addr. DLL, clock speeds, higher memory density, and reduced bias CS Counter Latch WE Control Row Read Data voltage, listing only a few new traits. In each successive Memory Strobe, CAS Logic Addr. Latch Drivers generation, SDRAM devices were tested for sensitivity to RAS MUX Array I/O Data, single event effects (SEE), among others [2]. Since the Mode Bank Gating, Data Registers Control Data Strobe, consideration for use of SDRAMs in space would extend to Logic Mask Data the 2 Gb DDR2 technology, we have examined the SEE Logic Mask Write Receiver, sensitivity of selected 2 Gb DDR2 devices. We have used the Column, Column FIFO, Input Address Control, Decode Driver Register Lawrence Berkeley National Laboratory (LBNL) 88-inch Address Logic, Register Latch cyclotron facility in order to carry out SEE testing with heavy ions and protons (<55 MeV). Fig. 1. Schematic diagram of a DDR2 SDRAM.

II. EXPERIMENTAL An exposure to heavy ions and protons took place on a test A functional diagram of a DDR2 SDRAM is shown in Fig. microcircuit imbedded in a SODIMM (small outlined dual in- 1. In various sections (such as the control section) of an line memory module). A SODIMM might be inserted in a SDRAM, we expect to find logic elements, which would be device exercise/evaluation platform (ML505 manufactured sensitive to SEE. Exposure to protons and heavy ions often by Xilinx) with DDR2 devices. Various modifications were results in observing the possible vulnerability of these devices made to accommodate acceptable read/write routines for SEE [3]-[5]. testing of DDR2 SDRAMs. Exposure to heavy ions was In order to prepare a DDR2 SDRAM for a functional made in various stages with the use of ions of varying energy memory, an initialization procedure must be carried out. At levels (and consequently varying ranges) available at the first, a sequence of power-up routines is applied. This LBNL 88-inch cyclotron facility. For many “delidded” includes an application of clock signals (> 200 Mbps). When devices (for which the thickness of the plastic encapsulation all signals and power lines are stable for at least several was uniformly reduced) it was possible to “measure” the hundred microseconds, a set of executable commands is remaining thickness of the encapsulation material with the applied for initialization. This second set of operations use of various ion species of known energy levels. We have (software conditioning) includes the enabling of DLL, determined the LET values at the sensitive regions, which execution of LOAD MODE REGISTER commands, and were recalibrated with the known range values of ions. performing of a REFRESH cycle procedure. After these Protons were also utilized at LBNL (the energy range was operations (power-up and software conditioning) are carried between 9.8 and 50 MeV) as well as at IUCF (for 200 MeV out successfully, an SDRAM “works” as a functional protons). A test sample was written with some fixed pattern before exposure. During exposure to ions, the sample was checked Manuscript received July 12, 2010. R. Koga, P. Yu, J. George, and S. Bielat are with The Aerospace for errors repeatedly. In this mode of operation, each upset Corporation, El Segundo, CA 90245 USA (telephone: 310-336-6583, e-mail: error was corrected during the read operation. (Occasionally [email protected]). we exposed a sample while the sample was simply refreshed,

but not read.) After exposure to a fixed fluence, the sample III. RESULTS AND DISCUSSION was checked for additional errors. If a numerous-bits upset All test samples were sensitive to various SEEs. However, took place (e.g., a few hundred upset bits for one exposure), they were not sensitive to single event latchup with the we examined whether or not (1) the number of upset bits was fluence levels utilized presently. We will describe the SEE finite (in a reasonable read time), (2) we could write over and sensitivity for each device type. read correctly again, (3) the sample required the software conditioning for recovery, or (4) the sample needed power cycling for recovery. The bias current level was monitored to A. Hynix DDR2 observe unusually high current conditions including single Heavy ions: SEE sensitivity of this device type included event latchup (SEL). The applied clock frequency values single event upsets (SEUs). All isolated SEUs that we varied from near 100 MHz to slightly above 400 MHz. detected were single bit upsets (SBUs), whose address A single event upset consisting of one bit upset in a word locations appeared to be randomly scattered in the address may be detected without much difficulty. When it is an upset space. Therefore, there was only one bit upset in one affected at one bit location, we have called this single bit upset (SBU.) byte. These SBUs took place separated in time during An SBU may be attributed to an upset at the memory storage irradiation. An SBU may be attributed to an upset at the area. For SBUs, we usually observe the characteristic (2) memory storage area. The SBU sensitivity is shown in Fig. 2. above, but we would not encounter (3) and (4) above. The LET threshold value is about 1 MeV/(mg/cm2). We did Another type of upset is made up of a burst of upset bits, not detect any SBUs at the LET of 0.1 and 1.4 with the which seem to have been caused by the effect of one ion present fluence levels yielding upper limits to the cross- strike on the control section. Often the upset bits are closely sections. All upset bits were from logical “1” to logical “0” located in the logical space of the memory organization. For for all irradiations. Since the numbers of upset bits were not those multiple bits upsets, we may notice that the large for all test runs for this device type, there would be characteristics (1) and (2) above are still true, and they would relatively large statistical uncertainties associated with them. not encounter (3) and (4) above. These are events with many In some cases the number of upset bits was about 3 for one upset bits and they do not show any permanent effects. On run, yielding the statistical uncertainty to about 60% (1.7/3) the contrary, events that would require a power cycle for for one standard deviation. In addition to SBUs, we observed restoration of memory functions is often an SEFI. If an SEFI burst upsets. Upsets at many logically (often) consecutive were to take place, we would normally encounter (3) and (4) address locations constituted one burst. In each burst there above as well as (1) and (2). In the event that the bias current were up to about 1000 affected address locations. At most to the test device were to increase abnormally, we might have address locations, there were more than one-affected bits (i.e., encountered an SEL. upsets). These were multiple-bit upsets (MBU) in the byte. All irradiations were carried out at room temperature. We These affected locations could be written over without a did not attempt to raise or lower the device temperature for power cycle and the number of affected locations never the present testing. The memory refresh time was a nominal exceeded about 1000. We call these burst upsets. It is value, 64 ms, throughout testing, corresponding to the refresh consistent that the location of the burst upsets was situated in rate of about 7.8 μs. When other values were utilized, they the control logic section. A burst upset often extends to were mentioned specifically in the text. The clock rate for hexadecimal 400 (400(Hex)) address locations, which is DDR2s was about 135 MHz in most cases. Since the number equivalent to 1024 in decimal number (e.g., from of test samples was not numerous, test results were combined 1FFFC00(Hex) to 1FFFFFF(Hex)). This is exactly the (while averaging test results in some cases) for plotting number of column addresses in this device type. Therefore, a purposes without specifying the test target serial numbers for burst upset would have been caused by an upset in the control specific data points. The nominal bias voltage was 1.8 V area where the column address is controlled. This might (VDD = 1.8 V.) include associated sense amplifiers along with the column We have chosen a few DDR device types as test samples decoder. as shown in Table 1. The feature sizes of these devices range We counted the numbers of burst upsets in order to somewhere between 80 and 90 nm. calculate the cross-sections. Unrelated to burst upsets, we observed SEFIs for which the affected address locations TABLE 1: TESTED 2GB DDR2 MEMORY DEVICES exceeded many more than 1000 and the affected locations could not be written over unless a power cycle had been Device ID Manufacturer Technology Organization applied. The sensitivity for burst upsets (relevant cross- MT47H256M8 Micron Tech. CMOS/DDR2 2 Gb, 32M x 8 K4T2G084QA Samsung CMOS/DDR2 2 Gb, 32M x 8 sections) exceeded that for SEFIs. We detected a SEFI at an H5PS2G83AFR S6C Hynix CMOS/DDR2 2 Gb, 32M x 8 LET value of 8.4, while upper limits to SEFI cross-sections EDE2108ABSE Elpida CMOS/DDR2 2 Gb, 32M x 8 were measured at other LET values. The LET threshold value

for burst upsets is above 0.1 MeV/(mg/cm2). Burst upset results, as well as SEFI results, are shown in Fig. 2. No SEL was observed.

10-6 B. Micron DDR2 Heavy ions: We observed single event upsets (SEUs). All 10-8

) isolated SEUs that we have seen were single bit upsets 2 10-10 Burst, upper limit at LET=0.1 (SBUs), whose address locations were scattered in the SBU, upper limit at LET=0.1, 1.4 address space. All upset bits were from logical “1” to logical 10-12 SEFI, upper limit at LET=0.1, 4.1, 29.1 “0” for all SBU. Since the number of upset bits was a few for each run, there would be a large statistical uncertainty -14 10 associated with the cross-section. The SBU sensitivity is Cross Section (cm Section Cross shown in Fig. 4. At LET of 0.1 we did not detect any sign of 10-16 SBU yielding an upper limit to upset at about 3x10-17 cm2/bit. 10-18 In addition to SBUs, we observed burst upsets. Upsets at 0 5 10 15 20 25 30 35 many logically (often) consecutive address locations LET (MeV-cm2/mg) constituted one burst. We counted the numbers of burst

Fig. 2. Heavy ion induced Burst Upset (cm2/dev.), SEFI (cm2/dev.), and upsets in order to calculate the cross-sections. These events SBU (cm2/bit) sensitivity for Hynix 2 Gb DDR2 SDRAM. took place at the LET values of 5.4 and 13 MeV/(mg/cm2). At other LET values, we did not detect burst upsets possibly Protons: SEE sensitivity of this device type for protons is due to higher rate of other SEEs. Unrelated to burst upsets, shown in Fig. 3. SBUs similar to those observed with heavy we observed SEFIs for which the affected address locations ions were present as shown in the figure. At all energy levels, exceeded many more than 1000 and the affected locations we detected SBU except at 9.8 and 20 MeV. At 20 MeV we could not be written over unless a power cycle had been did not detect SBU, which yielded upper limits to SBUs of applied. The sensitivity for SEFI often exceeded that for burst -21 2 about 3.0x10 cm /bit. All upset bits were from logical “1” upsets. SEFI results are shown in Fig. 4. At the LET value of to logical “0” for all proton irradiations. Since the numbers of 0.1 MeV/(mg/cm2), we did not detect SEFI yielding an upper upset bits were not large for all test runs for this device type, limit of about 6x10-8 cm2/device. No SEL was observed at all there would be relatively large statistical uncertainties LET values that we utilized. associated with them. In some cases the number of upset bits was about 2 for one run, yielding a statistical uncertainty of 10-2 about 70% (1.4/2) for one standard deviation. SEFI -4 sensitivity was not detected with the present level of applied 10

) -6 fluence, except at the energy level of 30 MeV with the 2 10 11 2 fluence of 1.0x10 protons/cm . At other energy levels, we 10-8 Burst, all pts upper limit except LET=5.4, 13 plotted the upper limits to SEFI. For example, the upper limit SBU, upper limit at LET=0.1 10-10 to SEFI at 200 MeV is about 2x10-11 cm2/device. In addition SEFI, upper limit at LET=0.1 to SBUs and SEFI, we tried to measure the burst upset 10-12 -14 sensitivity. The numbers of affected address locations for a (cm Section Cross 10 burst upset would be limited to less than about 1000. At all 10-16 energy levels, we did not detect burst upsets, which yielded -18 upper limits to burst upsets identical to those for SEFI as 10 shown in the figure. No SEL events were detected with this 0 5 10 15 20 25 30 35 LET (MeV-cm2/mg) device type yielding the upper limit to about 2x10-11 2 2 cm2/device at 200 MeV. Fig. 4. Heavy ion induced Burst Upset (cm /dev.), SEFI (cm /dev.), and SBU (cm2/bit) sensitivity for Micron 2 Gb DDR2 SDRAM.

10-8 Protons: SEE sensitivity of this device type for protons is 10-10 shown in Fig. 5. We observed SEFIs for this device type for protons of energy levels at 200 MeV through 12 MeV. ) 2 10-12 Relevant SEFI cross-sections are shown in the figure. High Burst, all pts upper limits 10-14 SBU, upper limit at 9.8, 20 MeV sensitivity to SEFI made detection of other SEEs more SEFI, all pts upper limit except 30 MeV difficult. In addition to SEFIs, we tried to measure the burst -16 10 upset sensitivity. The numbers of affected address locations 10-18 for a burst upset would be limited to less than about 1000. At Cross Section (cm Section Cross all energy levels, we detected burst upsets except at 9.8, 12 -20 10 and 20 MeV. At these energy levels, upper limits to burst -11 10-22 upsets ranged from about 1x10 (at 9.8 and 12 MeV) to -10 2 0 20 40 60 80 100 120 140 160 180 200 220 3x10 cm /device (at 30 MeV). SEL was not detected with Proton Energy (MeV) the present level of applied fluence. Therefore, the upper -9 2 Fig. 3. Proton induced Burst Upset (cm2/dev.), SEFI (cm2/dev.), and SBU limit to SEL at 200 MeV was about 1x10 cm /device. SBUs (cm2/bit) sensitivity for Hynix 2 Gb DDR2 SDRAM.

similar to those observed with heavy ions were present at an associated with them. In some cases the number of upset bits energy level of 12 MeV as shown in the figure. All upset bits was about 4 for one run, yielding the statistical uncertainty to were from logical “1” to logical “0” for all SBU. Since the about 50% (2/4) equal to one standard deviation. number of upset bits was 2, there would be a large statistical uncertainty associated with them. At other energy levels we 10-2 did not detect SBUs yielding upper limits. 10-4

) -6 -8 2 10 10 Burst, upper limit at LET=0.1 -8 10 SBU, upper limit at LET=0.1, 0.7, 1.1 10-10 10-10

) -12 2 10 -12 Burst, upper limit at 9.8, 12, 20 MeV 10 -14 10 SBU, all pts upper limit except 12 MeV -14

Cross Section (cm Section Cross 10 SEFI, upper limit at 9.8 MeV 10-16 10-16 10-18 10-18

Cross Section Section Cross (cm 0 5 10 15 20 25 30 35 -20 10 LET (MeV-cm2/mg)

10-22 Fig. 6. Heavy ion induced Burst Upset (cm2/dev.) and SBU (cm2/bit) 0 20 40 60 80 100 120 140 160 180 200 220 sensitivity for Elpida 2 Gb DDR2 SDRAM. Proton Energy (MeV)

Fig. 5. Proton induced Burst Upset (cm2/dev.), SEFI (cm2/dev.), and SBU In addition to SBUs, we tried to measure the burst upset (cm2/bit) sensitivity for Micron 2 Gb DDR2 SDRAM. sensitivity. The numbers of affected address locations for a burst upset would be limited to less than about 1000. At all energy levels, we detected burst upsets except at 9.8 and 12 C. Elpida DDR2 MeV. At 9.8 MeV we did not detect burst upsets, which Heavy ions: We observed single event upsets (SEUs). All yielded an upper limit to burst upsets of about 4.0x10-12 isolated SEUs that we observed were single bit upsets cm2/device. SEFI sensitivity was not detected with the (SBUs), whose address locations appeared to be randomly present level of applied fluence, therefore, the upper limit to scattered in the address space. These SBUs took place not at SEFI at 200 MeV was about 1x10-9 cm2/device. No SEL the same time; they were separated in time during irradiation. events were detected with this device type yielding the upper The SBU sensitivity is shown in Fig. 6. The LET threshold -9 2 2 limit to about 1x10 cm /device at 200 MeV. value is about 1 MeV/(mg/cm ). We did not detect any SBUs at LET values of 0.1, 0.7, and 1.1 yielding upper limits. All 10-8 SBU bits were from logical "1" to logical "0". But, the total upset bits were not numerous. Since the numbers of upset bits 10-10

(for SBU) were between 2 and 6 for each run, the associated ) -12 2 10 uncertainties might be close to the square root of 2. It would equal to about 70% (1.4/2) for one standard deviation. In 10-14 Burst, upper limit at 9.8, 12 MeV SBU, upper limit at 9.8, 12 MeV addition to SBUs, we observed burst upsets. The sensitivity 10-16 of burst results is shown in Fig. 6 as well. The sensitivity rises quickly with increasing LET at about 2 MeV/(mg/cm2) 10-18 Cross Section (cm Section Cross and it levels off. We did not detect SEFIs for this device type. 10-20 Therefore, the upper limit to SEFI at LET of 30 MeV/(mg/cm2) is about 1x10-4 cm2/device. No SEL was 10-22 observed at all LET values that we utilized. 0 20 40 60 80 100 120 140 160 180 200 220 Proton Energy (MeV)

2 2 Protons: SEE sensitivity of this device type for protons is Fig. 7. Proton induced Burst Upset (cm /dev.) and SBU (cm /bit) sensitivity for Elpida 2 Gb DDR2 SDRAM. shown in Fig. 7. SBUs similar to those observed with heavy ions were present as shown in the figure. At all energy levels, we detected SBUs except at 9.8 and 12 MeV. At 9.8 and 12 D. Samsung DDR2 MeV we did not detect SBUs, which yielded upper limits to Heavy ions: We observed single event upsets (SEUs) with SBU of a few times 1.0x10-21 cm2/bit. The cross-section at heavy ions of various LET values. All isolated SEUs that we 200 MeV did not increase drastically as compared to those at have seen were single bit upsets (SBUs), whose address around 50 MeV. All upset bits were from logical “1” to locations were scattered in the entire address space. Most logical “0” for all proton irradiations. Since the numbers of upset bits were from logical “1” to logical “0” for all upset bits were not large for all test runs for this device type, irradiations. Some (about 5%) were from logical “0” to there would be relatively large statistical uncertainties logical “1”. Since the number of upset bits was a few for each

run, there would be a large statistical uncertainty associated levels, we did not detect burst upsets. The upper limit to burst with the cross-section. The SBU sensitivity is shown in Fig. upsets was about 2x10-11 cm2/device at 200 MeV. SEL was 8. At LET of 0.1 we did not detect any sign of SBU yielding not detected with the present level of applied fluence. an upper limit to upset at about 5x10-17 cm2/bit. In addition to Therefore, the upper limit to SEL at 200 MeV was about SBUs, we observed burst upsets. Upsets at many logically 2x10-11 cm2/device. (often) consecutive address locations constituted one burst. We counted the numbers of burst upsets in order to calculate 10-8 the cross-sections. These events took place at the LET value 10-10 of 18 MeV/(mg/cm2). At other LET values, we did not detect ) 2 burst upsets possibly due to a higher rate of SEFIs. We 10-12 observed SEFIs for which the affected address locations Burst, all pts upper limits 10-14 SBU, upper limit for 9.8 MeV exceeded many more than 1000 and the affected locations SEFI, upper limit at 9.8, 12, 20, 30 MeV could not be written over unless a power cycle had been 10-16 applied. The sensitivity for SEFI often exceeded that for burst 10-18 upsets. SEFI results are also shown in Fig. 8. At the LET (cm Section Cross value of 0.1 MeV/(mg/cm2), we did not detect SEFI yielding 10-20 an upper limit of about 9x10-8 cm2/device. No SEL was 10-22 observed. 0 20 40 60 80 100 120 140 160 180 200 220 Proton Energy (MeV) -2 10 Fig. 9. Proton induced Burst Upset (cm2/dev.), SEFI (cm2/dev.), and SBU 2 10-4 (cm /bit) sensitivity for Samsung 2 Gb DDR2 SDRAM.

) -6 2 10 10-8 IV. SEE SENSITIVITY VARIATIONS WITH REFRESH RATE Burst, upper limit at LET=0.1, 1.6, 4.0 -10 10 SBU, upper limit at LET=0.1 SEE sensitivity variation for the change in the refresh rate 10-12 SEFI, upper limit at LET=0.1 was investigated with an Elpida DDR2. While irradiating

-14 with 50 MeV protons, we changed the refresh rate from the

Cross Section (cm Section Cross 10 normal value of 7.8 microseconds to a value that was four 10-16 times faster (1.95 microseconds) on one occasion and to a 10-18 value that was four times slower (31.2 microseconds) on 0 5 10 15 20 25 30 35 another occasion. The changes for the sensitivity are shown LET (MeV-cm2/mg) in Fig. 10.

Fig. 8. Heavy ion induced Burst Upset (cm2/dev.), SEFI (cm2/dev.), and SBU (cm2/bit) sensitivity for Samsung 2 Gb DDR2 SDRAM. 10-8

-10 Protons: SEE sensitivity of this device type for protons is 10

) -12 shown in Fig. 9. SBUs similar to those observed with heavy 2 10 ions were present as shown in the figure. Most upset bits Burst 10-14 were from logical “1” to logical “0” for all proton SBU irradiations. Some (about 5%) were from logical “0” to 10-16 logical “1”. Since the numbers of upset bits were near mid -18 10’s for most test runs above 30 MeV for this device type, 10 Cross Section (cm Section Cross there would be some statistical uncertainties associated with 10-20 them. In some cases the number of upset bits was about 30 10-22 for one run, yielding the statistical uncertainty to about 20% 0 5 10 15 20 25 30 35 (5.5/30) equivalent to one standard deviation. For runs below Refresh Rate (us) 30 MeV, the number of upset bits was about 4 for one run, Fig. 10. 50 MeV proton induced Burst Upset (cm2/dev.) and SBU (cm2/bit) yielding the statistical uncertainty to about 50% (2/4) sensitivity vs. Refresh Rate for Elpida 2 Gb DDR2 SDRAM. equivalent to one standard deviation. We observed SEFIs for this device type for protons of energy levels at 50 and 200 Since the numbers for events were not numerous, the MeV. Relevant SEFI cross-sections are shown in the figure. results indicate that there were no significant changes in No SEFIs were observed for energy levels below (and sensitivity for those rates that were utilized. We carried out including) 30 MeV yielding the upper limits to the cross- similar tests with heavy ions. The results for burst upset sections as shown in the figure. In addition to SBU and sensitivity are shown in Fig. 11. Again we did not observe SEFIs, we tried to measure the burst upset sensitivity. The any significant changes for the present range of the rate numbers of affected address locations for a burst upset would change. be limited to less than about 1000. However, at all energy

10-3 [3] R. Koga, et al., IEEE Radiation Effects Data Workshop Record, pp199- 203, 2007 LET = 6.9 MeV-cm2/mg [4] M. O’Bryan, et al., IEEE Radiation Effects Data Workshop Record, pp11-20, 2008 ) 2 [5] M. O’Bryan, et al., IEEE Radiation Effects Data Workshop Record, 10-4 pp15-24, 2009 [6] R. Ladbury, et al., IEEE Radiation Effects Data Workshop Record, pp42-46, 2008.

10-5 Cross Section (cm Section Cross

10-6 012345678910 Refresh Rate (microseconds)

Fig. 11. Heavy ion induced Burst Upset (cm2/dev.) sensitivity vs. Refresh Rate for Elpida 2 Gb DDR2 SDRAM.

V. TOTAL IONIZING DOSE TID sensitivity of these devices as measured with functional integrity seems to show that similar DDR2 devices are tolerant to a reasonably high dose (on the order of 100 krad(si)) [6]. It is our experience that present test samples exhibited similar results.

VI. DDR3 SDRAM SENSITIVITY A few DDR3 test samples manufactured by Elpida and Micron were tested for their sensitivity to 30 MeV protons recently. The nominal bias voltage was 1.5 V (VDD = 1.5 V.) Their test results appeared very similar to what we had obtained for DDR2 devices belonging to the same manufacturer. An Elpida DDR3 sample (EDJ1116BASE-AE- E) revealed that it was sensitive to SBU and burst upsets, but not to SEFI. However, a Micron sample (MT41J64M16) was sensitive to SBU and burst upsets, as well as to SEFI when irradiated with 30 MeV protons. The respective upset cross- sections were comparable to those obtained with DDR2 samples for the same manufacturer.

VII. CONCLUSION DDR2 SDRAMs of various manufacturers show varying sensitivity to SEE. Among various types of SEE, we have observed SBU, MBU, burst upset, and SEFI in varying degrees with the present test samples manufactured by Micron Tech., Samsung, Hynix, and Elpida. For device type such as Elpida, we have not detected SEL or SEFI sensitivity.

All trademarks, service marks, and trade names are the property of their respective owners.

VIII. REFERENCES; [1] J. Schaefer, et al., IEEE Radiation Effects Data Workshop Record, pp106-113, 2009. [2] R. Ladbury, et al., IEEE Radiation Effects Data Workshop Record, pp126-130, 2006.

90-nm Digital Single Event Transient Pulsewidth Measurements

Reed K. Lawrence, Jason F. Ross and Neil E. Wood

technique to measure digital SET (DSET) pulsewidths from a Abstract— Single event transient (SET) pulsewidth 90 nm test chip built on an epitaxial substrate. The results measurements were made on 9SF 90 nm shift registers built with shown will help circuit designers determine the temporal delay temporal delay latches on epitaxial substrates. Data was gathered required for a given SER. The objective of this work is to using heavy ions from LETs of 9.75 to 58.78 (MeV-cm2)/mg. increase the available information on SET pulsewidth measurements for the 90 nm technology node. Index Terms—single event transient, DSET

II. TEMPORAL LATCH DESCRIPTION I. INTRODUCTION ATCH hardening by temporal sampling techniques have A. Temporal Sampling Latch Laddressed both static latch SEUs (single event upsets) BAE Systems, with permission from MicroRDC, as well as SET induced errors. The objective has been to implemented a version of the temporal delay latch into a 90 reduce SERs (soft error rates) in modern microcircuits with nm test chip on a custom version of 9SF (22A gate oxide, minimal impact on design flow, physical layout area, and custom high Vt, low doped epitaxy on high doped substrate). circuit performance [1]. Reasons for circumventing SET BAE Systems did not manufacture the 90 nm test chip. The events evolve around the recognition that for scaled top sub-figure in Fig. 1 shows a schematic of the temporal technologies SETs can exceed a designed SEU hardening latch [1], and the bottom sub-figure in Fig. 1 shows a technique, and that SETs from combinational logic potentially schematic of the current starved inverter [6]. The structure is can exceed the SER as determined by static latch upsets and designed to measure the width of the heavy ion induced finally there are limited techniques to harden combinational transient pulse at various LETs. The analog pins, Vref P and logic. Successful SET reduction techniques use a rejection Vref N, control the temporal delay in the latch. This type of strategy of transients at the static latch structure. An test structure is useful for converting a transient pulse into the implementation of this technique is the use of the temporal measurable output of a static latch. The circuit allows a latch structure [1] [2]. The temporal latch rejects external or measurement of SETs at the circuit level as a function of SET internal heavy ion induced transients with a pulsewidth filter pulsewidth. below a design set point [2]. From an experimental standpoint, the temporal latch is good for measuring SET pulsewidths. In this study we use the temporal latch to measure static pulsewidths in a 9SF 90 nm MUX D drop-in test chip. Another useful technique (or circuit) is the ΔT MAJ Q measurement of the SET propagation distance through a chain of typical combinational cells. This propagation technique CLK 2ΔT relies on a target circuit functioning as the source of SETs which then propagates into a measurement circuit [3]. It has also been shown that the operating temperature of the die can impact the SET pulsewidth, but not the cross section [4]. The impact being that in a given environment, longer transients could be observed with increasing temperatures, but the transient count would not increase [4]. In this work we used the temporal latch measurement Fig. 1. Top: schematic drawing of variable temporal latch test structure used to pass or reject heavy ion induced transients; Bottom: schematic of current starved delay inverter. Manuscript was received on July 19, 2010. This work was supported by Defense Threat Reduction Agency (DTRA), under contract# DTRA 01-03-D- B. Temporal Sampling Latch 0007-000. BAE approved ID# ES-MVA-062410-0207. Fig. 2 shows the basic SET test structure used in this study. R.K. Lawrence, J.F. Zimmerman and J.F. Ross are with BAE Systems, 9300 Wellington Road, Manassas, VA 20110 USA, R.K. Lawrence phone: The circuit is a chain of 280 registers with two variable 703-367-2450; fax: 703-367-3540; e-mail: [email protected], temporal latches per register. The registers were designed with [email protected] and [email protected].

separate clocks. It takes two clock cycles to load a register. TABLE I The clock separation reduces timing sensitivity. We designed LBNL HEAVY ION PARTICULARS four chains. Two chains were 60x power level and two chains 10 MeV/nuc Beamline were 120x power level; where power is FET(width/length). The 120x is twice the drive strength of the 60x, and the 60x is LET Range Ion considered high power relative to minimum design rules. ((MeV-cm2)/mg) (μm)* Within each power level one chain had two current starved Ar 9.74 174.6 inverters in its ΔT delay path (termed short) and the other had Cu 21.17 108 four current starved inverters in its ΔT delay path (termed Kr 30.86 113.1 Δ long). In this abstract we show results for the 120x short T Xe 58.78 90 delay path latch. SETs generated within this circuit are only * Ion, LET and range are from LBNL; see captured if the amplitude and pulsewidth are at the switch http://user88.lbl.gov/subpage2.html point of the latch circuit (1.2V technology). Captured SET pulsewidths are SETs which will affect digital CMOS logic. SET pulses (no matter how wide) will not be captured if they IV. SET DATASET AND DISCUSSION have insufficient amplitude. This methodology allows the assessment of heavy ion induced transients on CMOS digital A. SET Capture Approach logic without the need to measure their pulse shape or SET testing utilized the approach of low error rate amplitude [2] detection. Each register string had 280 readable latches and the ideal error capture count per beam shot should be 15% or III. H EAVY ION TESTING less of the maximum latch count to avoid a double latch flip A DSET test was conducted at Lawrence Berkeley National condition. This test approach is controlled by proper selection Laboratory (LBNL) using their 88 inch cyclotron. The of a fixed beam fluence and beam flux at the beginning of exposures were done with V(I/O) = 1.2 V (nominal voltage), each ion selection. Shown in Fig. 3 are captured error counts Vdd = nominal – 10% (1.08 V), Vref N varied from 1.2 V per static beam shot versus ion and temporal latch delay. down to 0.5 V and Vref P varied from 0V up to 0.5V. Beam This dataset is for the 120x power design with the shorter 5 7 2 fluences varied from 2x10 to 1x10 ions/cm with fluxes ΔT delay starved inverter chain. For the ion Ar at 45-degree 3 5 2 varying from 2.4x10 to 1.5x10 ions/(cm -sec). Beam shots (LET = 13.77 ((MeV-cm2)/mg)) the base latch delay is were done normal (0-degree), 30 and 45 degree to die surface. sufficient to block the majority of SETs. For the larger LET Exposures and measurements were done at room temperature. ions (Cu through Xe) the temporal latch is able to capture the A JDI tester was used to load and read patterns. Testing used heavy ion induced transients and apply progressively patterns of all 0’s, all 1’s and checkerboard. The majority of increasing delay times sufficient to block the passing of all test results used a checkerboard pattern. All testing was done transients. The dataset of Kr at 0-degree is a good example of in static mode. Table I shows the ion particulars for the LBNL the linearity of a decreasing error capture count versus an beamline. increasing temporal latch delay time.

Clock Odd

Clock Even

Vref_N & Vref_P Data Out Data In D Q D Q D Q D Q D Q D Q > > > > > > Latch Latch Latch Latch Latch Latch

Register_1 Register_2 Register_280

Fig. 2. Schematic diagram of SET test register chain.

45 40 35 30 25 20 15 10

Number of Bit-Errors of Number 5 0

Berkeley-5 Dec 2009 10 MeV/nuc 83 ps 90 ps 83 ps 83 ps 83 ps 83 ps 90 ps 83 ps 83 ps 90 ps 118 ps 118 118 ps 118 ps 118 118 ps 118 100 ps 100 100 ps 100 ps 166 ps 310 ps 100 ps 166 ps 310 ps 100 ps 166 ps 310 ps 100 ps 166 ps 310 ps 100 ps 166 ps 310 100 ps 100 ps 166 ps 310 1.62 ns1.62 1.62 ns1.62 LET= 13.77 21.17 24.45 29.94 30.89 43.69 58.78 Ion= Ar Cu Cu Cu Kr Kr Xe Angle= 45 0 30 45 0 45 0

Fig. 3. Heavy ion dataset for the 120x short register.

B. Current Starved Inverter Sensitivity

As discussed in detail in [6], application of 90nm SET Structure Chain#3 120x Short (Device D4) reduced/increased voltage values to Vref-N/Vref-P decreases 40 35 the current through the starved inverter; and as such, the Kr(45) LET=43.69 response of the inverter is slowed. A caution does exist; there 30 is a voltage for which the delay quickly becomes nonlinear 25 (increases), and will cause a large measurement error. The top 20 Delay for Zero Upsets sub-figure in Fig. 4 shows a diagram indicating the signal 15 adj(value)= 400 ps Measured Value response for varying Vref P and Vref N. The bottom sub- 10 Above Prediction Threshold Number ofNumber Bit-Errors figure in Fig. 4 shows flush delay measurements for the 120x 5 chain. For our 120x short circuit, Vref-P = 0.5V and Vref-N = 0 0.7V was the voltage knee for the timing inflection point. 0 500 1000 1500 2000 Delay (ps) Fig. 5 shows a method to correct for the long delay step size for large delay times. In Fig. 5 we have plotted the error Fig. 5. Kr 45-degree dataset plotted versus delay time to show extraction of capture count versus delay time and utilized the linear long-time delay value. relationship observed from the other more well behaved lower C. Pulsewidth for Maximum SET Rejection LET datasets. This approach allows an adjusted delay to be The SET test structure used in this work allows for the extrapolated for the 100% SET blocking delay value. For the measurement of the width of an SET event by incrementally 120x chain this technique was used on the Kr 45-degree and increasing the delay (pulsewidth filter) until the circuit Xe 0-degree datasets. transitions from passing the transient to completely blocking

the transient. Fig. 6 shows the blocking transient pulsewidth for this dataset. The pulsewidths are in the range of 83 ps (circuit minimum) to just over 400 ps. These values compare low with respect to [3], and the likely reasons are our use of a higher power FET (size) design and the use of an epitaxial substrate. In [3], a SET propagation capture circuit was used; 10000 however, the overall number of inverters that can generate a 1000 transient is likely to be the same with respect to our use of a

100 Vdd= 1.08V temporally delayed latch. With regard to the measured (ps) 120x Short pulsewidths greater than a ns in Fig. 6 at higher LET values 10 120x Long (uncorrected values), our explanation for these values is due to

Flush Delta Delay Time DeltaFlush Time Delay 1 our large granularity in our Vref step size, but angular Vref (n)= 1.1 1.0 0.9 0.8 0.7 0.6 [V] sensitivity (charge sharing and nodal coupling) cannot be Vref (p)= 0.1 0.2 0.3 0.4 0.5 0.6 [V] excluded [5]. Fig. 7 shows the same data, but viewed for the observation of the known linear dependence with increasing Fig. 4. Top: diagram showing impact of Vref P and Vref N on starved LET [6]. Our weak dataset linear dependence is more a inverter signal; Bottom: Flush delta delay measurements from the 120x short and long current starved inverter chains reflection of the coarse Vref P and Vref N step size used than a deviation from the accepted linear relationship.

1800 E. Additional Characterization 1600 120x Short From The SET test circuits also were characterized versus 1400 Measurements temperature to see if SET pulsewidth broadening could be 1200 observed [4]. The circuits was heavy ion tested with Kr at 0- 1000 800 Extrapolated degree (LET=30.89) and 30-degree (LET=35.67). The 600 Values temperature measurement points were 25C, 50C, 100C and 400 140C. At each LET test point the flux and fluence were held

Delay For No Upsets (ps) No Upsets For Delay 200 constant. The error capture results for 30-degree are shown in 0 Fig. 8. A small increase in the error capture count with increasing temperature and a small increase in delay needed 9.74 11.25 13.77 21.17 24.45 29.94 30.89 43.69 58.78 LET ((MeV-cm2)/mg) for 100% SET blocking at 140C can be observed. Our conclusion was that our test circuit did not show a strong SET Fig. 6. The delay values for blocking all transients. The extrapolated values pulsewidth broadening dependence on temperature. used the technique as shown in Fig. 5.

12 600 120x short chain V(I/O)= 1.2 V, Vdd= 1.08 V 10 Vn(ref): 1.2 to 0.5 V; Vp(ref): 0 to 0.5 V

500 8

400 6 4 300 small Number of of Bit-Errors Number 2 increase 200 0

-2 100 Delay For For No Upsets Delay (ps) 120x Short 83 ps 83 ps 83 ps 83 ps 100 ps 100 ps 166 ps 310 ps 100 ps 166 ps 310 ps 100 ps 166 ps 310 100 ps 100 ps 166 1.62 ns 1.62 0 ns 1.62 Temp= 25C 50C 100C 140C 0 20406080LET= 35.67 Berkeley LET ((MeV-cm2)/mg) Ion= Kr Angle= 30 10 MeV/nuc Fig. 8. The delay values for blocking all transients. The extrapolated values Fig. 7. For the dataset from Fig. 6, a plot showing the near linear used the technique as shown in Fig. 5. dependence between delay and LET.

The SET test circuits were also characterized with low D. SET versus Internal Delay energy protons while at LBNL. The incident proton energies Fig. 8 shows the SET data plotted as cross section versus were 3 MeV (LET=0.08) and 1 MeV (LET=0.18). The testing LET as a function of delay time. This data represents the delay was done at 25C. The circuit voltage ranged from Vdd=1.08V within the variable temporal 120x short latch design. The to 0.9V (lowered to increase error capture sensitivity). No shortest delay was 83 ps. Consistent with [2] we observe a SETs were detected for all beam exposures and this distribution in SET pulsewidths at a given LET and an observance could be due to the use of a high power inverter improved SEE hardness with increasing the internal temporal design [7]. latch delay. SER calculations from Creme96 (NRL website) for a Geo-min environment with 100 mils of Al shielding V. SUMMARY indicate a reduction in SER from 4x10-9 u/b-d (Weibull #1) to This work has overviewed test results from a heavy ion SET 1x10-11 u/b-d (Weibull #3). pulsewidth characterization test on shift register chains built with temporal delay latches. The results are from a custom 90 1x101.E-06-6 nm 9SF design manufactured with thin epitaxy on a high Delay doped substrate. The latch delay values shown in this work are 83 ps 1.E-07-7 representative of a design with higher power inverters versus a 1x10 90 ps 100 ps commercial minimum-power design optimized for 1.E-08-8 performance. The results should assist designers by showing /register) 1x10 118 ps 2 166 ps the variation in delay values versus other sources of (cm -9 Spread in Cross Section 310 ps information in the open literature. 1x101.E-09 is Due to Delay in

SET Error Cross Section Weibull#1 Temporal Latch Weibull#2 1x10-10 VI. ACKNOWLEDGMENT 1.E-10 Weibull#3 0 20406080 LET ((MeV-cm2)/mg) The authors would like to thank A.T. Kelly, N.F. Haddad and J.C. Rodgers of BAE Systems for helpful discussions on Fig. 8. Dataset for 120x short chain. 90 nm circuits.

VII. REFERENCES [1] D.G. Mavis and P. H. Eaton, “Soft Error Rate Mitigation Techniques for Modern Microcircuits,” 40th Annual Intern. Reliability Physics Symposium, Dallas, TX, pp. 216-225, 2002. [2] J.M. Benedetto, P.H. Eaton, D.G. Mavis, M. Gadlage and T. Turflinger, “Variation of Digital SET Pulse Widths and the Implications for Single Event Hardening of Advanced CMOS Process,” IEEE Transactions on Nuclear Science, Vol. 52, pp. 2114-2119, 2005. [3] B. Narasimham, B.L. Bhuva, R.D. Schrimpf, L.W. Massengill, M.J. Gadlage, O. A. Amusan, W.T. Holman, A.F. Witulski, W.H. Robinson, J.D. Black, J.M. Benedetto and P.H. Eaton, “Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies,” IEEE Transactions on Nuclear Science, Vol. 54, pp. 2506- 2511, 2007. [4] M.J. Gadlage, J.R. Ahlbin, B. Narasimham, V. Ramachandran, C.A. Dinkins, B.L. Bhuva, R.D. Schrimpf and R.L. Shuler, “The Effects of Elevated Temperature on Digital Single Event Transient Pulse Widths in a Bulk CMOS Technology,” 47th Annual Intern. Reliability Physics Symposium, Montreal, Canada, pp. 170-173, 2009. [5] M.P. Baze, B. Hughlock, J. Wert, J. Tostenrude, L. Massengill, O. Amusan, R. Lacoe, K. Lilja and M. Johnson, “Angular Dependence of Single Event Sensitivity in Hardened Flip/Flop Designs,” IEEE TNS, Vol. 55, No. 6, pp. 3295-3301, 2008. [6] P. Eaton, J. Benedetto, D. Mavis, K. Avery, M. Gadlage and T. Turflinger, “Single Event Transient Pulsewidth Measurements Using a Variable Temporal Latch Technique,” IEEE Transactions on Nuclear Science, Vol. 51, pp. 3365-3368, 2004. [7] R.K. Lawrence, J.F. Ross, N.F. Haddad, R.A. Reed and D.R. Albrecht, “Soft Error Sensitivities in 90 nm Bulk CMOS SRAMs,” IEEE Radiation Effects Data Workshop, pp. 123-128, 2009.

SEE Results for a 4-Port SpaceWire Router

Craig Hafer , Member, IEEE , Brian Baranski, Jennifer Larsen, Fred Sievert, Anthony Jordan

space is provided for each port and having separate look up Abstract-- A 4-Port SpaceWire Router has been designed, tables reduces bottle necks by allowing each port access to a manufactured, and characterized for radiation effects. The non-shared lookup table. The device operates from -40°C to device is SEL immune and TID tolerant to 100 krad(Si). The +105°C at nominal power supply voltages of 3.3V I/O and SEE performance is summarized. 2.5V core.

I. INTRODUCTION III. SINGLE EVENT EFFECTS CHARACTERIZATION APPROACH HE SpaceWire protocol offers a number of advantages To characterize the 4-Port SpaceWire Router device for Tover other system communication protocols. The single event effects (SEE), gold, xenon, krypton, and argon protocol offers user defined packet structure, flexible heavy ions were used at an angle of incidence from normal operating frequencies, and a low voltage physical layer. (0°) to a maximum of 31°, producing a range of LETs from System reliability is improved in a distributed or centralized 10 to 102 MeV-cm2/mg. The testing was performed at the network where multiple routers allow for redundant data Texas A&M University Cyclotron Institute using the 15 paths. This router has been characterized for radiation MeV/amu beam energy. performance. The device is single event latchup (SEL) SEL testing was done at 105°C at maximum operating V immune to a linear energy transfer (LET) greater than 100 DD (3.6V I/O and 2.75V core) and SEU testing was done at 25°C MeV-cm2/mg. The device is total ionizing dose (TID) at minimum operating V (3.0V I/O and 2.25V core). A tolerant to 100 krad(Si). The single event upset (SEU) DD 255-land grid array (LGA) package was used during SEE performance has been characterized. testing. The entire device was exposed to the heavy ion beam. II. PRODUCT DESCRIPTION The device under test (DUT) board contained one socket to The 4-Port Router is capable of operating at data rates from accommodate the 255-LGA package. After milling away 10 to 200 Mbps. The router implements a non-blocking some of the thick socket material, the device was fully crosspoint switch and a "Round Robin" arbitration scheme exposed to the heavy ion beam with a maximum 31° angle of allowing all five receive ports, including the system interface rotation. The devices were statically biased and the power port, access to all five transmit ports. Path and logical supply current monitored during the duration of each SEL addressing schemes are supported and are compatible to test run. Before and after each SEL test run, the devices were ECSS-E-ST-50-12C [1]. Each of the four SpaceWire ports is functionally tested without cycling the power supply. capable of running at an independent speed which allows the A 4-Links tester [2] was used for both SEL and SEU system to be configured with nodes/instruments running at testing and supplied the router input with SpaceWire data different data rates. If different node/instrument sampling packets and monitored the output data of the 4-Port Router. times can vary, a more efficient power management scheme The Host Interface Port was connected to a Xilinx FPGA and can be achieved. The physical interface can be either LVDS was used to initialize the logic configuration, monitor the 4- or LVCMOS. This allows the user to select the interface that Port Router operation, and correct the logic configuration as best meets system and reliability requirements. The LVDS necessary. The 4-Links tester was used to initialize the 4- interface can directly connect and drive up to 10 meters of Port Router lookup tables for the lookup table test. The cable. The LVCMOS interface must interface to LVDS lookup table configuration was only used during SEU testing drivers and receivers. Independent look up table memory for the lookup table test. Properly encoded, per the SpaceWire Standard, ECSS-E-ST-50-12C, pseudo-random data was transmitted through the 4-Port Router device. The Manuscript received July 17, 2009. C. Hafer is with Aeroflex Colorado Springs, Colorado Springs, CO 80907 4-Links tester transmitted the data through Port 1 and through USA (telephone: 719-594-8319, e-mail: [email protected]). a daisy-chain pattern; the data was routed through all four B. Baranski is with Aeroflex Colorado Springs, Colorado Springs, CO ports and then received back into the 4-Links tester. The 4- 80907 USA (telephone: 719-594-8081, e-mail: [email protected]). J. Larsen is with Aeroflex Colorado Springs, Colorado Springs, CO Links tester categorized and logged the error types as listed. 80907 USA (telephone: 719-594-8449, e-mail: [email protected]). The category of error reported could be the result of a F. Sievert is with Aeroflex Colorado Springs, Colorado Springs, CO different type of error as noted in the Error End of Packet 80907 USA (telephone: 719-594-8423, e-mail: [email protected]). A. Jordan is with Aeroflex Colorado Springs, Colorado Springs, CO (EEP) description. 4-Port Router Protocol handling allows 80907 USA (telephone: 719-594-8252, e-mail: [email protected]). the device to fully recover after an error.

Parity Error – This error occurs when one bit in a word does not match the expected polarity (per ECSS-E-ST-50- Pre- Post- Effective Angle of IDD IDD Effective LET 12C Section 7.4). Serial Incidence Latchup I/O, Core I/O, Core Fluence (MeV- Incorrect Data – When this error occurs, the read data does Number Ion (°) (y/n) (mA) (mA) (ions/cm2) cm2/mg) not match the expected data. A bit flip in the data most likely 7 Au 31 n 93/6.8 93/6.8 1x107 102 7 occurred before the parity bit was calculated (per ECSS-E- 9 Au 31 n 89/7.2 89/7.2 1x10 102 7 ST-50-12C Section 10.5). 2 Au 31 n 90/7.2 90/7.2 1x10 102 10 Au 31 n 91/7.3 91/7.3 1x107 Incorrect Packet Length – When this error occurred a 200 102 byte packet was always received shorter than expected. V. SEU RESULTS Incorrect Packet Sequence – The cause of this error may be a dropped packet; the result of a parity error, time out error, The SEU Weibull parameters and error rate predictions are link reset, bad command, incorrect address, or an error in one shown in Table II. The error rate calculations were done with bit of the byte identifying the sequence. SpaceRadiation 5.0 using a Weibull analysis assuming a Error End of Packet (EEP) – During proper operation end geosynchronous orbit, the Adams 90% worst case of packet (EOP) is recorded. There is no check of the data environment, a device depth of 0.25µm, a funnel depth of before an EEP error is recorded and so the actual cause is not 0.25µm, and 100 mil aluminum shielding. A total of five directly known. EEP were mainly observed with incorrect router devices were SEU tested. The error frequency is the packet length errors (per ECSS-E-ST-50-12C Section 4.4). average time between bit errors to the device and assumes all Lookup Table – The 4-Port Router contains six lookup ports and lookup table bits are used. 4-Port Router Protocol tables with 2,016 memory cells per table. One table was handling allowed the device to fully recover after each error. interrogated directly to determine the SEU cross-section data Most of the test runs were performed with a clock speed of (per ECSS-E-ST-50-12C Section 4.4). 100MHz. Five test runs were done at a frequency of 10MHz 4-Link Stop – Program execution stops when this error as highlighted in Figs. 2 through 5 and generally yielded a occurs and requires a 4-Links software restart. No reset of lower cross-section as compared to the 100MHz data. the 4-Port Router device is necessary. This execution stop 2,016 cells (or bits) in one of six lookup tables were tested will not occur in a system with software which monitors the for SEUs. The calculated error frequency for the lookup run, full, and error flags and resets FIFOs or ports as tables assumes that all cells from all lookup tables are being appropriate. used. Fig. 1 shows a diagram of the SEU test system. TABLE II SINGLE EVENT UPSET WEIBULL PARAMETERS, AND ERROR RATE PREDICTIONS DUT Card Onset Event RX Saturated Cross- LET Frequency Port 1 Error Weibull Weibull Cross- section (MeV- Event- Event- (device- 4-Port TX 4-Links Router Tester Type Shape Width section Units cm2/mg) Rate Rate Units years/event)

RX Parity upsets/ 2.0 60 2.4x10-7 cm2/port 28 3.4x10-9 200,000 RX Port 2 Error port-day Xilinx Host TX Monitor TX Port RX Incorrect upsets/ 1.2 20 9.0x10-7 cm2/port 28 7.0x10-8 9,800 Port 3 Data port-day TX

RX Incorrect upsets/ 1.2 20 1.1x10-6 cm2/port 28 8.9x10-8 7,700 Port 4 Length port-day TX PC Incorrect upsets/ 1.2 20 1.1x10-6 cm2/port 28 8.9x10-8 7,700 Sequence port-day Fig. 1. Test setup for SEU testing. upsets/ EEP 1.2 20 1.1x10-6 cm2/port 28 8.9x10-8 7,700 port-day ESULTS IV. SEL R Lookup upsets/ 1.2 80 5.3x10-9 cm2/bit 28 1.7x10-11 13,000 Four router devices were tested for SEL. As seen in Table Table bit-day I, no single event induced latchups occurred when the devices 4-Link upsets/ 1.8 75 4.2x10-7 cm2/port 28 5.8x10-9 120,000 Stop port-day were exposed to xenon ions at an effective LET of 102 MeV- cm2/mg to an effective fluence of 1.0x107 ions/cm2. The devices tested for SEL were all functional both pre- and post- Cross-section versus LET data for all error types are irradiation. They were tested without cycling the power shown in Figs. 2 through 8. The numbers in the legend of supplies both before and after heavy ion beam irradiation. each plot represent the device serial number.

TABLE I SINGLE EVENT LATCHUP DATA FOR FOUR SAMPLES.

1E-6 1E-5 Weibull = zero errors represented with Weibull = zero errors represented with tail of arrow assuming 1 error tail of arrow assuming 1 error 10 10 9 9

/ port) 7 1E-6 / port) 2 7

1E-7 2 2 2 6 6 1E-7 2X

1E-8 1E-8 10 MHz Cross(cm Section

10 MHz (cm Section Cross

1E-9 1E-9 020406080100 0 20406080100 LET (MeV-cm2/mg) LET (MeV-cm2/mg)

Fig. 2. Parity Error – This error occurs when one bit in a word does not Fig. 5. Incorrect Packet Sequence – The cause of this error may be a match the expected polarity (per ECSS-E-ST-50-12C Section 7.4). dropped packet; the result of a parity error, time out error, link reset, bad command, incorrect address, or an error in one bit of the byte identifying the sequence. 1E-6

Weibull 1E-5 10 Weibull = zero errors represented with 9 10 tail of arrow assuming 1 error

/ port) 7 9

2 1E-7 1E-6 2 / port) 7 10 MHz 2 6 2 6 1E-7

1E-8 10MHz

1E-8

Cross Section (cm Section Cross = zero errors represented with

tail of arrow assuming 1 error Cross(cm Section 1E-9 0 20406080100 1E-9 LET (MeV-cm2/mg) 020406080100 LET (MeV-cm2/mg) Fig. 3. Incorrect Data – When this error occurs, the read data does not match the expected data. A bit flip in the data most likely occurred before the Fig. 6. Error End of Packet (EEP) – During proper operation end of packet parity bit was calculated (per ECSS-E-ST-50-12C Section 10.5). (EOP) is recorded. There is no check of the data before an EEP error is recorded and so the actual cause is not directly known. EEP were mainly observed with incorrect packet length errors (per ECSS-E-ST-50-12C 1E-5 Section 4.4). Weibull = zero errors represented with 10 tail of arrow assuming 1 error

9 1E-8 1E-6

/port) 7 2 2 6 10 MHz 1E-7 / bit) 2 1E-9

1E-8 Cross Section (cm Section Cross 1E-10

1E-9 Weibull

Cross(cm Section 10 0 20406080100 9 LET (MeV-cm2/mg) 1E-11 Fig. 4. Incorrect Packet Length – When this error occurred a 200 byte packet 0 20406080100 was always received shorter than expected. LET (MeV-cm2/mg)

Fig. 7. Lookup Table – The 4-Port Router contains six lookup tables with 2,016 memory cells per table. One table was interrogated directly to determine the SEU cross-section data (per ECSS-E-ST-50-12C Section 4.4).

1E-6

= zero errors represented with tail of arrow assuming 1 error / port)

2 1E-7

1E-8 Weibull 9

Cross Section (cm Section Cross 7 6 1E-9 0 20406080100 LET (MeV-cm2/mg)

Fig. 8. 4-Link Stop – Program execution stops when this error occurs and requires a 4-Links software restart. No reset of the 4-Port Router device is necessary. This execution stop should not occur in a system with software which monitors the run, full, and error flags and resets FIFOs or ports as appropriate.

VI. DISCUSSION Four devices were tested for SEL and found to be latchup immune to a LET of 102 MeV-cm2/mg to a fluence of 1x107 ions/cm2 when tested under worst case temperature and power supply voltage conditions. SEU testing was performed using a 4-Links tester. Aeroflex developed software code was programmed into a Xilinx FPGA on the device under test (DUT) card and in conjunction with the 4-Links tester, seven categories of errors were logged and reported. The minimum calculated average time between events for any of these error types is 7,700 years based on SpaceRadiation 5.0 calculations for geosynchronous orbit and the Adam’s 90% worst case environment. Fluences up to 1x108 ions/cm2 were used to generate the SEU data. 4-Port Router Protocol handling allows the device to fully recover after each error.

VII. REFERENCES [1] http://www.ecss.nl/ [2] http://www.4links.co.uk/index.htm

Current Single Event Effects Compendium of Candidate Spacecraft Electronics for NASA

Martha V. O’Bryan, Kenneth A. LaBel, Jonathan A. Pellish, Dakai Chen, Jean-Marie Lauenstein, Cheryl J. Marshall, Ray L. Ladbury, Timothy R. Oldham, Hak S. Kim, Anthony M. Phan, Melanie D. Berg, Martin A. Carts, Anthony B. Sanders, Stephen P. Buchner, Paul W. Marshall, Michael A. Xapsos, Farokh Irom, Larry G. Pearce, Eric T. Thomson, Theju M. Bernard, Harold W. Satterfield, Alan P. Williams, Nick W. van Vonno, James F. Salzman, Sam Burns, and Rafi S. Albarian

Abstract— We present the results of single event effects (SEE) Given this limitation of test data (application-specific), testing and analysis investigating the effects of radiation on studies discussed here were undertaken to establish the electronics. This paper is a summary of test results. sensitivities of candidate spacecraft electronics as well as new electronic devices to heavy ion and proton-induced single Index Terms—Single event effects, spacecraft electronics, event upset (SEU), single event latchup (SEL), and single digital, linear bipolar, and hybrid devices. event transients (SET). For total ionizing dose (TID) and displacement damage results, see a companion paper I. INTRODUCTION submitted to the 2010 IEEE NSREC Radiation Effects Data The performance of electronic devices in a space radiation Workshop entitled: “Current Total Ionizing Dose and environment is often limited by its susceptibility to SEE. Displacement Damage Compendium of Candidate Spacecraft Interpreting the results of SEE testing of complex devices is Electronics for NASA” by D. Cochran, et al. [2]. quite difficult. As discussed elsewhere [1], SEE test data is often application specific and adequate understanding of the II. TEST TECHNIQUES AND SETUP test conditions is critical. A. Test Facilities All SEE tests were performed between February 2009 and This work was supported in part by the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Projects, the Defense Threat February 2010. Heavy ion experiments were conducted at Reduction Agency (DTRA) under IACRO# 09-4587I and 10-4977I, Lawrence Berkeley National Laboratory (LBNL) [3], and at NASA/GSFC Internal Research & Development Program, and the Space Texas A&M University Cyclotron (TAMU) [4]. Both of these Radiation Element Human Research program at NASA/JSC. Martha V. O'Bryan is with MEI Technologies Inc., c/o NASA Goddard facilities are suitable for providing a variety of ions over a Space Flight Center (GSFC), Code 561.4, Bldg. 22, Rm. 062A, Greenbelt, range of energies for testing. The devices under test (DUTs) MD 20771 (USA), phone: 301-286-1412, fax: 301-286-4699, email: were irradiated with heavy ions having linear energy transfers [email protected]. 2 Kenneth A. LaBel, Jonathan A. Pellish, Jean-Marie Lauenstein, Cheryl (LETs) ranging from 0.59 to 120 MeV•cm /mg. Fluxes ranged 2 7 2 Marshall, Ray L. Ladbury, Martin A. Carts, Anthony B. Sanders, and Michael from 1x10 to 1x10 particles/cm /s, depending on device A. Xapsos are with NASA/GSFC, Code 561.4, Greenbelt, MD 20771 (USA), sensitivity. Representative ions used are listed in Table I. phone: 301-286-9936 (LaBel), 301-286-6523 (Pellish), 301-286-5587 (Lauenstein), 434-376-3402 (Marshall), 301-286-1030 (Ladbury), 301-286- LETs between the values listed were obtained by changing the 2600 (Carts), 301-286-8046 (Sanders), 301-286-2263 (Xapsos), email: angle of incidence of the ion beam with respect to the DUT, [email protected], [email protected], jean.m.lauenstein@ thus changing the path length of the ion through the DUT and nasa.gov, [email protected], [email protected], martin the "effective LET" of the ion [5]. Energies and LETs [email protected], [email protected], and michael.a.xapsos@ nasa.gov. available varied slightly from one test date to another. Dakai Chen, Hak S. Kim, Anthony M. Phan, and Melanie Berg are with Proton SEE tests were performed at three facilities: the MEI Technologies, Inc., c/o NASA/GSFC, Code 561.4, Greenbelt, MD 20771 University of California at Davis (UCD) Crocker Nuclear (USA), phone: 301-286-1023 (Kim), 301-286-1239 (Phan), 301-286-8595 (Chen), 301-286-2153 (Berg), email: [email protected], Anthony.M.Phan Laboratory (CNL) [6], the Indiana University Cyclotron @nasa.gov, [email protected] and Melanie.D.Berg @nasa.gov. Facility (IUCF) [7], and at a 2 MeV Van de Graaff particle Timothy R. Oldham is with Perot Systems Government Services, Inc., c/o accelerator. Proton test energies incident on the DUT are listed NASA/GSFC, Code 561.4, Greenbelt, MD 20771 (USA), phone: 301-286- 5489, email: [email protected]. in Table II. Stephen P. Buchner is with Global Defense Technology and Systems, Inc., Laser SEE tests were performed at the pulsed laser facility phone: 202-404-2352, email: [email protected]. at the Naval Research Laboratory (NRL) [8] [9]. The laser Paul Marshall is a Consultant, email: [email protected]. Farokh Irom is with JPL, email: [email protected]. light had a wavelength of 590 nm resulting in a skin depth Larry G. Pearce, Eric T. Thomson, Theju M. Bernard, Harold W. (depth at which the light intensity decreased to 1/e - or about Satterfield, Alan P. Williams, and Nick W. van Vonno, are with Intersil 37% - of its intensity at the surface) of 2 µm. A nominal pulse Corporation, Palm Bay, Florida, email: [email protected]. James F. Salzman is with Texas Instrument, email: [email protected]. rate of 1 kHz was utilized. Sam Burns, Rafi S. Albarian are from Linear Technology, emails: [email protected], [email protected].

TABLE I: HEAVY ION TEST FACILITIES AND TEST HEAVY IONS Biased – the DUT was biased and clocked while power Surface consumption was monitored for SEL or other destructive Energy LET in Si Range in Ion effects. In most SEL tests, functionality was also monitored. (MeV) (MeV•cm2/mg) Si (µm) (Normal Incidence) In SEE experiments, DUTs were monitored for soft errors, LBNL 18O 184 2.2 227 such as SEUs and for hard errors, such as single event gate 22Ne 216 3.5 175 rupture (SEGR). Detailed descriptions of the types of errors observed are noted in the individual test results [11]. 40Ar 400 9.7 130 65 SET testing was performed using a high-speed oscilloscope. Cu 659 21 110 Individual criteria for SETs are specific to the device being 86 Kr 886 31 110 tested. Please see the individual test reports for details [11]. 136Xe 1330 59 97 Heavy ion SEE sensitivity experiments include 10 MeV per AMU tune measurement of the Linear Energy Transfer threshold (LETth) 20 TAMU Ne 300 2.5 316 and cross section at the maximum measured LET. The LETth 40Ar 599 7.7 229 is defined as the maximum LET value at which no effect was 7 2 63Cu 944 17.8 172 observed at an effective fluence of 1×10 particles/cm . In the 84Kr 1259 25.4 170 case where events are observed at the smallest LET tested, 109 Ag 1634 38.5 156 LETth will either be reported as less than the lowest measured 129Xe 1934 47.3 156 LET or determined approximately as the LETth parameter 15 MeV per AMU tune from a Weibull fit. In the case of SEGR experiments, measurements are made of the SEGR threshold V as a 22Ne 545 1.8 799 ds function of LET at a fixed Vgs. 40Ar 991 5.5 493 84 2) SEE Testing - Proton Kr 2081 19.8 332 Proton SEE tests were performed in a manner similar to 139Xe 3197 38.9 286 heavy ion exposures. However, because protons cause SEE 25 MeV per AMU tune via indirect ionization of recoil particles, results are

TABLE II: PROTON TEST FACILITIES parameterized in terms of proton energy rather than LET. Because such proton-induced nuclear interactions are rare, University of California at Davis (UCD) Crocker Nuclear Laboratory (CNL), energy tunes ranged from 6.5 to 63 MeV, flux ranged from 8×107 proton tests also feature higher cumulative fluences and to 1×109 particles/cm2/s. particle flux rates than heavy ion experiments. Indiana University Cyclotron Facility (IUCF), energy ranged from 63 to 5 9 2 3) Pulsed Laser Facility Testing 198 MeV, flux ranged from 5×10 to 3×10 particles/cm /s. The DUT was mounted on an X-Y-Z stage in front of a

TABLE III: LASER TEST FACILITY 100x lens that produced a spot size of about 1.2 μm at full- Naval Research Laboratory (NRL) Pulsed Laser SEE Test Facility width half-maximum (FWHM). The X-Y-Z stage can be Laser: 590 nm, 1 ps pulse width, beam spot size ~1.2 μm moved in steps of 0.1 μm for accurate positioning of SEU sensitive regions in front of the focused beam. An illuminator

together with a charge coupled device camera and monitor B. Test Method were used to image the area of interest, thereby facilitating Unless otherwise noted, all tests were performed at room accurate positioning of the device in the beam. The pulse temperature and with nominal power supply voltages. We energy was varied in a continuous manner using a recognize that high-temperature and worst-case power supply polarizer/half-waveplate combination and the energy was conditions are recommended for single event latchup (SEL) monitored by splitting off a portion of the beam and directing device qualification. it at a calibrated energy meter. 1) SEE Testing - Heavy Ion: Depending on the DUT and the test objectives, one or III. TEST RESULTS OVERVIEW more of three SEE test methods were typically used: Abbreviations and conventions are listed in Table IV. Dynamic – the DUT was exercised continually while being Abbreviations for principal investigators (PIs) are listed in exposed to the beam. The events and/or bit errors were Table V, and SEE results are summarized in Table VI. Unless counted, generally by comparing the DUT output to an otherwise noted, all LETs are in MeV•cm2/mg and all cross unirradiated reference device or other expected output (Golden sections are in cm2/device. This paper is a summary of results. chip or virtual Golden chip methods) [10]. In some cases, the Complete test reports are available online at effects of clock speed or device operating modes were http://radhome.gsfc.nasa.gov [11]. investigated. Results of such tests should be applied with caution due to the application-specific nature of the results. Static – the DUT was loaded prior to irradiation; data were retrieved and errors were counted after irradiation.

TABLE IV: ABBREVIATIONS AND CONVENTIONS TABLE V: LIST OF PRINCIPAL INVESTIGATORS LET = linear energy transfer (MeV•cm2/mg) Principal Investigator (PI) Abbreviation LETth = linear energy transfer threshold (the minimum LET value for which a given effect is observed for a Melanie Berg MB fluence of 1x107 particles/cm2 – in MeV•cm2/mg) < = SEE observed at lowest tested LET Martin Carts MaC > = no SEE observed at highest tested LET σ = cross section (cm2/device, unless specified as cm2/bit) Dakai Chen DC σmax measured = cross section at maximum measured LET Hak Kim HK (cm2/device, unless specified as cm2/bit) ADC = analog to digital converter Kenneth LaBel KL App. Spec. = application specific Ray Ladbury RL BiCMOS = bipolar complementary metal oxide semiconductor Jean-Marie Lauenstein JML CMOS = complementary metal oxide semiconductor Cheryl Marshall CM DUT = device under test EDAC = error detection and correction Paul Marshall PM FPGA = field programmable gate array H = heavy ion test Timothy Oldham TO L = laser test Jonathan Pellish JP LCDT = low cost digital tester LDC = lot date code Anthony (Tony) Sanders AS N/A = not available Michael Xapsos MX P = proton test (SEE) PI = principal investigator POL = point of load SEE = single event effect SEFI = single event functional interrupt SEL = single event latchup SET = single event transient SEU = single event upset SiGe = silicon germanium SEGR = single event gate rupture Vds = drain-source voltage Vgs = gate-source voltage

TABLE VI: SUMMARY OF SEE TEST RESULTS

Test Results LET in Device Tech- Particle: MeV•cm2/mg σ in Part Number Manufacturer LDC 2 Function nology (Facility/Date) P.I., cm /device, unless Supply Supply Tested) Voltage Voltage (Number (Number

otherwise specified Test (Y/N) Reference App. Spec. Spec. App. Sample Size Size Sample ADC : Low energy proton testing to investigate direct ionization. Errors were observed at National proton energies near 1MeV No LDC P: (UCD09JUN) [12] ADC14155 Semi- ADC CMOS and above; All low energy N 5V 2 (test chip) MB [13] conductor errors were analog (no digital errors detected); Potential direct ionization was observed. delidded H: LETth <8.6 (no LET SEE); by TI Comple H: (TAMU09MAY) SEL LETth >75 Texas markings: mentary MB (w/Robert P: SEE σ ranged from 2x10-10 3.3V, H: 2 [13] ADS5483 ADC N Instrument AZ5483 Bipolar MacDowell) cm2/device at 75MeV to 5V P: 4 [14] TI 83K (BiCom3) P: (IU09AUG) MB 2.5x10-10 cm2/device at E7N0 G 198MeV. FPGA: Antifuse RTAX-S Tech- H: (TAMU09DEC) SEL LET >80; 1,5V Core, RTAX2000S Actel 0526 th Y 2 [15] FPGA nology/ MB 2.5 < SEU LETth <8.6 2.5V, 3.3V CMOS H: SEL LETth >75; SEU LETth <2; H: (TAMU09SEPT) P: SEUs observed for all MB; energies tested (0.9, 1.4, 2.3, XC5VLX30T- Virtex V 65nm 1,2V, 1.8V, Xilinx 0849 P: (UCD09JUN) 5.9, 7.8, 13.2, 21.8, and 63.8 Y 3 [17] 1FFG665GU FPGA CMOS -17 2.5V, 3.3V MB; P: (IU09AUG) MeV); SEU σ = 5x10 2 MB cm /bit at 0.9MeV; SEU σ max -14 2 measured = 2x10 cm /bit at ~ 20MeV.

otherwise specified Test (Y/N) Reference App. Spec. Spec. App. Sample Size Size Sample Linear Devices: H: SEL LETth > 49.6; SET LETth < 7.4 SET σ increases linearly with frequency. SETs from 10 MHz signals are relatively minor. At 100 MHz, the SETs appear H: (TAMU09MAY) mostly as short duration [18] Linear 0746; Differential SiGe 2 (May); LTC6400 DC; voltage spikes. At 1000 MHz, N 3 V [19] Technology 0705 Amplifier BiCMOS 1 (Aug) P: (IU09AUG) DC the majority of SETs “erase” [20] the signal for several cycles. -11 P: SET σmax measured 1.5 × 10 cm2 for a fluence of 1 × 1012 particles/cm2, with the device operating at 200 MHz. No SETs were observed at 10 MHz. SET LETth < 4.4 for 200 MHz Texas Operational SiGe H: (TAMU09AUG) waveforms, 15.6 for 100 MHz [20] THS4304 OCT04 N 2.5 V 2 Instrument Amplifier BiCMOS DC waveforms, and 31.2 for 10 [21] MHz waveforms Memory Devices: A commercial sample of a 90nm CMOS phase change non-volatile memory was tested for heavy ion SEE tolerance at TAMU. Static and dynamic tests were performed with a variety of test patterns including checkerboard and inverse checkerboard. Static testing indicated that the phase LDC and 90nm change storage cells were Phase H: (TAMU09AUG) die CMOS hard to the highest tested Part Number: Manufacturer: Change HK, KL; 2.7; 3.0; markings: Non- LET of 112. No permanent N 4 N/A unavailable unavailable Memory H: (TAMU09DEC) 3.6 V un- volatile device failures were (PCM) HK, KL available Memory observed. Even at elevated temperature (70ºC) and Vdd +10%, the device did not suffer permanent failures, though SEL was observed. However, the device showed low SEFI threshold at LET below 2.9 suggesting that control circuits are the weak link. Though non destructive, its low SEL LETth below 2.9 cannot be ignored either. H: SEU LETth<2.8; -3 2 σmax measured ~10 cm /dev; MCU: LETth~10; σmax measured ~5x10-4 cm2/dev; Block Error: LETth~2.8; σmax measured ~5x10-4 cm2/dev; 0813 Stuck bits seen near end of Markings: H: (TAMU09AUG) run; K4B1GO846D- SEC813H DDR3 65 nm Samsung RL SEFI seen at high LET, high Y 1.8 V 2 [22] HCH9 CH9 SDRAM CMOS -7 2 P: (IU09AUG) RL fluence (10 cm < σmax measured GNL037B -4 2 <10 cm ) B P: Tested at 25 MHz with PLL disabled. Proton SEU seen with 80 and 198 MeV protons. Block errors seen with 198 MeV protons.

otherwise specified Test (Y/N) Reference App. Spec. Spec. App. Sample Size Size Sample H: (TAMU09MAY) 0840; 3.3V for TO; AS Bit error LET ~2.8; 0843; 4Gbit NAND th SEU and K9F4G08U0A- H: (TAMU09AUG) Write mode failures were [23] Samsung 0846; Flash CMOS N SEFI, 3.6V 23 PCB0 TO w/F. Irom observed at 70ºC at LET [24] 0901; Memory (3.3 +10%) testing LDC 0907 54.8. 0907 for SEL only 31< SEL LETth <54.8; 2.8 < destructive failure 4Gbit NAND MT29F4G08AA H: (TAMU09AUG) (erase failure) < 8.4; Bit [24] Micron 0744 Flash CMOS N 3.3V 1 AWP TO w/ F. Irom errors were observed at 2.8; [25] Memory SEFIs were observed at LET 8.4; Power Devices: Commer cial 25V N- T NexFET SEB last pass/first fail V = Texas 0916C Channel H: (TAMU09DEC) ds 0Vgs, CSD16403Q5A M n- 13V/14V for LET=27 (Kr) & N 18 [26] Instrument 6W.08 Power JML 5Vgs, 7Vgs channel 41.5 (Ag), at all test V . MOSFET gs lat./vert. hybrid LET=28.1 (Kr): no failure at 0Vgs/400Vds; Failed at - No LDC. Gen 4 n- 15Vgs/330Vds (last pass International Markings Power channel H: (TAMU09MAR) 320V ). 0Vgs; IRH7360SE ds N 11 [27] Rectifier R473288- MOSFET VDMOS JML LET=41.9 (Ag): SEGR at -15Vgs 21 FET 0Vgs/210Vds (last pass 200Vds) and at -15Vgs/140Vds (last pass 130Vds). NA (Part H: (TAMU09MAY; in POL DC/DC SEL / SEB / SEGR ISL70001 Intersil BiCMOS TAMU09AUG) DC N 5.7V >10 [28] develop- Converter LETth>86.4 up to 125ºC w/Intersil ment) Positive and negative Linear Voltage transients were observed V = 5 V, MSK5820-2.5RH M.S. Kennedy 0923 Bipolar L: (NRL09OCT) JP Y in 1 [29] Regulator (−12 to +100 mV), up to a V = 2.5 V Hybrid out width of ~225 µs. Positive and negative Linear Voltage transients were observed V = 5 V, MSK5900RH M.S. Kennedy 0703 Bipolar L: (NRL09OCT) JP Y in 1 [30] Regulator (−20 to +40 mV), up to a V = 2.5 V Hybrid out width of ~200 µs. SET pulse includes a positive and negative voltage spike, with pulse amplitudes = -0.2 Texas Voltage V to 0.2 V and pulse width TPS79133 0710 BiCMOS L: (NRL09JUN) DC N 3.3 V 4 [31] Instrument Regulator (FWHM) = 10-20 µs for each spike. Pulse amplitude and width increase slightly at elevated temperature (373K). Test Chips: Completed further mapping of low-energy proton sensitivity. 2, com- 45 nm No LDC P: (UCD09JUN) JP High-energy proton testing bined Test Vehicle IBM SRAM SOI N 0.6-1.2 V [32] (test chip) P: (IU09AUG) JP was done at approximately from all CMOS 25 MHz for better MCU tests statistics. P: (GSFC09MAY) JP/MX H: (TAMU09MAY) H: SEL observed at effective JP/MX LETs as low as 30, though 6, com- 45 nm Texas No LDC P: (UCD09JUN) portions of SRAM are hard to bined Test Vehicle SRAM bulk N 1.2 V none Instrument (test chip) JP/MX SEL up to LET 60. from all CMOS P: (IU09AUG) P: No SEL observed with tests JP/MX 198MeV protons. H: (LBNL09SEP) JP/MX [33]

otherwise specified Test (Y/N) Reference App. Spec. Spec. App. Sample Size Size Sample Miscellaneous

Devices: Core 1.5 V; I/O 1.8V; No LDC 5 megapixel SEL LET > 87; Fluence H: (TAMU09SEPT) th Analog 2.8 OV5633 Omnivision (image Image CMOS corrected for time part spent N 4 none CM/MaC V; Pixel 2.8 sensor) Sensor in SEFI mode. V; MIPI 1.5V No SEL observed at 40 K, 48 K and 80 K to σlimiting ~2x10-7 cm2 for LET = 102; Single recoverable SEL event LDC and Read Out observed at 32 K to fluence = die Part Number: Manufacturer: Integrated 0.5 µm H: (TAMU09SEPT) 3.5x106 cm-2 at LET = 102; markings: N 5.7 V 2 [34] unavailable unavailable Circuit CMOS CM At 20 K, ROIC sensitive to un- (ROIC) SEL for 12 = LET < 102 with available 2.0x10-5 < σ < 3.7x10-4 cm2 (lowest test LET). At 300 K, SEL σ ~ 1x10-3 cm2 at LET = 87

IV. TEST RESULTS AND DISCUSSION • On-Chip High Impedance Analog Buffer As in our past workshop compendia of GSFC test results, • Efficient DDR LVDS-Compatible Outputs each DUT has a detailed test report available online at • Power-Down Mode: 70mW http://radhome.gsfc.nasa.gov [11] describing in further detail • Industrial Temperature Range: -40˚C to 85˚C the test method, SEE conditions/parameters, test results, and • 3 Vpp Differential Input Range graphs of data. • 5 V or 3.3 V Power supply

This section contains summaries of testing performed on a selection of featured parts. A. Texas Instruments ADS5483 ADC This study was undertaken to determine the Single Event Effects (SEE), susceptibility of the Texas Instruments (TI) ADC converter: ADS5483. The DUTs were evaluated with heavy ions and protons. There was a total of 7 ADC tested. 2 were made available for heavy ion testing, including 1 control saample. 4 devices were made available for proton testing. A TI Evaluation board with one embedded ADC (DUT) was used as a daughter card that was physically connected to the NASA Goddard low cost digital tester (LCDT). The TI Evaluation board number is ADS548xEVM. The identification information for these ADCs is as follows: Test Chip: ADS5483 Lot # unknown - delidded by TI Markings: Fig. 1. Functional Block Diagram of the ADS5483.

AZ5483 For reliable SEU response analysis, it is important to filter TI 83K out the non-SEU noise that is introduced from both the test E7N0 G vehicle and the ADC device. Subsequently, prior to radiation The DUT technology is Texas Instruments complementary testing, system noise was measured. A minimal error-bound bipolar process BiCom3x. The following aare some of the (EB) was calculated per test set-up such that no ADC output ADS5483 Features (please refer to the ADS5483 datasheet for code errors existed during operation and pre-irradiation. The a complete description): EB code value can be translated to its corresponding voltage • 16-bit resolution. 78 dBFS Noise Floor level (VEB) as illustrated in (1). • 170MSPS Sample Rate • SFDR = 95dBc

EB *Vpp As a summary, the SEU/SET response of the ADS5483 V = (1) EB 2 Nb consists of: 1. Code upsets that only last for one ADC clock cycle. Concerning (1), Nb is the number of ADC output bits (16- 2. Code upsets that last for multiple ADC clock cycles bits for the ADS5483) and V is the peak-to-peak pp (bursts). manufacturer supplied voltage range (3V for the ADS5483). pp a. Heavy ion bursts were not as frequent as proton bursts. Regarding heavy ion testing, the ADS5483 DUT was tested The longest heavy ion burst lasted for 39 ADC clock at the TAMU using a 15 MeV/amu tune at room temperature. cycles. All tests were run with 103

B. Actel RTAX2000S RTAX-S FPGA EDAC Memory Tests This study was undertaken to determine the single event destructive and transient susceptibility of the internal memory structures embedded in the RTAX-S FPGA family of devices. The DUTs were configured to have various forms of active embedded memory structures. The memory and its supportive circuitry were monitored for SET and SEU induced faults by exposing them to a heavy ion beam. The purpose of this RTAX-S memory evaluation was to enhance prior testing of the device. The study included both static and dynamic modes of memory control and operation for memory configurations Fig. 2. Heavy Ion SEU Error Cross Sections. that utilized the embedded EDAC circuitry provided by Actel versus memory configurations that did not contain EDAC. It is important to note that the embedded EDAC circuitry does not reside in the hardened by design user-cells of the RTAX. Therefore, the embedded circuitry is assumed to be more susceptible than custom user designed EDAC that would utilize the RTAX-S hardened cells. There was one RTAX-S device that contained the memory configuration under evaluation. The sample size per device (in this case) was not the focus since they are production- high speed parts with very little variation across the CMOS process. The emphasis was to test variations over the design state space. The devices were manufactured on an advanced 0.15µm CMOS Antifuse Process Technology with 7 layers of metal. The manufacturer is Actel. The devices tested had LDC of 0526.

Fig. 3. Proton SEU Error Cross Sections.

Additionally, we found that the LTC6400 was robust against high energy protons, with relatively low SET cross- sections. We irradiated 2 parts with 198 MeV protons. The increase in SET error cross-sections from 0° to 60° for DUT3 is unlikely due to angular effects that result from nuclear reactions, since the final 0° incident run produced a larger error cross-section than the initial normal incident run. We irradiated DUT4 at normal incidence to examine the effects of total dose and displacement damage on SET sensitivity. The significant scatter in the dataset suggests that the SET cross- sections more likely follow a Poisson distribution, and do not correlate strongly with accumulated dose. The different lot date codes of the parts may also contribute to the relatively Fig. 4. SEU Error Cross Sections. Static and dynamic memory reads were evaluated for several patterns for memory structures with and without EDAC large difference in the magnitudes of SET cross-sections. controls.

Fig. 4 illustrates that the memory bit-cell SEU cross sections over all data patterns were statistically equivalent. Dynamic tests consisted of read-write-modify cycles. Regarding memory cell SEU-cross sections, there was no statistical difference between dynamic memory operations during DUT irradiation versus static memory operation. With dynamic testing, multiple bit failures (MBUs) per address did occur at 8.5 MeV•cm2/mg. Because the EDAC structures are Single Error Correct Double Error Detect (SECDED), memory reads that utilized the embedded EDAC structures had failures. No testing was performed below 8.5 MeV•cm2/mg, therefore no on-set for memory MBU and EDAC failure has been determined. For LET > 20 MeV•cm2/mg, EDAC SEFI’s also occurred. An EDAC SEFI pertains to the event of the EDAC circuitry becoming stuck in a state where it cannot correct data and eventually Fig. 5. Heavy-ion-induced SET error cross-sections for large signals at 10, corrupts good data. EDAC SEFIs at LETs >20 MeV•cm2/mg 100 MHz, and 1 GHz. were significant and can be avoided by the user creating a custom EDAC with the RTAX-S user fabric [15]. Note, also see J. George, et al., [16].

C. Linear Technology LTC6400 Differential Output Amplifier/ADC Driver The LTC6400 is fabricated with the JAZZ-TOWER 0.35µm SiGe BiCMOS process. Two parts were irradiated at room temperature with the devices operating at VCC = 3 V, VCM = 1.25 V, sine wave inputs of 140 mVpp (large signal) or 2 mVpp (small signal), at frequencies of 10, 100, and 1000 MHz. Two ion species were used for this experiment: Ar and Kr. Fig. 5 shows the SET cross-sections from large signals at 10, 100, and 1000 MHz. We observed SETs down to the lowest LET of 7.4 MeV•cm2/mg for all frequencies of operation. The SET cross-sections increase linearly with increasing frequency. The worst case transients occur at 1000 MHz, where several cycles of the signal are erased from an SET. Fig. 6 shows an SET at 1000 MHz. No latchup events Fig. 6. SET cross section vs. accumulated dose for the LTC6400 operating at 200 MHz, irradiated with 198 MeV protons to a fluence of 1 × 1012 were observed. The supply current values remained relatively particles/cm2. unchanged, at ~ 90 mA, throughout irradiation.

D. Texas Instruments CSD16403QA Commercial Power MOSFET This study was undertaken to determine the single event gate rupture (SEGR) and burnout (SEB) susceptibility of the commercial CSD16403QA power MOSFET under heavy ion irradiation. The device is a 100 amp, 25 volt n-channel power MOSFET, manufactured under Texas Instruments’ recently acquired CICLON NexFETTM commercial process technology. The NexFET technology is a hybrid lateral- vertical power MOSFET (Fig. 7) featuring a lateral channel under a planar gate connecting the source to the lightly doped drain extension region (LDD), and a highly doped vertical drain “sinker” that brings the current flow vertically down to the backside drain contact. We believe that this test is the first to evaluate the heavy-ion response for this device type.

Fig. 8. SEE response curve.

Efforts to evaluate a p-channel NexFET were inconclusive due to the presence of an irremovable heat sink on top of the die obstructing more than 80% of the active region. As p- channel power MOSFETs do not suffer SEB, additional tests will reveal whether these commercial p-type structures will be naturally rugged under a heavy-ion space environment. [26] E. M.S. Kennedy Voltage Regulators MSK5900RH and MSK5820-2.5RH We undertook this study to characterize the application- specific SET behavior of the MSK5900RH and MSK5820- 2.5RH low dropout voltage regulators using pulsed laser irradiation. Both regulators are hybrid integrated circuits, which contain controller circuitry that governs a power PNP Fig. 7. Cartoon showing the structure of a n-type NexFET™ power MOSFET. bipolar transistor. The controller circuitry, manufactured by From: Electronics Design, Strategy, News, 12 Feb 2009. Linear Technology, is the LT1573 in the case of the MSK5900 Tests were conducted at normal incidence to the surface. and the RH1573K in the case of the MSK5820. The Each device was biased at one of three gate-source voltage LT1573/RH1573 is a low dropout PNP regulator driver. The (Vgs) biases, and the drain-source voltage (Vds) was RH1573K uses the same mask set as the LT1573, but has a incremented between beam runs until device failure was different passivation to improve its total ionizing dose observed. Currents were monitored at the gate and drain response. nodes during testing, and voltage transients were recorded across a small sense-resistor placed behind the drain stiffening capacitor. All device failures occurred during irradiation and were due to single event burnout, although in each instance the gate ruptured. As can be seen in Fig. 8, the SEE safe operating area is 52% of the maximum rated drain voltage, independent of the gate bias applied during testing. This gate- voltage independence is a hallmark of single-event burnout. In addition, both krypton at an incident LET of 27.4 MeV•cm2/mg and silver at an incident LET of 40.5 MeV•cm2/mg yielded the same SEE response curves.

Fig. 10. MSK5900RH transients.

Fig. 9. Micrographs of the MSK5900RH and MSK5820-2.5RH bipolar hybrid integrated circuits and the PNP driver regulator dice within. Note that (c) and (d) have been rotated so that their orientation is the same as in (a) and (b). The views in (c) and (d) are the same as what the laser sees through the 100x objective.

Package and die micrographs of the MSK5900RH/LT1573 and MSK5820-2.5RH/RH1573 are shown in Fig. 9. The MSK5900RH is packaged in a 12-pin flatpack and the MSK5820-2.5RH is packaged in a 5-pin single-inline package. It is clear from Figs. 9(c) and (d) that the LT1573 and RH1573 have the same mask set. The main difference is that the MSK5900RH is a positive adjustable regulator tuned with an external resistor network and the MSK5820-2.5RH is a fixed positive voltage regulator. Both regulators were configured with a 5.0 V input and a +2.5 V output. Fig. 11. MSK5820-2.5RH transients. We used the pulsed laser facility at the Naval Research Laboratory to perform single-photon absorption on the M.S. F. Intersil ISL70001 Point-of-load DC/DC Converter Kennedy voltage regulators with a 590 nm wavelength beam. The ISL70001SRH is a new point-of-load (POL) DC/DC The pulse energy for these experiments was in excess of an converter developed by Intersil Coporation. The part has been equivalent LET of 100 MeV•cm2/mg. qualified for total ionizing dose irradiation. Here we give a We scanned the laser spot across the entire surface of both short summary of the single event effects performance from the LT1573 in the MSK5900RH and the RH1573K in the heavy-ion irradiations. Details of the part’s radiation MSK5820-2.5RH. Two load conditions were used for each performance can be found in Intersil’s publication. [28] component. The MSK5900RH was irradiated with 25 mA and The ISL70001SRH was found to be free of 138 mA loads while the MSK5820-2.5RH was irradiated with SEL/SEB/SEGR up to an LET of 86.4 MeV•cm2/mg, with the 0.515 A and 2.45 A loads. Voltage transients were observed device operating at an input voltage of 5.7 V, output current of with all load conditions on each component. We observed 7 A, output voltage of 1.8 V, and case temperature up to both positive and negative transients (-20 to +40 mV), up to a 125oC. width of approximately 200 µs on the MSK5900RH. The The redundant PWM loop design of the ISL70001SRH is MSK5820-2.5RH also showed both positive and negative effective in limiting SETs. The worst case SET at an LET of transients (-12 to +100 mV), up to a width of approximately 86.4 MeV•cm2/mg was found to cause less than 1% change in 225 µs. These results are shown graphically in Fig. 10 and the output voltage. Fig. 11 [29] [30].

A SEFI phenomenon of the Softstart function was observed [11] NASA/GSFC Radiation Effects and Analysis home page, at an LET of 84.6 MeV•cm2/mg and 3 V input voltage only. http://radhome.gsfc.nasa.gov [12] Stephen Buchner, Melanie Berg, and Christina Seidleck, "Single Event The ISL70001SRH shuts down and then restarts normally Effects Testing of ADC14155WG-MLS Analog-to-Digital Converter through the Softstart function. The estimated cross section for (National Semiconductor),” http://radhome.gsfc.nasa.gov/ radhome/ this phenomenon is 1.4 x 10-6 cm2 at an LET of papers/ D062209_AD14155.pdf, Jun 2009. 2 [13] M. Berg, S. Buchner, H. Kim, M. Friendlich, C. Perez, A. Phan, C. 84.6 MeV•cm /mg and 3V input. With a 5 V input, the SEFI Seidleck, K. LaBel, and K. Kruckmeyer, "Enhancing Observability of cross section increased to ~ 6.5 x 10-8 cm2. [28] Signal Composition and Error Signatures during Dynamic SEE Analog to Digital Device Testing," to be published in RADiation Effects on Components & Systems (RADECS) 2009, Brugge, Belgium, Aug. 2010. V. SUMMARY [14] Melanie Berg, Hak Kim, and Anthony Phan, "Heavy Ion SEE Tests for We have presented current data from SEE testing on a Texas Instruments ADS5483 ADC," http://radhome.gsfc.nasa.gov/ radhome/ papers/ T052309_ IU081009_ ADS5483.pdf, May 2009. variety of mainly commercial devices. It is the authors' [15] Melanie Berg, Hak Kim, Mark Friendlich, and Christopher Perez, recommendation that this data be used with caution. We also "Heavy Ion SEE Tests for Actel RTAX2000SX/SL http://radhome.gsfc. highly recommend that lot testing be performed on any nasa.gov/ radhome/ papers/ T110909_RTAX2000SX, Nov. 2009. [16] Jeffrey S. George, Rocky Koga, and Mark Zakrzewski, “Single Event suspect or commercial device. Effects Tests on the Actel RTAX2000S FPGA,” IEEE Radiation Effects Data Workshop, pp. 140-147, Jul. 2009. VI. ACKNOWLEDGMENT [17] Melanie Berg, "Proton SEE Tests for Xilinx Virtex V XC5VLX30T- 1FFG665GU FPGA," http://radhome.gsfc.nasa.gov/ radhome/ papers/ The authors gratefully thank members of the Radiation D062209_XCVLX30T, Jun. 2009. Effects and Analysis Group who contributed to the test results [18] Dakai Chen and Hak Kim, "Test Report of Heavy-ion SEEs for the LTC6400-20 Differential ADC Driver," http://radhome.gsfc.nasa.gov/ presented here: Mark R. Friendlich, Megan C Casey, Michael radhome/ papers/ T052309_LTC6400.pdf, May 2009. J. Campola, Donald K. Hawkins, James D. Forney, Timothy [19] Dakai Chen, Anthony Phan, and Jonathan Pellish, "Proton Irradiation L. Irwin, Christina M. Seidleck, Stephen R. Cox, Christopher Test Report for the LTC6400-20 Differential ADC Driver," Perez, and Joseph W. Portner. The authors would also like to http://radhome.gsfc.nasa.gov/ radhome/ papers/ I080409_LTC6400.pdf, Aug 2009. thank Dale McMorrow for his expert help with laser testing at [20] D. Chen, A. Phan, H. Kim, J. Pellish, K. LaBel,S. Burns, R. Albarian, B. NRL, Kirby Kruckmeyer for his help with supplying test Holcombe, B. Little, J. Salzman, "Radiation Performance of devices and test boards for the ADC14155, and Duc Nguyen Commercial SiGe HBT BiCMOS High Speed Operational Amplifiers," submitted for publication in IEEE Radiation Effects Data Workshop, Jul. for his help with the testing at TAMU in August 2009 2010. of the Samsung K9F4G08U0A-PCB0 and the Micron [21] Dakai Chen and Anthony Phan, "Heavy-ion SEE at Elevated MT29F4G08AA AWP. Temperatures Test Report for the THS4304 Wideband Operational Amplifier," http://radhome.gsfc.nasa.gov/ radhome/ papers/ T082409_THS4304.pdf, Aug 2009. VII. REFERENCES [22] Ray Ladbury, H. Kim, M. Friendlich, "DDR3 SDRAM SEE Test Report," http://radhome.gsfc.nasa.gov/ radhome/ papers/ I081009_ [1] Kenneth A. LaBel, Lewis M. Cohn, and Ray Ladbury,"Are Current SEE T082409_ K4B1GO846DHCF8, Aug. 2009. Test Procedures Adequate for Modern Devices and Electronics [23] Tim Oldham, Mark Friendlich, Anthony B. Sanders, Hak Kim, and Technologies?," http://radhome.gsfc.nasa.gov/ radhome/ papers/ Melanie Berg, "Heavy Ion SEE Test Report for the Samsung 4Gbit HEART08_LaBel.pdf NAND Flash Memory for MMS,", http://radhome.gsfc.nasa.gov/ [2] Donna J. Cochran, Dakai Chen, Timothy Oldham, Hak Kim, Stephen radhome/ papers/ T052309_K9F4G08U0A, May 2009. Buchner, Kenneth A. LaBel, Jonathan Pellish, Martin A. Carts, Martha [24] T.R. Oldham, M.R. Friendlich, D. Nguyen, and F. Irom, "Heavy Ion V. O'Bryan, and Anthony B. Sanders, " Current Total Ionizing Dose and SEE Test of Micron and Samsung 4G NAND Flash Memories: Current Displacement Damage Compendium of Candidate Spacecraft Spike Experiment with JPL," http://radhome.gsfc.nasa.gov/ radhome/ Electronics for NASA," submitted for publication in IEEE Radiation papers/ T082409_K9F4G08U0_MT29F4G08AA, Aug. 2009. Effects Data Workshop, Jul. 2010. [25] Tim Oldham, Mark Friendlich, Anthony B. Sanders, Hak Kim, and [3] Lawrence Berkeley National Laboratory (LBNL), 88-Inch Cyclotron Melanie Berg, "Heavy Ion SEE Test Report for the Micron 4Gbit Accelerator Facility, http://cyclotron.lbl.gov/index.html, May 2007. NAND Flash Memory for MMS," http://radhome.gsfc.nasa.gov/, [4] B. Hyman, "Texas A&M University Cyclotron Institute, K500 T110308_ MT29F4G08AAAWP.pdf, Nov. 2008. Superconducting Cyclotron Facility," http://cyclotron.tamu.edu/ [26] Jean-Marie Lauenstein, Anthony Phan, Hak Kim, and Tim Irwin, facilities.htm, Jul. 2003. "Single event effects testing of the Texas Instruments Commercial [5] W.J. Stapor, “Single-Event Effects Qualification,” IEEE NSREC95 CSD16403Q5A Power nMOSFET," http://radhome.gsfc.nasa.gov/ Short Course, sec. II, pp 1-68, Jul. 1995. radhome/ papers/ T110909_CSD16403Q5A, Nov. 2009. [6] C. M. Castaneda, "Crocker Nuclear Laboratory (CNL) Radiation Effects [27] Jean-Marie Lauenstein, "Heavy Ion Testing of the International Measurement and Test Facility," IEEE NSREC01 Data Workshop, pp. IRH7360SE Rectifier Power MOSFET," http://radhome.gsfc.nasa.gov/ 77-81, Jul. 2001. radhome/ papers/ T030409_IRH7360SE, Mar. 2009. [7] C. C. Foster, S. L. Casey, P. Miesle, N. Sifri, A. H. Skees, K. M. [28] N. W. van Vonno, L. W. Pearce, H. W. Satterfield, E. T. Thomson, A. P. Murray, "Opportunities for Single Event and Other Radiation Effects Williams, T. E. Fobes, P. J. Chesley and J. S. Gill, "Total Dose and Testing and Research at the Indiana University Cyclotron Facility," Single Event Testing of a Hardened Point of Load Regulator," submitted IEEE NSREC96 Data Workshop, pp. 84-87, Jul. 1996. for publication in IEEE Radiation Effects Data Workshop, Jul. 2010. [8] J. S. Melinger, S. Buchner, D. McMorrow, T. R. Weatherford, A. B. [29] J. A. Pellish, S. Buchner, D. A. Batchelor, J. D. Forney, and C. M. Campbell, and H. Eisen, "Critical evaluation of the pulsed laser method Seidleck, "Pulsed Laser Single-Event Transient Testing of the M.S. for single event effects testing and fundamental studies," IEEE Trans. Kennedy 5820-2.5RH Radiation Hardened ULDO Fixed Positive Linear Nucl. Sci., vol 41, pp. 2574-2584, Dec. 1994. Voltage Regulator," http://radhome.gsfc.nasa.gov/ radhome/ papers/ [9] D. McMorrow, J. S. Melinger, and S. Buchner, "Application of a Pulsed NRL102709_MSK5820.pdf, Oct 2009. Laser for Evaluation and Optimization of SEU-Hard Designs," IEEE [30] J. A. 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[31] Dakai Chen, "Test Report for Elevated Temperature Laser Testing of the Texas Instrument TPS79133 Voltage Regulator," http://radhome. gsfc.nasa.gov/ radhome/ papers/ NRL062409_TPS79133, Jun. 2009. [32] D. F. Heidel, P. W. Marshall, J. A. Pellish, K. P. Rodbell, K. A. LaBel, J. R. Schwank, S. E. Rauch, M. Hakey, M. D. Berg, C. Castaneda, P. E. Dodd, M. R. Friendlich, A. D. Phan, C. M. Seidleck, M. R. Shaneyfelt, and M. A. Xapsos, "Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM," IEEE Trans. Nucl. Sci., Vol. 56, No. 6, pp. 3499 - 3504, Dec. 2009. [33] N. A. Dodds, R. A. Reed, R. D. Schrimpf, L. W. Massengill, R. A. Weller, J. M. Hutson, J. A. Pellish, M. A. Xapsos, H. S. Kim, M. D. Berg, M. R. Friendlich, A. M. Phan, C. M. Seidleck, X. Deng, R. C. Baumann, "Optimization of Well and Substrate Contact Spacing for Single Event Latchup Hardness," submitted for publication in IEEE Trans. Nucl. Sci., Dec. 2010.

Compendium of Test Results of Recent Single Event Effect Tests Conducted by the Jet Propulsion Laboratory

Steven S. McClure, Member, IEEE, Gregory R. Allen, Member, IEEE, Farokh Irom, Leif Z. Scheick, Member, IEEE, Philippe C. Adell, Member, IEEE, and Tetsuo F. Miyahira

1) Heavy Ion Facilities Abstract—This paper reports heavy ion and proton-induced single event effect (SEE) results from recent tests for a variety of Heavy ion measurements were performed at the microelectronic devices. The compendium covers devices tested Brookhaven National Laboratory (BNL) and Texas A&M over the last two years by the Jet Propulsion Laboratory. University Cyclotron (TAM) facilities. The BNL facility uses a twin Tandem Van De Graaff accelerator and TAM uses an Index Terms—Single event effects, compendium, analog 88” cyclotron. Both facilities are capable of providing a range switches, ADC, oscillators, SDRAM, FPGA, drivers, of particle beams and energies for radiation effects testing. microprocessors, voltage comparator, and voltage regulator. The longer-range ions at TAM allow most of the irradiations to be performed in air, whereas all testing at BNL took place I. INTRODUCTION in vacuum. Intermediate Linear Energy Transfer values ICROELECTRONICS used in space systems must survive (LETs) were acquired either through the use of degrader Mand operate in various radiation environments. To (TAM only) or by changing the angle of incidence of the ion ensure both survival and functionality of these devices for a relative to the device under test (DUT), changing the specific mission, accelerated ground-based testing is required effective LET. to define their susceptibility to single event effects (SEEs) 2) Proton Facilities caused by cosmic rays and heavy ions. The data presented in this paper were acquired by JPL to characterize the Proton tests were performed at the University of susceptibility of potential spacecraft microelectronics to California, Davis (UCD) Crocker Nuclear Laboratory (CNL) single event latchup (SEL), single event upset (SEU), single and at the Indiana University Cyclotron Facility (IUCF). event functional interrupt (SEFI), and single event transient Much of the work associated with recent proton testing has (SET). This compendium provides a summary of SEE data been associated with displacement damage effects, and are acquired within the last two years. included here. The majority of the representative proton data in this compendium is complimentary to heavy ion data, and was acquired to evaluate SEE rates for proton environments.

II. EXPERIMENTAL PROCEDURE B. Experimental Methods A. Test Facilities Details concerning experimental methodology, including A variety of ion facilities are available for SEE testing. The data acquisition, ion selection, biasing conditions, etc., vary criterion to select a test facility may include scheduling, ion from experimenter to experimenter and device to device. In range, and/or programmatic expenses. A high level view of many instances, devices were tested both at room temperature the facilities used is outlined below. The facility websites [1]- and at elevated temperature; results are shown for both [4] provide a detailed view of available ions, energies, and instances. Generally speaking, the procedure used by facility capabilities that are beyond the scope of this paper. experimenters followed the procedures documented in the

ASTM F1192 or JEDEC JESD57 standards for single-event testing [5], [6]. For details concerning the specifics of a test, please review the associated test report. Manuscript received July 15, 2010. This work was supported in part by NASA/JPL Flight Projects and the NASA Electronic Parts and Packaging Program (NEPP). III. DATA ORGANIZATION S. S. McClure, G. R. Allen, F. Irom, L. Z. Scheick, P. C. Adell, T. F. Miyahira are with the Jet Propulsion Laboratory, California Institute of This compendium is intended to serve as a reference list for Technology, 4800 Oak Grove Dr., Pasadena, CA, 91109. (e-mail: tested devices. The data tables contain abbreviated [email protected]; [email protected]; farokh.irom @jpl.nasa.gov; [email protected]; [email protected]; information mainly due to spatial constraints. It is highly [email protected].) recommended that the reader review the referenced article or

contact the principal investigator (PI) to acquire details concerning the data and test methodologies. Much of the SEE TABLE II ACRONYMS, ABBREVIATIONS, AND CONVENTIONAL SYMBOLS data presented here is dependent on the device’s bias and circuit configuration; e.g., SET data depends strongly on their output load; SEFI data are interpretive depending upon what ABBREVIATION DEFINITION the test defines as a SEFI. Generally speaking, the worst-case ADC ANALOG TO DIGITAL CONVERTER results are presented, but it is highly recommended that the ADI ANALOG DEVICES, INC. reader seek out the test report. Data that has not been ASIC APPLICATION-SPECIFIC INTEGRATED CIRCUIT CMOS COMPLEMENTARY METAL OXIDE SEMICONDUCTOR previously published but has a formal test report will be CPU CENTRAL PROCESSING UNIT released to the JPL parts radiation database [7]. Contact the DRAM DYNAMIC RANDOM ACCESS MEMORY principal investigator if data is not found on the database. DUT DEVICE UNDER TEST When possible, LET thresholds were shown to lie between FPGA FIELD PROGRAMMABLE GATE ARRAY a set of tested energies, otherwise they are simply shown to H HEAVY ION TEST be at or below a certain value or not seen at the highest tested I INTERNAL DOCUMENT (CONTACT PI FOR SOURCE DATA) LET. SEE results have been combined on a single line. For I/O INPUT/OUTPUT most SEL results, only the LET thresholds have been IBM INTERNATIONAL BUSINESS MACHINE provided. Saturated cross-sections and thresholds are LET LINEAR ENERGY TRANSFER (MEV•CM2/MG) provided for SEFI, SEU, and SET where available. Unless LETTH LINEAR ENERGY TRANSFER THRESHOLD 2 otherwise noted, all LET values are in MeV•cm /mg and all LTC LINEAR TECHNOLOGY 2 METAL OXIDE SEMICONDUCTOR FIELD EFFECT cross-sections in cm /device. MOSFET Table I lists the abbreviations for the PIs and Table II lists TRANSISTOR the acronyms, abbreviations, and conventional symbols used MUX MULTIPLEXOR in Table III. Table III provides the results of the SEE tests. NAND NOT AND LOGICAL OPERATION OP AMP OPERATIONAL AMPLIFIER PI PRINCIPAL INVESTIGATOR TABLE I LIST OF PRINCIPAL INVESTIGATORS σ CROSS-SECTION σ SAT SATURATED CROSS-SECTION PRINCIPAL INVESTIGATOR ABBREVIATION SDRAM SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY SEE SINGLE EVENT EFFECT PHILIPPE ADELL PA SEFI SINGLE EVENT FUNCTIONAL INTERRUPT GREG ALLEN GA SEL SINGLE EVENT LATCHUP FAROKH IROM FI SET SINGLE EVENT TRANSIENT LEIF SCHEICK LS SEU SINGLE EVENT UPSET TI TEXAS INSTRUMENTS

TABLE III SEE RESULTS

Tech- Test PI Test Date Device Function Mfg. Test Type Test Results Ref. nology Site ADC, 24-bit

FI 7/30/2008 AD7760BSVZ ADC, 24-bit ADI BiCMOS SEL TAM LETth < 8.3 @ 85°C [7] Analog Switches/MUXs

GA 10/26/2009 HS9-303ARH-Q Analog Switch Intersil CMOS SET TAM LETth < 84.6, Static Mode [7] Logic

PA 6/9/2008 NL17SZ00 NAND Gate ON Semi CMOS SEL BNL LETth > 75 @ 85°C [7]

PA 6/9/2008 NL17SZ125 Buffer, 3-state ON Semi CMOS SEL BNL LETth > 75 @ 85°C [7]

PA 6/9/2008 NL17SZ74 D Flip Flop ON Semi CMOS SEL BNL LETth > 75 @ 85°C [7]

PA 6/9/2008 NL17SZ14 Inverter ON Semi CMOS SEL BNL LETth > 75 @ 85°C [7]

PA 6/9/2008 IDTQS4A210 MUX/DEMUX IDT CMOS SEL BNL LETth > 75 @ 85°C [7] Microprocessor IBM PowerPC PowerPC No SEL FI 8/13/2009 IBM CMOS SEU/SEL TAM [8] 750FX Processor SEU LETth < 0.8 PowerPC IUCF/ No SEL FI 10/7/2009 IBM 750FX IBM CMOS SEU/SEL [8] Processor UCD SEU Energyth < 6.9 MeV PowerPC IUCF/ No SEL FI 2/11/2009 MC7447A Freescale CMOS SEU/SEL [8] Processor UCD SEU Energyth < 6.6 MeV

Tech- Test PI Test Date Device Function Mfg. Test Type Test Results Ref. nology Site PowerPC No SEL FI 9/1/2008 MC7447A Freescale CMOS SEU/SEL TAM [8] Processor SEU LETth < 1.7 Miscellaneous

FI 7/30/2008 VIRENA ASIC SRI CMOS SEL TAM LETth > 85 @ 85°C [7]

FI 11/11/2008 MV64460 Bridge Chip Marvell CMOS SEU/SEFI TAM SEU LETth < 1.7 [8] High current SEFIs IUCF/ FI 2/11/2009 MV64460 Bridge Chip Marvell CMOS SEU/SEFI SEU Energyth < 21MeV [8] UCD High current SEFIs Resolver to FI 7/30/2008 AD2S80A Digital ADI BiMOS SEL TAM LETth > 85 @ 85°C [7] Converter Switch Mode 23 > LET > 27 @ 25°C FI 8/13/2009 SI9112DY Siliconix CMOS SEL TAM th [7] Controller 19 > LETth >11 @ 85 C Extremely sensitive to heavy Transceiver, FI 7/30/2008 BCM5421KPF Broadcom CMOS SEL TAM ions (contact investigator for [7] LAN further details) Non-Volatile Memory Destructive high current FI 7/30/2008 S29GL512 NOR Flash Spansion CMOS SEU TAM [7] spikes in PROGRAM Mode 8Gb MLC SEL LET < 35 @ 25°C FI 1/12/2009 K9G8G08U0A Samsung CMOS SEU/SEL Finland th [9] Flash SEU LETth < 4 SEL LET < 35 @ 25°C FI 1/12/2009 K9F8G08U0M 8Gb SLC Flash Samsung CMOS SEU/SEL Finland th [9] SEU LETth < 4 Destructive high current FI 3/29/2009 MT29F8G08U0M 8Gb SLC Flash Micron CMOS SEE TAM [10] spikes in PROGRAM Mode Destructive high current FI 3/29/2009 K9F8G08U0M 8Gb SLC Flash Samsung CMOS SEE TAM spikes in READ and [10] PROGRAM Mode 8Gb MLC No SEL FI 5/8/2008 K9G8G08U0A Samsung CMOS SEU BNL [10] Flash SEU LETth < 4 Destructive high current 8Gb MLC FI 9/1/2008 K9G8G08U0A Samsung CMOS SEE TAM spikes in READ and [10] Flash PROGRAM Mode No SEL FI 10/29/2008 S29GL512 NOR Flash Spansion CMOS SEU/SEL BNL [7] SEU LETth < 4 No SEL FI 2/11/2009 S29GL512 NOR Flash Spansion CMOS SEU/SEL UCD [7] SEU Energyth < 20 MeV Op Amps

FI 5/8/2008 LT1498 Quad Op Amp LTC Bipolar SET BNL LETth < 8 [7] Precision Op LS 1/15/2010 AMP01 ADI Bipolar SET BNL SET > 200 mV @ LET = 15 [7] Amp LS 10/26/2009 OP470 Quad Op Amp ADI Bipolar SET TAM SET > 200 mV @ LET = 5 [7] LS 12/1/2009 OP470 Quad Op Amp ADI Bipolar SET BNL SET > 200 mV @ LET = 5 [7] Low Power Op FI 8/13/2009 TS951ILT STMicro CMOS SEL TAM LET > 85 @ 85°C [7] Amp th Instrumentation FI 8/13/2009 MAX4194 Maxim CMOS SEL TAM LET > 85 @ 85°C [7] Amp th Power Conversion DC Motor FI 8/13/2009 UCC2626 Driver TI Bipolar SEL TAM LETth > 85 @ 85°C [7] Controller No SEL and SET > 20 mV DC/DC Bipolar/ PA 12/17/2007 LS2803R3S/EM IR SET TAM @ LET = 51.5 for full input [7] Converter MOS voltage range and load

Tech- Test PI Test Date Device Function Mfg. Test Type Test Results Ref. nology Site No SEL and SET > 20 mV DC/DC Bipolar/ PA 5/8/2008 LS2803R3S IR SET BNL @ LET = 51.5 for full input [7] Converter MOS voltage range and load No SEL and SET > 20 mV DC/DC Bipolar/ PA 5/8/2008 LS2805S IR SET BNL @ LET = 51.5 for full input [7] Converter MOS voltage range and load No SEL and SET > 20 mV DC/DC Bipolar/ PA 5/8/2008 LS2812D IR SET BNL @ LET = 51.5 for full input [7] Converter MOS voltage range and load Dual Output SET LET < 84.6 GA 10/26/2009 HS-1825ARH Intersil BiCMOS SET/SEL TAM th [7] PWM SEL LETth > 84.6 @ 125°C Power SET LET > 84.6 static GA 10/26/2009 HS-4423BRH MOSFET Intersil BiCMOS SET/SEL TAM th [7] SET LET < 84.6 dynamic Driver th PWM FI 8/13/2009 HV9112NG Supertex CMOS SEL TAM LET > 85 @ 85°C [7] Controller th SDRAM

PA 7/30/2008 DS5108 SDRAM Elpida CMOS SEL TAM LETth > 85 @ 125°C [7]

FI 10/29/2008 MT46V64M8 SDRAM Micron CMOS SEU BNL LETth < 8 [7]

EDS5104ABTA- SDRAM, LETth > 2.7 PA 11/11/2008 Elpida CMOS SEU TAM -1 [7] 75 512Mbits σsat ~ 2×10 /device SDRAM No SEL @ 50 MeV FI 2/11/2009 MT46V64M8 Micron CMOS SEU/SEL IUCF [7] 64Mbits SEU Energyth < 50 MeV SEFI 1: recovered by mode register, LETth > 3.8 and σ ~ 1×10-3/device EDS5104ABTA- SDRAM, sat PA 9/1/2008 Elpida CMOS SEFI TAM SEFI 2: > 1,000 errors in a [12] 75 512Mbits row, LETth > 5.4 and σsat ~1×10-4/device, fixed by rewriting or power cycle Voltage Comparator Quad SET > 200 mV @ 15 MeV LS 12/27/2007 LM139 Various Bipolar SET IUCF [7] Comparator (effective) Dual LS 1/15/2010 LM119 NSC Bipolar SET BNL SET > 200 mV @ LET = 60 [7] Comparator Quad LS 10/26/2009 LM139 NSC Bipolar SET TAM SET > 200 mV @ LET = 15 [7] Comparator Voltage Reference Voltage LS 10/26/2009 LT1009 LTC Bipolar SET TAM SET > 200 mV @ LET = 15 [7] Reference Voltage LS 10/26/2009 IS1009 Intersil BiCMOS SET TAM SET > 200 mV @ LET = 15 [7] Reference Voltage FI 8/13/2009 MAX6050 Maxim CMOS SEL TAM LET > 85 @ 85°C [7] Reference th Voltage Regulator Voltage +SET LET < 2.7 FI 12/17/2007 RH-117H LTC Bipolar SET TAM th [11] regulator −SET LETth < 15 Voltage +SET LET < 4 FI 12/17/2007 HS-117RH Intersil Bipolar SET TAM th [11] regulator −SET LETth < 8.3 Voltage 250 mV > SET > 20 mV FI 1/31/2008 LM2941 NSC Bipolar SET BNL [7] regulator SET LETth > 1.4 Voltage LS 1/15/2010 LM117HV NSC Bipolar SET BNL SET > 200 mV @ LET = 60 [7] regulator

B. Intersil HS-4423BRH Pulse Width Modulator IV. TEST RESULTS AND DISCUSSION The HS-4423BRH is a radiation-hardened inverting, dual, This section contains selected test results and discussions monolithic high-speed, metal-oxide-semiconductor field of tests performed on parts not presently published in other effect transistor (MOSFET) driver designed to convert TTL works. level signals into high current outputs at voltages up to 18 V. This device was tested at TAM. Devices were subjected to a total fluence of 107 ions/cm2 with 15 MeV/amu Au (effective A. Analog Devices AD7760, 24-Bit, ADC LET 84.6 MeV-cm2/mg) at elevated temperature. The device The AD7760 is a high performance, 24-bit Σ-Δ analog-to- under test (DUT) was configured to allow two or four (as in digital converter (ADC). It combines wide input bandwidth the application circuit) of the outputs to be tied together and and high speed with the benefits of Σ-Δ conversion to achieve sent to the scope. Devices were tested with static inputs of 0V a performance of 100 dB signal-to-noise ratio (SNR) at and 5 V, as well as 5 V 1 kHz 50% duty cycle square wave. 2.5 MSPS, making it ideal for high speed data acquisition. No SEL/SEB events were observed. No SET was observed The reference voltage supplied to the AD7760 determines the for input conditions of 0 V and 5 V. SET were observed for analog input range. With a 4V reference, the analog input the 5 V, 1 kHz stimulus. The average SET width was 23 μs range is ±3.2 V differential biased around a common mode of and on the positive portion of the square wave (a negative 2V. The AD7760 ADC was tested for SEL at TAM. The going transient). No positive SET was observed on the zero 2 LETs of the ions used ranged from 8 to 86 MeV-cm /mg. All potential portion of the square wave. the measurements were done in the normal incident configuration. The beam flux ranged from 104 to 105 ions/ (cm2sec). Beam fluence of 107 ions/cm2 was used to C. On Semiconductor NL17SZ14 Inverter Schmitt Trigger determine each cross-section point. Tests were done in the air The NL17SZ14 is a single inverter with Schmitt trigger with a normal incident beam. An evaluation board, EVAL- that operates at low voltage. This device, among several AD7760, the companion Blackfin ADSP-BF537, and others of the device family, was tested at BNL for latchup. evaluation software, all available from Analog Devices were Three devices were subjected to an effective LET of 2 used for the test. The three components provided a means of approximately 81 MeV-cm /mg while device inputs were monitoring device functionality while the device was tested toggled from 0 to 5 V at 1 kHz and the temperature was 7 2 for SEL. maintained at 85°C. Beam fluence was 10 ions/cm with The AD7760 was tested at room temperature and at an beam flux ranging from 2×104 to 4×104 ions/ (cm2sec). No elevated temperature of 85°C. The sample size was two. latchup events were detected during this test. Latchup events were observed at both cases. The latchup events were observed at an LET as low as 8.3 MeV-cm2/mg. The latchup threshold therefore is below LET of 8.3 MeV- V. SUMMARY 2 cm /mg. Fig. 1 compares the results of the room temperature This paper presents recent data from SEE testing performed and elevated temperature measurements. These data indicate on a variety of semiconductor devices at the Jet Propulsion AD7760 is highly sensitive to latchup, and has an LET 2 Laboratory. These data can be used in support of the selection threshold below LET of 8.3 MeV-cm /mg. Furthermore, the of devices for use in space systems. It is the authors' cross section is relatively large, and gradually rising to recommendation that these data be used with caution as -4 approximately 5×10 at high LETs (saturation cross section). actual device performance can vary with application and from lot to lot.

1.E-03

1.E-04 VI. ACKNOWLEDGMENTS This research was carried out in part at the Jet Propulsion 1.E-05 Latchup AD7760

) Laboratory, California Institute of Technology, under 2 1.E-06 contract with NASA. The authors sincerely thank the members, past and present, of the JPL Radiation Effects 1.E-07 Group who contributed to the tests reported herein: Aaron 23 Degree C Kenna, Michael O’Connor, Steve Guertin, Duc Nguyen, Roy 1.E-08 85 Degree C Scrivner, Dennis Thorbourn, and Luis Selva. Cross Section Section Cross (Cm

1.E-09 VII. REFERENCES 0 20406080100 LET (MeV-cm2/mg) [1] Texas A&M Cyclotron webpage, http://cyclotron.tamu.edu [2] Brookhaven National Laboratory Tandem Van de Graaff Accelerator Facility webpage, http://www.tvdg.bnl.gov Fig. 1. AD7760 single-event latchup cross section at room and elevated [3] Indiana University Cyclotron Facility webpage, http://www.iucf. temperature. indiana.edu [4] UC Davis Crocker Nuclear Laboratory webpage, http://media.cnl.ucdavis.edu/Crocker/Website/default.php

[5] ASTM F1192M-95 “Standard Guide for the Measurement of SEP Induced by Heavy Ion Irradiation of Semiconductor Devices,” ASTM, 1919 Race St., Philadelphia, PA 19103. [6] JEDEC JESD57, “Test Procedure for the Management of Single-Event Effects in Semiconductor Devices from Heavy Ion Irradiation (JC 13.4),” EIA/JEDEC, 2500 Wilson Blvd., Arlington, VA 22201-3834. [7] Jet Propulsion Laboratory Electronic Parts and Engineering Office 514 Radiation Database, http://radcentral.jpl.nasa.gov/, July 2010. [8] S. M. Guertin, F. Irom, “Recent Results for PowerPC Processor and Bridge Chip Testing” accepted for the 2010 IEEE Radiation Effects Data Workshop. [9] F. Irom, “Comparison of TID Response and SEE Characterization of Single and Multi Level High Density NAND Flash Memories”, presented at the 2009 Radiation Effects on Components and Systems. [10] F. Irom, D. N. Nguyen; M. Bagatin, G. Cellere, S. Gerardin, A. Paccagnella, “Catastrophic Failure in Highly Scaled Commercial NAND Flash Memories,” IEEE Trans. on Nucl. Sci., vol. 57, no. 1, part 2, pp. 266 – 271, Dec. 2009. [11] F. Irom, T. F. Miyahira, P. C. Adell, J. S. Laird, B. Conder, V. Pouget, F. Essely, “Investigation of Single-Event Transients in Linear Voltage Regulators,” IEEE Trans. on Nucl. Sci., vol. 55, no. 6, part 1, pp. 3352 – 3359, Dec. 2008. [12] P. C. Adell, L. Edmonds, R. McPeak, L. Scheick and S. S. McClure “An Approach to Single Event Testing of SDRAMs”, presented at the 2009 Radiation Effects on Components and Systems and accepted for publication in IEEE Trans. on Nucl. Sci.

Cross Comparison Guide for Results of Neutron SEE Testing of Microelectronics Applicable to Avionics

Eugene Normand, Senior Member, IEEE and Laura Dominik

Abstract - A cross comparison of SEU, SEFI and SEL sections in SRAMs. In addition, data pertaining to responses in >30 devices (SRAMs µprocessors and single event functional interrupt (SEFI) in FPGAs) using different neutron/proton beams leads to microprocessors and FPGAs and single event latchup observation that SEU and SEFI cross sections from 14 (SEL) in SRAMs have also been collected in this MeV neutrons are within <2 compared to LANL paper to allow a cross comparison for these effects. neutron beam. Here we collect this data from the previously published reports, based on tests performed by I. INTRODUCTION diverse testing groups, and display it in a format that The paper provides a cross comparison of the enhances the comparison. The focus of this report is results of performing single event effects testing on on the comparison of SEE cross sections measured in current microelectronics using the Los Alamos various facilities, with the requirement that one of the National Laboratory neutron source and other high testing sources was the WNR (Weapons Neutron energy particle beams. The main way this cross Research) facility at the Los Alamos National comparison is conducted is by providing specific Laboratory (LANL). However, not in all cases was it examples, i.e., published (or proprietary) data on the possible to obtain WNR SEE cross sections. single event effects (SEE) testing of a number of devices in a variety of particle beam facilities. II. HIGH ENERGY BEAM FACILITIES This paper is based on a report [1] for AVSI, the The atmospheric neutrons have an energy spectrum Aerospace Vehicle Systems Institute, which was a that extends over more than 10 orders of magnitude, dedicated extension of a previous AVSI report [2] but the main focus is on the high energy end, on that provided the overall basis for defining the energies of > 10 MeV, since these neutrons cause various types of high energy beam facilities that most of the single event effects in microelectronics. could be used as testing sources. The IEC standard To simulate the reactions and the rate of high energy regarding single event effects in avionics IEC TS neutrons inducing SEE in microelectronics both 62396-1 [3] provided the basic information on the neutron and proton beams have been used. test facilities, but [2] was more specific in their details. A. LANL Spallation Neutron Source Even with the availability of [2] and [3], there is still a need to perform cross comparisons between the Spallation neutron sources have energy spectra that results from the SEE testing of microelectronics in are most similar to that of the actual cosmic ray the different types of high energy beam facilities. neutrons in the atmosphere. At a spallation neutron Only from such cross comparisons can some general source a beam of monoenergetic high energy protons principles be inferred in terms of the SEE cross is accelerated into a high Z target, producing neutrons section of these devices, and how they vary from one with a distinct energy spectrum. facility to the next. For many years the high energy neutron beam Fortunately recent papers have published this kind available at LANL was used to simulate the effect of of data, mostly single event upset (SEU) cross atmospheric neutrons on microelectronics [4] via the Weapons Neutron Research facility, WNR, which Manuscript received July 15, 2010 provides neutron beams with energies of up to ~800 E. Normand is with the Boeing Research & Technology, MeV. The energy spectrum of the 30 Left beam Seattle, WA 98124 (phone: 206/544-0365) and also with EN matches that of the atmospheric neutrons very Associates LLC, Seattle, WA 98118 (phone 206/725-2070) closely. The neutron flux within the 30 Left WNR L. Dominik is with Honeywell, Minneapolis, MN 55433 (phone: 763/ 957-3802) beam has varied but it has always been higher than the neutron flux at aircraft altitudes by a large factor,

978-1-4244-8404-1/10/$26.00 ©2010 IEEE in the range of 2×105 – 1.2×106. The facility was 14 MeV neutron generators are available in the US upgraded in the late 1990s and is now called the ICE [3]. (Irradiation of Chips and Electronics) House, with 1 Monoenergetic neutron beams area also available hour in the beam now being equivalent to ~1×106 at lower energies, e.g. 3 and 5 MeV via the D-D hours at 40,000 ft. reaction. For purposes of SEE testing, this energy is considered too low to be very useful for avionics B. TRIUMF Spallation neutron source purposes, since the SEU cross section at 3 MeV, if it is non-zero, is still too low to be applicable for The neutron facility at TRIUMF (Tri- University avionics purposes. Meson Facility) at the University of British Columbia in Vancouver, Canada is a spallation neutron source E. Quasi-monoenergetic neutron beam [5]. The TRIUMF Neutron Facility (TNF) is similar to the WNR in terms of how the neutrons are Quasi-monoenergetic neutrons (qmn) are produced produced. Although the original facility was limited by a similar mechanism to the D-T reactions, but the by the access to the neutron beam, a recent upgrade monoenergetic proton beam is accelerated into a Li has significantly improved upon this. Neutrons are or Be target. The neutrons produced have an unusual produced with energies of up to 400 MeV, and the energy distribution, essentially a two-part energy energy spectrum of the neutrons is rather similar to distribution. About half of the neutrons have a that of the atmospheric neutrons. Figure 1 compares pseudo peak energy within a few MeV of the neutron spectra from WNR and TRIUMF and the initiating proton beam, and the remaining neutrons atmospheric neutron spectrum at 40,000 ft [6]. are distributed in energy, from the high energy pseudo peak down to a few MeV. The lower energy C. Monoenergetic proton beam neutrons constitute what is called the “low energy tail”. For energies above approximately 50 MeV, protons However, we follow the advice of [6] that “at and neutrons produce approximately the same effect present (2006) there is too much uncertainty in electronics in terms of single event effects [7]. regarding the use of this type of source for SEU and Monoenergetic proton beams are available from a SER measurements to recommend it.” Thus, no data

1E+10 collected in this report is from testing performed with 10 10 a qmn source.

1E+9 109

1E+8 III. CROSS COMPARISON OF SEE RESPONSES TESTED 108 AT DIFFERENT FACILITIES

7 10 1E+7 In order for a cross comparison to be meaningful it is necessary to compile data from a variety of sources

6 10 1E+6 ICE House (WNR) Measured Spectrum, 2005 to demonstrate that conclusions which may be

Diff.Neut Flux, n/cm²MeVhr TRIUMF at 100µA inferred are independent of particular devices or of Msr'd Atmos Spectrum @ 40,000 ft×1.2E6 5 10 1E+5 testing groups. Using various literature sources, for 1 10 100 1000 SRAMs we have compiled data from many different Neutron Energy, MeV groups and also include SEU data on microprocessors Fig. 1 Comparison of Neutron Spectra and a FPGAs that were tested by other groups. In the original report a total of 34 data sets were tabulated, larger number of accelerator facilities located in the however we have expanded upon this by adding 10 around the world (see Appendix A in [3] for a more data points from tests performed in Russia [8, listing). In general, it is preferable to use facilities 9]. with beams with E > 100 MeV, in order for the SEE In all cases these test groups used several different testing to be able to detect single event latchup (SEL) high energy neutron and proton beams. Most all in CMOS devices in addition to single event upset include measurements made in the WNR beam, but SEU and SEFI. some also include measurements made at TRIUMF. They also include measurements made with D.14 MeV neutron beam monoenergetic proton beams of various energies, and One type of high energy monoenergetic neutron made with a 14 MeV neutron beam. source is available and it produces 14 MeV neutrons This data is summarized in terms of three separate from a deuteron-triton (D-T) reaction. A number of tables, one for SEU, one for SEFI and the third for SEL. The vast majority of the data is tabulated in Table 1 which is for SEU, and is based on the testing The WNR cross section is usually larger than the 14 of SRAMs, microprocessors and FPGAs. SEFI data MeV cross section by a factor of 3-5. is summarized in Table 2 and is based on data from In Table 2 we present the same kind of data for the testing of microprocessors and FPGAs. Table 3 SEFI in FPGAs and microprocessors. What is summarizes the data for SEL and is based on the notable is that there are many fewer data points testing of a three SRAMs. compared to Table 1 for SEU. Thus, from Table 2 Table 1 contains the data for SEU. We believe that we can draw the preliminary observation that it this data demonstrates that 14 MeV neutrons can be appears that 14 MeV neutrons can be used for testing used for testing devices that are susceptible to SEU, devices that are susceptible to SEFI, with the with the resulting SEU cross section being within resulting SEFI cross section being within a factor of 2 about a factor of 2 of what would be expected if the of what would be expected if the devices were tested devices were tested using higher energy sources, e.g., using higher energy beams. However, since there are the WNR or TRIUMF neutron beams or a 200 MeV so few data points, this observation cannot be monoenergetic proton beam. considered conclusive. This is shown very clearly in Fig. 2, in which we In Table 3 we present the same kind of data for plot several ratios of the high energy beam SEU cross single event latchup in SRAMs. Even though the section / 14 MeV SEU cross section. The ratio is data covers only 3 devices, it indicates that SEL cross within an upper and lower bound of a factor of 2 for sections measured using a proton beam with an recent devices, i.e., those with a feature size of < 500 energy of 100-120 MeV will result in about the same nm. For older devices (1990s), having larger feature SEL cross section as would be measured using the sizes, using data taken from [7], this does not hold. WNR neutron beam.

TABLE I TABULATION OF SEU CROSS SECTIONS FROM TESTS PERFORMED USING THE LANL NEUTRON SOURCE AND HIGH ENERGY MONOENERGETIC PROTON/NEUTRON SOURCES

Part Feature LANL SEE Hi E Pro E 14 MeV N. Calct’d Fit Ref Size/ Oth X-Sct, SEU X-Sct, Prot, SEU X-Sct, SEE X-Sct, Data cm²/bit cm²/bit MeV cm²/bit cm²/bit SRAM A 0.5µm 5.90E-14 1E-13 500 3.80E-14 8.70E-14 10 1 Mbit 7E-14 150 8.6E-14 100 9E-14 50 SRAM D 0.18 µm 4.30E-14 4.4E-14 500 4.00E-14 4.10E-14 10 4 Mbit 3.7E-14 200 2.7E-14 150 3.4E-14 100 4E-14 50 SRAM B 0.25µm 5.8E-14 5.8E-14 500 5.50E-14 10 1 Mbit 5.2E-14 350 4.5E-14 100 5.2E-14 50 SRAM H 0.25µm 4.1E-14 5E-14 500 3.60E-14 10 4 Mbit 3.1E-14 150 4E-14 100 5E-14 50 M5M5408 0.4µm 1.70E-13 9.5E-14 490 1.60E-13 1.06E-13 11 (SRAM) D/C 9839 1E-13 9.5E-14 195 5V (TRIUMF) 1E-13 63 9E-14 20 TABLE I-CONTINUED Part Feature LANL SEU Hi E Pro E 14 MeV N. Calct’d Fit Ref Size/ Oth X-Sct, SEU X-Sct, Prot, SEU X-Sct, SEE X-Sct, Data cm²/bit cm²/bit MeV cm²/bit cm²/bit 4Mbit 0.25µm 1.9E-14 2.5E-14 170 2.5E-14 12, SRAM D/C 0036 3.1E-14 6.5E-14 110 [qmn, auth 14 1.8V (TRIUMF) 4.6E-14 90 corrected] 1.7E-14 43 (qmn, corr) HM628512A 0.5µm 6.00E-14 5.4E-14 490 5.40E-14 6.20E-14 11 (SRAM) D/C 9809 4.6E-14 5.4E-14 195 5V (TRIUMF) 7.5E-14 63 2E-14 20 Mfr C, Dev 1 ? µm, 2001 2.5E-14 2.5E-14 150 1.5E-14 11 2.3E-14 3.2E-14 100 [qmn, avg (TRIUMF) 2.5E-14 50 (pk, (all qmn ) pk+tail)† 8Mbit 0.13µm, 4E-14 9E-14 170 3E-14 7.3E-14 12, SRAM D/C 0311, 4E-14 7E-14 110 [qmn, auth 13 1.8V (TRIUMF) 7.5E-14 85 Correctd] 4Mbit 0.18 µm 2.5E-14 3.5E-14 170 8.3E-14 12, SRAM No D/C 3.9E-14 6E-14 110 [qmn, auth 14 1.8V (TRIUMF) 5.7E-14 90 correctd] (qmn, corr) 8Mbit 0.13µ 2E-14 3.8E-14 170 2.5E-14 4E-14 12, 13 SRAM D/C 0251 2.4E-14 3.5E-14 110 [qmn, auth 3V (TRIUMF) 4E-14 85 Correctd] 6E-14 50 4 Mbit, low 0.090 µm N/A 3-7E-14 203 N/A 15 Pwr SRAM, 1.1V 4-5E-14 147 Commercial 3.5-5E-14 98 2.5-5E-14 46 1.5-3E-14 32 1.2-2E-14 17 KM684000BLP 0.4µm 8.00E-14 5.5E-14 490 7E-14 11 (SRAM) D/C 9844 6E-14 5.5E-14 190 5V (TRIUMF) 7.5E-14 74 BS62LV1025P 0.18µm 2.8E-14 250 2.9E-14 8 1Mbit SRAM K6R4008C1D 0.18µm 1.5E-14 250 1.8E-14 8 4Mbit SRAM K6R4008V1D 0.18µm 1.5E-14 250 2.4E-14 8 4Mbit SRAM AS7C4096 0.18µm 1E-14 1E3 2.5E-14 8 4Mbit SRAM IDT71256 0.3 µm 4E-14 250 2.7E-14 8 256K SRAM Virtex II 0.15µm 2.56E-14 3E-14 198 16, 17, 18 FPGA 1.5V (3/08) 3.3E-14 150 SEU-Config 2V6000 2.9E-14 3E-14 104 RAM (9/03) 2.8E-14 74 TABLE I-CONTINUED Part Feature Size/ LANL SEU Hi E Pro SEU E 14 MeV N. Ref Oth Data X-Sct, X-Sct, cm²/bit Prot, MeV SEU X-Sct, cm²/bit cm²/bit Virtex II 0.15µm 2.64E-14 3.4E-14 198 16, 17 FPGA 1.5V (3/08) 3.8E-14 150 18 SEU-Block 2V6000 3.5E-14 104 RAM 3.2E-14 74 Virtex II 0.15µm 6.2E-7 N/A N/A 3.36E-7 19 XC2V3000 D/C AGT0337 SEU(cm²/ dev) F2149925 Virtex IIPro 0.13µm 2.74E-14 3E-14 200 16, 17 FPGA 1.5V (3/08) 1E-14 104 20 SEU-data 2VP4 2.98E-14 1E-14 65 Cache-embed (9/04) 1E-14 20 PowerPC XQR2VP4 3.3E-14 200 Virtex 4o 0.090µm, 1.55E-14 1.9E-14 200 16 FPGA, 4VLX, 1.2V 1.1E-14 100 21 4VSX 1.3E-14 45 SEU-Config RAM 9E-15 20 Virtex 4o 0.090µm 2.74E-14 3.2E-14 200 16 FPGA, 4VLX, 1.2V 3.7E-13 100 21 4VSX 2.7E-14 45 SEU-BRAM 1.8E-14 20 MPC7447A 0.13 µm 1.00E-14 N/A N/A 7.00E-15 22 µprocessor cache MPC7448 0.09 µm 8.10E-15 6.5E-15 198 1.30E-14 23 µprocessor cache Type 1 µprocessor 0.5 µm 5.9E-14 180 4.7E-14 9 SEU in cache 1.7E-14 250 1.8E-13 1000 Type 2 µprocessor 0.5 µm 4.8E-14 180 4.9E-14 9 SEU in cache Type 3 µprocessor SOI 1.0E-14 180 2.6E-14 9 SEU in cache 1.5E-14 250 3.9E-14 1000 Type 4 µprocessor 0.35 µm 2.7E-14 180 4.0E-14 9 SEU in cache 4.2E-14 250 7.8E-14 1000 Type 5 µprocessor 0.35 µm 3.1E-14 180 4.8E-14 9 SEU in cache

5 Ratio WNR/14 MeV Neut SEU X-Section Ratio TRIUMF/14 MeV SEU X-Section 4 Ratio Hi E Proton/14 MeV Ratio WNR/14 MeV Neut X-Section, 90s SRAMs Within Factor of 2, Lower Bound Within Factor 2, Upper Bound 3

1 Ratio WNR X-Sctn/14 MeV X-Sctn MeV X-Sctn/14 Ratio WNR 0 0 100 200 300 400 500 600 Feature Size, nm

Fig.2 Ratio of SEU Cross Sections [WNR or High Energy Proton]/[14 MeV Neutron] for Recent Devices

TABLE II TABULATION OF SEFI CROSS SECTIONS (CM²/DEV), TESTS PERFORMED USING HIGH ENERGY BEAMS

Part Feature Size/ LANL SEE Hi E Pro E 14 MeV N. Ref Oth Data X-Sct, SEU X-Sct, Prot, SEU X-Sct, cm²/bit cm²/bit MeV cm²/bit Virtex II 0.15µm N/A 3-6E-13 198 18 FPGA 1.5V 1.3E-12 150 (POR) 2V1000 6.5E-13 104 4-8E-13 74 1-3E-13 9 VII-XC2V3000 0.15µm 8.2E-8 N/A N/A 4.7E-8 19 D/C AGT0337 Virtex II 0.15µm 5E-10 120 24 XC2V3000 1.5V (few evts) Virtex IIPro 0.13µm N/A 4E-10 200 25 FPGA 1.5V Emb PowerPC XQ2VP40 Virtex IIPro 0.13µm, N/A 9.9E-10 120 26 FPGA, 1.5V Emb PowerPC XC2VP4 Virtex 4o 0.090µm 7E-11 105 27 4VLX FPGA 1.2V MPC7447A 0.13 µm 1.10E-09 N/A N/A 5.90E-10 22 µprocessor MPC7448 0.09 µm 5.60E-10 1.6E-11 198 2.70E-10 23 µprocessor

Table III TABULATION OF SEL CROSS SECTIONS (CM²/DEV), TESTS PERFORMED USING HIGH ENERGY BEAMS

Part Feature Size/ LANL SEU Hi E Pro E 14 MeV N. Ref Oth Data X-Sct, cm²/bit SEU X-Sct, Prot, SEU X-Sct, cm²/bit MeV cm²/bit SRAM B 0.14 µm 1.00E-10 4E-11 105 28 SEL (cm²/ dev) 3.6/1.6 V 2.5E-10 200 SRAM B 0.18 µm 2.80E-08 1E-7 500 29, 30 SEL (cm²/ 5.5V 3E-8 100 dev) 4Mbit 1E-8 50 HM628512B 0.35 µm, 1.5E-9 6.10E-09 490 11 SEL (cm²/ dev) D/C 9925 4.60E-09 360 3.20E-09 200 1.00E-09 100 3.70E-10 50

increases with temperature, devices should be tested at IV. CONCLUSIONS both ambient and elevated temperatures to obtain worst- The cross comparison as documented in Tables I-III, case SEL susceptibility. covering SEU, SEFI and SEL measurements taken by a variety of testing groups on SRAMs and µprocessors with The generalized conclusion is that monoenergetic different neutron and proton beams, allows useful proton and neutron beams may be used for single event conclusions to be drawn. upset testing as a substitute for using a spallation neutron source, such as the WNR neutron beam, provided that SEU results accurate to within a factor of 2 are acceptable. Based on the comparisons shown in Table I and Fig. 2, Thus, for purposes of measuring the atmospheric neutron the SEU cross section obtained from testing with SEU cross section in devices such as SRAMs, FPGAs, monoenergetic proton and 14 MeV neutron beams is microprocessors, and SDRAMs, truly monoenergetic expected to result in SEU cross sections that are within proton and neutron beams may be utilized. This may also less than a factor of 2 of what would be obtained from apply to SEFI, but there isn’t enough data to state this testing with the LANL neutron beam. conclusively. For purposes of testing devices for susceptibility to SEL SEFI from atmospheric neutrons, a monoenergetic proton beam The limited amount of SEFI data contained in Table II with energy in the range of 100-120 MeV may be used as leads to the preliminary conclusion that the SEFI cross a substitute fro the LANL neutron beam, with agreement section obtained from testing with monoenergetic proton expected to be within a factor of 2. If a proton beam with and 14 MeV neutron beams may be expected to result in a higher energy (> 120 MeV) is used and the SEL response SEFI cross section that is within about a factor of 2 of is measured, the SEL cross section may be higher than the what would be obtained from testing with the LANL SEL cross section that would be obtained using the LANL neutron beam. Data on additional parts would be needed neutron beam. Thus using higher energy (E>120 MeV) to be more conclusive. protons for SEL testing may yield conservative results compared to testing with the LANL neutron beam. SEL Based on the limited amount of SEL data contained in V. REFERENCES Table III, this data is consistent with the idea that the SEL cross section measured using a proton beam with an [1] E. Normand, AVSI Report “Cross Comparison Guide energy of 100-120 MeV will result in about the same SEL for Results of SEE Testing of Microelectronics (Los cross section as would be measured with the LANL Alamos Spallation Neutron Source vs. Other Beams),” neutron beam. For the examples cited, the agreement December 2008 between the proton SEL cross section (100-120 MeV) and [2] E. Normand, AVSI Report “Assessment of Alternative the LANL SEL cross section was within about a factor of Facilities to the Los Alamos National Laboratory 2, and usually closer. Because the SEL cross section (LANL) for Avionics Single Event Effects (SEE) [17] J. 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Commercially Designed and Manufactured SDRAM SEE Data

Craig Hafer , Member, IEEE, Matthew Von Thun, Member, IEEE, Mike Leslie, Fred Sievert, Anthony Jordan

column-address generation, to interleave between internal Abstract-- A commercially designed and manufactured banks to mask pre-charging time, and to randomly change 512Mb SDRAM is Single Event Latchup (SEL) immune and 100 column addresses on each clock cycle during a burst access. krad(Si) TID tolerant. It is packaged for application use into With a column address strobe (CAS) latency of 3 the device both a 2.5Gb and a 3Gb MCM configuration [1]. The Single will operate at 133 MHz. The device operates from -40C to Event Effects (SEE) performance is reported. +105C. I. INTRODUCTION III. SINGLE EVENT EFFECTS CHARACTERIZATION APPROACH lectronic applications in any operational environment Erequire fast, high-density memory for intensive data To characterize the 512Mb SDRAM device for SEE, the applications which accompany microprocessors and for data Lawrence Berkeley National Laboratory (LBNL) 10 recorders. A commercially designed and manufactured MeV/amu cocktail of heavy ions was used at an angle of 512Mb Synchronous Dynamic Random Access Memory incidence from normal (0°) to a maximum of 60°. The cocktail ions were B, O, Ne, Ar, Cu, Kr, and Xe producing an (SDRAM) has been characterized for radiation effects 2 performance and has been packaged into both a 2.5Gb and effective LET range from 0.9 to 111 MeV-cm /mg. A total 3Gb multi-chip module (MCM) for high density memory of 15 packaged devices were used for the heavy ion testing. applications. The device is single event latchup (SEL) Nine devices in several configurations were tested for upsets immune to a linear energy transfer (LET) of 111 MeV- and six devices were tested for latchup immunity. cm2/mg and 100 krad(Si) total ionizing dose (TID) tolerant. The individual SDRAM devices were packaged into Single event effects performance is reported. ceramic 144-pin grid array (PGA) packages. The SEL testing was done at maximum specified temperature and voltage of 105C and 3.6V V ; SEU testing was performed at 25C and II. PRODUCT DESCRIPTION DD 3.0V VDD. The SDRAM devices are high performance, highly Prior to SEL irradiation, the devices were initialized by integrated multi-chip modules (MCMs). Total module configuring the control registers and writing data into the density is 2,684,354,560 bits for the 2.5G device and memory. The devices were then left statically biased during 3,221,225,472 bits for the 3G device. The devices are the irradiation with the current monitored during each test organized as 64M x 40 (16M x 40 x 4 banks) and 64Meg x 48 run. Four of the six components were exposed to an effective (16Meg x 48 x 4 banks). The SDRAMs are specified for fluence of 1.0x107 ions/cm2; two devices were irradiated to a operation at 3.3V in a temperature range from -40C to lower fluence. Each device was tested for functionality pre- +105C. An auto-refresh mode is provided, along with a irradiation and at one or more test points during the fluence power-saving, power-down mode. All inputs and outputs are accumulation without cycling the power. LVTTL compatible. SDRAMs offer significant advances in The SEU testing was performed using a proprietary DRAM operating execution, including the capability to Aeroflex developed Xilinx-based memory tester operating synchronously burst data at a high data rate with automatic with a clock speed of 80 MHz. The Aeroflex memory tester would initialize the SDRAM device by configuring the

Manuscript received July 17, 2009. control registers and then writing an A5h (10100101) pattern M. Von Thun is with Aeroflex Colorado Springs, Colorado Springs, CO to each even 8-bit address location and a 5Ah (01011010) 80907 USA (telephone: 719-594-8344, e-mail: [email protected]). pattern to each odd 8-bit address location. During heavy ion C. Hafer is with Aeroflex Colorado Springs, Colorado Springs, CO 80907 beam exposure, the tester would continuously cycle through USA (telephone: 719-594-8319, e-mail: [email protected]). M. Leslie is with Aeroflex Colorado Springs, Colorado Springs, CO all addresses in a read mode. Errors were counted and 80907 USA (telephone: 719-594-8148, e-mail: [email protected]). categorized with three signatures: 1) single bit errors, 2) data F. Sievert is with Aeroflex Colorado Springs, Colorado Springs, CO alignment, and 3) all ones/zeros. Since the last two 80907 USA (telephone: 719-594-8423, e-mail: [email protected]). A. Jordan is with Aeroflex Colorado Springs, Colorado Springs, CO categories are indicative of a single event functional interrupt 80907 USA (telephone: 719-594-8252, e-mail: [email protected]). (SEFI) type of error, an event count was issued rather than counting all incorrect bits. The data alignment error occurs

when the expected data is opposite the actual data. That is, if failing bits, so multiple bit upsets (MBUs) within a word an A5h data pattern is expected and a 5Ah pattern is read, could not be summarized. then the error is categorized as a data alignment error and may be the result of incorrectly addressing an even rather than an odd address (or vice versa). The all ones or zeros error could occur with the device outputs in a tri-state condition. Once an error was detected, the tester would increment the number of failing bits, or events, and then re- write the correct data to that address before continuing to read through the memory array. The memory refresh period was set to 64ms for testing which demonstrated margin to the specified device refresh period of 32ms. Shielding was placed on several devices to mask the logic circuitry (array open) and to mask the array (array blocked - logic circuitry and some small amount of array circuitry exposed) from the ion beam. In these two configurations, the devices were exposed to the heavy ion beam only at normal incidence. Data was also taken with the entire device exposed (no shield) to the ion beam. Photographs of the shielding and open die configurations are shown in Figs. 1 to Fig. 2. Copper tape shield exposing logic circuitry (array blocked). Some of 3. the array is exposed in order to ensure that all of the logic circuitry is exposed to the heavy ion beam.

Fig. 1. Stainless steel shield exposing only the array (array open). Some of the array is blocked in order to ensure that only memory array is exposed to Fig. 3. This configuration allows heavy ion exposure to the entire device (no the heavy ion beam. shield).

Error data was logged at the rate of 15 data log lines per The bit errors were recorded as a function of heavy ion second. Post processing of the data was done to determine effective LET and effective fluence. The effective LET is the number of events as opposed to the number of failing bits. equal to the LET at normal incidence multiplied by the secant The data for both the “no shielded” devices and the “array of the angle of incidence. The effective fluence is equal to blocked” (logic exposed) devices were filtered for events by the fluence at normal incidence multiplied by the cosine of counting contiguous lines of logged data with failing bits as the angle of incidence. The effective LET and effective one event. That is, contiguous rows of failures in the logged fluence calculations pertained only to the no shield data for any category - single bit errors, data alignment fails, configuration since the beam was normally incident for the or all ones/zeros fails, constituted a single ion event. The “array open” and “array blocked” configurations. flux during irradiation was set to a level which would result in errors occurring from a single ion strike at the rate of IV. SEL RESULTS approximately one event per second. Six “no shield” devices were tested for SEL immunity of The “array open” (logic circuitry blocked) data were not the SDRAM. As seen in the Table I summary, no single filtered. Each line in the run log recording errors (i.e. a event induced latch-ups were observed to an effective LET of number greater than zero) constituted a single ion strike 111 MeV-cm2/mg when exposed to Xe ions at LBNL to an event. The data recording did not include address location of

7 2 effective fluence of 1x10 ions/cm . SEL Testing was 50 performed at 105C with VDD set at 3.6V. 48 46 TABLE I SINGLE EVENT LATCHUP DATA FOR SIX SDRAM TESTED SAMPLES. 44

Effective Effective ) 42 Fluence LET Serial Wafer Latchup 40 Number Number (y/n) (ions/cm2) (MeV-cm2/mg) (mA DD I 38 12n5.0x106 111 22n1.0x107 111 36 15 7 n 1.0x107 111 34 29 21 n 1.0x107 111 32 7 32n1.0x10 111 30 6 18 7 n 1.0x10 111 250 500 750 1000 Time (s)

Power supply current measurements were recorded Fig. 5. Run 1 (serial number 1, wafer number 2) power supply current as a approximately every 2.7 seconds during each SEL run. Fig. 4 function of time. run 5 is an example of the current measurements taken during 50 the entire irradiation and measurement periods. The higher 48 current points in these plots at non-irradiation times occur 46 during device initialization and during read operation where 44 the currents are higher than the standby current recorded 42 during irradiation.

(mA) 40 DD 60 I 38 36 55 34 32 50 30

45 0 500 1000 1500 (mA)

DD Time (s) I 40 Fig. 6. Run 2 (serial number 2, wafer number 2) power supply current as a function of time. 35 Beam on 50 48 30 46 0 200 400 600 800 1000 1200 1400 Time (s) 44

Fig. 4. Run 5 (serial number 3, wafer number 2) power supply current as a 42 function of time. The “beam on” lines indicate the time period of irradiation 40 (mA) DD exposure. I 38 36 To avoid confusion when inspecting these current 34 measurement graphs, Figs. 5 through 10 contain only the 32 current measurements during irradiation. The current is quite 30 stable during the irradiation with a few current excursions 200 400 600 800 1000 1200 observed in Figs. 5 through 9 (runs 1 to 5). It appears from Time (s) the current excursion levels that the device may go into a read mode for a short duration. Fig. 10 (run 6) exhibits no current Fig. 7. Run 3 (serial number 15, wafer number 7) power supply current as a function of time. excursions.

50 TABLE II 48 SINGLE EVENT UPSET WEIBULL PARAMETERS AND ERROR RATE 46 PREDICTIONS 44 Onset Event Saturated LET Frequency 42 Shield Weibull Weibull Cross- (MeV- (device- 40 Configuration Shape Width section cm2/mg) Event-Rate days/event) (mA) DD I 38 No Shield 4307.6x10-10 0.2 1.1x10-10 17 36 Array Open 4307.6x10-10 0.2 1.1x10-10 17 34 Array 32 Excluding 3.7 40 7.6x10-10 1.4 4.0x10-11 47 30 Single-Bit Upsets 200 700 1200 1700 2200 Time (s) Array 2.4 30 1.8x10-2 0.2 2.3x10-2 43 Blocked Fig. 8. Run 4 (serial number 29, wafer number 21) power supply current as a function of time. 50 Figs. 11 to 13 contain plots of event cross section versus 48 LET for the tested devices and a Weibull curve shown with a thin solid line. The Weibull parameters for the no shield and 46 array open have been set to the same values. Obviously the 44 “no shield” device cannot have lower cross section data than 42 the array open device. It is possible that SEFI events during 40 (mA) testing of the no shield devices masked some single bit errors DD I 38 resulting in cross section values below the Weibull curve. 36 1E-9 34 32 1E-10 / bit) 30 2 1E-11 0 200 400 600 800 1000 1200 Time (s) 1E-12

Fig. 9. Run 5 (serial number 3, wafer number 2) power supply current as a 28_21 1E-13 function of time. 16_7 22_21 1E-14 50 4_2 48 17_7 1E-15 Weibull 090819 46 (cm Section Cross Event 1E-16 44 0 20 40 60 80 100 120 42 LET (MeV-cm2/mg) 40 (mA) Fig. 11. Event cross section versus effective LET data for the SDRAM DD I 38 device fully exposed to the ion beam (no shield). With no shielding the 36 device was rotated to achieve the higher effective LETs. The numbers in the legend indicate serial number and wafer number. 34

32 Event cross section is in units of cm2/bit for Figs. 13 and 14 30 and is calculated by dividing the number of errors by the 250 300 350 400 450 500 550 600 effective fluence and dividing again by the number of Time (s) exposed bits or memory cells. The bond wires block about Fig. 10. Run 6 (serial number 18, wafer number 7) power supply current as a 10% of the device. Therefore, the number of bits used in the function of time. no shield calculations is 483,183,821 (90% of 229). About 50% of the memory cells were blocked from the heavy ion V. SEU RESULTS irradiation for the array open configuration due to the shield Nine SDRAM devices were tested for SEU and SEFI itself and the bond wires. Calculations were performed for performance. Table II contains the associated Weibull fit the array open configuration assuming 268,435,456 (50% of parameters and error rate calculations done with 229) bits or memory cells were exposed to the heavy ion SpaceRadiation 5.0 assuming the Adams 90% worst case beam. Events for the array blocked configuration are related environment, a geosynchronous orbit, and 100mil aluminum to the logic circuitry, and so the event cross section is shielding for each set of SEU data. An error rate calculation calculated in terms of events per device. was also generated for the array open data using event data for only ion strikes with multiple bits upset. See Fig. 14 for number of bits upset during a single ion strike.

1E-9 Single Bits Upset with One Ion Strike (data has no address resolution) 1E-10 100% / bit)

2 12-Bits 1E-11 11-Bits 80% 10-Bits 1E-12 9-Bits 60% 8-Bits No 1E-13 errors 7-Bits to a 40% 6-Bits 1E-14 Weibull fluence of 1E7 5-Bits 11_7 2 Zero error run ions/cm 4-Bits 1E-15 to a fluence of 10_7 20% Event Cross-Section (cm 1E7 ions/cm 2 2 or more bits/event 3-Bits 1E-16 2-Bits 0% 0 102030405060 1-Bit 2 LET (MeV-cm /mg) 3 0 7 4 3 n39 n3 n35 n41 n n42 n43 u u un u u u r r -ru -r -r Fig. 12. Event cross section versus effective LET data for the SDRAM e-r B-run32B-r O- O- Ar Ar Kr-ru Kr device with the logic circuitry blocked (array open) to the ion beam. To Ne-run34 Cu-run36 X maintain the benefit of the shield the device could not be rotated and the ion Fig. 14. This plot shows the number of bits upset with one strike for the runs strikes were all normally incident to the device. The numbers in the legend with the array open. Address location information for the failing bits could indicate serial number and wafer number. A Weibull curve which only not be acquired with this test setup. counts events affecting 2 or more bits is also shown. TABLE III

1E+0 SDRAM MEMORY DEVICE OPERATION RECOVERY Recovery to LET 1E-1 functional Run Serial Wafer Shield (MeV- Fluence operation and 2 2

/ device) / Number Number Number Conf. Ion cm /mg) (ions/cm ) correct data 2 1E-2 34 of All All Up to All All All Read/Write 36 runs others others 1.0x107 1E-3 Re-initialzation No 20 16 7 Xe 55 1.0x104 including memory Shield 1E-4 re-write Re-initialzation 1E-5 Array 3 Weibull (array blocked) 51 12 7 Xe 55 9.8x10 including memory blocked 14_7 re-write 1E-6 12_7

Event Cross-Section (cm Cross-Section Event For comparison only - Weibull (no shield) 1E-7 VI. DISCUSSION 0 102030405060 SEE testing was performed on a 512Mbit SDRAM device LET (MeV-cm2/mg) at the Lawrence Berkeley National Laboratory (LBNL) using Fig. 13. Event cross section versus effective LET data for the SDRAM their 10 MeV/amu heavy ion beam cocktail from their 88- device with the logic circuitry open (array blocked) to the ion beam. To maintain the benefit of the shield the device could not be rotated and the ion inch Cyclotron. The devices were shown to be immune to strikes were all normally incident to the device. Note that the data in this single SEL to a LET of 111 MeV-cm2/mg when exposed to graph is plotted on a per device basis. The Weibull curve from the no shield heavy ions at 105°C and 3.6V V (considered worst-case data is included for comparison only. The numbers in the legend indicate DD serial number and wafer number. conditions for SEL). The 512Mbit SDRAM device was also tested for SEU at 25°C and 3.0V VDD (considered worst-case The test setup did not allow for address location of the conditions for SEU). A SEU event rate of 1.1x10-10 failing bits. The array open data in Fig. 14 shows the number events/bit-day was calculated for the 90% worst-case of bits upset during a single ion strike. As can be seen, as the environment in the geosynchronous orbit (based on ion type increases in mass the number of failing bits per ion SpaceRadiation 5.0). This event rate can be converted to an strike increases. event frequency of 17 device-days/event. As described previously, after initializing the device the test program would continuously read the device, report the VII. REFERENCES number of failing bits due to an ion strike, and then re-write correct data to the failing address locations. In all but two [1] http://www.aeroflex.com/ams/pagesproduct/datasheets/U SEU runs (#20 & #57) a read and re-write corrected the data T8SDMQ64.pdf and recovered the device to fully functional operation. Runs 20 and 57 recovered fully after re-writing the mode registers. Table III highlights the full operation recovery method during the SEU testing.

SEE Testing of National Semiconductor’s LM98640QML System on a Chip for Focal Plane Arrays and Other Imaging Systems

Kirby Kruckmeyer, Member, IEEE, Robert Eddy, Alex Szczapa, Bill Brown and Tom Santiago

the device under test (DUT) must be controlled and monitored Abstract—National Semiconductor’s LM98640QML is a remotely, requiring as much as 30 feet of cabling. At most complex signal processing solution interface for CCDs and heavy ion test facilities the DUT is in a vacuum chamber, CMOS imagers used in focal plane arrays and other imaging requiring the control and monitor signals to be fed through a systems. This complex system on a chip (SOC) consists of an integrated 14 bit analog-to-digital converter (ADC), correlated metal wall. These cabling issues coupled with the high double sampler, delay-locked loop (DLL), serial interface, digital- background noise at a heavy ion test facility make it difficult to-analog converters (DAC), programmable variable gain to get a clean signal to the DUT and out of the DUT to the test amplifiers and other components. Single event effect (SEE) equipment. For a precision Analog-to-Digital Converter characterization of a complex, precision SOC with many (ADC) it is difficult to detect SEE errors on the order of different operating modes can present significant challenges. magnitude of the precision of the part (0.1 mV for a 14 bit Heavy ion test challenges, solutions and results are presented here. ADC with a 2 V input range). The test challenges, solutions and results for the LM98640QML are presented here.

I. INTRODUCTION CD and CMOS imaging chips, used in space applications Csuch as earth observation or star tracking, require careful conversion of their analog outputs to a digital signal for processing by an FPGA or ASIC. Previously, the analog front end (AFE) electronics for analog signal conditioning and digital conversion were developed using discrete radiation hardened analog-to-digital converters (ADC), amplifiers digital-to-analog converters (DAC) and serializers, resulting in a relatively bulky solution that had to be located remotely. National Semiconductor’s LM98640QML, a complex system on a chip (SOC), incorporates all analog signal processing and digital conversion on a single chip [1] (Fig. 1). This level of Fig. 1. Application diagram of the LM98640QML. integration allows the chip to be located right on the focal plane board. Moving the analog signal processing closer to II. PRODUCT DESCRIPTION the imaging chip results in better imagine resolution. The LM98640QML is a fully integrated, dual channel, 14 bit This high level integration on a single precision SOC signal processing solution for high performance imaging presents new challenges for single event effect (SEE) applications (see Fig. 2 for block diagram). It has an internal characterization. A mixed signal SOC can have both digital Correlated Double Sampling (CDS) mode for CCD arrays and and analog inputs and outputs and different types of signals to a Sample and Hold (S/H) mode for Contact Image Sensors and control and monitor. There are many different types of SEEs CMOS Image Sensors. It supports sampling rates between 5 that can occur and must be monitored. One type of test system and 40 mega samples per second (MS/s). There are many may not be adequate to monitor all of the different types of integrated features for compensating for the performance signals. Due to radiation safety issues at a heavy ion facility, variations in imaging sensors, such as offset correction and

Manuscript received July 14, 2010. sampling edge adjustment. The data output is presented in a Kirby Kruckmeyer is with National Semiconductor, 2900 Semiconductor serial low voltage differential signal (LVDS) format at either Drive, Santa Clara, California 95052-8090, phone: (408) 721-3548, email: 16X the sample rate in a dual output lane, or 8X the sample [email protected] Robert Eddy and Tom Santiago are with National Semiconductor, Santa rate in a quad output lane. Clara, CA 95052 LM98640QML is a dual channel 14 bit analog-to-digital Alex Szczapa and Bill Brown are with National Semiconductor, South converter (ADC), with the channels designated as OS1 and Portland, ME 04106

Fig. 2. LM98640QML Block Diagram

OS2 (Fig. 2). The analog circuitry runs off the nominal 3.3 V (indicated in the triangle marked “CDS S/H in Fig. 2). In supply, while the digital circuitry runs off the nominal 1.8 V “Correlated Double Sampling” mode (CDS), the input signal supply. is sampled twice during the same pixel clock and the The sampling rate of the LM98640QML is set to the pixel difference between the two samples is processed by the ADC rate of the CCD or Active Pixel Sensor by the differential (Fig. 4). This is to accommodate the operation of many clock frequency on the LVDS clock inputs (INCLK+ and image sensors, where at the beginning of each pixel cycle, the INCLK-). The on-board Delay-Locked Loop (DLL) generates pixel cell is reset to a reference or black level, before an internal clock 64X the pixel clock rate to enable the internal capturing the image data [2],[3]. This reference or black level timing required to process the signals. The LM98640QML can vary from cell to cell. The sample and hold circuits are generates an LVDS double data rate (DDR) Output Clock at switched capacitor structures. TXCLK+ and TXCLK- for data capture of the LVDS Serialized output. The Output Clock signal is a square wave of seven pulses, followed by a gap in the pulse (see Fig. 3).

Fig. 4. Correlated double sampling. The sampling windows are adjustable and moveable.

In CDS mode, the settling time of the sample and hold circuit is longer, and too long for the higher sample rates. To accommodate CDS mode, a second CDS circuit was added for each channel (not shown in Fig. 2). During the first pixel clock, the first CDS circuit (designated “Even”), is used. On Fig. 3. LM98640QML timing diagram in quad lane mode. the next pixel clock, the second CDS circuit (designated The LM98640QML can operate in two different sampling “Odd”) is used. Which CDS circuit being used is indicated by modes. In “Sample and Hold” (S/H) mode, the input signal is the Frame output (TXFRM+ and TRFRM- in Fig. 3). When sampled and held once per sample cycle like any typical ADC. Even is being used, the Frame will be high for 5 clock cycles, For S/H mode, one sample and hold circuit is used per channel while Frame will be high for 3 clock cycles when Even is used

(Fig. 3). Differences in the signal paths between Even and The biggest challenge to testing the Output Code errors Odd can result in an offset on the output between alternating was supplying a clean input voltage to the DUT with a noise pixel clocks. These offsets can be corrected during post level magnitude lower than the precision of the part. The processing outside the part. LM98640QML has 14 bit ADC for an Output Code range of The LM98640QML has a programmable DAC output that 16384 and input voltage range of 2 V, for an output precision can be used as an adjustable reference voltage (VCLP in Fig. of 0.1 mV. The LM98640QML has many options for 2). conditioning the input signal before going to the ADC for After the sample and hold or CDS, there are digital-to- conversion, including a programmable gain amplifier (PGA), analog converters (shown as “FINE DAC” and “COARSE for amplifying low level input signals and an internal DAC to DAC” in Fig. 2) that can be programmed to add an offset to apply an offset correction. Any noise on the input voltage the input signal, to compensate for variations in sensor could be multiplied by this signal conditioning. performance. Even with no analog signal on the input of the A clean supply voltage and analog input to the DUT are LM98640QML, it is possible to get an output signal by required for a precise digital output with a minimal amount of adjusting these DACs. The DACs are a resistor ladder design. noise. Even with a precision power supply, it can be difficult The S/H or CDS and the Offset DACs feed the to get a clean signal to the DUT, due to the long cables programmable gain amplifier (“PGA” in Fig. 2) which can be coupling with the background noise of the test facility. With used to increase or decrease the signal prior to digitization in the supplies being fed through the wall of a vacuum chamber, the ADC core. the supplies can also couple with the external input clock, The output of the ADC is a 14 bit serial LVDS signal. In running at 40 MHz. “dual lane” mode, there is a single output line for each channel The outputs to be monitored for SEU were high frequency (TXOUT0+ and TXOUT0- for OS1 and TXOUT2+ and signals. The Output Clock, generated by the internal DLL TXTOUT2- for OS2) and the output bits are clocked on the runs between 40 to 320 MHz (8X the input clock). For each rising and falling edges of the output clock (TKCLK), as in channel, the Output Code is a 14 bit serialized signal, with two Fig. 3. In “quad lane” mode, for each channel, the 14 bit bits clocked out on two output lines on each clock cycle. Due output is split between the two output lines for each channel. to the high speed of these signals, it is necessary to capture the The operating configuration of the LM98640QML is signals as close to the DUT as possible. programmed through a separate serial interface (“Digital Control and Config Registers” in Fig. 2). Along with the IV. TEST SOLUTION AND METHOD operating modes mentioned above, there are a number of other Each DUT was delidded and soldered to a separate operating options, including a 1X or 2X gain option in the S/H LM98640CVAL Evaluation Board [7] (Fig. 5). The board has or CDS and the ability to adjust the sampling window. The the option to power the DUT from an onboard regulator or configuration of the registers can be read out through the serial from an external power supply. The LM98640CVAL boards interface. were connected to a WaveVision 5 board [8], which contains a The LM98640QML is fabricated using National Xilinx Virtex 4 FPGA (Fig. 5). Communication with the Semiconductor’s 180 nm CMOS9 process. The active areas WaveVision 5 board is through a laptop PC connected by a are on a thin EPI layer on top of a very low resistivity USB cable. The FPGA was programmed with AFEval substrate. From the top of the upper passivation layer, through software [7] to control the evaluation board and DUT and the metal layers, active areas and EPI to the substrate is less capture data from the DUT. For the SEE testing, the laptop than 12 µm. PC was networked to a second laptop PC so that it could be run remotely from the facility control room. Different III. TEST CHALLENGES configurations were used for each type of SEE.

To fully characterize the LM98640QML, it was necessary to test for the following Single Event Effects: Latchup (SEL), Functional Interrupt (SEFI) and Upset (SEU) of the digital Output Code, Output Clock and Frame signals. Simultaneously testing for all of these effects was not possible. The probability of these different effects occurring was orders of magnitude different. Some events had to be tested at a higher ion flux so a significant amount of data could be collected in a reasonable amount of time, while other events required a low flux so that events would not overlap.

To test for SEL, it is necessary to monitor the supply current Fig. 5. LM98640CVAL and WaveVision 5 boards. DUT has lid taped on. to DUT. A remote power supply and current monitor can result in a noisy output. SEL testing requires the DUT to be Heavy ion testing was performed at the 88” Cyclotron tested at elevated temperature and maximum supply voltage Facility at Lawrence Berkeley National Laboratory (LBNL) while SEU testing is typically done at room temperature and located in Berkeley, California. The 4.5 and 10 MeV/nucleon minimum supply voltage [4]-[6]. beams were used. See [9] for penetration depths and linear

energy transfer (LET) of the ion beams. The heavy ion beam change in the output code or for the part to stop operating exposure is inside a vacuum chamber. correctly, until the part is reset. The overall integrity of the register design was indirectly monitored during every ion run A. SEL Test Method C. Clock and Frame Signals SEU Test Method Two units (CDS1 and SH2) were tested for SEL. Testing The differential probes were connected to WaveVision 5 was done with the DUT junction temperature at 125°C. board at the socket where the Output Clock (TXCLK) and The DUT was heated by attaching resistive spiral heater to Frame (TXFRM) signals from the DUT entered the board. the backside of the LM98640CVAL board, directly under the The differential probes were connected to a Tektronix 1103 DUT. The temperature was monitored by a thermistor Tekprobe Power Supply. The output of 1103 was fed through attached to the topside of the board next to the DUT (Fig. 5). the vacuum wall chamber and connected to a Tektronix 7404B The heater and thermistor were controlled by a Lakeshore 332 oscilloscope. temperature controller. Before heavy ion testing, the The oscilloscope was set on “width trigger” so that scope thermistor reading was correlated to a junction temperature of triggered on the rising edge of the differential input signal. If the DUT by heating the DUT and measuring the die surface the falling edge of the signal was outside a set time limit, the temperature with a Fluke 80T-IR Infrared Temperature Probe. scope would capture the screen and the data would be saved The probe was pointed at an area of the die where there was (see Fig. 4). Since the Frame signal alternates in width no metal coverage. A thermistor reading of 90ºC equated to a between Even (5 clock cycles) and Odd (3 clock cycles), the die surface temperature of 125°C as measured by the 80T-IR. limits for Frame had to be wide enough so that neither Even The LM98640CVAL board was configured so that the 3.3 nor Odd would cause an error to be recorded. and 1.8 V DUT supply voltages were powered by remote power supplies. The supply current of each was monitored by lower limit a multimeter. The power supplies were adjusted so that the upper l im it supply voltages at the LM98640CVAL boards were at the maximum of the operating range, 3.45 V for the 3.3 V supply clock output signal and 1.9 V for the 1.8 V supply. When the DUT was exposed voltage to the beam, the supply currents were monitored for any time abrupt changes. If there were no abrupt and permanent supply current changes greater than 1 mA, after being exposed to the 7 2 heavy ion beam to a fluence of 1 x 10 ions/cm , the DUT would be considered immune to SEL at the effective linear Fig. 6. Scope triggering mode for clock and frame SEUs. energy transfer (LET) of that ion. The input clock was set at 40 MHz. SH2 was configured Testing was done on DUT CDS1 with the input clock at 5, for Sample and Hold mode and CDS1 was configured for 20 and 40 MHz. Scope trigger limits are shown in Table II. Correlated Double Sampling mode. Because of the different The testing was performed using the 4.5 MeV/nucleon beam, operating modes, the two DUTs had different supply currents with ions runs at various LETs. (Table I).

TABLE I TABLE II SUPPLY CURRENTS SCOPE TRIGGER LIMITS FOR CLOCK AND FRAME SEU TESTING DUT Sampling 1.8 V Supply 3.3 V Supply Input Output Lower Upper Frame Lower Upper Mode Current (mA) Current (mA) Clock Clock Limit Limt Limit Limit CDS1 CDS 43.93 132.16 (MHz) (MHz) (ns) (ns) (MHz) (ns) (ns) SH2 S/H 44.96 95.73 54012145 20 160 2.8 3.2 20 11 20 40 320 1.5 1.8 40 6.5 10 The SEL tests were performed using the 4.5 MeV/nucleon beam. The ion runs were with Bismuth, with the DUT at 35° incident angle for an effective LET of 120 MeV-cm2/mg. D. Output Code SEU Test Method B. SEFI Test Method To capture Output Code upsets, the Virtex 4 FPGA on the SEFI immunity was monitored in two ways, directly and WaveVision 5 board was programmed with a code error indirectly. Before and after each ion run for SEL testing on routine. The FPGA would monitor the four different sets of DUTs CDS1 and SH2, the configuration registers were read output codes (Even and Odd on OS1 and Even and Odd on and then compared. If no registers changed after an ion run to OS2), and average each of those. For each channel, limits a fluence of 1 x 107 ions/cm2, the DUT could be considered could be set around the outputs. If the Even or Odd Output SEFI immune to the effective LET of the ion used. An upset Code for that channel was outside those limits, an error would in many of the individual configuration registers would result be recorded including the value of either Even or Odd in a change in the operation of the part that could result in (whichever sample and hold circuit was active at the time of

the error) and a time stamp, counted in samples. Due to and various ions. limitations in the system, the limits for each channel were set around both Even and Odd. If there was an offset between V. RESULTS Even and Odd, the error limits had to be widened to A. SEL Test Results compensate for the offset. SEL testing was performed on two units at an effective LET The environment at LBNL can be very noisy. It can be very 2 7 2 difficult to get a clean analog signal to the input of the DUT, of 120 MeV-cm /mg to a fluence of 1 x 10 ions/cm with a DUT junction temperature of 125°C. No measurable increase resulting in a clean output signal. In addition, with a voltage in supply current was seen to the 0.01 mA resolution of the on the input, the offset between Even and Odd is magnified multimeters. and can be multiplied by the gain of the PGA. To get the cleanest output, with the least amount of noise and least amount of offset between Even and Odd, DUT CDS1 was B. SEFI Test Results tested with the inputs floating. The output code was set by Before and after each ion run for SEL testing, the enabling the Coarse and Fine DACs (both set at 435 for OS1 configuration registers were read and compared. There were and 445 for OS2) and gaining the signal with the PGA. With no changes in the registers after the ion runs. In addition, this set up, the Output Code limits could be set tighter in order there were no detectable changes in the operation of any of the to detect smaller upsets of the Output Code. Testing was done DUTs during any of the ion runs. The only detected errors with the DUT in CDS mode. The setup and the average were on the Output Clock and Frame signals and Output Code. All these signals recovered without the DUT having to be Output Code for each channel are summarized in Table III. reset. DUT CDS4 was tested with an input voltage of 1.25 V (OS+ in Fig. 2) and a 2.2 V reference (OS-). To reduce the C. Clock Signal SEU Test Results input noise, LM4050WG2.5RLQV, 2.5 V precision voltage Three types of Output Clock SEUs signatures were references [9] were used to supply the input voltages. The detected: clock pulse narrowing, clock pulse broadening and a references and passive components were soldered to a small glitch pulse (Fig. 7). In all cases the error lasted only one daughter board that was attached to the LM98640CVAL board clock cycle. Most of the errors were either widening or close the DUT (Fig. 5). The daughter board was supplied with narrowing of the clock pulse. Less than 10% were due to a 5 V taken from the LM98640CVAL board. The 2.5 V output glitch.). of the LM4050WG2.5RLQV was divided down to the 1.25 V. The 2.2 V reference was supplied by using the VCLP 0.8 reference DAC on the LM98640QML (Fig. 2). The input and reference voltages were passed to the DUT through a switch to 0.7 simulate the output of a CCD for CDS mode. The PGA gain 0.6 was set to 0.7 for OS1 and 1 for OS2. Testing was done with the Coarse and Fine DACs enabled (set at 225 for both DACs 0.5 and channels) and disabled to determine the impact of the DACs on the SEU performance of the part (summarized in

Voltage (V) Voltage 0.4 Table III). Additional steps were taken to reduce the background noise. 0.3 The spiral heaters and thermister for SEL testing were removed from the LM98640CVAL board. The differential 0.2 probe and probe test points were removed from the -20.0 -10.0 0.0 10.0 20.0 30.0 WaveVision 5 board. The DUT was powered by the onboard Time (ns) voltage regulators. The supply voltages were set at nominal Fig. 7. Scope capture of an example of a clock output glitch caused by an values as determined by the fixed outputs of the regulators. ion strike. The glitch is seen at 0 ns, when it caused a scope trigger. The gaps seen at -15 and +5 ns are by design and part of the normal operation of the Testing was performed using the 10 MeV/nucleon beam clock.

TABLE III DUT CONFIGURATION FOR SEU TESTING Fine and Output Output DAC Channel Input Coarse PGA Vclamp Code Code DUT Condition DAC Setting Gain DAC Average Error Limits OS1 Floating 435 1.0 Disabled 1109 ±25 CDS1 Enabled OS2 Foating 445 4.0 Disabled 6444 ±50 OS1 1.2 V 255 0.7 2.2 V 10961 ±480 CDS4 Enabled OS2 1.2 V 255 1.0 2.2 V 7314 ±480 OS1 1.2 V Disabled 0.7 2.2 V 10901 ±480 CDS4 Disabled OS2 1.2 V Disabled 1.0 2.2 V 7187 ±480

The threshold LET (LETth) is the minimum LET where no D. Frame Signal SEU Test Results SEUs are detected. For the Output Clock, LETth was between 2 Four types of Frame SEU signatures were detected: 3 and 6 MeV-cm /mg. The cross section is a relative broadening of the frame signal, a positive glitch when the indication of the probability of an SEU and is calculated by Frame should be low, negative glitches when the Frame dividing the number of upsets by the fluence for any particular should be high (Fig. 9) and an attenuation of the differential LET. For the output clock at 320 MHz, the SEU cross section signal. A small amount of widening of the Odd Frame or vs. LET with the is plotted in Fig. 8, along with a Weibull fit narrowing of the Even Frame would not be detected as the [9]. The SEU cross section continued to increase with LET 2 -6 2 scope limits were widened to accommodate the differences in and was at 100 MeV-cm /mg was 9.5 x 10 cm , the highest the Even and Odd pulses. The Frame SEU cross sections were LET tested. The Weibull fit parameters are listed in Table IV. about half that for the Output Clock. The Frame SEU cross sections are shown in Table VI. 1.E-04 0.8

0.6 1.E-05 0.4 ) 2 1.E-06 0.2 Data Weibull Fit 1.E-07 0

-0.2

Cross Section (cm Section Cross 1.E-08 -0.4 Differential Voltage (V)

1.E-09 -0.6 0 20406080100120 -30.0 -10.0 10.0 30.0 50.0 70.0 90.0 LET (MeV-cm2/mg) Time (ns) Fig. 8. Clock SEU cross section vs. LET. Fig. 9. Frame glitch due to ion strike. This was the worst case glitch detected during the testing. TABLE IV WEIBULL FIT PARAMETERS FOR OUTPUT CLOCK SEU TABLE VI ALoWs FRAME SEU CROSS SECTIONS -6 9.52 x 10 3.08 60 2.4 Input Output LET Cross Clock (MHz) Clock (MHz) (MeV-cm2/mg) Section (cm2) -6 The worst case condition for a clock upset was with the 20 160 77.5 1.9 x 10 -6 clock at the maximum operating frequency. Table V shows 20 160 87.1 1.6 x 10 -6 the SEU cross sections at an LET of 100 MeV-cm2/mg for 40, 40 320 99.7 5.1 x 10

160 and 320 MHz output clock frequencies.

TABLE V E. Output Code SEU Test Results CLOCK OUTPUT SEU CROSS SECTIONS VS. FREQUENCY All Output Code SEU testing was done with the input clock Input Output Cross set at 20 MHz. A total of 8000 events were recorded at the various LETs. The majority of events lasted only one pixel Clock (MHz) Clock (MHz) Section (cm2) -6 cycle, and the Output Code recovered on the next pixel cycle. 5402.9 x 10 Except for three events, the longest events seen lasted 5 pixel -6 20 160 7.5 x 10 cycles (125 ns). There were two events that lasted 6 cycles, -6 40 320 9.5 x 10 and one that lasted 61 cycles (1525 ns). The average length of the events was dependent upon the LET. Table VII shows the

breakout in percentages of the event lengths at different LETs for channel OS1 with the inputs floating.

TABLE VII BREAKOUT OF EVENT LENGTH VS. LET. THESE DATA ARE FOR OS1 WITH THE INPUTS FLOATING AND THE LIMITS AT ±25. PIXEL CLOCK IS SET AT 20 MHZ AND EACH CYCLE IS 125 NS.

LET (MeV-cm2/mg) 102.5 87.9 76.7 67.9 58.8 48.0 37.7 30.9 19.8 9.7 4.4 1 Cylce 56% 56% 58% 64% 62% 71% 75% 83% 91% 98% 100% 2 Cylce 24% 29% 27% 26% 32% 23% 24% 12% 8% 2% 0% 3 Cylce 19% 14% 14% 10% 6% 6% 1% 5% 1% 0% 0% 4 Cylce 1%1%0%1%0%0%0%0%0%0%0% 5 Cylce 0%1%0%0%0%0%0%0%0%0%0%

The majority of the Output Code errors were small in TABLE VIII magnitude. On DUT CDS1 (see Table III for DUT WEIBULL FIT PARAMETERS FOR ALL EVENTS DETECTED FOR CDS1, CHANNEL OS1 configuration), only 12% (7% for channel OS1 and 16% for OS2) of the upsets had a code error magnitude greater than ALoWs -4 480, which equates to ±60 mV or ±3% of full scale. Some of 5.88 x 10 0351.8 the events had very large magnitude errors and during some events, the Output Code hit 0 or full scale. A histogram of To determine if the input circuits and DACs would have an the error magnitudes for one ion run is shown in Fig. 10. The impact on the Output Code SEU cross section, another DUT magnitudes of errors were independent of LET down to 20 2 (CDS4) was tested in a simulated CDS mode with a 1.25 V MeV-cm /mg. Below that LET, the maximum error input and 2.2 V reference as described above. The DACs magnitude decreased with decreasing LET. Channel OS1 were enabled and disabled for different ion runs (see Table III Output Code SEU cross section vs. LET is plotted in Fig. 11 for settings). Due to the noisier outputs and the greater Even for all errors greater outside with magnitude greater than ±25 and Odd offsets, the Output Code error limits were set to and ±480. ±480. The SET cross sections with the simulated CDS input A Weibull fit is shown for all errors greater than ±25 and (1.25 V Input) are compared those with the floating inputs in the Weibull parameters are listed in Table VIII. An LETth Fig. 12. The only configuration setting that appears to have a was not determined as SEUs were detected at the lowest LET 2 significant impact on SEU cross section is the PGA gain. It tested, 0.89 MeV-cm /mg. was set at 4 for OS2 with floating inputs. For all other test conditions, PGA gain was either 0.7 or 1 (Table III). 10000

8000 1.E-03

6000

4000 1.E-04 ) 2 2000

0 1.E-05 1 60 119 178 237 296 355 414 473 532 -2000 No Input; Gain = 4

Code Error Magnitude Error Number 1.E-06 No Input; Gain = 1 -4000

Cross Section (cm 1.25 V Input; DAC Off -6000 1.25 V Input; DAC On 1.E-07 -8000 0 20 40 60 80 100 120 LET (MeV-cm2/mg) Fig. 10. Histogram of the Output Code error magnitude for DUT CDS1, Fig. 12. Output Code SEU vs. LET for different operating conditions. See channel OS2 during a xenon ion run (LET=87.8 MeV-cm2/mg) taken to a TABLE III for details. fluence of 9.5 x 105 ions/cm2. The average output code was 6444, so that the maximum error magnitude would be -6444 to 9940. Both the 0 and full scale rails were hit. VI. CONCLUSION

A complex, mixed-signal SOC presents many challenges 1.E-03 for SEE characterization. One test system may not be sufficient for monitoring the different types of single event 1.E-04 effects. Modifications to the LM98640QML evaluation boards allowed for a comprehensive SEE characterization. ) 2 The LM98640QML was immune to the hard SEEs, those 1.E-05 requiring the part to be reset. Most events lasted less than 6 Error magnitude > +/- 25 pixel cycles, which is sufficient for most imaging systems as Error magnitude > +/-480 Weibull Plot the errors can be averaged out. 1.E-06 The characterization indicated that the input stage of the

Cross Section (cm LM98640QML, mainly the sample and hold and the offset DACs, were relatively SEE immune. This was not 1.E-07 unexpected as these are mostly switched capacitor and resistor 0 20 40 60 80 100 120 ladder structures. The internal gaining of the input signal LET (MeV-cm2/mg) could significantly increase the Output Code SEU cross section. Fig. 11. Output Code SEU vs. LET for channel OS1 of DUT CSD1 for all events recorded (diamonds) and for just those events were the code error magnitude was greater than ±480 which equates to ±60 mV or ±3% of full scale (triangles).

VII. REFERENCES [1] “LM98640 QML Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS”, May 10, 2010, National Semiconductor, Santa Clara, California http://www.national.com/pf/LM/LM98640QML.html [2] “CCD University, Correlated Double Sampling”, Apogee Instruments, Inc., Roseville, California, http://www.ccd.com/ccd107.html [3] “Correlated double sampling”, Alireza Moini, Centre for High Performance Integrated Technologies and Systems (CHIPTEC), University of Adelaide, Australia http://www.iee.et-tudresden.de/iee/analog/papers/mirror/visionchips/ vision_chips/aps_cds.html49 [4] “Test Procedures for the Measurement of Single-Event Effects in Semiconductor Devices from Heavy Ion Irradiation”, EIA/JEDEC Standard, EIA/JESD57, JEDEC, Arlington, Virginia http://www.jedec.org/download/search/jesd57.pdf [5] “Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices”, ASTM F1192, ASTM International, West Conshohocken, Pennsylvania http://www.astm.org/Standards/F1192.htm [6] “Single Event Effects Test Method and Guidelines”, ESCC Basic Specification No. 25100, European Space Agency, Paris, France https://escies.org/ReadArticle?docId=229 “LM139A/LM139QML Low Power Low Offset Voltage Quad Comparators”, National Semiconductor, Apr. 2, 2008, http://www.national.com/ds/LM/LM139A.pdf [7] “LM98640QML Evaluation Board User’s Guide”, September, 2009, National Semiconductor, Santa Clara, California, http://www.national.com/pf/LM/LM98640QML.html#Boards [8] Lawrence Berkeley National Laboratory website http://cyclotron.lbl.gov/ [9] ”Reliability and Risk Analysis”, N. J. McCormick Academic Press, NY, NY 1981

Single Event Latchup (SEL) and Total Ionizing Dose (TID) of a 1 Mbit Magnetoresistive Random Access Memory (MRAM)

Jason Heidecker, Gregorry Allen, Member, IEEE, Douglas Sheldon, Member, IEEE

current pulses are passed through a digit line and a bit line, Abstract—A 1 Mbit MRAM, a nonvolatile memory that uses writing only the bit at the cross point of those two lines [2]. magnetic tunnel junction (MJT) storage elements, has been During the read operation, the target bit’s isolation transistor characterized for total ionizing dose (TID) and single event is turned on to bias the MTJ, and the resulting current is latchup (SEL). Our results indicate that these devices show no compared to a reference to determine if the resistance state is 2 single event latchup up to an effective LET of 84 MeV-cm /mg low or high. This is shown (where our testing ended) and no bit failures to a TID of 75 krad in Fig. 2. (Si).

I. INTRODUCTION

AGNETORESISTIVE random access memory (MRAM) is Ma nonvolatile memory in which the storage element is a magnetic tunnel junction (MJT). These devices are inherently immune to single event upset (SEU) and have been found to Sense Layer 2 be latchup free up to an effective LET of 84 MeV-cm /mg Tunnel Layer (the maximum LET tested) and operational to a TID of 75 krad (Si). Reference Layer Results presented here are for the 1 Mbit device from Everspin Corporation that utilizes a 1-transistor, 1-MJT bit storage element that operates in “toggle” mode. Toggle mode

MRAM uses the exact same pulse sequence to write a “0” or “1” and is not susceptible to the single-line disturb phenomenon that previous MRAM technologies suffered. The MJT storage elements are created during backend Fig. 1. Cross-section of magnetic tunnel junction structure used to store process steps between the last two metallization layers. MJTs memory bit in 1 Mbit MRAM [3]. are material stacks consisting of a fixed magnetic layer, a thin dielectric tunnel barrier and a free magnetic layer as shown in Fig. 1. The magnetic field of the free layer can be oriented either in the parallel or anti-parallel direction to that of the pinned layer. Parallel programmed cells exhibit relatively less resistance than that of an anti-parallel programmed cells. Experimental results have documented magnetoresistive changes from 20% to 50% [1]. During the write operation,

Manuscript received July 12, 2010. The research in this paper was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under contract with the National Aeronautics and Space Administration (NASA). Copyright 2010 California Institute of Technology. Government sponsorship acknowledged. J. L. Heidecker is with the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA 91109 (telephone: 818-393-7567, e-mail: [email protected]). G. R. Allen is with the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA 91109 (telephone: 818-393-7558, e-mail: [email protected]). D. J. Sheldon is with the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA 91109 (telephone: 818-353-5113, e-mail: Fig. 2. Schematic operation of 1-transistor, 1-MJT memory cell [3]. [email protected]).

front of the DUT in order to approximate a thermal equilibrium for the die. Custom JDI ATV software was developed to fully functionally exercise the device. The test procedure was as follows: 1. Power-up the device and heat it to 100°C. 2. Perform March X test to verify functionality. 3. Fill the DUT with ‘all ones’ pattern. 4. Begin a constant read loop of the entire device. 5. Irradiate the DUT to 1x107 ions/cm2. 6. Stop the read and repeat March X test. 7. Repeat. Functional testing involved performing a March X test [4] on the entire array before and after irradiation. Prior to irradiation each device was filled with logic ‘1’ which was then read out in a constant loop during irradiation. Summary of ion beams used for SEL testing is given in Table 1.

Fig. 3. A 1 Mbit MRAM die packaged in a 40-pin dual-in-package (DIP) for SEL testing (top) and thin-small-outline-package (TSOP) for TID testing TABLE I (bottom). ION BEAMS USED FOR SEL TESTING. NO LATCHUP WAS OBSERVED DURING ANY TESTING. Run II. EXPERIMENTAL PROCEDURE Run Energy Energy Time # Device (MeV/AMU) (MeV) Ion Eff. LET (s) Fluence A. Tester Used 1 1 25 1766 Kr 21.2 177 2.0E+05 All testing of the 1 Mbit MRAM was done with the JD Instruments’ Automated Test Vector (ATV) digital memory 2 1 25 1766 Kr 21.2 242 3.0E+06 tester. 3 1 25 1766 Kr 21.2 45 5.0E+06 4 1 25 313 Kr 39 54 5.0E+06 B. Single Event Latchup Test Setup and Procedure 5 1 25 1077 Xe 56 51 5.0E+06 SEL testing was performed at the Texas A&M cyclotron 6 2 25 1077 Xe 56 61 5.0E+06 on three devices up to an LET of 84.1 MeV-cm2/mg. Device 7 2 25 1077 Xe 56 62 5.0E+06 under test (DUT) was Everspin 1 Mbit MRAM, MR0A08B 8 2 15 2429 Au 84.1 89 1.0E+07 (128k x 8-bit) built on a 130 nm commercial CMOS process. 9 3 15 2429 Au 84.1 79 1.0E+07 The devices were biased to 3.63 volt V and heated to a DD 10 4 15 2429 Au 84.1 54 1.0E+07 nominal temperature of 100°C. The DUTs were acquired as bare die in order to avoid having to remove the mu layer that C. March X Test for Functionality is on top of the packaged device. Bare die was necessary in The March X is one of many memory tests designed to order to have enough remaining ion range to perform the SEL uncover a variety of faults (MATS+, March B, March C, test. For the SEL test, the die were packaged in custom 40- March G, March RAW, to name just a few). The March X pin ceramic packages as shown in Fig. 3. was chosen based on its high level of fault coverage and ease An HP6629A power supply was used to power the core of programming [4]. It is formally written as: supply the DUT. The JDI ATV was placed in the beam room {Ú(w0); ×(r0, w1); Ø(r1, w0); Ú(r0)} and interfaced to the control laptop in the user room via a This involves doing the following operations to the entire USB extension cable. The 6629A was placed in the beam memory array: write 0 with up addressing order; read 0 and room and controlled via a GPIB interface to a laptop running write 1 with up addressing order; read 1 and write 0 with custom Visual Basic software. The software monitored and down addressing order; and finally read 0 with up addressing strip-charted the voltage and current of the DUT. If a current order. reading beyond the predefined threshold was read, the software will power cycle the DUT and increment the SEL D. Total Ionizing Dose Test Setup and Procedure count. TID testing was done on three samples of Everspin Although the DUT was powered to the specified maximum PR0A08BCYS35 (128k X 8) in TSOP package at the JPL voltage of 3.63 V, the inputs were driven from the JDI ATV HDR Co-60 facility, which is compliant to MIL-STD-883, at 3.3 V. A common ground was shared between the JDI Method 1019. For the first sample, electrical measurements ATV and HP 6629A. The DUT was heated to a nominal were made at 0, 25, 50, 70, 80, 90, 100, 110, 120, 130, 140, temperature of 100°C via an electric heater strip placed on the and 150 krad. The two subsequent samples were tested at 0, back of the ceramic package and a heat gun blowing on the 50, 75, 90, 105, 120, 135, and 150 krad. The dose rate was front of the die. Thermocouples were placed behind and in 25 rad/second, and the device was statically biased to

nominal voltage levels and tested at room temperature. Bias At 100 krad all VOL measurements failed the nominal conditions are given in Table II. specification limit of 1.5 V. This phenomenon was observed TABLE II in all DUTs and shown in Fig. 5: DUT BIAS CONDITIONS USED IN TID TEST. “PULL DOWN” OR “PULL UP”

MEANS 1 KΩ RESISTOR BETWEEN PIN AND EITHER GROUND OR VDD. MRAM Pin Bias Condition Address[0:7] Pull Down Chip Enable (/E) Pull Up Write Enable (/W) Pull Up Output Enable (/G) Pull Up Upper Byte Select (/UB) Pull Up Lower Byte Select (/LB) Pull Up Data[0:7] Pull Up

Power Supply (VDD) 3.3V Ground (VSS) GNGND

Prior to any irradiation, a checkerboard pattern was written to half of the memory, that half remained as read-only for Fig. 5. VOL as a function of TID. duration of testing. The memory was then irradiated to the dose steps as defined above. After eacch dose step the The device passes parametric tests out to 100 krad and checkerboard pattern was read from the read-only portion of appears to be fully functional up to 75 krad (Si). This is the the DUT. A write zero-read zero, write ones-read ones, and point where functional failures began to occur (bit errors March X test was then performed on the other half of the observed). Bit error data for write1/read1 and write0/read0 is device, followed by the parametric measurements including: given in Fig. 6-7: VOH, VOL, VIH, VIL, IIL, and IIH.

III. RESULTS A. Single Event Latchup The 1Mbit MRAM shows no single event latchup up to an effective LET of 84 MeV-cm2/mg, where testing ended. No latchup was observed at any fluence. Testing ending with a total fluence of 1x107 ions/cm2 subjected to each of the three devices. Functional testing was performed before and after each irradiation, and no degradation was observed. Functional testing involved performing a March X test on the entire array before and after irradiation. Prior to irradiation each Fig. 6. Write Zeros, Read Zeros as a function of TID. device was filled with logic ‘1’ which was then read out in a constant loop during irradiation. B. Total Ionizing Dose

Static IDD remained constant at 30 mA until approximately 100 krad when it doubled to 60 mA as shown in Fig. 4. This happened at approximately the same dosage level for all devices tested.

Fig. 7. Write Ones, Read Ones as a function of TID.

A small “baseline” level of bit errors was observed in the devices even prior to irradiation. This is suspected to be the result of using unscreened, prototype-quality devices.

Fig. 4. Static IDD as a function of TID.

IV. CONCLUSIONS The 1 Mbit MRAM has been characterized for SEL and TID performance. The 1 Mbit MRAM memory cells are inherently immune to single event upset (SEU) due to the structure and materials used to make them. It has also been observed in our testing that they are latchup free to an effective LET of 84 MeV-cm2/mg, the maximum LET at which our testing ended. Latchup immunity is most likely the result of design changes as well as adding an epitaxial layer when the manufacturer moved from a 150 nm to 130 nm process. As for TID response, the device was operational to a TID of 75 krad (Si).

V. ACKNOWLEDGMENT The research in this paper was carried out by the Jet Propulsion Laboratory, California Institute of Technology, under contract with the National Aeronautics and Space Administration. Copyright 2010 California Institute of Technology. Government sponsorship acknowledged.

Special thanks to Everspin Corporation for test samples and support.

VI. REFERENCES [1] J. M. Slaughter, E. Y. Chen, R. Whig, B. N. Engel, J. Janesky, and S. Tehrani, “Magnetic Tunnel Junction Materials for Electronic Applications,” Member J. Minerals, Metals Materials Soc., Jun. 2000. Electronic supplement. [2] M. Durlam, P. Naji, M. DeHerrera, S. Tehrani , G. Kerszykowski, K. Kyler, “Nonvolatile RAM Based on Magnetic Tunnel Junction Elements”, IEEE International Solid-State Circuits Conference, 2000. [3] Everspin Corporation. “MRAM Technical Guide,” http://everspin.com/. [4] A. J. Van de Goor, "Testing Semiconductor Memories," Theory and Practice, John Wiley and sons, Chichester, UK, 1991.

TID and SEE Responses of Rad-Hardened A/D converters

Géraldine Chaumont, André Uguen, Christophe Prugne, Florence Malou

Abstract-- We present Single Event Effects characterization II. TOTAL IONIZING DOSE and Total Ionizing Dose behaviour up to 300 krad(Si) on Rad- Hardened A/D converter. A. Experimental methods The high dose rate test has been performed at the Co60 I. INTRODUCTION CEA Saclay (France) source. HIS paper deals with the test setups to characterize the Radiation testing was done using the MIL-STD-883, Test TSEE and TID susceptibilities of the 12-bit A/D converter Method 1019.7 as a guide. The IC technology used for from STMicroelectronics, test results obtained and analysis of RHF1201 has already been demonstrated via characterization the result. This product, renowned for its excellent merit testing not to exhibit TDE changes. So no accelerated Speed annealing test has been done after the irradiation and the factor , is issued from a full CMOS technology, so extended room temperature anneal. Power During the RHF1201 QML-V qualification the worst case only High Dose Rate (HDR) test has been done. bias for irradiation has been determined (Figure 1) with AV The space flight community needs data of radiation effects CC = DV = V = V = 2.5V, Internal REFP & INCM, [1-2]. The test results presented here enrich the list of CC CC BE CC BI R = 12kΩ. Five parts have been irradiated. One part was candidate devices which may be used in space applications. POL kept as a reference. The main features of the RHF1201 are shown in the table I.

TABLE I RHF1201 ADC FEATURES

Fig. 1. Bias condition for RHF1201.

For the accuracy and the dynamic characteristics, the part has been tested at two different frequencies:

FS = 50Msps square, FIN = 15MHz,

FS = 5Msps square, FIN = 1MHz.

The electrical measurements have been done in the

Manuscript received August 03, 2010. differential input configuration (Figure 2). Géraldine Chaumont is with STMicroelectronics, 3 rue de Suisse, 35200 Rennes, FRANCE (telephone: 0033-299-264-966, e-mail: The HDR test was performed at 55 rad(Si)/s up to [email protected]). 300krad(Si). Intermediate measurements have been done at André Uguen is with STMicroelectronics, 3 rue de Suisse, 35200 Rennes, FRANCE (telephone: 0033-299-264-809, e-mail: [email protected]). 100 and 200 krad(Si). Christophe Prugne is with STMicroelectronics, 12 rue Jules Horowitz, 38000 Grenoble, FRANCE (telephone: 0033-476-585-965, e-mail: [email protected]). Florence Malou is with the Centre National d’Etudes Spatiales (CNES), 18 av. Edouard Belin, 31400 Toulouse, FRANCE (telephone: 0033-561-273- 262, e-mail: [email protected]).

Fig. 2. Differential input configuration.

Fig. 5. Differential Non Linearity @ FS=50Msps.

B. RHF1201 TID results Only the behavior of the main parameters of the RHF1201 will be shown in this study. All key parameters are within specifications after irradiation up to 300 krad(Si) + 24h anneal @ 25°C.

Fig. 6. Differential Non Linearity @ FS=5Msps.

Fig. 3. Analog supply current.

Fig. 7. SFDR @ FS=50Msps.

Fig. 4. Digital supply current.

Fig. 8. SFDR @ FS=5Msps.

Fig. 9. Signal to Noise Ratio @ FS=50Msps. Fig. 13. THD @ FS=50Msps.

Fig. 10. Signal to Noise Ratio @ FS=5Msps. Fig. 14. THD @ FS=5Msps.

Fig. 11. SINAD @ FS=50Msps. Fig. 15. ENOB @ FS=50Msps.

Fig. 12. SINAD @ FS=5Msps. Fig. 16. ENOB @ FS=5Msps.

III. SINGLE EVENT EFFECTS

A. Experimental methods

The Single Event Effects characterization of the RHF1201 has been performed at the UCL (Belgium). The Single Event Effects have been characterized at 125°C for Single Event Latch-up and Single Event Functional Interrupt and at room temperature for Single Event Transient and Single Event Upset. These tests were performed to a total fluence of not less than 1x107ion/cm² for SEL / SEFI and 1x106ions/cm² or until a statistically significant number of events were captured for Fig. 17. Offset Error @ F =50Msps. S SET / SEU.

The SEL / SEFI tests have been done at 125°C with a LETeff ≥ 111 MeV.cm²/mg. The ions cocktails used for SET / SEU characterization is shown in the table II. The SEL / SEFI characterization has been done at the maximum supply voltages. The SET / SEU characterization has been done at the minimum supply voltages.

TABLE II IONS USED FOR THE SET/SEU TESTS

Fig. 18. Offset Error @ FS=5Msps.

B. RHF1201 SEE characterization

Neither SEL nor SEFI have been detected up to a LET of 111MeV.cm²/mg at 125°C and a fluence of 1x107ions/cm² on the RHF1201. Some SETs have been detected on the voltage reference pin. These events have generated a large number of Fig. 19. Gain Error @ FS=50Msps. conversions errors in a short lapse of time. The figure 19 shows the SEU cross-section per device for RHF1201. Following is the key information of this characterization:

-4 σsat = 3.5x10 cm²/device at 111MeV.cm²/mg

Fig. 20. Gain Error @ FS=5Msps.

Fig. 21. SEU cross-section/device

IV. CONCLUSION The STMicroelectronics A/D convert RHF1201 has been TID and SEE characterized. All parameters are within specifications after 24h anneal @ 25°C up to 300 krad(Si) at high dose rate.. The RHF1201 is also SEL / SEFI immune for LET ≤ 111 MeV.cm2/mg at 125°C. The SET / SEU have been characterized.

V. REFERENCES [1] D.J. Cochran, et al., “Compendium of Recent Total Ionizing Dose Results for Candidate Spacecraft Electronics for NASA”, IEEE NSREC 2008 Data Workshop, pp. 5-10, Jul. 2008. [2] M.V. O’Bryan, et al., “Compendium of Recent Single Event Effects Results for Candidate Spacecraft Electronics for NASA”, IEEE NSREC 2008 Data Workshop, pp. 11-20, Jul. 2008. Total Dose and Single Event Testing of a Hardened Point of Load Regulator

N. W. van Vonno (Senior Member, IEEE), L. G. Pearce, J. S. Gill, H. W. Satterfield, E. T. Thomson, T. E. Fobes, A. P. Williams and P. J. Chesley Intersil Corporation, Melbourne, Florida

ABSTRACT - We report the results of total dose and single-event effects testing of the ISL70001SRH hardened AVDD AGND DV DD DG ND EN point of load (POL) voltage regulator and discuss part POWER- ON PORSEL design, performance and applications. The part is RE SET (POR ) implemented in a submicron BiCMOS process and uses PVINx integrated power MOSFET switching transistors. CURRENT SE N S E SLOPE SS SOFT START COMPENSATION PWM Index Terms — Integrated circuits, power management, EA GM CONTROL GATE LXx FB LOGIC DRIVE power MOSFET, radiation hardening, single-event effects.

COMPENSATION

PGNDx I. INTRODUCTION UV he ISL70001SRH is a high efficiency monolithic PGOOD POWER-GOOD

synchronous buck regulator with integrated power PWM TDI REF REFERENCE BIT T 0. 6 V TDO MOSFET devices, eliminating the need for external

MOSFET devices. The part is designed for point of load TRIMTR IM ZAP

(POL) power management applications for complex digital SYNC parts such as programmable gate arrays (FPGA), memories M/S and logic arrays in space-qualified systems. The greatly increased use of these devices and their unique low Fig. 1: ISL70001SRH block diagram. Note the six switching power voltage, high current power requirements has profoundly MOSFET blocks driven in parallel by the gate drive function. changed power management approaches. The ISL70001SRH is designed and rated for the total dose and single-event effects environments and is manufactured and II. INTEGRATING THE POWER MOSFET: qualified in compliance with MIL-PRF-38535 (QML). It ISL70001SRH PROCESS AND DESIGN operates over an input voltage range of 3 V to 5.5 V and The ISL70001SRH is fabricated on a 0.6 µm BiCMOS provides a regulated output voltage that is externally junction isolated process optimized for power management adjustable from 0.8 V to ~85% of the input voltage. The applications. The process uses three layers of analog- output load current capacity is 6 A for junction o compatible interconnect metal, which is a necessity for temperatures up to +125 C. The ISL70001SRH utilizes integrated power MOSFET applications. Active devices peak current mode control and switches at a fixed include low voltage CMOS and high voltage DMOS devices frequency of 1 MHz. The high level of integration provided as well as complementary bipolar transistors. The process is by integrating the power MOSFET devices makes the part in volume production under MIL-PRF-38535 certification a logical choice for powering small form factor and is used for a wide range of commercial power applications in space systems. The POL function is a very management devices. In order to retain the advantages of this demanding application, and primary tradeoffs include volume production base, the ISL70001SRH was designed for efficiency, regulation, current capacity, thermal total dose and SEE hardness using well-known ‘hardened by considerations, form factor, cost and radiation hardness. design’ methodologies, including closed geometry N-channel devices, guard rings and latchup-prevention layout techniques. The 14 nm gate oxide shows excellent total dose Manuscript received 19 July 2010. hardness to 300 krad(Si). The ISL70001SRH is hardened by design for a total ionizing dose (TID) rating of 100 krad(Si) N. W. van Vonno, L. G. Pearce, J. S. Gill, H. W. at 50-300 rad(Si)/s as well as the standard < 10 mrad(Si)/s Satterfield, E. T. Thomson, T. E. Fobes, A. P. Williams low dose rate. Total dose testing has shown good results to and P. J. Chesley are with Intersil Corporation, Specialty 150 krad(Si) at high and low dose rate, with no dose rate Products, Palm Bay, FL 32905, USA. sensitivity as discussed below.

978-1-4244-8404-1/10/$26.00 ©2010 IEEE Latchup from either electrical or single-event causes is or bias sensitivity. The part is considered free of ELDRS a key issue, and latchup suppression was assured through and bias effects to its specified 100 krad(Si) rating. well-known techniques such as guard rings and N- and P- channel devices in separate isolation regions. Single-event 0.606 transients (SETs) have turned into a major consideration in High dose rate, grounded POL regulators, as even a short-term overvoltage at the 0.604 High dose rate, biased regulator output can result in immediate, destructive Low dose rate, grounded damage to sensitive loads such as processors or FPGA 0.602 Low dose rate, biased devices. SET hardening of the ISL70001SRH was carried out at the architectural as well as the gate level by the use 0.6 of redundancy, large device geometries and filtering, and

SET hardness was assured by rigorous circuit simulations Reference voltage, V 0.598 and extensive SEE testing. The balance of this paper discusses the results of total dose and single-event effects 0.596 testing of the part. 0.594 0 25 50 75 100 125 150 III. TOTAL DOSE TESTING OF THE ISL70001SRH Total dose, krad(Si) High dose rate testing of the part was performed using a 60 Fig. 2: ISL70001SRH reference voltage as a function of total dose Gammacell 220 Co irradiator located in the Palm Bay, irradiation at low and high dose rate for the unbiased and biased cases. The Florida Intersil facility. Low dose rate testing was carried SMD limits are 0.594 – 0.606 V. out in the same facility using a J. L. Shepherd and 60 Associates (JLS) model 484 low dose rate Co irradiator. 0.25 The high dose rate irradiations were carried out at 55 0.2 High dose rate, grounded High dose rate, biased rad(Si)/s and the low dose rate work was performed at .010 0.15 Low dose rate, grounded rad(Si)/s, both per MIL-STD-883 Test Method 1019. 0.1 Low dose rate, biased

Dosimetry for both tests was performed using Far West 0.05 Technology radiochromic dosimeters and on-site readout 0 equipment. A PbAl box was used to shield the test fixture -0.05 and samples against low energy secondary radiation. -0.1

uA current, bias pin Feedback The experimental matrix was configured per the Method -0.15 1019 diagnostic procedure for low dose rate sensitivity. A -0.2 total of 21 samples drawn from preproduction lots were -0.25 0 25 50 75 100 125 150 used; five were irradiated at low dose rate under bias, five Total dose, krad(Si) were irradiated at low dose rate with all pins grounded, five were irradiated at low dose rate under bias and five were Fig. 3: ISL70001SRH feedback pin bias current as a function of total dose irradiated at low dose rate with all pins grounded. The irradiation at low and high dose rate for the unbiased and biased cases. The SMD limits are -1 to 1 µA. samples were processed through the standard burnin cycle before irradiation and were screened to the SMD 5962- 0.4 09225 limits at room, low and high temperature. The configuration used for biased irradiation was in 0.3 conformance with the SMD. Downpoints were 10 krad(Si), 0.2 25 krad(Si), 50 krad(Si), 100 krad(Si) and 150 krad(Si). Both the high and low dose rate tests of the ISL70001SRH 0.1 are complete and showed no reject devices after irradiation, 0 screening to the SMD pre-irradiation limits. For this part, High dose rate, grounded the post-irradiation limits are the same as the pre-irradiation uA leakage, LX1 -0.1 High dose rate, biased Group A specification limits for all parameters. -0.2 Low dose rate, grounded

Low dose rate, biased The ISL70001SRH is a complex part with some 250 -0.3 datalogged parameters. The plots in Figures 2 through 11 -0.4 show data for selected key parameters at all downpoints. 0 25 50 75 100 125 150 The plots show the median as a function of total dose for Total dose, krad(Si) each of the irradiation conditions; we elected to use the Fig. 4: ISL70001SRH LX1 LOW leakage current as a function of total sample median as an indicator due to the relatively small dose irradiation at low and high dose rate for the unbiased and biased cases. sample size involved. All samples showed excellent stability The SMD limit is -1 µA maximum. over irradiation, with no observed low dose rate sensitivity 0.5 240

High dose rate, grounded 0.4 220 High dose rate, grounded High dose rate, biased High dose rate, biased 0.3 Low dose rate, grounded 200 Low dose rate, grounded

0.2 Low dose rate, biased Low dose rate, biased 180

0.1 160 0 140 -0.1 LX1 Low leakage, uA leakage, Low LX1 120 -0.2

Average lower FET ON resistance, mohm FET ON resistance, lower Average 100 -0.3

-0.4 80 0 25 50 75 100 125 150 0 255075100125150 Total dose, krad(Si) Total dose, krad(Si)

Fig. 5: ISL70001SRH LX1 HIGH leakage current as a function of total Fig. 8: ISL70001SRH average lower (N-channel) FET Rds(ON) resistance dose irradiation at low and high dose rate for the unbiased and biased cases. as a function of total dose irradiation at low and high dose rate for the The SMD limit is 15 µA maximum. unbiased and biased cases. The SMD limit is 77 – 236 milliohms.

1150 340

320 High dose rate, grounded

1100 High dose rate, biased 300 Low dose rate, grounded 280 1050 Low dose rate, biased 260

1000 240

220 High dose rate, grounded 950 200 High dose rate, biased Average oscillator frequency, KHz frequency, oscillator Average Low dose rate, grounded 180

900 mohm ON FET upper resistance, Average

Low dose rate, biased 160

850 140 0 25 50 75 100 125 150 0 25 50 75 100 125 150 Total dose, krad(Si) Total dose, krad(Si)

Fig. 6: ISL70001SRH average oscillator frequency as a function of total Fig. 9: ISL70001SRH average upper (P-channel) FET Rds(ON) resistance dose irradiation at low and high dose rate for the unbiased and biased cases. as a function of total dose irradiation at low and high dose rate for the The SMD limits are 850 – 1150 KHz. unbiased and biased cases. The SMD limit is 122 – 346 milliohms.

1.5

36 High dose rate, grounded 1 High dose rate, biased 34 Low dose rate, grounded 0.5 Low dose rate, biased 32

0 30

High dose rate, grounded -0.5 28 High dose rate, biased Operating current, 4.15V, mA 4.15V, current, Operating Low dose rate, grounded -1

26 mV supply, high voltage, offset amplifier Error Low dose rate, biased

-1.5 24 0 25 50 75 100 125 150 0 25 50 75 100 125 150 Total dose, krad(Si) Total dose, krad(Si) Fig. 10: ISL70001SRH error amplifier offset voltage (high supply) as a Fig. 7: ISL70001SRH operating current at 5.5V supply voltage as a function of total dose irradiation at low and high dose rate for the function of total dose irradiation at low and high dose rate for the unbiased unbiased and biased cases. Error amplifier offset voltage is an and biased cases. The SMD limit is 65 mA maximum. informational parameter and is not formally specified.

0.81 45 8 units 10 units 40 0.805 Tcase = 125ºC 35 Vout=1.8V, Iout=7A 0.8 30 Ag@60º = 86.4 MeV/(mg/cm2) 25 0.795 Pass Fail 20 41 40

Output voltage, V voltage, Output High dose rate, grounded 0.79 15 4 2 units High dose rate, biased 4 units 10 Low dose rate, grounded 8 4 units 0.785 14 6 2 units Low dose rate, biased 5 10

Total Effective FluenceTotal (Mp/cm^2) 4 2 4 0.78 0 0 25 50 75 100 125 150 5.50 5.60 5.70 5.80 5.90 6.00 Total dose, krad(Si) Input Voltage, Vin (V) Fig. 11: ISL70001SRH output voltage (low supply) as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. Fig. 12: SEL/SEB/SEGR testing summary for the ISL70001SRH point of The SMD limits are +/-2%, which equals 0.784 to 0.816 V. load converter. Samples were tested at high temperature and output current and at increasing input voltage until failure occurred. Samples were taken from three ISL70001SRH fabrication lots. The horizontal axis shows the input voltage to the device under test. The vertical axis shows the total IV. SEE TESTING OF THE ISL70001SRH fluence at each input voltage level, while pass/fail results are indicated by Single-event testing of the ISL70001SRH was carried blue and red fill, respectively. out during three 2009 testing campaigns at Texas A&M. Partial support of this work under the NASA/GSFC NEPP program is gratefully acknowledged. SEL susceptibility and First, several ISL70001SRH devices were neutron- SET performance were characterized; in addition, as the irradiated on a diagnostic basis to a fluence of 1 x 1012 power MOSFET devices are integrated, their SEB and n/cm2 at White Sands Missile Range (WSMR). Neutron SEGR response had to be determined as well. irradiation causes displacement damage and reduced minority carrier lifetime, which in turn will reduce the gain of parasitic bipolar devices in the substrate that are the root A. SEL/SEB/SEGR Testing cause of SEB. This BJT gain degradation would be expected to lower SEL/SEB sensitivity but have no effect on SEGR. For these tests, conditions were selected to maximize the SEL/SEB/SEGR testing of the neutron-irradiated devices at electrical and thermal stresses on the device under test TAMU showed marginal improvement of the maximum (DUT), insuring a worst-case environment. Input voltage input voltage (VIN). As a second experiment, several (VIN) was used as the independent variable; it was initially ISL70001SRH samples were fabricated using a thicker gate set to 5.5 V, the recommended operating supply voltage oxide (170 Å vs. 140 Å). SEL/SEB/SEGR testing of these rating, and then increased in 0.1 V increments above that samples at TAMU showed an increase from 5.7 V to 6.1 V value. Output voltage (VOUT) was set to 1.8 V. Output in the maximum input voltage. current (IOUT) was set to 7 A, which is 1 A above the 6 A current rating for the device. Case temperature was The results of these two experiments implicate SEB of maintained at 125 ºC. This insured that the junction the output NMOS power FET as the likely failure temperature of the DUT was well in excess of 125 ºC, which mechanism. The evidence is not considered conclusive; the is the maximum anticipated junction temperature. Samples experimentally obtained 5.7 V to 6.1 V maximum input from three fabrication lots were irradiated with Ag ions at a voltage range is in quite good agreement with published 60-degree incident angle, resulting in an effective LET of SEGR predictions [1 - 3] for the 140Å gate oxide used in the 86.4 MeV/mg/cm2. Figure 12 summarizes the results of ISL70001SRH process, but further work remains to be done. SEL/SEB/SEGR testing in bar chart format. Additional SEE testing using Au ions at an LET of 86.4 MeV/mg/cm2 and zero degrees is planned, as the normal The criterion for failure was a greater than 5% increase incidence to the chip surface is considered worst-case for in the no-load operating input current. Failed devices were SEGR. not further irradiated. Failure analysis of three failed samples revealed damage to the output NMOS device, but a root cause of failure determination proved elusive as the failure signatures of SEL, SEB and SEGR can appear quite similar. To assist with root cause identification, two additional experiments were performed. C. SET Testing of Hardened Devices at 5.5V B. Baseline SET Testing of Unhardened Parts Next, seventeen unmodified ISL70001SRH samples

were irradiated under the test conditions shown in Table 1, Analog SET is a key issue in this application, as the low below. The beam used Ag ions at 0 degree incident angle, voltage, high current loads being driven are sensitive to resulting in an LET of 43.2 MeV/mg/cm2. For these tests, even short-term overvoltage conditions. To better assess the samples were operated at input voltage of 4.5 to 5.5 V, effectivity of the SET hardening efforts carried out during output current of 4 A and output voltage of 1.8 V. the design process, an ISL70001SRH chip was modified by focused ion beam (FIB) techniques to disable two of the Table I: ISL70001SRH SET tests. three redundant PWM control loops. This “nonhardened” part was then irradiated at an LET of 43.2 MeV/mg/cm2. Samples Fluence Runs Total fluence The test configuration used VIN = 5 V, VOUT = 1.8 V and 4 6 2 IOUT = 4 A; the flux was 1.82 x 10 to 3 x 10 ions/cm /s 6 7 2 and the total fluence was 3 x 106 ions/cm2. 11 4.5 x 10 15 6.75 x 10 ions/cm 5 4.5 x 106 5 2.25 x 106 ions/cm2 1 4.1 x 107 1 4.1 x 107 ions/cm2

During these extensive SET tests, a total of 11,530 events were captured for a combined fluence of 1.31 x 108 ions/cm2. Fig. 14 shows a benign SET that was representative of 99.5% of the events encountered. The remaining events were non-benign and took several forms, one of which is shown in Fig. 15. These non-benign events showed a strong flux dependence, which suggested they may have resulted from double ion strikes affecting the redundant PWM control loops and were hence artifactual.

Fig. 13: Worst case pulse width (∆PW) SET in a baseline ‘nonhardened’ ISL70001SRH with its PWM loop redundancy disabled through FIB modifications. The lower trace shows five full-width LX pulses. The upper trace (VOUT) shows a 20% increase in VOUT, which would be expected to cause immediate, destructive damage in an actual application. The horizontal axis is calibrated in 2 microseconds per division.

Testing of this modified ISL70001SRH sample produced a total of 211 pulse width change (∆PW) SETs, 260 pulse period change (∆T) SETs and 21 PGOOD logic SETs, with cross-sections of approximately 7 x 10-5 cm2, 8.7 x10-5 cm2 and 7 x 10-6 cm2, respectively. The best case SET observed resulted in two double-width LX pulses and an output voltage perturbation of ~5%. The worst case SET is shown in Fig. 13; it resulted in five full-width LX pulses and an output voltage perturbation of ~20%; this would be expected to cause immediate and destructive damage in an Fig. 14: Typical benign pulse width SET event at LET of 43 MeV/mg/cm2, unmodified ISL70001SRH device. The lower trace shows the LX pulses as actual power supply application. Clearly, SET hardening of the regulator switches the input power on and off; this pulse train will be the part must be addressed to provide predictable and reconstructed into DC by the output LC lowpass function. The upper trace reliable performance in the space environment. represents the DC output voltage of the converter. The SET is seen in the slight widening of the LX pulse just before the t=0 mark. The effect of the SET event on the DC output voltage is less than 1%.

1.0 0.9 0 from 4 x 1.1e7 p/cm2 (each stripe) 0.8 0.7 93 from 4 x 1.45e7 p/cm2 0.6 0.5 5V CLP Stripes LET=86 0.4 5V CLP Open LET=86 0.3 0.2

Normalized Probability Density0.1 0.0 0.0E+00 5.0E-07 1.0E-06 1.5E-06 2.0E-06 Estimated X-Section (Binomial Distribution, cm2)

Fig. 16: Summary of SET tests of shielded samples. The figure plots the probability density as a function of cross-section for shielded and unshielded parts. ‘Stripes’ refers to the shielded samples, while ‘Open’ Fig. 15: Disruptive pulse width SET event, also at LET of 43 refers to unshielded ones. MeV/mg/cm2. The lower trace shows six wide pulses followed by recovery (off-screen) of the DC-DC converter. The upper trace represents the DC output voltage; the effect of the SET event on the DC output voltage is D. SET Testing of Hardened Parts at 3 V about 90mV. This SET signature showed strong flux dependence, suggesting double ion events in the PWM control loop. Following the 4.5/5.5 V input test runs, eighteen additional ISL70001SRH devices were irradiated at an input Follow-up SET testing was carried out to validate the voltage of 3 V under test conditions otherwise similar to theory that the non-benign SET events seen during baseline those used before. During the 3 V SET tests, a total of 20,083 SET testing were the result of very high flux test rates that events were captured, including some SEFI signatures that would not be encountered in a natural space environment. If had not been seen at 4.5/5.5 V. The vast majority (19,848) of the flux is high enough, it is likely that two of the three the SET events were benign single pulse events, resulting in redundant PWM control loops would receive an ion strike slightly lengthened or shortened LX pulses and less than 1% within a short interval of time. If that interval of time is less perturbation of VOUT. The remaining events (about 1.2%) than the recovery time (which can be up to 1 ms) of a were non-benign, and showed a strong flux dependence as redundant PWM control loop, then the redundancy will be was seen during the baseline VIN = 5 V +/-10% SET testing. defeated and non-benign SETs could result. We then have a classical example of an excessively accelerated test driven into a nonlinear response range.

To validate this theory, four ISL70001SRH samples were prepared with two of the three redundant PWM control loops shielded using standard Kovar lid material shields. Three shield patterns were prepared by precision milling, covering two of the three redundant loops in turn. Four samples of each shielding pattern were prepared and tested for SET to a fluence of 1.1x107 ions/cm2. No disruptive SETs were captured during irradiation of these shielded samples using Ag ions at 60º incident angle, resulting in an effective LET of 86.4 MeV/mg/cm2. The composite of the 12 shielded units provides an aggregate exposure of the entire die to a total fluence of 4.4x107 ions/cm2. This result indicates that the redundant PWM control loop technique is highly effective in limiting SETs to less than a single LX Fig. 17: SEFI signature at 3 V supply. The functional interrupt results in a pulse disturbance and an output voltage (VOUT) controlled shutdown of the converter with no preceding transients. Switching perturbation of less than 1%. The results of these diagnostic terminates (both power FET’s are OFF), both PGOOD and SS reset, and the part proceeds through a normal soft start sequence (which is well beyond the tests are summarized in Fig. 16. time scale of this plot) without external intervention.

1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 5V, LET=86, 1/1.0e8, 8 0.2 3V, LET_eff=86, 18/2.2e7, 2

Normalized Probability Density 0.1 3V, LET_eff=61, 0/4.4e7, 4 3V, LET=43, 0/4.4e7, 4 0 0.0E+00 2.5E-07 5.0E-07 7.5E-07 1.0E-06 1.3E-06 1.5E-06 Estimated X-Section (Binomial Distribution, cm2)

Fig. 18: Summary of 3 V SEFI tests. The figure plots the probability of SEFI occurrence as a function of cross-section for four combinations of Fig. 20: Benign SET at 3 V supply and 43 MeV/mg/cm2, showing a LET and supply voltage. The phenomenon has a cross section of 7.6 x 10-7 lengthened LX pulse resulting in a positive output voltage perturbation of at 3 V and LET of 86 MeV/mg/cm2 and a near-zero cross section for the approximately 1%. The vast majority (99.8%) of the benign events at 3.0 V other three sets of conditions. The near-zero cross section curves coincide. displayed this signature. The SYNC and PGOOD waveforms are shown as well as the LX and output voltage waveforms. Figs. 19 and 20 show sample benign SET signatures at 3 V supply. The signature shown in Figure 19 accounted for the great majority (99.8%) of these events. In both V. CONCLUSION signatures the output voltage perturbation of the converter was less than 1%. We report the results of total dose and single-event testing of the ISL70001SRH point of load regulator. The results demonstrate the effectivity of the hardened by design approach used for the part.

Total dose testing was carried out at high and low dose rate per MIL-STD-883, under biased and unbiased conditions. The samples showed excellent stability through 150 krad(Si) at high and low dose rate. All samples met the SMD pre-irradiation limits after irradiation, indicating ELDRS-free performance in accordance with the criteria set forth in MIL-STD-883 Test Method 1019. No bias sensitivity was observed at either dose rate.

SEL/SEB/SEGR immunity was demonstrated to an effective LET of 86.4 MeV/mg/cm2 at an input voltage up to 5.7 V, an output current up to 7 A and a case temperature up to 125ºC. The redundant PWM control loop design was found to be effective in limiting SETs to less that one LX Fig. 19: Benign SET at 3 V supply and 43 MeV/mg/cm2, showing a pulse perturbation and less than 1% perturbation of the output shortened LX pulse resulting in a negative output voltage perturbation of less voltage to an LET of 86.4 MeV/mg/cm2. Various SET and than 1%. The SYNC and PGOOD waveforms are shown as well as the LX and output voltage waveforms. SEFI signatures were observed, including some consecutive long pulse events that were verified by shielding experiments to be double ion strike events. These double ion events are an interesting limitation of high-flux ion beam testing and are considered artifactual.

VI. REFERENCES

[1] Brews, J. R., Allenspach, M., Schrimpf, R. D. and Galloway, K. F., “A conceptual model of single-event gate rupture in power MOSFET’s”, IEEE Trans. Nuc. Sci., vol. 40, no. 6, pp. 1959 – 1966, December 1993.

[2] Titus, J. L. and Wheatley, C. F., “Experimental studies of single-event gate rupture and burnout in vertical power MOSFET’s”, IEEE Trans. Nuc. Sci., vol. 43, no. 2, pp. 533 – 544, April 1996.

[3] Sexton, F. W., Fleetwood, D. M., Shaneyfelt, M. R., Dodd, P. E. and Hash, G. L., “Single event gate rupture in thin gate oxides”, IEEE Trans. Nuc. Sci., vol. 44, no. 6, pp. 2345 - 2352, December 1997.

Total Dose and Single Event Testing of a Hardened Single- Ended Current Mode PWM Controller

N. W. van Vonno (Senior Member, IEEE), L. G. Pearce, G. M. Wood, J. D. White, E. J. Thomson, T. M. Bernard, P. J. Chesley and R. Hood Intersil Corporation, Melbourne, Florida

Abstract - We report results of total dose and SEE testing of the ISL7884xASRH hardened single-ended current mode PWM controller including discussion of part design, process and radiation testing results. The part is implemented in submicron BiCMOS.

Index Terms— Integrated circuits, power management, power MOSFET, radiation hardening, single-event effects.

I. INTRODUCTION he ISL7884xASRH is a high performance hardened Tdrop-in replacement for the commercial 28C4x and 18C4x PWM controllers. The part is suitable for a wide range of DC-DC power conversion applications including flyback, boost and isolated output configurations. Features include up to 13.2 V operation, low operating current, 90 µA typical startup current, adjustable operating frequency of up to 1 MHz and 1 Ampere peak MOSFET drive current capability with 50 ns rise and fall times. The product family consists of four variants with different undervoltage Fig. 1: ISL7884xASRH block diagram. lockout (UVLO) and duty cycle characteristics, as defined in Table I. The part is produced under MIL-PRF-38535 certification and detailed specifications are defined in II. ISL7884XSRH PROCESS AND DESIGN SMD 5962-07249. It is available in an 8-lead hermetic The ISL7884xASRH family is implemented in a flatpack and in die form. submicron BiCMOS process optimized for power management applications, with 0.6 µm minimum ground Table I: ISL7884xASRH variants. rules and three layers of interconnect. The process features salicided source/drain regions for low contact resistance, Intersil part number Rising UVLO Maximum which is a necessity for power management applications. duty cycle Active devices include low voltage CMOS and high voltage ISL78840ASRH 7.0V 100% DMOS devices as well as complementary bipolars. The ISL78841ASRH 7.0V 50% process is in volume production and has been used for a ISL78843ASRH 8.4V 100% wide range of commercial power management devices. In ISL78844ASRH 8.4V 50% order to retain the advantages of volume production, the ISL7884xASRH was designed using a hardened version of the commercial process, using well-known ‘minimally invasive’ processing methods. The excellent total dose Manuscript received 19 July 2010. hardness of the 140 Å gate oxide was demonstrated during the development by transistor-level testing to 300 krad(Si). N. W. van Vonno, L. G. Pearce, G. M. Wood, J. D. White, E. J. Thomson, T. M. Bernard, P. J. Chesley and R. Hood Latchup from either electrical or single-event causes is a key are with Intersil Corporation, Specialty Products, Palm issue, and suppression was insured through layout Bay, FL 32905, USA. techniques including guard rings and separate isolation tubs for the N- and P-channel devices. Single-event transients (SETs) are a major consideration in any power management application, as even a short disturbance of the DC-DC

978-1-4244-8404-1/10/$26.00 ©2010 IEEE converter output voltage can result in permanent damage to the load. SET hardening was carried out at the architectural as well as at the gate level by the use of redundancy, large device geometries and filtering.

III. TOTAL DOSE TESTING OF THE ISL7884XASRH High dose rate testing of the ISL7884xASRH was performed using a Gammacell 220 60Co irradiator located in the Palm Bay, Florida Intersil facility. Low dose rate testing was carried out in the same facility using a J. L. Shepherd and Associates (JLS) model 484 low dose rate 60Co irradiator. The high dose rate irradiations were carried out at Fig. 2: ISL7884xASRH Irradiation bias configuration per Standard 55 rad(Si)/s to a total dose of 125 krad(Si) and the low dose Microcircuit Drawing (SMD) 5962-07249, as used for both low and high rate work was performed at .010 rad(Si)/s to a total dose of dose rate irradiation. 150 krad(Si), both per MIL-STD-883 Test Method 1019. Dosimetry for both tests was performed using Far West Technology radiochromic dosimeters and on-site readout equipment. A PbAl box was used to shield the test fixture and samples against low energy secondary radiation.

A total of 12 samples drawn from preproduction lots were used; four were irradiated at high dose rate and under bias, four were irradiated at low dose rate and with all pins grounded and four were irradiated at low dose rate and under bias. The samples were processed through the standard burnin cycle before irradiation and were then screened to the SMD 5962-07249 limits at room, low and high temperature. The configuration used for biased irradiation was in conformance with the SMD and is shown in Figure 2. Downpoints were 10 krad(Si), 25 krad(Si), 50 krad(Si), 100 krad(Si) and 150 krad(Si) for the low dose rate test and 10 krad(Si), 25 krad(Si), 50 krad(Si), 100 krad(Si) Fig. 3: ISL78845ASRH operating supply current as a function of total and 125 krad(Si) for the high dose rate test. High and low dose irradiation at low and high dose rate. The low dose rate was dose rate tests of the ISL7884xASRH are complete and .01rad(Si)/s and the high dose rate was 55 rad(Si)/s. Sample size for each showed no reject devices, screening to the SMD post- cell was 4. The SMD limit for this parameter is 5.5mA. irradiation limits.

The plots in Fig. 2 through 11 show data on key parameters at all downpoints. The plots show the median as a function of total dose for each of the irradiation conditions; we elected to use the sample median as an indicator due to the relatively small sample size. All samples showed excellent stability over irradiation, with no observed low dose rate sensitivity or bias sensitivity.

Fig. 4: ISL78845ASRH startup current as a function of total dose irradiation at low and high dose rate. The low dose rate was .01 rad(Si)/s and the high dose rate was 55 rad(Si)/s. Sample size for each cell was 4. The SMD limit for this parameter is 500 µA maximum.

Fig. 5: ISL78845ASRH master reference output voltage as a function of Fig. 8: ISL78845ASRH error amplifier reference voltage as a function of total dose irradiation at low and high dose rate. The SMD limits for this total dose irradiation at low and high dose rate. The SMD limits for this parameter are 4.925 – 5.050 V. parameter are 2.475 – 2.530 V.

Fig. 6: ISL78845ASRH current sense amplifier input bias current as a function of total dose irradiation at low and high dose rate. The SMD limits Fig. 9: ISL78845ASRH error amplifier feedback pin bias current as a for this parameter are -1.0 – 1.0 µA. function of total dose irradiation at low and high dose rate. The SMD limits for this parameter are -1.0 – 1.0 µA.

Fig. 7: ISL78845ASRH current sense amplifier gain as a function of total dose irradiation at low and high dose rate. The SMD limits for this Fig. 10: ISL78845ASRH oscillator frequency as a function of total dose parameter are 2.5 – 3.5 V/V. irradiation at low and high dose rate. The SMD limits for this parameter are 48 – 53 KHz.

Fig. 12: SEL/SEB/SEGR evaluation board schematic, with the part in an open-loop configuration. For the SET testing, the board was configured to place the device in a closed loop configuration

Fig. 11: ISL78845ASRH oscillator frequency variation with VDD as a No latch up condition requiring manual intervention or function of total dose irradiation at low and high dose rate. The SMD limit for this parameter is 1% maximum. other destructive effects were observed. Momentary disruption in the output which self recovers to normal IV. SEE TESTING OF THE ISL78845ASRH operation was seen. The results are summarized in Table II, below. The single-event performance of the ISL78845ASRH was validated through a testing campaign conducted at Texas Table II: SEL/SEB testing results for the ISL7884xASRH. No A&M during August 2009. Support of the testing by failures were encountered for a total fluence of 3.99 x 107 ions/cm2. NASA/GSFC under the NEPP program is gratefully acknowledged. SEL/SEB susceptibility and SET Sample LET Fluence, SEL/SEB events ions/cm2 performance were characterized. The 15 MeV/amu beam was 2 6 109 1 86 MeV/mg/cm 9.98 x 10 0 used with Ag ions. The basic LET for these conditions is 2 6 2 2 86 MeV/mg/cm 9.98 x 10 0 43 MeV/mg/cm , while exposure at 60 degrees provided a 3 86 MeV/mg/cm2 1 x 107 0 2 higher LET of 86 MeV/mg/cm . The extensive testing carried 4 86 MeV/mg/cm2 9.98 x 106 0 out on the ISL78845ASRH generated a large amount of data, Total fluence 3.99 x 107 and only a limited sampling will be discussed in this paper due to space constraints. B: SET testing

A. SEL/SEB/SEGR Testing The SET fixture placed the ISL7884xASRH in a closed loop configuration representative of an actual application, using a switching frequency of 200 kHz, RT=17.8kΩ and The SEL/SEB test fixture placed the ISL78845ASRH in an CT=220 pF. The circuit was configured as the PWM open loop configuration. The test jig contained four of these controller of a buck DC-DC converter at a constant input boards and was wired to the data room using a 20-foot cable. voltage of 13.5 V and an output voltage of 12 V; the output The DUT signals were connected to three LeCroy storage current was 1 A. As for the SEL/SEB testing, a 0.22 µF oscilloscopes. The supply voltage for the destructive SEE test capacitor was connected from the VREF pin to GND as a runs was set at 14.7 V, with the case temperature controlled o bypass. Connecting the part in this actual application at 125 C. A total of four samples were tested. SEB was configuration provides a more realistic evaluation of the defined as an increase in the supply current of greater than SET vulnerability of the part but obviously requires 5% as measured after exposure to the beam. A 0.22 µF thorough shielding of the other active DC-DC converter capacitor was connected from the VREF pin to GND to components on the test fixture in order to produce valid bypass this node. The 14.7 V defines the absolute maximum data. The converter design is important for the proper VDD that can be applied to the device under beam. Figure 12 evaluation of the SEE performance under beam. In shows the SEL/SEB/SEGR evaluation board schematic. For particular one should ensure that the magnetic components the SET testing, the board was populated with the used in the design do not saturate under wide pulse components shown in the above schematic to place the conditions. This can be made possible by choosing the device in a closed loop configuration. right magnetic component and appropriately setting the pulse by pulse current limit thresholds. Failure to do this can result in the observation of SEE events not related to the device being tested. We defined two classes of SET: a perturbation of the output resulting in one or more missing pulses or changes in pulse width, or a change in the period of the output waveform. The stability of the converter output voltage was tracked as well.

Table III: SET test results for the ISL78845ASRH based on period and pulse width variation triggering. Tested at 25oC, closed loop, LET=43.2 MeV/mg/cm2 (109Ag), fluence per run 2 x 106 ions/cm2.

Sample Fluence, SET events Cross-section, cm2 ions/cm2 SET events based on period triggering 21 2.00 x 106 266 1.33 x 10-4 22 2.00 x 106 254 1.27 x 10-4 Total 4.00 x 106

SET events based on pulse width triggering 21 2.00 x 106 1276 6.38 x 10-4 22 2.00 x 106 1311 6.56 x 10-4 Total 4.00 x 106 Fig. 14: Typical ISL78845ASRH period SET event at LET=43.2 2 MeV/mg/cm , closed loop configuration, .022 µF VREF to ground bypass. The output voltage is 12 V at 1 A and the input voltage is 13.5 V. Note Table III summarizes SET testing results for the missing pulse and 50 mV negative output voltage transient. The horizontal ISL78845ASRH based on period and pulse width variation scale is 10 µs/division. events. Two samples were run at a total fluence of 2 x 106 ions/cm2, triggered on missing pulses or pulse width In Fig. 14 we see a missing pulse at t = 0 on the upper variations and on changes in the period of the output trace, which results in 100 mV negative drop in the converter waveform (changes in switching frequency). The calculated output voltage as seen in the lower trace. The converter cross-section for the period capture runs was 6.47 x 10-4 recovers to the nominal 12 V output in 20 µs. cm2.

In Fig. 13 through 18 we show typical period trigger SET events for the ISL78845ASRH. The upper traces show the output waveform of the controller, while the lower traces show the output voltage of the entire DC-DC converter on an expanded scale. In Fig. 13 a wide pulse is seen at t = 0 on the upper trace, which results in a positive disturbance of 100 mV to the converter output voltage. The converter recovers to the nominal 12 V output in 25 µs.

Fig. 15: Typical ISL78845ASRH period SET event at LET=43.2 MeV/mg/cm2, closed loop configuration, .022 µF VREF to ground bypass. The output voltage is 5 V at 1 A. Note positive VREF transient and resulting 250 mV positive output voltage transient, both at t= - 2.2 µs. The horizontal scale is 10 µs/division.

The SET signature in Fig. 15 shows a positive transient (upper trace) of the on-chip voltage reference, resulting in a 250 mV transient on the converter output voltage (lower trace). The converter recovers to the nominal 5 V output in Fig. 13: Typical ISL78845ASRH period SET event at LET=43.2 10 µs with a slight undershoot. MeV/mg/cm2, closed loop configuration, .022 µF VREF to ground bypass. The output voltage is 12 V at 1 A and the input voltage is 13.5V. Note wide pulse at t=0 (upper trace) followed by 100 mV output voltage increase and missing pulse as the converter corrects (lower trace) for the overvoltage. The horizontal scale is 10 µs/division.

Fig. 16: Typical ISL78845ASRH pulse width SET event at LET=43.2 MeV/mg/cm2, closed loop configuration, .022 µF VREF to ground bypass. The output voltage is 12 V at 1 A. Note wide pulse at t=0, followed by 100 Fig. 18: Typical ISL78845ASRH pulse width SET event at LET=43.2 2 mV positive output voltage transient, recovering in 4 µs. The horizontal MeV/mg/cm , closed loop configuration, .022 µF VREF to ground bypass. scale is 10 µs/division. The output voltage is 5 V at 1 A. Note negative VREF transient at t=0, followed by a missing pulse and a minimal output voltage transient. The horizontal scale is 10 µs/division. The SET signature in Fig. 16 shows a wide pulse (upper trace) at t=0, resulting in a 100 mV transient on the The SET signature in Fig. 18 shows a negative VREF converter output voltage (lower trace). The converter transient resulting in a missing pulse and a nearly recovers to the nominal 12 V output in 40 µs. undetectable output voltage transient.

V. CONCLUSION

We report the results of single-event and total dose testing of the ISL78845ASRH, a high performance hardened drop-in replacement for the commercial 28C4x and 18C4x PWM controllers.

Total dose testing of the ISL7884xASRH to 150 krad(Si) at low dose rate and 125 krad(Si) at high dose rate is complete and showed no rejects for either test. The part is considered ELDRS-free to its 100 krad(Si) data sheet limit. No bias sensitivity was noted.

Extensive SEE testing of the ISL7884xASRH was carried out during 2009. The part was found to be free of destructive SEE at an effective LET of 86.4 MeV/mg/cm2 and fluence of 4 x 107 ions/cm2 using a maximum input o Fig. 17: Typical ISL78845ASRH pulse width SET event at LET=43.2 voltage of 14.7V and case temperature of +125 C. SET MeV/mg/cm2, closed loop configuration, .022 µF VREF to ground bypass. testing was performed in a closed-loop DC-DC converter The output voltage is 12 V at 1 A. Note greatly narrowed pulse (near zero application schematic and resulted in various event width) at t=0, followed by 50 mV negative output voltage transient, signatures, including missing, narrow and wide pulses and recovering in 2 µs. The horizontal scale is 10 µs/division. variations in output waveform period. The SET disturbance The SET signature in Fig. 17 shows a narrow pulse of the converter output voltage was less than the 3% (upper trace) at t=0, resulting in a 50 mV transient on the maximum specified in the SMD in all cases. converter output voltage (lower trace). The converter recovers to the nominal 12 V output in 20 µs.

Single Event and Low Dose-Rate TID Effects in the DS16F95 RS-485 Transceiver

Andrew T. Kelly, Patrick R. Fleming, Ronald D. Brown, and Frankie Wong

DUT CONDITIONINGS DURING IRRADIATION Abstract-- Characterization of single event and low dose-rate TID effects in National Semiconductor’s DS16F95 Radiation- Active Bias Unbiased Hardened RS-485 Transceiver is reported. Onset LET for upset Pin Number Pin Name Dose Condition Dose Condition of less than 5 MeV-cm2/mg was observed, and a dependency on 1RON/CN/C operating condition was established. Samples under ELDRS 2RE/5.5VGND investigation adhered to electrical specification after irradiation 3DEGNDGND to 30 krd(Si) at 10 mrd(Si)/s. 4DI5.5VGND 5 GND GND GND I. INTRODUCTION 6 A Bus Port I/O N/C GND 7 B Bus Port I/O N/C GND HE DS16F95 is a unique device in that it is one of a 8N/CN/CGND Tlimited number of RS-485 Bus Transceivers that are 9N/CN/CGND marketed as radiation-hardened. The standard microcircuit 10 VCC 5.5V GND drawing (SMD#5962-89615) specifies total ionizing dose tolerance to 300 krd(Si)[1]. Additionally, the manufacturer The expected range of values and measurement conditions identifies Single Event Latchup (SEL) immunity for any LET were taken from the National Semiconductor DS16F95, < 120 MeV-cm2/mg [2]. However, this is the extent of DS36F95 EIA-485/EIA-422A Differential Bus Transceiver information currently available for radiation hardness Datasheet and DSCC SMD 5962-89615, with the SMD assurance. As a linear bipolar device, comprehensive low taking precedence. dose-rate TID testing is necessary for assurance against Devices were tested using two bias conditions. Five enhanced low dose-rate sensitivity [3]. As a mixed-signal devices were statically and five were biased with all pins tied interface device, SEU rates and SET characterization are to ground. The details of each bias condition are presented in necessary before this device can be appropriately qualified Table I. These devices were irradiated to a maximum total for use in critical space missions [4]. This work focuses on ionizing dose level of 30 krd(Si) with incremental readings at the investigation for and characterization of these 5 and 10 krd(Si). Two additional modules were withheld phenomena. from irradiation as control modules. Electrical testing occurred within one hour following the end of each II. EXPERIMENTAL SETUPS irradiation segment. For intermediate irradiations, the units were tested and returned to total dose exposure within two A. Low Dose-Rate Testing hours from the end of the previous radiation increment. The The low dose-rate 60Co TID testing was performed by ELDRS bias board was positioned in the Co-60 cell to Radiation Assured Devices, Inc. in Colorado Springs, CO. provide the required 10 mrd(Si)/s and was located inside a The testing was performed on 10 parts, with 2 controls. All lead-aluminum dose-enhancement box. The final dose rate devices were from Lot/Date Code 0732A. The devices were within the lead-aluminum box was determined based on TLD exposed to a maximum of 30 krd(Si) at a dose rate of 0.01 dosimetry measurements just prior to the beginning of the rd(Si)/s. Intermediate measurements were taken at 5 and 10 total dose irradiations. The final dose rate for this work was krd(Si). Testing was performed within compliance of MIL- 10 mrd (Si)/s with a precision of ±5%. STD-883G, Method 1019.7, Condition D.

B. Single Event Effects Testing SEE Testing was performed at the Texas A&M University TABLE I Cyclotron Institute in College Station, TX, on October 1-2, Manuscript received July 15, 2010. 2009, using the available 25 MeV/amu ion selections. The A. T. Kelly, P. R. Fleming, and R. D. Brown are with BAE Systems goal of the testing was to characterize the design’s Space Products and Systems, Manassas, VA 20110 USA (telephone: 703- susceptibility to heavy-ion SEU, SET, and SEL. Using a 367-2456, e-mail: [email protected]). F. Wong is with Space Systems/Loral, Palo Alto, CA 94303 (telephone: combination of beam degrader foils and angles of beam 650-825-5517, email: [email protected]).

Fig. 1. Test circuit for SEE chatacterization of DS16F95 tranceiver modules. Each module contains a differential signal driver and receiver module. 120Ω termination loads specified by RS-485 standard. 620Ω and capacitive loads model end-application specifications. Digital test system supplies the TTL data patter and monitors its transmission through the wrap-around RS-485 network. Real-time scope monitors differential signal nodes A and B for SETs. incidence on the DUT, LET values ranging from 1.9 to 120 The Keithley 740 thermometer measured the case MeV-cm2/mg were achieved. temperature of each DUT individually. The heating of the Each DUT was prepared for heavy ion radiation testing by DUTs were controlled by the Agilent 3632, which supplied the removal of the package lid and direct soldering of the part current to resistive metal-filament strip heaters, attached to to its unique position on a custom designed printed circuit the backside of each DUT. These instruments were board. Prior to radiation exposure, the test board was monitored and controlled manually. subjected to a complete electrical demonstration of test SEU testing was conducted at ambient room temperature methodology at 3 supply voltages (4.5V, 5.0V, and 5.5V) and (30°C) and 125°C, at 90% (4.5V) of nominal VDD (5.0V) 2 temperatures (25oC and 125oC). levels. SEL testing was conducted at 125°C, at 110% (5.5V) The five DUTs were configured in a RS-485 multi-point of nominal VDD levels. Exposures were carried out to a network. Each DUT was individually exposed to the heavy fluence of 107 particles/cm2 or until a significant number of ion beam, while the effects on the output of all 5 devices errors had been observed (>>100). were being monitored. The test circuit schematic is presented Two test conditions were investigated. The first condition in Fig. 1. Network Nodes ‘A’ and ‘B’ represent the had the driver of the DUT under irradiation enabled and complimentary nodes of the differential bus network, while transmitting a user defined data pattern (Checkerboard: Driver In (DI) and Receiver Out (RO) represent the ‘0,1,0,1,…etc,’ 0’s: ‘0,0,0,0,…etc,’ or 1’s: ‘1,1,1,1,…etc.’) individual digital interfaces to each device. DE denotes The second condition had the driver of the DUT under Driver Enable, while RE denotes Receiver Enable. irradiation disabled along with all other drivers. In this A JD Instruments ATV digital test system supplies the data condition, the analog 485 Bus was held to a static differential pattern to the single driver and monitors the receiver output voltage of approximately 440 mV, which is nominally data patterns of all 5 DUTs. The real time oscilloscope decoded as a ‘1’ by the receivers. monitors the analog transmission bus for single event By monitoring the receiver output patterns, cross sections transients (SETs). for the driver and receiver modules could individually be A real time oscilloscope monitored the analog transmission measured: bus for single event transients (SETs). For this, a Tektronix The upsets observed in those receivers not in the TDS5104 Digital Phosphor Oscilloscope was operated in its beam line identify which transients originating in FastFrame mode of operation, which takes advantage of the irradiated driver have sufficient propagation memory segmentation to rapidly detect, record, and rearm the characteristics to generate down-network bit trigger system with minimal dead time. upsets. The Keithley 2420 DC Sourcemeter supplied power to the device under test (DUT) throughout testing, and was controlled remotely via GPIB interface to allow supply current to be monitored throughout each heavy ion exposure (1 second sampling rate).

2.2x10-2 -1 Specifiaction Maximum: 2.8x10-2 A Specifiaction Minimum: -2x10-5 A 10 mrd(Si)/s 10 mrd(Si)/s -2 2.1x10-2 A)

μ -3 ( (A) IL 2.0x10-2 -4 CC-Enabled I Pin RE I -2 1.9x10 -5 Average Biased Average Biased Average Un-Biased Average Un-Biased -6 -2 1.8x10 0102030 0102030 Total Dose (krad(Si))

Total Dose (krad(Si)) Fig. 4. Measured IIL vs. γ dose for DS16F95 modules’ Receiver Enable Fig. 2. Measured ICC vs. γ dose for DS16F95 modules in enabled state. SMD pin. SMD 5962-89615 specifies a minimum of -20 µA (sink) for this 5962-89615 specifies a maximum of 28 mA for this parameter, which all parameter, which all devices met to a total dose of 30 krd(Si). The average devices met to a total dose of 30 krd(Si). The average data points comprise a data points comprise a sample set of 5 biased and 5 unbiased devices. sample set of 5 biased and 5 unbiased devices. Error bars correspond to Error bars correspond to Ps(99/90) end point limits based on a tolerance Ps(99/90) end point limits based on a tolerance limit (KTL) of 4.666. limit (KTL) of 4.666.

1.60x10-2 -4 Specifiaction Minimum: 2.5x10-2 A Specifiaction Minimum: -2E-05 A 10 mrd(Si)/s -5 10 mrd(Si)/s

-2 1.55x10 -6 A) μ (A) ( -7

1.50x10-2 IL -8 CC-Disabled I

Pin DE I DE Pin -9 1.45x10-2

Average Biased -10 Average Active-Biased Average Un-Biased Average Un-Biased 1.40x10-2 0102030 0102030 Total Dose (krd(Si)) Total Dose (krad(Si))

Fig. 3. Measured ICC vs. γ dose for DS16F95 modules in disabled state. Fig. 5. Measured IIL vs. γ dose for DS16F95 modules’ Driver Enable pin. SMD 5962-89615 specifies a maximum of 25 mA for this parameter, which SMD 5962-89615 specifies a minimum of -20 µA (sink) for this parameter, all devices met to a total dose of 30 krd(Si). The average data points which all devices met to a total dose of 30 krd(Si). The average data points comprise a sample set of 5 biased and 5 unbiased devices. Error bars comprise a sample set of 5 biased and 5 unbiased devices. Error bars correspond to Ps(99/90) end point limits based on a tolerance limit (KTL) of correspond to Ps(99/90) end point limits based on a tolerance limit (KTL) 4.666. of 4.666.

The difference in the error counts observed in the III. EXPERIMENTAL RESULTS receiver of the irradiated DUT and those off-beam constitute those errors generated directly within A. Low Dose-Rate TID the receiver module. The devices were comprehensively tested against all The oscilloscope records transients on the RS-485 parameter limits specified in Standard Microcircuit Drawing Bus, and monitors the JDI ATV Tester’s error #5962-89615 and remained within specification after 30 detection strobe to correlate detected transients to krd(Si). Radiation Hardness End Point Limit Analysis, as the presence of down-network upsets. specified in MIL-HDBK-814, further assures the lot under

-2.0 10-3 Specifiaction Minimum: -2E-05 A 10 mrd(Si)/s

-2.5 -4

) 10 2 A) μ (

IL -3.0 10-5

Pin D I -3.5 Average Biased 10-6 Cross-section (cm Average Un-Biased Driver Cross Section (cm2/dev) -4.0 Receiver Cross Section (cm2/dev) 10-7 0 102030 0 20406080100 Total Dose (krad(Si)) LET (MeV-cm2/mg)

Fig. 6. Measured IIL vs. γ dose for DS16F95 modules’ Driver Input pin. Fig. 8. Cross-section vs. LET plot for DS16F95, with Driver disabled. -4 SMD 5962-89615 specifies a minimum of -20 µA (sink) for this parameter, Weibull fit parameters, Driver: L0 = 10, W = 125, S = 2.2, σ = 1.5x10 . -4 which all devices met to a total dose of 30 krd(Si). The average data points Weibull fit parameters, Receiver: L0 = 0.5, W = 12, S = 1.5, σ = 1x1.2 . comprise a sample set of 5 biased and 5 unbiased devices. Error bars correspond to Ps(99/90) end point limits based on a tolerance limit (KTL) of 4.666.

10-3 3.0 No Upsets Detected 10-4 2.0 Associated with Upsets ) 2 1.0 10-5 0.0

-6 10 -1.0

Cross-section (cm Cross-section LET: 30 MeV-cm2/mg 10-7 (V) Error Value Peak -2.0 Pattern: CKBD Driver Cross Section (cm2/dev) Receiver Cross Section (cm2/dev) -3.0 -8 10 0 0.2 0.4 0.6 0.8 1 0 20 40 60 80 100 120 FWHM Duration (µs) LET (MeV-cm2/mg)

Fig. 7. Cross-section vs. LET plot for DS16F95, with Driver enabled. Fig. 9. Single Event Transient measurements on differential data bus for a -5 2 Weibull fit parameters, Driver: L0 = 1, W = 20, S = 4, σ = 4x10 . Weibull fit single exposure of 30 MeV-cm /mg Xe. -4 parameters, Receiver: L0 = 3, W = 15, S = 3, σ = 1x10 .

test to a 99% probability level and confidence level of 90. each plot for reference. Similar analysis was performed on all other parameters specified in the SMD, and similarly little, The corresponding tolerance limit (KTL) for each sample of 5 devices per bias condition is 4.666. Measurements on key if any, shift was observable. All measurements recorded parameters are presented in Figs. 2 – 6. Figs. 2 and 3 present were within compliance of SMD specifications, as were all calculated Ps(99/90) end point limits. ICC for the module in its enabled state (Fig. 2) and its disabled state (Fig. 3). Figs. 4 -6 present input current leakage for 3 pins: Receiver Enable (Fig. 4), Driver Enable (Fig. 5), and Driver Input (Fig. 6). Figs. 2 -6 identify very little parametric shift at 30 krd(Si), with respect to their specified limits, as taken from SMD5962-89615. Each parameter’s limit is specified within

TABLE II DS16F95 WEIBULL PARAMETERS & CORRESPONDING SOFT ERROR RATES: M3 GEOSYNCHRONOUS ORBIT

SER Error Mode Onset Width Power Saturation (cm2) (Upsets/device-day)

Drive Enabled: Driver Upsets 1 20 4 4.0x10-5 3.60x10-5 Driver Enabled: Receiver Upsets 3 15 3 1.0x10-4 2.24x10-4 Driver Disabled: Driver Upsets 10 125 202 1.5x10-4 4.06x10-6 Driver Disabled: Receiver Upsets 0.5 12 1.5 1.2x10-4 1.58x10-3

3.0 Driver errors are defined as those errors that were observed No Upsets Detected in any of the devices outside of the beam, while receiver 2.0 Associated with Upsets errors are defined as those only observed in the DUT within 1.0 the beam. Consecutive bit-errors are considered a single event, and can be identified in the raw error files generated by 0.0 the JDI tester. According to the cross section plots, it is clear that the dominant error mechanism resides within the -1.0 receiver. This is intuitive, because it is likely that the common mode rejection characteristics of the driver mitigate -2.0 LET: 40.9 MeV-cm2/mg Peak Error Value (V) Value Error Peak Pattern: CKBD a significant portion of locally generated transients. -3.0 Table II presents the Weibull parameters fitted to the corresponding plots, and the error rates generated from these 0 0.2 0.4 0.6 0.8 1 FWHM Duration (µs) values. Error rates correspond to the M3 90% worst-case background environment for a geosynchronous orbit. Both Fig. 10. Single Event Transient measurements on differential data bus for a the charge funnel and device depth is assumed to be 1µm in single exposure of 40.9 MeV-cm2/mg Xe. length. Calculations were performed with Space Radiation™ 5.0. Transient waveforms detected by the oscilloscope were exported in text files and sorted by pulse magnitude (peak 3.0 error voltage) and duration. The peak error voltage was No Upsets Detected calculated by subtracting the transient waveform from a 2.0 Associated with Upsets reference waveform. The reference waveform was derived from the pristine section of the measured waveform. 1.0 Additionally, the JDI Test System features an ‘Any Error’ signal which triggers on the detection of any upset. This 0.0 signal was recorded along with the detected transient signals, to identify which transients register as false data, and which -1.0 do not. Figs. 9-14 compare all transients detected during single exposures of ions of assorted LETs and operating

Peak Error Value (V) Error Value Peak -2.0 LET: 93.3 MeV-cm2/mg conditions. Pattern: CKBD Figs. 9-11 represent exposures in which a dynamic checkerboard pattern was transmitted through the data -3.0 network, for LETs of 30 (Fig. 9), 41 (Fig. 10), and 00.20.40.60.8193 MeV-cm2/mg (Fig. 11). Figs. 12-14 represent exposures FWHM Duration (µs) in which a static data pattern of logic-0 is transmitted through the data network, for LETs of 6 (Fig. 12), 20 (Fig. Fig. 11. Single Event Transient measurements on differential data bus for a 2 single exposure of 93.3 MeV-cm /mg Xe (LETeffective). 13), and 30 (Fig. 14). Two devices were screened for latchup susceptibility. Latchup runs were conducted with VCC=5.5V and TCASE = 125ºC. The effective fluence was 107 particles/cm2. The ion B. Single Event Effects species was 25 MeV/amu Xenon (LETnom = 60 MeV- cm2/mg) at an incident angle of 60º, for an effective LET of SEU results are plotted in Figs. 7 and 8. Fig. 7 119.17 MeV-cm2/mg. Latchup was not detected in either corresponds to those experiments conducted with the DUT device. driver (i.e. the driver within the beam line during exposure) enabled. Fig. 8 corresponds to those experiments conducted with the DUT driver disabled.

IV. CONCLUSION 3.0 No Upsets Detected The DS16F95 Radiation Hardened RS-485 Differential LET: 5.7 MeV-cm2/mg Bus Transceiver has been investigated for low dose-rate TID Pattern: 0's and single-event effects. It has been demonstrated that at 2.0 10 mrd(Si)/s, date code 0732A meets all electrical specifications after 30 krd(Si). Full mixed-signal SEE characterization has been completed. Transmission bit errors have been represented in cross-section vs. LET plots and used 1.0 to furnish soft error rates. It has been demonstrated that the onset for Single Event Upset is below an LET of 5 MeV- 2 Peak Error Value (V) Value Error Peak cm /mg. SET characterization on the differential data bus has provided as well. It has been confirmed in two samples that 0.0 the device do not exhibit Single Event Latchup below an LET 0.7 0.75 0.8 0.85 of 119 MeV-cm2/mg. FWHM Duration (µs)

Fig. 12. Single Event Transient measurements on differential data bus for a single exposure of 5.7 MeV-cm2/mg Ar. V. ACKNOWLEDGMENT 3.0 The authors would like to acknowledge Dr. Joseph No Upsets Detected Benedetto and Radiation Assured Devices, Inc. for their technical contributions during TID testing; and John C. LET: 20.7 MeV-cm2/mg Rodgers of BAE Systems and Pablito Yra of Space 2.0 Pattern: 0's Systems/Loral for technical input during SEE test planning.

VI. REFERENCES [1] http://www.dscc.dla.mil/Downloads/MilSpec/Smd/89615.pdf 1.0 [2] http://www.national.com/appinfo/space/files/ROM_Interface.pdf [3] R. L. Pease, R. D. Schrimpf, and D. M. Fleetwood, "ELDRS in Bipolar Linear Circuits: A Review," IEEE Trans. on Nucl. Sci., vol. 56, no. 4, Peak Peak Error (V) Value pp. 1894-1908, Aug. 2009. [4] T. L. Turflinger, “Single-Event Effects in Analog and Mixed-Signal 0.0 Integrated Circuits,” IEEE Trans. On Nucl. Sci., vol. 43, no. 2, pp. 594- 602, April 1996. 0.7 0.75 0.8 0.85 FWHM Duration (µs)

Fig. 13. Single Event Transient measurements on differential data bus for a single exposure of 20.7 MeV-cm2/mg Kr.

3.0 No Upsets Detected LET: 30 MeV-cm2/mg Pattern: 0's 2.0

1.0 Peak Error Value (V) Error Value Peak

0.0 0.7 0.75 0.8 0.85 FWHM Duration (µs)

Fig. 14. Single Event Transient measurements on differential data bus for a single exposure of 30 MeV-cm2/mg Kr.

Radiation test of 8 bit Microcontrollers ATmega128 & AT90CAN128

A.Schüttauf Astrium Space Transportation GmbH, Member IEEE, S.Rakers, Astrium Space Transportation GmbH, C.Daniel Astrium Space Transportation GmbH

• One power line for the microcontroller DUTs Abstract---We have performed heavy ion tests of the ATmega128 (piggy pack) and the temperature sensor and AT90CAN128 micro controller. These COTS devices have • A temperature out signal for the digital voltmeter. shown a quite different sensitivity to SEL/SEU errors, where the current consumption showed a step like behaviour. Detailed measurements, analyses and on-orbit rates are presented.

I. INTRODUCTION HE usage of commercial off the shelf components T (COTS) in space environment has become unavoidable since many semiconductor manufacturers have discontinued offering dedicated space or military grade components. Especially the availability of "state of the art" microcontrollers for space applications at a reasonable price is limited. The typically used 80C32 controller does often not match the nowadays needed performance and interface capabilities for modern payloads. In this framework we tested two general-purpose 8-bit microcontrollers (ATMEL ATmega128-AU16, AT90CAN128-AU16) in a heavy ion radiation test to assess their SEL/SEU sensitivity. Figure 1: Radiation setup used for the test at Jyväskylä/ Finland. These high performance low power 8-bit microcontrollers provide 128kBytes in-system programmable flash memory, Outside the vacuum chamber was a power supply, a windows 4kBytes EEPROM and 4kBytes internal SRAM. They use an laptop, a Break-out box (BOB), a relay box, an USB Hub and advanced RISC architecture up to 16 MIPS. Further built-in a LAN switch. The BOB is connected to an 8-port relay box features are a master/slave TWI serial interface (I²C bus and the relay box is connected to the power supply. The relay interface), an 8-channel, 10-bit AD converter with box is controlled by the Windows laptop. In this way up to programmable gain set used for the inputs of primary current eight DUTs can be powered controlled by the windows and temperature signals, and 53 digital I/O lines. The basic laptop without changing the wiring at the BOB. functional difference between the two microcontrollers is the CAN-bus interface, which only the AT90CAN128 offers. The power supply provides two channels: • Channel 1: Power supply for the DUT. This power supply is controlled via an Ethernet interface to a II. TEST ENVIRONMENT Laptop in the control room. This power supply has a fast over-voltage cut-off switch which is triggered Tests with heavy ions have been carried out at the JYFL by a latch-up. The software automatically resets the cyclotron in Jyväskylä/Finland where a LET range of 2 – 62 fuse after the latch-up is quenched. MeV mg-1cm2 is available. • Channel 2: Power supply for the heaters. All

samples are heated to 80°C during testing. The In Figure 1 we show the setup used during the test. The supply sits in the same mainframe like the DUT Device Under Test (DUT) board was placed inside the power supply and is also fully remote controllable. vacuum chamber holding 2 piggy-boards with three microcontrollers on top for each derivate. Further the DUT board provided: A. SEU test application During the irradiation the microcontrollers AT90CAN128 and ATmega128 executed permanently a memory test • Three power lines for the heaters program to detect SEUs. In a sequence the flash memory (128 kB), the EEPROM (4 kB) and the RAM (4 kB) was filled with pseudo random pattern. In this endless loop

various memory areas are compared with the previously the analysis we attributed similar power consumption to each generated pseudo random pattern. The duty cycle of this test microcontroller type and subtracted 75% of the measured was 95% for Flash, 2.5% for EEPROM and 2.5 % for RAM. current consumption during the non-irradiating phase. The In case of a negative result of the comparison the program Latch-up condition was fulfilled when a microcontroller indicates the fault by one signal (positive edge) " µC_out ". passed during irradiation a fixed current threshold (Ithr) which Due to this the memory fault is overwritten by the program was set at the power supply [3]. with the correct pattern and the comparison process is The fluence, needed to calculate the cross section, was continued. The watchdog of the different microcontrollers is individually dead-time corrected. To estimate the systematic enabled and the timeout is typically 0.26 s (256K cycles). uncertainty of this correction we compared the reconstructed The test program was placed in the boot-loader area of the with a fixed (3 s) dead-time per Latch-up. This systematic flash memory, which was not included in the comparison error for the cross section is below 1 % and folded into the process. An oscilloscope outside the irradiation chamber was statistical error. ATMega SEL used to count the transients appearing on the "fault & −3 2 10 µC_out" line and the fault pulses generated by the (device) cm σ microcontroller. 10−4

10−5 B. SEU results

10−6 The SEU cross sections are presented in Figure 2 for the 0 102030405060 MeV cm2 LET ( mg )

ATmega128 (upper) and AT90CAN 128 (lower) were the AT90Can128 SEL

−2 error-bars include the statistic and systematic errors. For the 2 10 (device) cm

Weibull fit we assumed a vanishing cross section at 10% of σ −3 the Krypton LET (32.1 MeVcm-2 mg-1). The parameters of 10 these fits are noted in Tab. 1. A comparison between the two 10−4 microcontrollers shows, that the AT90CAN128 has a 3 orders -2 10−5 of magnitude higher SEU saturation cross section (8.0 10 0 102030405060 MeV cm2 cm2) than the ATmega128 (1.11 10-5 cm2). LET ( mg )) Figure 3: ATmega128 (upper) and AT90CAN128 (lower) SEL cross sections (cm2) plotted versus the LET (MeVcm-2mg-1). For the ATmega128 we show ATMega SEU on top the cross section enhancement by reducing the Latch-up threshold −4 2 10 (IThr) to 0.3 and 0.2 (A) using open squares and triangles, respectively.

(device) cm σ 10−5 In the Figure 3 we present the measurement for the Latch- up test together with a Weibull fit though the data for the 10−6 ATmega128 (upper plot) and AT90CAN (lower plot). Both microcontrollers were tested with Iron and Krypton ions at a

10−7 6 4 0 102030405060 MeV cm2 fluence of 10 and 10 respectively. To perform the Weibull LET ( mg ) AT90Can128 SEU fit we assumed a vanishing Latch-up cross section at 30 % 2 1 (ATmega128) and 10 % (AT90CAN128) of the Krypton LET (device) cm

σ (32.2 MeVcm-2 mg-1). The saturation cross section resulting −1 10 from the Weibull fit shows, that the Latch-up probability differ by one order of magnitude (ATmega128 1.18 10-4 cm2, −2 10 AT90CAN128 1.0 10-3 cm2). Comparing the SEL and SEU saturation cross sections it follows that the ATmega128 has 10−3 0 102030405060 MeV cm2 LET ( mg ) an order of magnitude and the AT90CAN128 a two orders of Figure 2: ATmega128 and AT90CAN128 SEU cross sections (cm2 /device) magnitude lower sensitivity to Latch-ups. versus the LET (MeVcm -2mg-1)

C. Latch-up test application During the irradiation the SELs were determined by a current threshold of the individual DUTs. All measurements were performed using a heating device for each DUT to a temperature of 80 °C. D. SEL results The microcontroller setup consists out of 4 devices powered by a mezzanine board, 3 for the irradiation test and 1 as a reference sample. The power for the mezzanine board was supplied by a standalone low voltage power supply. For

0.45 I (A) 0.4 ATMEGA AT90CAN

0.35 6 0.3 5

0.25

0.2 5 0.15 4

0.1 4 0.05

0 3 4500 4550 4600 4650 4700 4750 4800 4850 Measured time (s) Cross section enhancement factor 3 Cross section enhancement factor

2 0.45 2 I (A) 0.4

0.35 1 1 0.3

0.25 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Latch−up Threshold (A) Latch−up Threshold (A) 0.2 0.15 Figure 5: The cross section enhancement factor in relation to the applied 0.1 Latch-up threshold Ithr (A) for the ATmega128 (left) and AT90CAN128 0.05 (right). The red triangles represent the calculation for the Iron LET and the 0 20300 20400 20500 20600 20700 20800 20900 21000 blue squares for the Krypton LET. Measured time (s) Figure 4: The ATmega128 (upper) and AT90CAN128 (lower) current (I) distribution depending on the irradiation time in seconds (s). The current is E. Fit parameters corrected for the offset introduced by the 3 additional microcontrollers on the piggy-board (not irradiated). The data from the ATmega128 and AT90CAN128 microcontrollers have been fitted by Weibull distributions. To determine the cross section in relation to the Latch-up threshold (Ithr ) the current measurement was used (Figure 4) Table 1 shows the resulting fit parameters. to calculate the electrical energy spectrum for each microcontroller individually. By integrating this spectrum for TABLE 1: WEIBULL FIT PARAMETERS FOR THE ATMEGA128 AND different current settings and normalizing it to the measured AT90CAN128 MICROCONTROLLER. current spectrum, we were able to correct the fluence of each ATmega128 SEU W [MeV cm-2 mg-1] 13,49 microcontroller individually. To minimize the statistical error S 2,0 L0 [MeV cm-2 mg-1] 4,0 we used all measurements at a given LET. The σ0 [cm2] 2.0E-05 microcontroller dependent cross section enhancement factor AT90CAN128 SEU W [MeV cm-2 mg-1] 18,8 is shown in Figure 5. for two different LET settings S 2,0 (18,2;32,2 MeV cm-2 mg-1). This factor has a hyperbolic L0 [MeV cm-2 mg-1] 4,0 dependence towards lower thresholds with a microcontroller σ0 [cm2] 8,00E-02 -2 -1 dependent maximum (6-8). As a side remark it has to be ATmega128 Latch-up W [MeV cm mg ] 20,1 S 2,0 pointed out, that the enhancement factor is insensitive to the L0 [MeV cm-2 mg-1] 12,0 LET of the irradiating particle. Therefore we can fold this σ0 [cm2] 1,8E-04 function with the measured cross section to get an estimate AT90CAN128 Latch-up W [MeV cm-2 mg-1] 20,1 for the Latch-up enhancement towards lower thresholds S 2,0 L0 [MeV cm-2 mg-1] 4,0 (Ithr).The reason to lower this threshold is based on the "step σ 2 like" current distributions (Figure 4) during the irradiation of 0 [cm ] 1,0E-03 both microcontrollers and the limiting DC currents for the ATmega128 and AT90CAN128 with 200-400 and 200 mA F. In orbit calculations respectively. These different thresholds can partially explain The data has been folded with the particle fluxes in the their different Latch-up cross sections. The overall trend for International Space Station (ISS) environment given in [1] for the current consumption during irradiation is presented in 500 and 100 mils shielding. Figure 4, were the ATmega128 has "plateau like" behaviour before the Latch-up condition is fulfilled the AT90CAN128 tends to have "step like" behaviour which sets in at lower currents.

TABLE 2: UNDER NOMINAL CONDITIONS WITH 500 MILS SHIELDING, THE found for the SEU-tests where the ATmega128 has a rate of ATMEGA128 WILL LATCH ONCE IN 1310 YEARS AND THE AT90CAN128 once in 690 years and the AT90CAN128 once in 3 month. ONCE IN 57 YEARS. THE SEU RATE FOR THE ATMEGA128 WILL BE ONCE IN 1630 YEARS AND FOR THE AT90CAN128 ONCE IN 7 MONTH. Both SEEs rates are calculated for 100 mils aluminum shielding at an inclination of 51° and 400 km under quiet ISS LEO solar conditions. 500 mils This significant difference between the 2 microcontrollers Function Nominal Maximum Flare Max.Fl. Unit Peak Orbit was not expected from their electrical and technological average properties. Comparing the thermal and electrical properties of Latch-up the ATmega128 (-40-125 o C, 200-400 mA) and the -1 ATmega 2,09 10-6 5,42 10-4 7,87 10-5 Day AT90CAN128 we can point towards the difference, that the Latch-up o AT90CAN 4,76 10-5 1,29 10-4 1,63 10-3 Day-1 AT90CAN128 has the smaller temperature range -40-85 C SEU and a lower DC current limit 200 mA, except the CAN-bus ATmega 1,68 10-6 4,56 10-4 5,61 10-5 Day-1 interface. Additionally the current consumptions for both SEU microcontrollers showed "step like" time dependence (Figure -1 AT90CAN 4,17 10-3 1,13 1,43 10-1 Day 2). This effect points towards a slow charging of sensitive structures or "Micro Latch Ups". During this behavior the TABLE 3: UNDER NOMINAL CONDITIONS WITH 100 MILS SHIELDING, THE ATMEGA WILL LATCH ONCE IN 481 YEARS AND THE AT90CAN ONCE IN 24 microcontrollers did not show any degradation in terms of YEARS. THE SEU RATE FOR THE ATMEGA128 WILL BE ONCE IN 690 YEARS performance or reliability. AND FOR THE AT90CAN128 ONCE IN 3 MONTH. To minimize the overall power consumption of the microcontrollers we developed a method to determine a cross ISS LEO section enhancement factor in relation to the applied Latch-up 100 mils threshold (I ). This method uses the current measurement Function Nominal Maximum Max.Fl. Unit thr Flare Peak Orbit (Figure 2) during irradiation to determine the electrical average energy spectrum for each microcontroller individually. In Latch-up first order the derived functions are independent on the LET -1 ATmega 5,69 10-6 1,07 10-1 1,76 10-2 Day of the ion species and show a hyperbolic shape towards Latch-up -1 smaller threshold currents (Figure 3). For both AT90CAN 1,14 10-4 1,92 10-4 2,73 10-3 Day SEU microcontrollers we determined for low current thresholds -1 ATmega 3,97 10-6 6,44 10-2 8,22 10-3 Day (Ithr< 50 mA) a cross section enhancement of ~10. As a result SEU we recommend for the ATmega128 a Latch-up threshold of -1 AT90CAN 1,0 10-2 168 23,8 Day 150-200 mA which would enhance the cross sections by a

o factor 2.0-2.5, but keeps the current consumption well below For a geostationary orbit at 38000 km with 0 inclination and the DC limit of 400 mA. For the AT90CAN128 this method 100 mils shielding the following results were reached using leads to the conclusion that this microcontroller should not be the SPACERAD program with the CRÈME space weather used for space application due to its high Latch-up and SEU conditions (M1, M2, and M3). rates.

TABLE 4 CONSIDERING ONLY THE GALACTIC COMPONENT IN THE CREME CODE (M1), THE ATMEGA WILL LATCH ONCE IN 24 YEARS AND THE References AT90CAN ONCE IN 1.5 YEARS. THE SEU RATE FOR THE ATMEGA WILL BE [1] NASA SSP30512, Space Station Ionizing Radiation ONCE IN 56 YEARS AND FOR THE AT90CAN ONCE IN 1 MONTH. Design Environment

GEO 100 [2] NASA SSP30513, Space Station Ionizing Radiation mils Environment Effects Test and Analysis Techniques Function CRÈME CRÈME CRÈME Unit M1 M2 M3 Latch-up [3] ASTRIUM Space Transportation, SPAICE-RIBRE-TN- ATmega 1,12 10-4 1,07 10-4 1,77 10-4 Day-1 0018 Radiation Test Report Latch-up AT90CAN 1.61 10-3 1,57 10-3 2,60 10-3 Day-1 SEU ATmega 4,84 10-5 4,62 10-5 7,65 10-5 Day-1 SEU AT90CAN 1,78 10-2 1,37 10-1 2,26 10-1 Day-1

I. SUMMARY & CONCLUSION A radiation test was performed using Iron and Krypton ions at a LET of 18.5 and 32.1 MeVcm-2mg-1. For the ATmega128 microcontroller we measured a Latch-up rate (SEL) of once in 481 years and for the AT90CAN128 a Latch-up rate of once in 24 years. A similar pattern was

ELDRS Characterization for a Very High Dose Mission

Richard D. Harris, Member, IEEE, Steven S. McClure, Member, IEEE, Bernard G. Rax, Dennis O. Thorbourn, Aaron J. Kenna, Karla B. Clark, and Tsun-Yee Yan

Abstract--Evaluation of bipolar linear parts which may have tests on a number of bipolar linear devices. Enhanced Low Dose Rate Sensitivity (ELDRS) is problematic During the course of testing this methodology, data have for missions that have very high dose radiation requirements. been acquired which show functional or parametric failures at The accepted standards for evaluating parts that display fairly high dose levels (50 to 150 krad(Si)) during low dose ELDRS require testing at a very low dose rate which could be rate (LDR) irradiation only. Failure in these parts was not prohibitively long for very high dose missions. In this work, a seen during high dose rate (HDR) irradiation up to methodology for ELDRS characterization of bipolar parts for mission doses up to 1 Mrad(Si) is evaluated. The procedure 1 Mrad(Si), considerably higher than the LDR failure doses. employs an initial dose rate of 0.01 rad(Si)/s to a total dose of 50 This behavior rules out the use of trend data to extrapolate krad(Si) and then changes to 0.04 rad(Si)/s to a total dose of 1 LDR performance using an enhancement factor on the HDR Mrad(Si). This procedure appears to work well. No change in performance data. In other words, test methods must include rate of degradation with dose has been observed when the dose LDR testing to levels greater than the mission dose in order rate is changed from 0.01 to 0.04 rad(Si)/s. This is taken as an to bound device performance. indication that the degradation due to the higher dose rate is equivalent to that at the lower dose rate at the higher dose levels, II. TEST METHODOLOGY at least for the parts studied to date. In several cases, significant parameter degradation or functional failure not observed at The accepted standards for evaluating parts with ELDRS HDR was observed at LDR at fairly high total doses (50 to 250 require testing at a very low dose rate which could be krad(Si)). This behavior calls into question the use of dose rate prohibitively long for very high dose missions. The dose rates trend data and enhancement factors to predict LDR used to determine if a specific part displays ELDRS are performance. governed by MIL-STD-883, Method 1019 [1] and require comparing the degradation with irradiation under a high dose I. INTRODUCTION rate (HDR) of 50 – 300 rad(Si)/s with that under a low dose ADIATION poses a unique technical challenge for any rate (LDR) of 0.01 rad(Si)/s. If there is an increased Rpotential mission to the moons of Jupiter since the degradation per unit dose at the lower dose rate, the part is spacecraft would spend a significant amount of time in the concluded to have ELDRS. Once this determination is made, harsh Jovian radiation belts. The radiation dose level all subsequent evaluation and qualification must be experienced by a mission to, say, Europa would be performed at the low dose rate. The difficulty for these very unprecedented for a NASA mission. Due to the very strong high dose scenarios is that the time required for testing to 300 magnetic field of Jupiter, the radiation belt has a large flux of highly energetic electrons. Dose levels could easily be several to 1000 krad(Si) levels at the required LDR would take 1 to 3 Mrads behind 100 mil of aluminum shielding. Devices within years, much too long to comply with mission parts approval electronic boxes could be subjected to as much as 300 to requirements. 1000 krad(Si). Various methods have been proposed to accelerate the This TID level poses a risk since many linear bipolar lengthy testing protocol for very high dose missions. These devices are not available as radiation hardened nor have been include: irradiating at elevated temperature [2], using trend tested to such a high level. In order to support such a mission data to predict LDR performance based on using an scenario, we evaluated a test methodology for Enhanced Low enhancement factor on the measured HDR data [3], and using Dose Rate Sensitivity (ELDRS) susceptible devices which a dose-rate switching technique [4]. These procedures have addresses this high dose environment and performed initial not met with universal acceptance [5]. However, the challenges of very high dose missions make some sort of accelerated method necessary. Manuscript received July 29, 2010. This work was carried out at the Jet A reasonable potential mission could be at Europa for 3 Propulsion Laboratory, California Institute of Technology, Pasadena CA, under contract with the National Aeronautics and Space Administration months, after spending 3 months between reaching Jupiter (NASA). and achieving Europa orbit insertion. In such a scenario, The authors are with the Jet Propulsion Laboratory, California Institute of almost the entire dose would be expected to be received Technology, Pasadena, CA 91109 USA ([email protected], (phone: 818-393-6872, fax: 818-393-4559); [email protected]; during this 6 month portion of the mission. A total dose of (phone: 818-354-0482, fax: 818-393-4559)). 300 to 1000 krad(Si) received over a 6 month time period

TABLE I DESCRIPTION OF TESTED PARTS AND THE CURRENT DOSE LEVEL

Generic P/N Full Part Number Description MF Date Code HDR Level LDR Level

AD537 AD537SH/883B Voltage to Frequency Conv. ADI 0719A/B 1 Mrad 1 Mrad AD606 AD606JRZ-ND Demodulating Log Amp ADI 0650 1 Mrad 1 Mrad AD652 AD652SQ/883B Voltage to Frequency Conv. ADI 0745 1 Mrad 1 Mrad AD667 AD667-713F 12 bit ADC ADI 0438 1 Mrad 1 Mrad RH117 RH117H Regulator LTC 0750A n/a 1 Mrad AD574 5962R8512701VXA 12 bit ADC ADI 0247A/0622 100 krad 1 Mrad AD648 AD648TQ/QMLV Bi-FET Op-Amp ADI 0629 1 Mrad 1 Mrad AD8138 AD8138ARM-ND Differential ADC Driver ADI MAR 08 3 Mrad 1 Mrad LM113 5962-9684302VXA Voltage Reference NSC 01A n/a 1 Mrad AD590 5962R8757104VXA Temperature Transducer ADI 0435A 1 Mrad 1 Mrad OP400 5962-8777101VBA Op-Amp ADI 0502 1 Mrad 1 Mrad RH1078 RH1078MW Dual Op-Amp LTC 0741A n/a 1 Mrad RH1814 RH1814MW Quad Op-Amp LTC 0414A n/a 1 Mrad PM139 5962R8773901VDA Quad Voltage Comparator ADI 0046A n/a 1 Mrad

results in a time average dose rate of approximately 0.02 to a dose of at least 50 krad(Si) and 0.04 rad(Si)/s to 1 Mrad(Si)

0.06 rad(Si)/s. or to failure. To address such a scenario, a test procedure was evaluated B. Electrical Tests where parts are irradiated to at least 50 krad(Si) at 0.01 rad(Si)/s, the accepted low dose rate, then continued at an Electrical tests were performed on-site at JPL using one of increased dose rate of 0.040 rad(Si)/s until a total dose of two mixed signal testers; either an ETS-300 or an LTS-2020. 1 Mrad(Si) was reached, or the parts failed, whichever came In general, all parameters specified by the manufacturer were first. The initial low dose rate step serves three purposes: 1) it measured. Measurements were performed prior to the start of sets a baseline comparison to Method 1019, 2) it provides a irradiation and following a variety of levels throughout the worst-case bound on performance for the dose received irradiation. The target levels generally included: 5, 10, 20, 30, during the cruise stage, and 3) it is compatible with a JPL 50, 75, 100, 150, 200, 250, 300, 500, 700, and 1000 krad(Si); mission (Juno) for which testing was ongoing. This third some allowance was made at LDR to allow for convenient purpose permits the use of parts for which the NRE efforts measurement times. Irradiation and measurements were are already completed and the initial data are already taken. performed at room temperature. The higher LDR step, 0.040 rad(Si)/s, is a compromise to C. Procedure address the 300 to 1000 krad dose level accumulated over the Samples of each device type were divided into four groups 6 months near Jupiter. of four to five parts for each irradiation condition. These The parts selected for this initial testing were parts for included HDR and LDR with parts both biased and unbiased which testing was already in progress for the ongoing Juno at each rate. In all cases, all parts of a particular type were project. This project required LDR testing to 50 krad(Si) and from the same date code. The irradiation bias conditions for HDR testing to 100 krad(Si). Testing was extended to biased irradiations were in accordance with either the 1 Mrad(Si) for the study presented in this paper. Test devices manufacturer’s recommendation or the application condition. evaluated to date are identified in Table I which includes part Parts in the unbiased groups had all leads shorted and details and the TID level reached. grounded.

III. EXPERIMENTAL DETAILS IV. EXPERIMENTAL RESULTS A. Total Dose Facilities Table II summarizes the failures observed to date. The Total dose irradiations for all devices were performed at failures listed here are divided into 3 categories: functional the Co-60 HDR and LDR facilities at the Jet Propulsion failures (where the part is no longer functional), extreme Laboratory. The dose rate capability obtained by employing parametric failures (where the part is still functional but so far both sources spans from 0.001 to 50 rad(Si)/s. For all high out of spec as to be unusable) and mild parametric failures dose rate exposures, a dose rate of 25 rad(Si)/s was used. (where the parameters are out of spec, but the device may still Low dose rate exposures were carried out at 0.01 rad(Si)/s to be useable if the parameter drift can be accounted for in

TABLE II FAILURES OF TESTED PARTS AND FAILURE LEVEL

Failure Generic P/N Failing Parameters Failure Type Failure Condition Level AD537 Linearity Error, Output Frequency Extreme Parametric HDR, LDR unbiased 150 krad AD606 Log Conformance, Log Intercept, Slope Extreme Parametric LDR unbiased 150 krad AD652 Voltage Reference Mild Parametric All 10 krad AD667 INL, DNL, UZE, BZE Mild Parametric LDR unbiased 10 krad RH117 Reference Voltage, Dropout Voltage Mild Parametric LDR unbiased 150 krad AD574 INL, DNL, Bipolar Zero Error Functional LDR unbiased 50 krad AD648 Input Bias Current, AOL Extreme Parametric All 5 krad AD8138 None - - - LM113 Dynamic Impedance Mild Parametric LDR unbiased 50 krad AD590 Temperature Error Extreme Parametric LDR both 20 krad Offset Voltage Functional HDR both, LDR unbiased 25 krad OP400 Input Bias Current Extreme Parametric All 5 krad RH1078 Offset Voltage, Source Current Mild Parametric LDR unbiased 250 krad 50 krad RH1814 Sink Current Mild Parametric LDR biased but recovers PM139 None - - -

the circuit design). ELDRS effect as the LDR unbiased case shows the most Selected parameters are discussed and their radiation degradation at the lowest doses, but the effect is small. The dependence is plotted in the following sections. In all more significant factor is the bias during irradiation with subsequent plots the average values of the parts irradiated unbiased parts showing more degradation at both dose rates. under a particular condition are shown. In addition, the Parametric failures in the linearity error (not shown) begin specification limits are shown. to appear at 100 krad(Si) and become extreme by 150 krad(Si). There is no ELDRS effect in the failure as both A. AD537 Voltage to Frequency Converter LDR and HDR unbiased cases display the same behavior. Parametric failures in the AD537 begin to appear in the Again, there is a significant bias effect. input bias current at about 30 krad(Si) for all irradiation Significant parametric shifts in the output frequency (not conditions, as shown in Fig. 1. Extreme parametric failure shown) appear above 75 krad(Si) for all but the biased HDR sets in above about 300 krad(Si) for both unbiased cases; the case. This degradation was most significant at higher input apparent recovery after this level is actually a result of the voltage values, indicating that device performance is device no longer functioning properly. There may be an improved by limiting the input voltage range. These results indicate that this device is not usable beyond 800 150 krad(Si) unless it is used only in the biased condition 700 AD537 with no unbiased units. 600 B. AD606 Logarithmic Amplifier Extreme parametric failures were observed for the LDR 500 unbiased irradiation condition at 150 krad(Si) for log slope 400 (not shown), log conformance (Fig. 2), and the intercept point (not shown). Both HDR and LDR biased conditions 300 LDR Biased continued to be functional until 700 krad(Si), above which all 200 LDR Unbiased parameters fail for the LDR biased case. These results HDR Biased Input Bias Current Current (nA) Bias Input indicate that this device is not usable beyond 150 krad(Si) 100 HDR Unbiased spec limit unless it is used only in the biased condition with no unbiased 0 units. 0 200 400 600 800 1000 C. AD652 Voltage to Frequency Converter Total Dose (krad(Si)) Fig. 1. AD537 Input Bias Current. Mild parametric failure is observed The voltage reference of the AD652 degraded very rapidly above about 30 krad(Si). Extreme parametric failure has set in above about with extreme parametric degradation setting in by 10 krad(Si) 300 krad(Si) for both unbiased cases; the apparent recovery after this level is as shown in Fig. 3. As a result, this part must be used with an actually a result of the device no longer functioning properly.

2 2.5

1 AD606 AD667 2 0 1.5 -1 LDR Biased LDR Unbiased -2 1 HDR Biased LDR Biased HDR Unbiased -3 LDR Unbiased spec limit HDR Biased Log Conformance (dB) 0.5 -4 HDR Unbiased spec limit Integral Non-Linearity (LSB) -5 0 0 200 400 600 800 1000 0 200 400 600 800 1000 Total Dose (krad(Si)) Total Dose (krad(Si)) Fig. 2. AD606 Log Conformance. Extreme parametric failure is observed Fig. 4. AD667 Integral Non-Linearity. Mild parametric degradation is above about 150 krad(Si) in the LDR unbiased condition. All parameters fail observed beginning at about 10 krad. Degradation appears to saturate at above 700 krad(Si) for the LDR biased condition. about 300 krad(Si); the apparent recovery after this level is actually a result of the device no longer functioning properly. external reference. ELDRS and bias effects are readily apparent with the LDR unbiased irradiation condition being then devices were left overnight with no irradiation. The the worst case. As a result, this part must be used with an remaining tests were performed the next day and were likely external reference. not performed as quickly after irradiation leaving open the Other parameters in this part remained well behaved. possibility that the observed spike was due to an effect that is relatively fast annealing. This interpretation is somewhat D. AD667 12-bit Analog to Digital Converter speculative at this time, and more investigation will be The integral non-linearity (INL, Fig. 4) and differential necessary to be sure. non-linearity (DNL, not shown) of the AD667 both showed The reference voltage (not shown) for this device indicated gradual degradation beginning by 10 krad(Si). The low dose no significant degradation to the highest levels tested. All rate unbiased case performed the worst; the change in INL devices continue to work to at least 1 Mrad and remain usable was up to about 2 LSB by 300 krad(Si). The degradation provided the parametric degradation can be tolerated in the appears to saturate at this point. application. Both unipolar zero offset (UZE, not shown) and bipolar zero offset (BZE, not shown) demonstrated a significant E. RH117 Regulator spike around 300 krad(Si) for the HDR biased case. This Only two (2) parts were available for the RH117 resulting behavior appears to be a real effect as it occurred in all the in only LDR unbiased irradiations being performed. The devices. This behavior, or at least the recovery after 300 degradation of the reference voltage (VREF) is shown in krad(Si), may be due to the timing of tests. Test levels up to Fig. 5. This parameter exceeds specification above 150 300 krad(Si) were done rapidly within the first day of testing, krad(Si) and then begins a precipitous fall after 300 krad(Si). The dropout voltage (not shown) is out of spec above 200 6 krad(Si) (not shown). Similar behavior is also observed for AD652 VREG and VOUT (not shown). 5.5 F. AD574 12-bit Analog to Digital Converter Functional failures in the AD574s began to appear in 5 integral non-linearity (INL) and differential non-linearity (DNL) in unbiased LDR devices at 50 krad(Si). By 4.5 100 krad(Si), all devices exhibited functional failures. The 4 INL behavior is depicted in Fig. 6. Prior to the functional LDR Biased failure there was no indication of ELDRS with all groups LDR Unbiased Reference Voltage 3.5(V) HDR Biased performing similarly. HDR Unbiased Mild parametric failures began to appear in INL and DNL spec limit 3 at 30 krad(Si) for all bias and dose rate conditions, and the HDR and biased LDR parts continued in this mild degraded 0 200 400 600 800 1000 state to the highest doses tested. This includes the biased Total Dose (krad(Si)) Fig. 3. AD652 Reference Voltage. Extreme parametric failure is LDR group which performed very well beyond 300 krad(Si) observed above about 10 krad. Other parameters in this part remained well and is still functional at 1 Mrad(Si). behaved. As a result, this part must be used with an external reference. The general behavior of the bipolar zero error (not shown)

1.4 700

1.2 600 AD648 1 RH117 500

0.8 400

0.6 300 LDR Biased LDR Unbiased 0.4 LDR Unbiased 200 spec limit HDR Biased

Reference Voltage (V) HDR Unbiased Input Bias Current (pA) 0.2 100 spec limit

0 0 0 200 400 600 800 1000 0 200 400 600 800 1000 Total Dose (krad(Si)) Total Dose (krad(Si)) Fig. 5. RH117 Reference Voltage. VREF falls out of spec above 150 Fig. 7. AD648 Input Bias Current. Mild parametric failure is observed at krad(Si) and then falls dramatically after 300 krad(Si). the first irradiation step of 5 krad increasing to extreme parametric failure by 30 krad(Si). is quite similar to that of INL. Functional failure is observed following about 75 krad(Si) for the LDR unbiased case. All degradation with irradiation. During the HDR irradiation, the other conditions continue to function. dose level was extended to 3 Mrad(Si) to see if the good These results indicate that use of this device beyond 30 performance would continue; which it did. For the very little krad(Si) would have to be limited to a biased condition with degradation seen, there is no apparent bias or dose rate no unbiased units. If this were done, for levels above about dependence. As a result of the lack of degradation, no figures 400 krad(Si), the mild parametric failures would need to be of the AD8138 performance are shown. tolerated by the circuit design. This part is fabricated with a complementary high speed process that is expected to be very radiation tolerant. These G. AD648 Bi-FET Op-Amp results support that expectation. The input bias current on the AD648 exhibited mild I. LM113 Voltage Reference parametric failure at the first irradiation step of 5 krad(Si) and increased to extreme parametric failure by 30 krad(Si), as There were only a limited number of LM113 parts available for this test. As a result, the parts were only shown in Fig. 7. Open loop gain (AOL, not shown) exhibits mild parametric failure beginning at 30 krad(Si) and irradiated under LDR conditions. Most parameters remained increased to functional failure by 100 krad(Si). There does in specification, including the reference voltage (not shown) not appear to be any bias or dose rate dependence in the which while showing a gradual degradation with increasing degradation rate. Other parameters also showed extremely dose, is still well within spec at 1 Mrad(Si). poor performance. The dynamic impedance, shown in Fig. 8, displays steady and rapidly increasing mild parametric degradation at LDR, H. AD8138 Differential ADC Driver exceeding the spec value at about 50 krad(Si). The step at 133 The parameters of the AD8138 show very little to no krad(Si) is due to the irradiation being stopped at this point and then restarted after a 16 month anneal. It is interesting 4.5 that after restarting, the degradation resumes its initial degradation curve. The devices are still functional and remain 4 usable provided the parametric degradation can be tolerated 3.5 in the application. 3 J. AD590 Temperature Transducer 2.5 AD574 LDR Biased Parametric degradation begins at the first irradiation level 2 LDR Unbiased and results in failures in the temperature error for LDR after 1.5 HDR Biased 20 krad(Si) and for HDR after 75 krad(Si) as shown in Fig. 9. HDR Unbiased Due to the failures at low doses at LDR, the irradiation was 1 spec limit not extended beyond 50 krad(Si) at LDR nor 100 krad(Si) at

Integral Non-Linearity (LSB) Non-Linearity Integral 0.5 HDR. 0 K. OP400 Operational Amplifier 0 200 400 600 800 1000 Parametric degradation of the offset voltage (not shown) Total Dose (krad(Si)) proceeds slowly until functional failure occurs at ~25 Fig. 6. AD574 Integral Non-Linearity. Functional failure is observed krad(Si). Failure occurs for all cases except the LDR biased above about 50 krad for the LDR unbiased case. To use this part above 50 krad it must be kept in a biased condition. case below 100 krad(Si). The LDR biased case is still

6 0 )

Ω -5 5 -10 OP400 -15 4 LM113 -20 3 -25 LDR Biased -30 LDR Biased LDR Unbiased 2 LDR Unbiased spec limit -35 HDR Biased -40 1 (nA) Bias Current Input HDR Unbiased -45 spec limit Dynamic Impedance @1mA ( @1mA Impedance Dynamic 0 -50 0 200 400 600 800 1000 0 200 400 600 800 1000 Total Dose (krad(Si)) Total Dose (krad(Si)) Fig. 8. LM113 Dynamic Impedance. Mild parametric degradation begins Fig. 10. OP400 Input Bias Current. Very rapid degradation is observed at about 50 krad(Si). The devices are still functional and remain usable resulting in failure above 5 krad(Si) for all cases. provided the application can tolerate the amount of degradation. interesting case where the LDR biased values drift up out of functional and in specification at 1 Mrad(Si). specification at ~50 krad(Si), but then drift back down into The input bias current degrades very rapidly, resulting in specification and remain in specification until at least failure above 5 krad (Si) for all cases as shown in Fig. 10. 1 Mrad(Si). This unusual behavior is not understood. Input offset current (IIO) and large signal voltage gain (AVS) show similarly rapid degradation and failures. N. PM139 Quad Voltage Comparator Only a limited number of parts were available for the L. RH1078 Dual Operational Amplifier PM139 resulting in only LDR irradiations being performed. Only a limited number of parts were available for the All parameters for the PM139 are still within spec at the RH1078 resulting in only LDR irradiations being performed. present dose level of 300 krad(Si). As a result of the lack of The offset voltage, shown in Fig. 11, begins to exceed the degradation, no figures of the PM139 performance are spec limit above 250 krad(Si) for the LDR unbiased case and shown. above 300 krad(Si) for the LDR biased case. The source current is not shown. For both bias cases the V. DISCUSSION parameter is above the spec limit above ~250 krad(Si). Similar behavior is also observed for power supply rejection An accelerated test method has been evaluated on a ratio (PSRR) and slew rate (both not shown). number of bipolar linear parts which appears to produce acceptable results. This method employs a LDR value of 0.01 M. RH1814 Quad Operational Amplifier rad(Si)/s until a dose of 50 krad(Si) is reached and then Only a limited number of parts were available for the increases the LDR to 0.04 rad(Si)/s until 1 Mrad(Si) is RH1814 resulting in only LDR irradiations being performed. reached. This decreases the total irradiation time from 3.2 The only parameter which drifted out of spec is the sink years for a constant LDR of 0.01 rad(Si)/s to 0.9 years for the current (ISINK) shown in Fig. 12. This is an unusual and

1100 0 RH1078 900 AD590 -20 700

-40 500

LDR Biased -60 LDR Unbiased 300 LDR Biased HDR Biased (µV) Offset Voltage LDR Unbiased HDR Unbiased 100 spec limit -80 spec limit

Temperature Error (°C) Error Temperature -100 -100 0 200 400 600 800 1000 0 200 400 600 800 1000 Total Dose (krad(Si)) Total Dose (krad(Si)) Fig. 11. RH1078 Offset Voltage. Parametric degradation begins to Fig. 9. AD590 Temperature Error. Parametric failures observed after 20 exceed spec for the LDR unbiased case above 250 krad and above 300 krad krad(Si) at LDR and after 75 krad(Si) at HDR. for the biased case.

-20 linear bipolar devices tested are experiencing either parametric or functional failure in the unbiased condition at -25 RH1814 50 to 150 krad(Si), while failure is not occurring for the -30 biased condition. This indicates that leaving devices in a -35 powered state is a mitigation strategy that should be considered. -40

-45 VI. CONCLUSIONS AND RECOMMENDATIONS No previous work has addressed hardness assurance

Sink Current (mA) -50 LDR Biased methods for assessing ELDRS for very high dose missions. -55 LDR Unbiased Also, very little data exists for ELDRS evaluations beyond spec limit 100 krad(Si). This work has shown that, at least for the -60 scenario used here, a practical test method can be developed. 0 200 400 600 800 1000 Further work is recommended to verify that this method Total Dose (krad(Si)) bounds device performance for longer missions with lower Fig. 12. RH1814 Sink Current. This parameter drifts out of spec at about 50 krad(Si) and then immediately drifts back into spec for the LDR biased dose rate requirements. Additional device tests including long case. This is an unusual behavior and not understood. term verification test condition at 0.01 rad(Si)/s to compare with the two dose rate test condition should be performed to accelerated two rate method. With this accelerated method, determine how well the proposed test method bounds device the testing can be completed in a more manageable, albeit performance. still long, time. Several general observations can be made: 1) Significant parametric degradation or functional failure was observed at VII. REFERENCES fairly high total dose levels (50 to 150 krad(Si)) for almost [1] MIL-STD-883G Test Method Standard, Microcircuits, Department of half of the parts studied. This behavior rules out the use of Defense, Defense Supply Center Columbus, Columbus, OH, February trend data to extrapolate LDR performance by using an 28, 2006. [2] S.C. Witczak, R.D. Schrimpf, D.M. Fleetwood, K.F. Galloway, R.C. enhancement factor on the HDR performance data. In other Lacoe, D.C. Mayer, J.M. Puhl, R.L. Pease, J.S. Suehle, “Hardness words, mission assurance test methods must include LDR Assurance Testing of Bipolar Junction Transistors at Elevated testing to levels greater than the mission dose (with RDF) in Temperatures,” IEEE Trans. Nucl Sci., NS-44, p. 1989, 1997. [3] R.L. Pease, L.M. Cohn, D.M. Fleetwood, M.A. Gehlhausen, T.L. order to bound device performance. 2) No obvious change in Turflinger, D.B. Brown, and A.H. Johnston, “A Proposed Hardness degradation rate is observed when LDR dose rate is increased Assurance Test Methodology for Bipolar Linear Circuits and Devices from 0.01 to 0.04 rad(Si)/s. This is an indication that the test in a Space Ionizing Radiation Environment,” IEEE Trans. Nucl Sci., NS-44, p. 1981, 1997. method might also provide a bounding test condition for high [4] J. Boch, Y. Gonzalez Velo, F. Saigné, N. J.-H. Roche, R. D. Schrimpf, dose missions where the dose rate is even lower than the J.-R. Vaillé, L. Dusseau, C. Chatry, E. Lorfèvre, R. Ecoffet, and scenario imagined here. However, additional rate comparison A. D. Touboul, “The use of a dose-rate switching technique to characterize bipolar devices,” Trans. Nucl Sci., NS-56, p. 3347, 2009. testing would be required to verify this. 3) These results [5] R.L. Pease, M. Gehlhausen, J. Krieg, J. Titus, T. Turflinger, D. Emily, indicate the present extended test method would be a and L. Cohn, “Evaluation of proposed hardness assurance method for practical method for the characterization and RLAT testing bipolar linear circuits with enhanced low dose rate sensitivity for such an envisioned Europa mission. 4) Almost half of the (ELDRS),” IEEE Trans. Nucl Sci., NS-45, p. 2665, 1998. The Effects of ELDRS at Ultra-Low Dose Rates

Dakai Chen, Member, IEEE, James D. Forney, Ronald L. Pease, Fellow, IEEE, Anthony M. Phan, Martin A. Carts, Stephen R. Cox, Kirby Kruckmeyer, Member, IEEE, Sam Burns, Rafi Albarian, Bruce Holcombe, Bradley Little, James Salzman, Geraldine Chaumont, Herve Duperray, Al Ouellet, and Kenneth LaBel, Member, IEEE

Abstract—We present results on the effects on ELDRS at elevated temperature method is inconsistent across a variety dose rates of 10, 5, 1, and 0.5 mrad(Si)/s for a variety of of devices, for example the LM2941 [4]. The switched-dose radiation hardened and commercial devices. We observed low rate method has several issues including the large number of dose rate enhancement below 10 mrad(Si)/s in several different samples required, and the difficulty in finding the transition parts. The magnitudes of the dose rate effects vary. The dose from the threshold degradation region to the power-law TL750L, a commercial voltage regulator, showed dose rate dependence in the functional failures, with initial failures region [3]. The current U.S. military test standard, MIL-STD- occurring after 10 krad(Si) for the parts irradiated at 0.5 883G TEST METHOD 1019.8, requires irradiating bipolar mrad(Si)/s. The RH1021 showed an increase in low dose rate circuits at a minimum dose rate of 10 mrad(Si)/s. The low enhancement by 2× at 5 mrad(Si)/s relative to 8 mrad(Si)/s and dose rate enhancement factor (LDR EF), which is the ratio of high dose rate, and parametric failure after 100 krad(Si). the relative degradation at low and high dose rate, is a Additionally the ELDRS-free devices, such as the LM158 and standard figure-of-merit for ELDRS. The part is considered LM117, showed evidence of dose rate sensitivity in parametric ELDRS sensitive if the EF for any parameter is > 1.5, as degradations. Several other parts also displayed dose rate specified in TM1019. enhancement, with relatively lower degradations up to ~ 15 to 20 However the saturation dose rate for parametric krad(Si). The magnitudes of the dose rate enhancement will likely increase in significance at higher total dose levels. degradation varies for different parts. In fact, many linear bipolar devices exhibit significant degradation for dose rates I. INTRODUCTION less than 10 mrad(Si)/s [1], [5]. For example, the LDR EF for the LM324 increases by a factor of 6 from 5 mrad(Si)/s (EF = inear bipolar circuits are known to exhibit enhanced-low- 2) to 2 mrad(Si)/s (EF = 12). Such a large increase in Ldose-rate-sensitivity (ELDRS) in an ionizing radiation degradation will exceed the ×1.5 overtest factor for 10 environment. The physical mechanisms for ELDRS have mrad(Si)/s irradiations, as stated in TM1019.8. been discussed in several previous publications [1], [2]. Manufacturers have since produced parts that are tolerant ELDRS has introduced new challenges for radiation hardness at low dose rate environments. The ELDRS-free parts, such assurance. The primary challenge is the significant irradiation as the LM136 voltage reference, can exhibit less degradation time required to examine a part for ELDRS, which is a at low dose rate (10 mrad(Si)) than at high dose rate [6]. But burden to a project’s schedule and budget. There are several the critical question is how the ELDRS-free parts will proposed accelerated tests, such as the elevated temperature respond at lower dose rates. There have been several recent irradiation and the switched-dose rate method [1], [3]. The studies on the role of hydrogen to low dose rate sensitivity [3], [5], [6]. Hydrogen contamination from certain packaging can enhance the effects of ELDRS [8]. These studies lead to ______the suggestion that the transition point for exhibiting ELDRS

Manuscript received on July 15, 2010. is moved to lower dose rates. Therefore while the ELDRS- This work is supported in part by the NASA Electronics Parts and free parts are guaranteed to function within specification at Packaging program (NEPP) and the Defense Threat Reduction Agency 10 mrad(Si), the degradation may increase significantly at (DTRA) under IACRO#09-4587I. lower dose rates. Dakai Chen, James Forney, Martin Carts, and Anthony Phan are with MEI Technologies Inc., c/o NASA/GSFC, Greenbelt, MD, USA 20771 The perpetual introduction of new devices, with various (phone: 301-286-8595, e-mail: [email protected]). innovative processes and circuit designs, necessitates the Ronald Pease is with RLP Research RLP Research, 8 Songbird Lane, understanding of the different degradation behaviors at ultra- Los Lunas, NM 87031 (email: [email protected]). low dose rates. Here we examine the effects of ELDRS for a Kirby Kruckmeyer is with National Semiconductor, 2900 Semiconductor Dr., Santa Clara, CA 95052 (email: large sample of commercial and radiation hardened devices [email protected]) from different manufacturers, at dose rates of 10, 5, 1, and 0.5 Stephen Cox and Kenneth LaBel are with NASA/GSFC, Greenbelt, mrad(Si)/s. MD, USA 20771 (email: [email protected]). Samuel Burns and Rafi Albarian are with Linear Technology Corp., XPERIMENTAL ETAILS Milpitas, CA, USA 95035 (email: [email protected], II. E D [email protected]). Bruce Holcombe, Bradley Little, and James Salzman are with Texas We examine more than twenty different parts from Instruments, Inc., 6412 Highway 75 South, Sherman, Texas, USA75090 Linear Technology, Texas Instruments, National (email: [email protected]). Geraldine Chaumont and Herve Duperray are with ST Semiconductor, and ST Microelectronics. The various part Microelectronics, Inc., 3 rue de Suisse – CS 60816, F-35208 Rennes types include voltage reference, voltage regulator, operational Cedex 2, France (email: [email protected]). amplifiers, and voltage comparators. They include radiation Al Ouellet is with ST Microelectronics, Inc., 10 Maguire Rd., hardened (lot tested at high dose rate), ELDRS-free (lot tested Lexington, MA 02421 (email: [email protected]). at 10 mrad(Si)/s), and commercial devices. The parts are

Part Number (package type) Lot-Date-Code Function Irradiation Bias Summary of Results

Texas Instruments LT1009IDR • Parameters within specification after 100, 30, and 15 0606 2.5V internal reference All pins grounded (8-SOIC) krad(Si) for the 5, 1, and 0.5 mrad(Si) parts. • Parameters within specification after 80, 20, and 15 LM317KTTR Positive volt reg 3- 0608 All pins grounded krad(Si) for the 5, 1, and 0.5 mrad(Si) parts. (3-DDPAK) terminal • LDR enhancement: 5 − 0.5 mrad(Si)/s • LDR enhancement for functional failures. TL750L05CDR LDO positive voltage 5 mrad(Si)/s: 35 < V < 40 krad(Si) 0605 All pins grounded out (8-pin plastic SOIC) reg 5V 1 mrad(Si)/s: 10 < Vout < 15 krad(Si) 0.5 mrad(Si)/s: 7.5 < Vout < 10 krad(Si).

• Vout failure levels (IO = 10 mA) TL750M05CKTRR 5 mrad(Si)/s: 70 < V < 80 krad(Si) 0707 LDO voltage regulator All pins grounded out (TO263-3) 1 mrad(Si)/s: > 20 krad(Si) 0.5 mrad(Si)/s: > 15 krad(Si). National Semiconductor • LDR enhancement observed for V degradation. LM117HRQMLV ref 7D5867L019 Voltage comparator All pins grounded • (TO-39 metal can) Parameters within specification after 90, 20, and 15 krad(Si) for the 5, 1, and 0.5 mrad(Si)/s parts. LM158AJRLQMLV • LDR enhancement: 5 − 0.5 mrad(Si)/s. 7W4453G019 Op-Amp All pins grounded (8-lead CERDIP) 5 mrad(Si)/s (1 part): 60 < Ib < 70 krad(Si).

LM136 • Parameters within specification after 100, 20, and 10 200746K019 Voltage Reference 2.5 All pins grounded (3-lead TO-46) krad(Si) for the 5, 1, and 0.5 mrad(Si) devices. LM124AJRQMLV 9R5469G019 Operational amplifier Biased and grounded In progress (14-lead CERDIP) LM139AWRQMLV JM046X13 Voltage comparator Biased and grounded In progress (14-lead CERDIP) Linear Technology RH1013MH 0329A (TO-5 metal can) • Parameters within specification after 100, 20, and 10 Dual precision op-amp Biased and grounded RH1013MJ8 krad(Si) for 5, 1, and 0.5 mrad(Si). 0305A (Ceramic DIP) RH1021CMH-5 9783A • LDR enhancement: 5 mrad(Si)/s. (TO-5 can) Precision 5V Reference All pins grounded 5 mrad(Si) (TO-5): 90 < V < 100 krad(Si). RH1021CMW-5 (Flatpack) 0123A z RH1009MW 0649A • ELDRS observed. (Flatpack) 2.5V Reference All pins grounded 5 mrad(Si)/s TO-46 cans: 80 < Vz < 90 krad(Si) RH1009MH (TO-46 can) 0829H 5 mrad(Si)/s Flatpacks: 100 < Vz < 120 krad(Si). RH1078MW 0741A Single supply, precision (Glass sealed Flatpack) Biased and grounded In progress op-amp RH1078MH (TO5 metal can) 0325A ST Microelectronics RHFL4913ESY332 30828A (TO-257) • Negligible degradations levels. Parameters within Voltage regulator All pins grounded specification after 10 and 13 krad(Si) for the 10 and 1 RHFL4913KP332 (Flat-16) 30814B mrad(Si) devices.

RH310 (Ceramic Flat-8) 30849A Operational amplifier Biased and grounded In progress Precision single RHF43B (Ceramic Flat-8) 30820A Biased and grounded In progress operational amplifier available in a variety of package types: ceramic, flatpack, 0.5 mrad(Si)/s. Four to five samples of each part are metal can, and dual-inline-package (DIP). In some cases the irradiated for each dose rate. At least two samples of each same part is available in both flatpack/DIP and metal can part are used as controls. Most of the parts, including voltage packages. regulators and references, are irradiated with all pins The irradiations are performed with a 60Co gamma ray grounded. The operational amplifiers and voltage source at room temperature. The dose rates are 10, 5, 1, and

Fig. 1. Average input bias current (3 parts with 2 devices each) vs. TID Fig. 2. Change in the input bias current vs. dose-rates at various TID levels for the LM158 operational amplifier from National Semiconductor from 2.5 to 20 krad(Si) for the LM158 operational amplifier from National irradiated with all pins grounded. Semiconductor. comparators are irradiated with both biased and unbiased (all device increases to beyond specification (> 50 nA) after 70 pins grounded) conditions. krad(Si). We characterized the electrical parameters onsite, with Figure 2 shows the change in Ib with dose rate at the exception of the devices from National Semiconductor, different TID levels. We observed dose rate enhancement in which were also shipped back to the manufacturer’s testing the Ib degradation after 15 krad(Si), where the degradation facility at select doses. The test and bias circuits, where increases with decreasing dose rate. In general, the LDR EF applicable, were fabricated in-house. We used the Agilent for Ib is less than 1, but increases with TID. The average EF 6624 power supply, the HP34401 digital multimeter, and the for the 5 mrad(Si)/s devices increases to 1.2 after 70 krad(Si), Keithley 2425 source meter to characterize the RHF4913 and owing to the enhanced degradation of one part. We will LM117 voltage regulators. We also used the HP34401 and realize the significance of the dose rate enhancement at Agilent 33250A waveform generator to characterize the higher TID levels. CMRR and open loop gain for the operational amplifiers. In addition we used the Agilent 4156 and Keithley 4200 B. RH1021 parameter analyzer to characterize all other parts. We used DC characterization to measure any DC parameter, whereas The RH1021 is a voltage reference from Linear for some parts the parametric specifications were obtained Technology previously qualified at high dose rate. We using the manufacture’s specific pulse techniques. evaluate two package types: RH1021CMH (TO-5 metal cans) and RH1021CMW (10-lead ceramic flatpacks). Figure 3 III. RESULTS shows the reference voltage (Vref) with increasing TID at 5 and 8 mrad(Si)/s, and at high dose rate for the TO-5 Table I. is a list of all devices under investigation. The packages. The 8 mrad(Si)/s and high dose rate data show table includes the part number, package type, lot-date-code, similar levels of degradation. However the 5 mrad(Si)/s part function, bias configuration, and a short summary of response showed significantly higher degradation. The LDR results. Here we show highlight results from several select EF increases by a factor of 2 after 30 krad(Si). Therefore the parts. part is ELDRS sensitive at ≤ 5 mrad(Si)/s. The reference voltage failed specification after 100 krad(Si). A. LM158A We also found that the TO-5 packages degraded more significantly than the flatpacks at dose rates of 5, 1, and 0.5 The LM158AJRQMLV is an ELDRS-free low power mrad(Si)/s. Figure 4 compares the two package types at 5 dual operational amplifier manufactured by National mrad(Si)/s. The results indicate that the flatpack devices here Semiconductor, qualified up to 100 krad(Si) at 10 mrad(Si)/s. do not exhibit hydrogen contamination effects that can Figure 1 shows the average input bias current (Ib) vs. total enhance ELDRS [8]. dose at various dose rates. The input bias current is the average of the positive and negative input currents on one C. TL750L device for all parts. The error bars indicate part-to-part variation. There is minimal device-to-device variation within The TL750L05CDR is a commercial low-dropout a package. We note that the increasing error bars for the 5 voltage regulator manufactured by Texas Instruments. We mrad(Si)/s data is due to one part showing significant observed distinct dose rate dependence for the functional degradation relative to the other two parts. The Ib of the rogue failures. The initial failures occur after 40, 20, and 10

Fig. 3. Reference voltage vs. TID at different dose rates for the Fig. 4. The change in reference voltage vs. TID for the RH1021 voltage RH1021CMH-5 voltage reference from Linear Technology, irradiated reference in TO-5 cans and Flatpacks, irradiated at 5 mrad(Si)/s with all with all pins grounded. pins grounded.

Fig. 5. Number of part failures vs. TID at different dose rates for the Fig. 6. Change in reference voltage vs. TID for the LM117 adjustable TL750L voltage regulator from Texas Instruments, irradiated with all voltage regulator irradiated at 5, 1, and 0.5 mrad(Si)/s pins grounded. krad(Si) for the 5, 1, and 0.5 mrad(Si)/s parts, respectively. Figure 5 shows the number of part failures (from 4 parts at D. LM117H each dose rate) vs. total dose. The functional failures are characterized by the failure of the output voltage (Vout) to The LM117HRQMLV is an ELDRS-free adjustable regulate with 100 mA load, while remaining functional with positive voltage regulator manufactured by National 10 mA load. In most cases the part fails to regulate with 10 Semiconductor, qualified up to 100 krad(Si) at 10 mrad(Si)/s. mA load at the next dose step. Figure 6 shows the change in the reference voltage (Vin = 40 The failures were abrupt, without gradual degradation to V and Iout = 10 mA) with TID at different dose rates,. Figure the output voltage or any other measured parameter. The 7 shows the dose at which the reference voltage degrades degradation behavior is similar to the 29372 low-dropout beyond the pre-irradiation specification (Vref = 1.3 V). We regulator from a previous study [9]. The output voltage failed observed dose rate dependence for the dose at which Vref to regulate the preset load, as the maximum output drive exceeds the pre-irradiation specification: 20, 15 and 10 current degrades with total dose [9]. Consequently the output krad(Si) for the 5, 1, and 0.5 mrad(Si)/s parts. The post- failed to regulate for the 100 mA load prior to failure with the irradiation specification limit for the reference voltage is 1.35 10 mA load. V. The dose rate enhancement will likely become more It is also possible that the radiation-induced leakage evident at higher TID levels. current becomes significant, so that the internal current limiting protection circuitry shuts down the device. This is E. LM317 consistent with the fact that the failed devices do not draw any current. The 10 mrad(Si)/s irradiations are currently in The LM317KTTR is a commercial adjustable voltage process. regulator manufactured by Texas Instruments. The parts are

Fig. 7. Dose that Vref exceeds pre-irradiation limit (Vref = 1.3 V) vs. dose Fig. 8. Average output voltage vs. TID for the LM317 adjustable voltage rate for the LM117 adjustable voltage regulator.. regulator irradiated at 5, 1, and 0.5 mrad(Si)/s

Fig. 9. Change in the output voltage vs. dose rate at 15 krad(Si) for the Fig. 10. Average reference voltage vs. TID for the LM117 adjustable LM317 adjustable voltage regulator operating with 80 and 800 mA voltage regulator irradiated at 5, 1, and 0.5 mrad(Si)/s. output load. grounded during irradiation. The device parameters, increases to ~ 13 for the TO-46 devices after 90 krad(Si). The including the output voltage, line and load regulations, are average reverse breakdown voltage exceeds specification within specification at this stage of the irradiation. Figure 8 (2.495 V) after 90 krad(Si) for the TO-46 packages. shows the change in Vout with Vin = 40 V and Iout = 80 mA. Therefore the results indicate that these devices are The output voltage decreases with increasing TID. Figure 9 susceptible to ELDRS at 5 mrad(Si)/s. shows the change in Vout as a function of dose rate at 15 Additionally, the TO-46 and flatpacks exhibit opposing krad(Si). We observed dose rate enhancement in the Vout degradation trends. The TO-46 devices showed decreasing degradation. The dose rate enhancement is significantly (negative-going) Vout, while the flatpack devices show higher with the larger output load (Iout = 800 mA). increasing (positive-going) Vout with TID. The device packaging may have affected the different degradation F. RH1009 behaviors. However we also observed increasing Vout for the 1 and 0.5 mrad(Si)/s TO-46 parts. Therefore the different Figure 10 shows the reverse breakdown voltage vs. total behaviors of the package types at 5 mrad(Si)/s are more likely dose for the RH1009 voltage reference manufactured by due to part-to-part variation. Linear Technology. Two types of packages are included: RH1009MH (TO-46 metal can) and RH1009MW (ceramic IV. CONCLUSION flatpack). Figure 10 also contains data from high dose rate results on parts from the same date code. We observed We have presented results of the effects of ELDRS for a enhanced degradation for the 5 mrad(Si)/s data relative to the variety of radiation hardened and commercial devices, at dose high dose rate data. The LDR EF = 4.2 and 3.6 for the TO-46 rates varying from 10 to 0.5 mrad(Si)/s. We observed low cans and flatpacks, respectively, after 50 krad(Si). The EF dose rate enhancement in several parts, where the degradation increases with decreasing dose rate to as low as 0.5 mrad(Si)/s. The degradation enhancement is severe for some parts. For example the TL750L exhibited dose rate enhancement for the functional failures. The initial failures occur after 10 krad(Si) at 0.5 mrad(Si)/s. While the RH1021 displayed similar degradation levels at ~ 8 mrad(Si)/s as at high dose rate, the low dose rate EF increased by a factor of 2 at 5 mrad(Si)/s, after 30 krad(Si). Parametric failure occurs after 100 krad(Si). The cases presented here, in addition to previous examples in [1], illustrate the significance and pervasiveness of low dose rate enhancement at dose rates lower than 10 mrad(Si). The ELDRS-free devices, as shown for the LM158 and LM117, are also susceptible to enhanced degradation at the lower dose rates. The low dose rate EF for the devices that exhibit dose rate enhancement will likely continue to increase with increasing total dose, until we establish the transition dose for exhibiting ELDRS (EF = 1.5), followed by the damage saturation point. These results present further challenges for radiation hardness assurance of bipolar linear circuits.

V. ACKNOWLEDGEMENT

This work was supported in part by the NASA Electronic Parts and Packaging Program (NEPP) and the Defense Threat Reduction Agency (DTRA) under IACRO# 10-4977I. The authors would like to thank Tom Ward and Yevgeniy Geraschenko for organizing the radiation schedule.

VI. REFERENCES

[1] R. L. Pease, R. D. Schrimpf, and D. M. Fleetwood, “ELDRS in bipolar linear circuits: a review,” IEEE Trans. Nuc. Sci., vol. 56, Aug. 2009, pp. 1894 – 1908. [2] D. M. Fleetwood, S. L. Kosier, R. N. Nowlin, R. D. Schrimpf, R. A. Reber, Jr., M. DeLaus, P. S. Winokur, A. Wei, W. E. Combs, and R. L. Pease, “Physical mechanisms contributing to enhanced bipolar gain degradation at low dose rates,” IEEE Trans. Nuc. Sci., vol. 41, Dec. 1994, pp. 1871 – 1885. [3] J. Boch, Y. G. Velo, F. Saigne, N. J.-H. Roche, R. D. Schrimpf, J-R. Vaille, L. Dusseau, C. Chatry, E. Lorfevre, R. Ecoffet, and A. D. Touboul, “The use of a dose-rate switching technique to characterize bipolar devices,” IEEE Trans. Nuc. Sci., vol. 51, Oct. 2004, pp. 2896 – 2902. [4] W. Abare, F. Brueggman, R. Pease, J. Krieg, and M. Simons, “Comparative analysis of low dose-rate, accelerated, and standard cobalt-60 radiation response data for a low-dropout voltage regulator and a voltage reference,” 2000 IEEE Radiation Effects Data Workshop Record, pp. 177-180. [5] A. H. Johnston, G. M. Swift, and B. G. Rax, “Total dose effects in conventional bipolar transistors and linear integrated circuits,” IEEE Trans. Nuc. Sci., vol. 41, Dec. 1994, pp. 2427 – 2436. [6] R. L. Pease et al., “The Effects of Hydrogen on the Enhanced Low Dose Rate Sensitivity (ELDRS) of Bipolar Linear Circuits,” IEEE Trans. Nuc. Sci., vol. 55, Dec. 2008, pp. 3169 – 3173. [7] K. Kruckmeyer, L. McGee, B. Brown, and L. Miller, “Low dose rate test results for National Semiconductor’s ELDRS-free LM136-2.5 bipolar reference,” IEEE Radiation Effects Data Workshop, Jul. 2009, pp. 47 – 50. [8] R. L. Pease, G. W. Dunham, J. E. Seiler, D. G. Platteter, and S. McClure, “Total dose and dose rate response of an AD590 temperature transducer,” IEEE Trans. Nuc. Sci., vol. 54, Aug. 2007, pp. 1049 – 1054. [9] R. L. Pease, S. McClure, J. Gorelick, and S. C. Witczak, “Enhanced low-dose-rate sensitivity of a low-dropout voltage regulator,” IEEE Trans. Nuc. Sci., vol. 45, Dec 1998, pp. 2571 – 2578.

Total Ionizing Dose and Displacement Damage Compendium of Candidate Spacecraft Electronics for NASA

Donna J. Cochran, Dakai Chen, Timothy R. Oldham, Anthony B. Sanders, Hak S. Kim, Michael J. Campola, Stephen P. Buchner, Kenneth A. LaBel, Cheryl J. Marshall, Jonathan A. Pellish, Martin A. Carts, and Martha V. O’Bryan

Abstract-- Vulnerability of a variety of candidate spacecraft A. Test Methods – TID electronics to total ionizing dose and displacement damage is TID testing was performed according to the MIL-STD- studied. Devices tested include optoelectronics, digital, analog, 883 1019.8 test method unless otherwise noted. [2] linear bipolar devices, and hybrid devices. B. Test Methods – Proton Index Terms- Displacement Damage, Optoelectronics, Proton Proton damage tests were performed on biased devices. Damage, Single Event Effects, and Total Ionizing Dose. Functionality and parametrics were measured either continually during irradiation (in-situ) or after step I. INTRODUCTION irradiations (for example: every 10krad(Si), or every 1x1010 Long-term radiation induced failure modes play a protons/cm2). Table I lists the proton damage test facilities significant role in determining space system reliability. As and energies used on the devices. such, the effects of total ionizing dose (TID) needs to be evaluated in order to determine risk to space projects. TABLE I The test results presented here were gathered to establish PROTON TEST FACILITIES Proton Energy, the sensitivity of candidate spacecraft electronics to TID. Facility (MeV) This testing serves to determine the appropriateness of a University of California at Davis ~ 63 candidate device which may be used in space applications. Crocker Nuclear Laboratory (UCD-CNL) For similar results on single event effects (SEE), a companion paper has also been submitted to the 2010 IEEE III. TEST RESULTS OVERVIEW NSREC Radiation Effects Data Workshop entitled: “Current Abbreviations for principal investigators (PIs) are listed in Single Event Effects Compendium of Candidate Spacecraft Table II. Abbreviations and conventions are listed in Table Electronics for NASA” by M. O’Bryan, et al [1]. III. Please note that these test results can depend on operational conditions. Complete test reports are available II. TEST TECHNIQUES AND SETUP online at http://radhome.gsfc.nasa.gov [3]. Unless otherwise noted, all tests were performed at room temperature and with nominal power supply voltages. TABLE II LIST OF PRINCIPAL INVESTIGATORS Abbreviation Principal Investigator (PI) SB Stephen Buchner MaC Martin Carts MiC Michael Campola This work was supported in part by the NASA Electronic Parts and DC Dakai Chen Packaging Program (NEPP), NASA Flight Projects, and the Defense Threat HK Hak Kim Reduction Agency (DTRA) under IACRO# 09-4587I and 10-4977I. KL Kenneth LaBel Donna J. Cochran, MEI Technologies, Inc., c/o NASA Goddard Space CM Cheryl Marshall Flight Center (GSFC), Code 561.4, Bldg. 22, Rm. 062A, Greenbelt, MD 20771 (USA), phone: 301-286-8258, fax: 301-286-4699, email: TO Timothy Oldham [email protected] JP Jonathan Pellish Dakai Chen, MEI Technologies, Inc., c/o NASA/GSFC, Code 561.4, AS Anthony Sanders Greenbelt, MD 20771 (USA), phone: 301-286-8595, email: MX Michael Xapsos [email protected] Timothy R. Oldham is with Dell Perot Systems Government Services, Inc., c/o NASA/GSFC, Code 561.4, Greenbelt, MD 20771 (USA), phone: 301-286-5489, email: [email protected] Hak S. Kim, Michael J. Campola, and Martha V. O’Bryan are with MEI Technologies, Inc., c/o NASA Goddard Space Flight Center (GSFC). Anthony B. Sanders, Kenneth A. LaBel, Cheryl J. Marshall, Jonathan A. Pellish, and Martin A. Carts are with NASA/GSFC, Code 561.4, Greenbelt, MD 20771 (USA), phone:301-286-8046 (Sanders), 301-286-9936 (LaBel), email: [email protected], [email protected]. Stephen P. Buchner is with Global Defense Technology and Systems, Inc., phone: 202-404-2352, email: [email protected]

TABLE III ABBREVIATIONS AND CONVENTIONS ACRONYM/ DEFINITION ACRONYM/ DEFINITION A = amp P+ = protons ASIC = application specific integrated circuit N/A = not available CMOS = complementary metal oxide semiconductor NMRC = National Microelectronics Research DD = Displacement Damage Centre DIP = dual inline package PI = principal investigator DNL = Differential Non-Linearity ROIC = Read Out Integrated Circuit ELDRS = Enhanced Low Dose Rate Sensitivity SEE - single event effects FET = field effect transistor Spec = specifications Ib = bias current TID = total ionizing dose Ic = collector current Vbias = bias voltage Icc= power supply current Vcc = power supply voltage If = forward current Vce = collector emitter voltage INL = Integral Non-Linearity VCO = voltage-controlled oscillator Ios = offset current Vdo = dropout voltage Iout = output current VENABLE = enable voltage ISTDBY = standby current Vos = offset voltage IUCF = Indiana University Cyclotron Facility VOL = output saturation voltage LDC = lot date code Vout = output voltage MeV = mega electron volt Vref = reference voltage mA = milli amp Vz = reverse breakdown voltage op amp = operational amplifier

TABLE IV SUMMARY OF TID AND DD TEST RESULTS

Part

Technology/ Manufacturer LDC Date/PI Summary of Results Number Device Function

Dose rate Test (Y/N) Test App. Spec. Spec. App. Deg. Level Level Deg. (rads(Si)/s) (rads(Si)/s) (krads (Si)) (Si)) (krads

Data Converters

Differential Non-Linearity (DNL) exceed specs for Digital to Analog two parts between 10 & 20 krad(Si). Integral Non- 10

Linear Power Amplifier/ Input offset voltage for two parts exceeded PA10 Apex 60024 APR09/SB N 0.01 30< V <40 Linear Bipolar specifications. os Tested to verify operation over elevated temperature Texas Voltage Regulator/ (30ºC, 55ºC, 75ºC), part’s supply current, adjust LM317 39600 APR09/MiC Y 10 >100 Instruments Linear Bipolar current, and output voltage stayed within specification. 2.5V internal 0.005 Vz >100 Texas V degrades with TID. Parameters within LT1009IDR 0606 reference/ JUNE09/DC z N 0.001 Vz >100 Instruments specification for all dose rates. (on-going) Linear Bipolar 0.0005 Vz >100 Positive volt reg 0.005 Vout >80 Texas LM317KTTR 0608 3-terminal/ JUNE09/DC V shows dose rate enhancement. (on-going) N 0.001 Vout >20 Instruments out Linear Bipolar 0.0005 Vout >15

0.005 Vout <20 LM117HRQMLV 7D5867L01 Comparator/ Natl Semi JUNE09/DC V shows dose rate enhancement. (on-going) N 0.001 Vref <15 (TO-39 metal can) 9 Linear Bipolar out 0.0005 Vref <10

0.01 Ib >100 LM158AJRLQMLV 7W4453G01 Op Amp/ 0.005 60 < Ib <70 Natl Semi JUNE09/DC Ib shows dose rate dependence. (on-going) N (8-lead CERDIP) 9 Linear Bipolar 0.001 Ib >30 0.0005 Ib >15 0.005 Vz >100 LM136 (3-lead TO- Voltage Reference V degrades with TID. Within specification for all Natl Semi 200746K019 JUNE09/DC z N 0.001 Vz >20 46) 2.5/Linear Bipolar dose rates. (on-going) 0.0005 Vz >10 RH1013MH 0329A/9513 Dual precision I degrades with TID.Parameters within 0.005 I >80 (TO5 metal can) Linear A b b op-amp/Linear JUNE09/DC specification for different dose rates and package N RH1013MJ8 Technology 0305A/0337 Bipolar types. (can and DIP). (on-going) 0.005 I >80 (Ceramic DIP) A b 0.005 Vz >90 RH1021CMW-5 Linear Precision 5V 5 mrad(Si)/s show enhanced degradation to V 0123A JUNE09/DC z N 0.001 Vz >20 (Flatpack) Technology Reference/Linear relative to 8 mrad(Si)/s. (on-going) 0.0005 Vz >10

Part

Technology/ Manufacturer LDC Date/PI Summary of Results Number Device Function

Dose rate Test (Y/N) Test App. Spec. Spec. App. Deg. Level Level Deg. (rads(Si)/s) (rads(Si)/s) (krads (Si)) (Si)) (krads

Precision 5V 0.005 80 20 (TO-5 can) Technology cans. (on-going) Bipolar 0.0005 Vz >10

0.005 100 20 (Flatpack) Technology Linear Bipolar rate. (on-going) 0.0005 Vz >10

0.005 80 20 (TO-46 can) Technology Linear Bipolar rate. (on-going) 0.0005 Vz >10

RHFL4913ESY332 ST Voltage Regulator/ We have observed negligible degradation. 0.001 Vout >10 30828A JUNE09/DC N (TO257) Microelectronics Linear Bipolar Parameters within specification. (on-going) 0.0005 Vout >13 RHFL4913KP332 ST Voltage Regulator/ We have observed negligible degradation. 0.01 Vout >10 30814B JUNE09/DC N (Flat-16) Microelectronics Linear Bipolar Parameters within specification. (on-going) 0.001 Vout >13 Memory K9F4G08UOA- CMOS/ No errors @100 krad (Si), errors but functional Samsung 0840 MAY09/TO/AS N 12 >100 PCB0 4Gb NAND Flash @125 krad(Si), functional failure @150 krad(Si). K9F4G08UOA- CMOS/ No errors @ 100 krad(Si), errors but functional Samsung 0843 MAY09/TO/AS N 12 >100 PCB0 4Gb NAND Flash @ 125 krad(Si), functional failure @ 150 krad(Si). K9F4G08UOA- CMOS/ No errors @ 125 krad(Si), errors but functional Samsung 0846 MAY09/TO/AS N 12 >125 PCB0 4Gb NAND Flash @ 150 krad(Si), functional failure @ 175 krad(Si). K9F4G08UOA- CMOS/ No errors @ 125 krad(Si), errors but functional Samsung 0901 MAY09/TO/AS N 12 >125 PCB0 4Gb NAND Flash @ 150 krad(Si), functional failure @ 175 krad(Si). K9F4G08UOA- CMOS/ No errors @ 125 krad(Si), errors but functional Samsung 0907 MAY09/TO/AS N 12 >125 PCB0 4Gb NAND Flash @ 150 krad(Si), functional failure @ 225 krad(Si). A commercial sample of a 90nm CMOS phase change non-volatile memory was tested for TID tolerance using a nominal 30 rads(Si)/sec dose rate 90 nm CMOS/ at room temperature. Samples were biased during Phase Change N/A N/A N/A NOV09/KL/HK irradiation and tested in step dose level increments N 30 >300 Non-Volatile then tested for functional operation (read, write, Memory erase with checkerboard and inverse checkerboard patterns). No degradation was noted to the maximum tested level of 300 krad(Si).

Part

Technology/ Manufacturer LDC Date/PI Summary of Results Number Device Function

Dose rate Test (Y/N) Test App. Spec. Spec. App. Deg. Level Level Deg. (rads(Si)/s) (rads(Si)/s) (krads (Si)) (Si)) (krads

Miscellaneous Complex 45nm processor was tested for TID tolerance using a nominal 30 rads/sec dose rate at room temperature. Samples were biased during irradiation and tested in step dose level increments Complex 45nm 45 nm CMOS/ then shipped via dry ice to an off-site test N/A N/A 09/KL/MaC N 30 >1000 Processor Processor organization for full parametric characterization within a 48 hour period. Functionality was checked on these devices prior to shipping. No degradation was noted to the maximum tested level of 1 Mrad(Si). Complex 65nm processor was tested for TID tolerance using a nominal 30 rads/sec dose rate at room temperature. Samples were biased during irradiation and tested in step dose level increments Complex 65nm 65 nm CMOS/ then shipped via dry ice to an off-site test N/A N/A 08/KL/MaC N 30 >1000 Processor Processor organization for full parametric characterization within a 48 hour period. Functionality was checked on these devices prior to shipping. No degradation was noted to the maximum tested level of 1 Mrad(Si). Field Effect Tested to verify annealing at cold temperature (- RadFET NMRC 201 APR09/MiC Y 10 <100 Transistor/CMOS 55C). Threshold voltage shift, no failure. ROIC imaging during exposure. No significant 0.5 µm CMOS degradation at 40 K for bias currents and voltages, N/A N/A N/A ReadOut Integrated SEPT08/CM N 85 >35 at 40K dark current, noise, photo-response and base line Circuit (ROIC) levels. * Proton test performed:

No significant degradation in ROIC parameters that respond to TID and DD for bias currents and InGaAsP QWIP & voltages, dark current, noise, photo-response and 0.5 µm CMOS/ base line levels. An increase in hot pixels was Quantum Well CNL/08NOV/ observed in 1 DUT but room temperature annealing N/A N/A N/A N 85 ~15 Infrared Photo- CM was very effective. Transient study for ROIC and detector (QWIP) QWIP performed at 9 MeV and 63 MeV. Large Array & ROIC positive-going transients were seen to occur with the probability of ~10-6 per incident 63.3 MeV proton, corresponding to the approximate probability for a proton nuclear reaction event. Resulting single event functional interrupt may require power cycle.

Part

Technology/ Manufacturer LDC Date/PI Summary of Results Number Device Function

Dose rate Test (Y/N) Test App. Spec. Spec. App. Deg. Level Level Deg. (rads(Si)/s) (rads(Si)/s) (krads (Si)) (Si)) (krads Power LDO positive 0.005 Vout <40 Functional failures (V ) show dose rate TL750L05CDR Texas Instruments 0605 voltage reg 5V/ JUNE09/DC out N 0.001 Vout <15 dependence. (on-going) Linear Bopolar 0.0005 Vout <10 LDO positive V degrades with TID. Parameters within TL750M05CKTRR Texas Instruments 0707 voltage reg 5V/ JUNE09/DC out N 0.005 V >80 specification for I = 10 mA. (on-going) out Linear Bopolar out Minimal change in forward I-V, reverse I-V, and ST Power Diode/ STPSC806D 0818 NOV09/DC capacitance-voltage characteristics after N 6-17 >9000 Microelectronics SiC Substrate 9000 krad(Si). Minimal change in forward I-V, reverse I-V, and ST Power Diode/ STPSC1006D 0830 NOV09/DC capacitance-voltage characteristics after N 6-17 >9000 Microelectronics SiC Substrate 9000 krad(Si). Test Parts 65nm test Test Transistors Texas Instruments N/A MAR09/MX/JP No degradation observed. N 3.3 >300 transistors/CMOS IBM 5AM SiGe 5AM SiGe/ IBM Test Vehicle JUL09/JP Unexpected collector current shift during TID. [4] N 3.3 >1000 HBT 0.5x5 µm2 BiCMOS

IV. TEST RESULTS AND DISCUSSION making them promising candidates for most NASA As in our past workshop compendia of GSFC test missions. results, each DUT has a detailed test report available online at http://radhome.gsfc.nasa.gov [3] describing in further detail, test method, TID conditions/parameters, test results, and graphs of data. A. STPSC1006D/ ST Microelectronics/Power Diode The ST Microelectronics power diode STPSC1006D was tested for TID tolerance using a Co60 source. The power diodes are robust against TID up to highest tested level of 9 Mrad(Si). The reverse current showed slight increase from approximately 120 V to 250 V. The forward current-voltage and capacitance-voltage characteristics remain unchanged after irradiation. Thus there were minimal degradation to the diode’s physical and electrical Fig. 2. Samsung 4G NAND Flash TID Results. properties, including the Schottky contact, doping C. TL750L05CDR/ Texas Instruments/Voltage Regulator concentration, and series resistance. The TL750L05CDR is a commercial low-dropout voltage regulator manufactured by Texas Instruments tested for extreme enhanced low dose rate sensitivity (ELDRS) as research. Detailed description of the results for this part and other parts in the ELDRS study can be found in [5]. Fig. 3 shows average output voltage (from 4 parts at each dose rate) vs. TID. We observe distinct dose rate dependence for functional failures of the Vout. The initial failures occur after 40, 20, and 10 krad(Si) for the 5, 1, and 0.5 mrad(Si)/s parts, respectively. In the 5 mrad(Si)/s case, one part each failed after 40 and 50 krad(Si). Two parts failed after 80 krad(Si). In the 1 mrad(Si)/s case, two parts failed after 20 krad(Si), while two parts remain functional. In the 0.5 mrad(Si)/s case, two parts failed after 10 krad(Si), while two parts remain functional. The device failures are characterized by the Fig. 1. Reverse bias I-V characteristics for the STPSC1006D power diode pre-irradiation and after 9 Mrad(Si). functional failure of the output voltage. The parts failed abruptly, without gradual degradation to Vout or any other measured parameter. B. 4G NAND Flash/ Samsung TID results for the Samsung 4G NAND Flash are presented in Fig. 2. Twenty five samples were tested, five each from five different LDCs. Parts were exposed in a Co-60 source at the rate of 12 rad(Si)/sec. Nominal bias for these parts is 3.3 V, but testing was done at nominal VDD+10% (per TM 1019.8), or 3.6 V. Parts were biased , but not actively exercised during exposures. There were no errors in any part from any LDC at less than 100 krad(Si), which is sufficient for many NASA missions. At higher doses, there were some errors, which could be reset, however, the parts worked properly after being reset, until functional failure occurred, at 150-225 krad(Si), depending on LDC. The differences between LDCs were not large but measurable indicating one source of uncertainty when dealing with unhardened commercial technology. When functional failure occurred, it was due to the erase function Fig. 3. Average output voltage vs. TID for different dose rates failing in all cases. Although these parts represent for the TL750L voltage regulator, irradiated with all pins grounded. unhardened commercial technology, we note that their radiation tolerance is dramatically better than the nearest commercial equivalent parts from ten or fifteen years ago,

V. SUMMARY We have presented data from recent TID and proton- induced damage tests on a variety of primarily commercial devices. It is the authors' recommendation that this data be used with caution. We also highly recommend lot and application specific testing be performed on any suspect or commercial device.

VI. ACKNOWLEDGMENT The authors thank members of the Radiation Effects and Analysis Group (REAG) who contributed to the test results presented here, Craig Stauffer, Anthony M. Dung-Phan, Donald K. Hawkins, Martin A. Carts, James D. Forney, Tim Irwin, Christina M. Seidleck, Stephen R. Cox, Christopher Perez, and Mark Friendlich.

VII. REFERENCES [1] Martha V. O’Bryan, et al., "Current Single Event Effects Compendium of Candidate Spacecraft Electronics for NASA," submitted for publication in IEEE NSREC10 Data Workshop, July 2010. [2] Department of Defense "Test Method Standard Microcircuits," MIL-STD-883 Test Method 1019.8 Ionizing radiation (total dose) test procedure, September 30, 2006, http://www.dscc.dla.mil/ Downloads/MilSpec/Docs/MIL-STD-883/std883_1000.pdf [3] NASA/GSFC Radiation Effects and Analysis home page, http://radhome.gsfc.nasa.gov. [4] P. E. Cheng et al., IEEE TNS, vol. 56, no. 6, p. 3318, Dec. 2009. [5] Dakai Chen, et al., “The Effects of ELDRS at Ultra-low Dose Rates,” submitted for publication in IEEE NSREC10 Data Workshop, July 2010.

Comparison of TID Response of Micron Technology Single-Level Cell High Density NAND Flash Memories

Duc N. Nguyen, IEEE member, and Farokh Irom

high internal voltages that are needed for erase and write ABSTRACT - Total ionizing dose (TID) response for Micron operations. Technology single-level cell (SLC) 1 Gb, 2 Gb, 4 Gb and 8 Gb The NAND structure is more compact than NOR since it NAND flash memories are reported. Scaling effects in TID does not provide contacts to individual source and drain response is discussed. Floating gates bit error scales with feature regions. Memory cells in the NAND structure require reading size. Also, charge pump TID degradation and standby current and writing through the other cells in the stack. Data can be improves with scaling. interpreted as zero, "0", when charges (electrons) are placed in the floating gate. When electrons are removed from the Index Terms—non-volatile memory, single event upset, floating gate, data become one,"1". The configuration is single event effect, total ionizing, floating gate, single level. known as single level or one-bit per- cell storage since the read-out data can be identified either as "1" or "0". In terms of cell threshold voltage, sense-amp circuitry recognizes "1" I. INTRODUCTION optimally at the level of 2.7V and "0" at 5.7V. In order to Non-volatile memories are widely used in many obtain higher density, flash memory structures have been commercial as well as space applications. NAND flash scaled down in size. memories are attractive choices for the massive data recorder Flash memory cells are not as sensitive to data loss, or bit requirements for space missions. Previous solid state upsets induced by single event effects (SEE), compared to recorders were designed around reliable, robust and radiation those experienced by static random access memory (SRAMs) tolerant dynamic random access memories (DRAM) but and dynamic random access memory (DRAMs). Information current recorders for space missions are being built with on floating gates (FGs) is embedded by the presence or commercial-off-the-shelf flash memory. absence of trapped charge on an electrically isolated The overall architecture of flash memory is very complex. conductor. Nevertheless, flash memories are susceptible to Reading can be done relatively rapidly using conventional upset and degradation from radiation and more information is circuitry for access and readout. However, erasing and writing needed on their radiation characteristic before they can be are very slow operations (on the order of milliseconds) used in space. compared to conventional memories. To overcome this In evaluating flash memories for use in space, it is limitation, flash memories are subdivided into blocks, important to recognize how they will be used. Read mostly allowing erasing and writing to be done at the block level. applications such as code storage (replacing PROMS) are Internal registers and buffers provide temporary storage for natural fits because of the very slow write and erase time. In pages of data, allowing more transparent interface. A write these applications they might not be powered except for brief state machine and a command state machine are used to periods when it is necessary to read their contents. The devices control the complex sequences of operations that are needed. in this work were irradiated in either of two bias conditions: A charge-pump circuit is also required in order to provide the (1) static biased, where the device is powered, but no address cycling or data access operations are used; and (2) unbiased (all pins grounded). If the radiation tolerance is deemed acceptable by NASA flight projects, additional irradiations ______with more severe operational conditions (erasing and Manuscript received July 16, 2010. The research in this paper was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under .programming) will be under taken at a later time. contract with the National Aeronautics and Space Administration (NASA), Flash memories have been the subject of several ionizing under the NASA Electronic Parts and Packaging Program. radiation effects studies in recent years, regarding both total D. N. Nguyen is with the Jet Propulsion Laboratory, California Institute of ionizing dose (TID) and SEE [1-9] experiments. In both cases, Technology, Pasadena, CA 91109 (USA), phone: 818-354-8554, fax: 818- 393-1755, e-mail: [email protected] the complex control circuitry has been demonstrated to be the F. Irom is with the Jet Propulsion Laboratory, California Institute of most vulnerable part of commercial devices. The functionality Technology, Pasadena, CA 91109 (USA), phone: 818-354-7463, email: of flash memories begins to fail as TID accumulates during a [email protected] space mission. Older generations of flash memories

functionally failed during erase/write modes at approximately these measurements was three. TID measurements were 10 krad (Si) [1]. performed in following two modes: At present, the industry trend is to continue with feature- A. Refresh Mode (Erase/Program/Read): size scaling. Decreasing feature size improves the possibility of increasing density. Also, because of thinner oxide layers, a. Erase, write, and read to validate programmed numbers. the total dose response is improved, although the tunnel oxides b. Irradiate DUTs with static bias. have not been scaled as aggressively as other oxides, because c. Read numbers to ensure data retention. of concerns about retention [2]. The last several generations of d. Repeat steps a to c for each radiation increment. NAND flash memories have had only 7-10 nm tunnel oxides. High density commercial non-volatile flash memories with B. No Refresh Mode (Read Only): the NAND architecture are now available from different a. Erase, write, and read to validate programmed manufacturers. This paper examines TID response in Micron numbers. Technology single-level cell (SLC) 1 Gb, 2 Gb, 4 Gb and 8 b. Irradiate DUTs with static bias. Gb NAND flash memories. c. Read numbers to ensure data retention. d. Repeat steps b to c for each radiation increment. II. DEVICE DESCRIPTION The parts information are summarized in Table I. The parts IV. TEST RESULTS under study in this paper are nominally 3.3 V parts, with an allowed range of 2.7-3.6 V. A. Refresh Mode In general, a NAND structure consists of 32 cells. For SLC In Refresh Mode, three samples of each device were devices, a cell has 1-bit data, and 2,162,688 NAND cells irradiated until failure of charge pump. Table II reside in a block. The program and read operations are summarizes the TID levels that parts failed after the total executed on a page basis, while the erase operation is executed accumulated dose. on a block. TABLE II. TABLE I. SUMMARY OF TID JUST PRIOR TO CHARGE- PUMP FAILURE FOR MICRON PARTS INFORMATION. TECHNOLOGY SLC NAND FLASH MEMORY IN REFRESH MODE. Part Number Density Date Code Feature Size (Gb) (nm) Part TID level (krads) MT29F1G08AAC 1 0912 120 Micron SLC 1 Gb 55 MT29F2G08AAD 2 0902 90 Micron SLC 2 Gb 75 MT29F4G08AAC 4 0932 72 Micron SLC 4 Gb 70 MT29F8G08AAA 8 0834 51 Micron SLC 8 Gb 40

III. EXPERIMENTAL PROCEDURE B. No Refresh Mode Total dose measurements were performed on Micron Technology SLC 1 GB, 2 GB, 4 GB AND 8 GB NAND flash In No Refresh Mode, Co-60 irradiations were performed memory parts using the JPL Co-60 facility at a dose rate of 50 on Micron Technology SLC devices up to 80 krad (Si). rad (Si) per second at room temperature. Table III summarizes the bit error TID results for 4 Gb The TID data were taken using a commercial memory tester samples as an example. Fig. 1 displays the percentage of called the JD Instruments (JDI) tester. The JDI ATV tester erroneous bits versus dose for three samples of 4 Gb uses both custom ASIC and FPGA hardware with a built in devices as an example. Three measurements show good graphical interface. The JDI tester is fully capable of agreement. performing high-speed testing on memory systems using algorithmically generated test vectors [10]. Up to 50 million waveforms per second can be applied. The maximum operating frequency of the JDI is a 50 MHz cycle time. The operating frequency during the measurements was 17 MHz. The DUTs were programmed in all “0” patterns and leakage current was measured prior to irradiation. In all measurements the devices under test (DUTs) were under static bias during irradiation, but not actively exercised, because this corresponds to the actual operating condition during most of an extended space mission. In all measurements, the standby currents were measured for each dose increment. We also counted bit errors, which were produced when the voltage shift is sufficiently large. The sample size of each device for

TABLE III. TABLE IV. SUMMARY OF BIT ERROR TID RESULTS FOR MICRON TECHNOLOGY 4 GB SLC SUMMARY OF BIT ERROR TID RESULTS FOR MICRON TECHNOLOGY 1 GB, 2 NAND FLASH MEMORY IN NO REFRESH MODE SHOWING SEPARATE SAMPLES. GB, 4 GB AND 8 GB NAND FLASH MEMORY IN NO REFRESH MODE AVERAGED OVER THREE SAMPLES. TID (krad) Errors Errors Errors TID Errors Errors 2 Errors 4 Errors 8 (Sample #1) (Sample #2) (Sample #3) (krad) 1 Gb Gb Gb Gb

0 0 0 0 00 0 00 25 2 2 2 10 0 0 0 0 40 1,300 469 1,537 25 N/A 108 2 43 50 70,087 70,996 198,185 30 1,063 N/A N/A 137 60 4,109,638 12,606,641 17,659,915 35 N/A N/A N/A 2,844 65 29,695,240 221,228,189 107,230,956 40 1,498,107 1,048,024 1,102 N/A 50 145,557,656 528,616,073 113,089 N/A 60 276,057,030 1,174,465,793 11,458,731 N/A 65 766,853,454 1,464,210,083 119,384,795 N/A 70 1,028,052,213 1,284,552,054 N/A N/A

Fig. 1. Percentage of data errors versus dose for three samples of Micron Technology 4 Gb SLC NAND flash memory in No Refresh Mode.

Table IV summarizes the average bit error TID results of three samples for each device. Also, Fig. 2 displays the average percentage of erroneous bits versus dose for three samples measurements for each device. For a particular TID Fig. 2. Percentage of data errors versus dose for Micron Technology 1 Gb, 2 Gb, 4 Gb and 8 Gb SLC NAND flash memory in No Refresh Mode level, the number of errors decreases with increase density. averaged over three samples.

The standby current measurements versus the dose for the average of three devices in Refresh Mode and No Refresh Mode measurements for 1 Gb, 2 Gb and 4 Gb parts are displayed in Figs. 3 and 4, respectively. The standby current for both Refresh and No Refresh mode scales with feature size.

of heavy ion effects in floating gate memory arrays”, IEEE Trans. on Nucl. Sci. 54 (6), pp. 2371–2378, Dec. 2007. [5] M. Bagatin, S. Gerardin, G. Cellere, A. Paccagnella, A. Visconti, S. Beltrami, R. Harboe Sørensen, and A. Virtanen, “Key contributions to the cross section of NAND flash memories irradiated with heavy ions,” IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 3302–3308, Dec. 2008. [6] F. Irom and D. N. Nguyen, “Single event effect characterization of high density commercial NAND and NOR nonvolatile flash memories,” IEEE Trans. Nucl. Fig. 3. Standby current results versus dose for Micron Technology 1 Gb, 2 Sci., vol. 54, no. 6, pp. 2547–2553, Dec. 2007. Gb and 4 Gb SLC NAND flash memory in Refresh Mode. [7] H. R. Schwartz, D. K. Nichols, and A. H. Johnston, “Single-event upset in flash memories,” IEEE Trans. Nucl. Sci., vol. 6, pp. 2315–2324, Dec. 1997. [8] R. Koga et al., “SEE sensitivities of selected advanced flash and first-in-first-out memories,” IEEE Radiation Effects Data Workshop, pp. 47–52, 2004. [9] M. V. O’Bryan et al., “Recent Radiation Damage and Single event effect results for microelectronics,” IEEE Radiation Effects Data Workshop, pp. 1–14, 1999. [10] F. Irom, D. N. Nguyen, G. Cellere, M. Bagatin, S. Gerardin, and A. Paccagnella, “Catastrophic Failure in Highly Scaled Commercial,” to be published in Feb. issue of TNS. Fig. 4. Standby current results versus dose for Micron Technology 1 Gb, 2 [11] http://www.jdinstruments.net/ Gb and 4 Gb SLC NAND flash memory in No Refresh Mode.

V. CONCLUSION We have studied the TID response of the advanced commercial high density SLC 1 Gb, 2 Gb, 4 Gb and 8 Gb NAND flash memory from Micron Technology. The parts of different feature sizes were irradiated up to 80 krad (Si). As the feature size increases, the standby current decreases with the density of the DUTs. Also, the number of errors for a particular TID level decreases with the density. The charge pump circuitry was still functional at high dose levels. This is an improvement compared to the older generation of flash memories in which the charge pump circuitry failed at about 10 krad (Si).

VI. REFERENCES [1] D. N. Nguyen, S. M. Guertin, G. M. Swift, and A. H. Johnston, “Radiation effects on advanced flash memories,” IEEE Trans. Nucl. Sci., vol. 46, no. 6, pp. 1744–1750, Dec. 1999. [2] T. R. Oldham et al., “SEE and TID characterization of an advanced commercial 2 Gbit NAND flash nonvolatile memory,” IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3217–3222, Dec. 2006. [3] H. Schmidt, D. Walter, F. Gliem, B. Nickson, R. Harboe Sørensen, and A. Virtanen, “TID and SEE tests of an advanced 8 Gbit NAND-flash memory,” IEEE Radiation Effects Data Workshop, pp. 38–41, 2008. [4] G. Cellere, A. Paccagnella, A. Visconti, M. Bonanomi, R. Harboe Sørensen, and A. Virtanen, “Angular dependence

Performance of Commercial Off-the-Shelf Microelectromechanical Systems Sensors in a Pulsed Reactor Environment

Keith E. Holbert, Senior Member, IEEE, A. Sharif Heger, Steven S. McCready

Abstract—Prompted by the unexpected failure of piezoresistive II. BACKGROUND sensors in both an elevated gamma-ray environment and reactor Since the primary focus of this paper is reporting the core pulse tests, we initiated radiation testing of several MEMS piezoresistive accelerometers and pressure transducers to performance of COTS MEMS piezoresistive sensors in the ascertain their radiation hardness. Some commercial off-the- pulsed reactor environment, we dedicate this background shelf sensors are found to be viable options for use in a high- section to understanding the operation of MEMS energy pulsed reactor, but others suffer severe degradation and piezoresistive sensors and to surveying prior research into even catastrophic failure. Although researchers are promoting radiation effects on such devices. the use of MEMS devices in radiation-harsh environment, we nevertheless find assurance testing necessary. A. Piezoresistive MEMS Sensors In 1954 Smith reported on the piezoresistance effect in Index Terms—microelectromechanical devices, nuclear germanium and silicon [2]. In the late 1950s and early 1960s, radiation effects, piezoresistive devices, transducers. silicon strain gages were commercialized. Silicon pressure transducers were developed in the 1960s into the 1970s. The I. INTRODUCTION first piezoresistive silicon accelerometer was reported in 1979 [3]. Piezoresistive accelerometers are essentially semi- ONDUCTING a systems test in a high-energy pulsed conductor strain gages possessing large gage factors since the reactor can pose several instrumentation problems. C material resistivity primarily depends on the stress rather than Transducers intended for measuring properties such as the dimensions [4]. These micromachined accelerometers temperature, pressure, and acceleration can be damaged by using a piezoresistive detection principle are mainly used in exposure to the radiation, or they may be affected by the automotive applications [5], but have also been used in space radiation such that measurement error is introduced. When applications [6]. In the case of MEMS accelerometers, several selecting transducers such factors must be considered together transducer concepts are in use including piezoresistive, with requirements related to preventing the sensor presence piezoelectric, variable capacitance, and force rebalance [7]. from perturbing the system under study. In addition, pulsed Piezoresistive transducers often consist of four resistors radiation can induce current into the sensing cables [1]. arranged in a Wheatstone bridge circuit. The variation of We present total dose testing of several microelectro- resistivity with strain is then exploited to obtain an output mechanical systems (MEMS) accelerometers and pressure signal proportional to an input force. In a pressure transducer, transducers to ascertain their radiation hardness after the resistors are integrated into a diaphragm; for example, Fig. piezoresistive sensors failed unexpectedly in an elevated 1 shows the sensing chip of the Kulite pressure transducers gamma-ray environment and reactor core pulse tests. Such tested in this work. For an accelerometer, the resistors are instrumentation is attractive to reactor experiments due to their incorporated into the supports for a mass; for instance, the small size and broad range of frequency response. The overall construction of the Endevco accelerometer internals is shown goal of this study is to assess the usefulness of commercial in Fig. 2. In the pressure and acceleration transducers tested in off-the-shelf (COTS) sensors for experiments, especially this work, all four arms of the bridge are within the device, but shock testing, taking place in a pulsed reactor core. are not necessarily active. An alternative, common design is to include two of the resistors on the sensing element in a “half bridge” arrangement with the other two reference

Manuscript received July 16, 2010. This work was supported by the U.S. resistors being placed in an external portion of the circuit. Department of Energy under contract W-7405-ENG-36. Another variation incorporates additional resistors on the K. E. Holbert is with the School of Electrical, Computer and Energy sensing element to compensate for the temperature Engineering, Arizona State University, Tempe, AZ 85287-5706 USA (phone: dependence of the sensing material resistivity. 480-965-3424; fax: 480-965-3837; email: [email protected]). A. S. Heger and S. S. McCready are with Los Alamos National The Kulite pressure transducer utilizes a silicon-on- Laboratory, PO Box 1663, Los Alamos, NM 87545 USA (email: insulator (SOI) process, which is thoroughly documented in [email protected]; [email protected]).

[8]. The SOI process is beneficial to device design as it allows elements extend over the gap; their distance from the hinge for complete isolation of the active areas of the device from controls the sensitivity and range of the sensor. The operation the silicon substrate. This effectively prevents any problems of the particular device shown in Fig. 2 is as follows. The due to photocurrents from ionizing radiation or even an inertial mass is free to move in a direction normal to the electromagnetic pulse, and has proven a viable technology in central hinge that connects the inertial mass to the fixed core radiation-hard device design. The structure of the Kulite of the accelerometer. This allows acceleration in the force- pressure transducer resembles that shown in Fig. 1 [9]. The sensitive direction to induce a stress in the piezoresistors—one operation of this device is as follows. Four piezoresistive piezoresistor is placed in tension and the other in compression. sensing elements atop the silicon wafer are arranged in a The piezoresistors are placed in adjacent arms of a half-active Wheatstone bridge circuit. An applied pressure at the top of Wheatstone bridge with 500 Ω fixed resistors in the other the sensor bends the diaphragm, inducing a stress in the (passive) half of the bridge. piezoresistors on top. The stress is proportional to the B. Radiation Effects on MEMS Sensors difference between the applied pressure and the reference pressure of the isolated aperture beneath the wafer. Applied Compared to radiation effects studies on conventional pressure causes the outer piezoresistors to be placed in tension technologies, sparse research has been performed to determine and the inner piezoresistors to be in compression; the outer the effects of radiation on MEMS devices, particularly those two resistors are on opposite sides of the Wheatstone bridge as that employ piezoresistors. Since MEMS devices are are the inner two resistors. The supporting member at the fabricated in a manner similar to present semiconductor bottom has a twofold purpose—it provides mechanical electronics, they are expected to be susceptible to the same stability for the transducer, as well as forms the sealed cavity types of radiation damage. underneath the sensing device. Researchers have noted that there is little scientific literature on radiation effects in MEMS and that the field is in its infancy [11]-[13]. Although specific results from radiation testing of MEMS devices is very limited, scientists tout the use of MEMS in radiation environments based on extending their understanding of radiation effects on semiconductor devices to MEMS. For example, the advantage of using MEMS-based satellites due, in part, to their high resistance to radiation was noted in [14]-[16]. A few papers have reported on radiation effects to non-sensor applications of MEMS. Schanwald et al. found that the radiation sensitivity of ground

MEMS comb drives and microengines to be approximately Fig. 1. Kulite piezoresistive pressure transducer construction, adapted from [9]. 14 2 Applied pressure induces stress in the four piezoresistors, which are arranged in 10 electrons/cm (~100 kGy SiO2) [11]. McClure et al. a Wheatstone bridge configuration. reported on radiation effects on MEMS radio frequency relays [17]. Caffey and Kladitis report on the effects of photon

irradiation of actuators [18]. Miyahira et al. examined the effects of gamma radiation on MEMS optical mirrors [19]. In the 1990s, a few researchers reported on radiation effects in two MEMS accelerometers [20]-[22]. These references describe radiation testing of capacitance type MEMS sensors—the Analog Devices ADXL50 and the Motorola XMMAS40G. Reference [20] found that exposure to protons and heavy ions caused changes in the output voltage due to charge generation, which altered the electric field distribution. In addition, exposure of the ADXL50 to a 250 Gy(Si) gamma dose, created a hysteresis effect at zero g where the device appeared to become stuck [21], [23]. Boyadzhyan and Choma Fig. 2. Completed Endevco accelerometer device, adapted from [10]. The two report on a tunneling accelerometer that was not affected by a piezoresistors are located on opposite sides of the hinge and they traverse the air 1 kGy gamma dose from Co-60 [24]. gap between the fixed core and movable inertial mass. Acceleration-induced force on the movable central mass produces tensile and compressive stress, More recently, Zhu et al. fabricated one polycrystalline and respectively, in the two piezoresistors. two silicon-on-insulator (SOI) piezoresistive pressure sensors [25]. They found that a gamma dose of 23 kGy(H2O) caused a Endevco utilizes a bulk micromachining technique on a slight shift (~ a few mV) in the offset voltages of the three silicon wafer to produce the cantilever-type accelerometer sensors, but no degeneration of linearity or sensitivity. depicted in Fig. 2 [10]. The p-type silicon piezoresistors are Because of the limited scientific literature concerning radiation testing of MEMS devices, information regarding formed by boron diffusion, and they are surrounded by a SiO2 layer. The two serpentine-shaped piezoresistive gage radiation testing of piezoresistive sensors in general (not

specifically MEMS) was sought. The findings within the environments of the Sandia Pulse Reactor (SPR-III) and/or the literature are summarized in Table I. Annular Core Research Reactor (ACRR) located at Sandia National Laboratories (SNL), NM. Initial testing in the SPR- TABLE I III provided a smaller ratio of gamma-to-neutron radiation and PIEZORESISTIVE SENSOR RADIATION TESTING RESULTS IN THE LITERATURE shorter pulse widths as compared to the ACRR. The ACRR provides pulse-integrated radiation of about a factor of ten Radiation Reference Sensor Type Key Findings larger than the SPR-III, and the ACRR irradiation cavities can Exposure and Date Semiconductor 1015 n/cm2 and Less than 1% Terry et al. accommodate physically larger experiments. strain-gage 10 kGy(C) of change in sensitivity 1965 [30] A. Pulsed Reactor Characteristics pressure gamma transducers The SPR-III is a Godiva-type, fast neutron reactor providing 15 2 Piezoresistive 6×10 n/cm Satisfactory Chapin et al. a unique, near-fission-spectrum radiation environment (see accelerometers and 3 MGy(C) dynamic 1966 [31] gamma performance; Table II). SPR-III produces intense neutron bursts for significant changes radiation effects testing of materials and electronics. SPR-III in unstrained has a 17-cm (diameter) central irradiation cavity that extends resistance Piezoresistive 5×1015 n/cm2 Satisfactory Langdon et through the core [32]. The reactor is operated in two basic accelerometers in TRIGA operation; negligible al. 1970 [26] modes: (1) short duration steady state at low power (10 kW), (18) reactor to drastic change in and (2) fast pulses (bursts). strain resistance Polysilicon and 60Co γ-rays; Sensitivity and Zhu et al. SOI pressure dose of 23 linearity did not 2001 [25] TABLE II sensors kGy(H2O) degenerate; offset NOMINAL PULSE OPERATING PARAMETERS OF THE SPR-III AND ACRR [32] voltage shift Characteristic SPR-III ACRR Langdon et al. described combined neutron and gamma Pulse Yield 11 MJ 300 MJ irradiation testing of two models of piezoresistive Peak Power 1.5×105 MW 3.0×104 MW Pulse Width (FWHM) 76 µs 7.0 ms accelerometers employing a strain gage element; however, Peak Gamma Dose Rate 15 MGy(Si)/s 3 MGy(Si)/s their work was reported in 1970, which was essentially pre- Peak Neutron Flux 8.0×1018 n/cm2·s 6.0×1017 n/cm2·s MEMS [26]. They exposed 18 accelerometers to neutron Gamma Dose 1.7 kGy(Si) 30 kGy(Si) fluences as high as 5×1015 epithermal n/cm2 in a TRIGA Total 6.1×1014 n/cm2 6.0×1015 n/cm2 14 2 15 2 reactor (the concomitant gamma dose was unspecified). In Neutron >10 keV 6.1×10 n/cm 3.9×10 n/cm Fluence 1 MeV (Si 5.4×1014 n/cm2 2.8×1015 n/cm2 that testing, the resistance of an unnamed accelerometer, using equivalence) unbonded piezoresistive gages that were probably moderately doped, increased dramatically due to the neutron dose. The ACRR is a pool-type reactor capable of pulsed (see Another manufacturer’s model utilizing bonded Table II), steady-state and tailored-transient operation [32]. semiconductor strain gages, which likely were highly doped, The internal diameter of the ACRR dry central irradiation operated satisfactorily at all neutron exposures and the gage cavity is 23 cm. In addition, a fuel-ringed external cavity resistance showed no significant change. (FREC) is available with a larger diameter of 51 cm for Bouche [27], Thomas [28], and Bierney [29] discuss the FREC-II [33]. Kelly et al. discuss simulation fidelity issues design of piezoresistive and piezoelectric accelerometers for and compare the radiation environments of the SPR-III and the operation in nuclear reactor environments. Each of these three ACRR (including the FREC) in [34]. Endevco authors cites two other less-accessible company B. Pulsed Reactor Experiments publications dealing with piezoresistive sensor test results: (1) a 1965 Phillips Petroleum Company report by Terry et al. The seven reactor experiments, which were carried out over [30], and (2) a 1966 Battelle report by Chapin et al. [31]. a four-year period, are summarized in Table III. Each pulse Terry et al. exposed semiconductor strain-gage pressure within Experiments 2, 3 and 4 was of nearly identical transducers to 1015 n/cm2 and 10 kGy(C) of gamma radiation magnitude; the magnitudes of consecutive pulses in with less than 1% change in sensitivity. Chapin et al. exposed Experiments 5, 6 and 7 were systematically increased from piezoresistive accelerometers to 6×1015 n/cm2 and 3 MGy(C) ~30 to ~275 MJ. A brief description of each experiment and of gamma radiation with the sensors exhibiting satisfactory the exposed sensors is given in the remainder of this section. dynamic performance but undergoing significant changes in The tested sensors were not specifically designed for radiation unstrained resistance. Thomas states that heavily doped gages environments; rather they were COTS devices. For added are far more resistant to reactor radiation effects since the details on these experiments, the reader is directed to [35]. radiation damage mechanism involves changes in the 1) Experiment 1 crystalline lattice structure [28]. During February 2000, the first experiment was performed at the SPR-III. During that test, one Kulite pressure III. PULSED REACTOR TESTING AND RESULTS transducer model number CT-190-25A and a Taber strain gage-based pressure transducer (model 2215) were utilized. The tested sensors were operated in the pulsed reactor The Kulite CT-190 is similar to the XTE-190, except that the

CT-190 is designed for cryogenic applications with an transducers qualitatively showed no noticeable degradation to operating temperature range of –320°F to 250°F. The two the four reactor pulses, although quantitative comparisons of sensors were measuring the pressures of different volumes. before and after calibration data were not performed. The The two pressure sensors and a thermistor survived the 11 MJ Taber pressure sensor also faired well in the testing. These SPR-III pulse as seen in Fig. 3. No other conclusions can be three pressure sensors survived an approximate total neutron drawn from this test aside from the fact that both the Kulite fluence of 2.4×1015 n/cm2 and gamma dose of 6.8 kGy(Si). and Taber pressure transducers survived on a non-quantitative basis. 30 Referring to Fig. 3, note that all three sensors exhibit a prompt (impulse-like) change at the time of the reactor pulse. 25 The Kulite pressure transducer is a MEMS device relying on . resistance changes as the sensing methodology, whereas the 20 Thermistor (°C) Taber is a strain gage-based pressure transducer. Recall that a Kulite (psia) Taber (psia) thermistor has an inverse (and nonlinear) relationship between 15 its resistance and the sensed temperature. All three responses 10 are consistent with the data acquisition system perceiving a Measurement Sensor decrease in the resistance of each sensor. The fact that all 5 three sensors exhibit similar response to the reactor pulse appears indicative of a common factor, which might be 0 induced charge/current, and/or cable effects. In other words, -0.02 -0.01 0 0.01 0.02 0.03 the recorded temperature and pressure readings during the Time (sec) actual pulse are artifacts of the reactor pulse originating from radiation-induced signals. Fig. 3. Thermistor and pressure transducer response to an 11-MJ pulse at t=0 during SPR-III test. The responses of the Kulite and Taber pressure transducers exhibit initial prompt drops, followed a slight increase in steady- TABLE III state pressure corresponding to the increased pressure. PULSED REACTOR TESTING OF MEMS PIEZORESISTIVE SENSORS 3) Experiment 3 Ex- Total Exposure Experiment MEMS Sensors In September 2001, a larger scale experiment was peri- Gamma Neutron Description (model number) ment (kGy) (n/cm2) conducted in the fuel-ringed external cavity (FREC-II) of the SPR-III One pressure trans- ACRR. The sensors were consecutively subjected to the 1 1.7 6.1×1014 (1 pulse) ducer (Kulite CT-190) radiation fields created by two reactor pulses, which were Two pressure trans- SPR-III conducted about 90 minutes apart. The two MEMS pressure 2 6.8 2.4×1015 ducers (Kulite XCE- (4 pulses) 062 and XTE-190) transducers and two MEMS piezoresistive accelerometers Two pressure trans- were contained within an aluminum canister. ducers (XCE-062 and ACRR The time responses of the two Kulite piezoresistive pressure 3 18 3.4×1015 XTE-190); Two accel- (2 pulses) erometers (Endevco transducers of Experiment 3 are shown in Fig. 4. The pressure 7264C and 7270A) transducers respond as showing a peak that is coincident with One pressure trans- the reactor pulse; the XCE-062 and the XTE-190 exhibit a ACRR ducer (reused XTE- 4 44 8.7×1015 (5 pulses) 190); Two acceler- negative and a positive response, respectively, to the pulse. ometers (7264B) These sensor outputs during the pulse are most likely from ACRR Two pressure trans- 5 37 7.4×1015 radiation-induced current and/or system generated (3 pulses) ducers (XTE-190) electromagnetic pulse (SGEMP) into the sensor cabling. The ACRR Two pressure trans- 6 55 1.1×1016 (4 pulses) ducers (XTE-190) XCE-062, however, exhibits anomalous behavior immediately ACRR Two pressure trans- after the pulse; specifically, its output returns to a near zero 7 55 1.1×1016 (4 pulses) ducers (XTE-190) value and then wavers rather than reaching a constant steady- state value as it should. This Kulite XTE-190, which shows 2) Experiment 2 no such anomalous behavior, was used later in Experiment 4 Also in February 2000, a series of four SPR-III bursts were where it was exposed to five additional ACRR pulses. produced for pressure transducer evaluation. The experiment 4) Experiment 4 included a Kulite XCE-062 and an XTE-190, whose use was In May 2002, another sensor evaluation experiment was favored by Los Alamos National Laboratory personnel based conducted in the ACRR central cavity. The test consisted of on their small size and prior experience (1970s) with the five reactor pulses delivered with approximately one-half hour Kulites in the ACRR. These tests incorporated one Teledyne of rest between shots. Important to note is that decay heat Taber model 2215 strain gage-based pressure transducer too. generation causes the reactor to continue to operate at Use of the Taber was promoted by SNL personnel because of significant power for two seconds following a high intensity their experience with those transducers. All three sensors pulse. Each pulse in this experiment involved an energy were connected the same volume. The two Kulite pressure release of approximately 87 MJ with a peak reactor power of

1200 MW. An 87 MJ ACRR pulse delivers about the same de-energizing it. The oscillations present in the accelerometer fluence and dose in the central cavity as a 285 MJ pulse data two seconds after the pulse are most likely the result of delivers in the FREC-II; however, the larger (285 MJ) pulse reactor control rod chain-drive operation. Notice that the has a shorter FWHM pulse duration than the smaller (87 MJ) accelerometer post-pulse outputs are biased from their pre- pulse (in general, as the pulse magnitude becomes larger, the pulse zero acceleration values. Specifically, the test results full-width half-maximum becomes shorter). Although Fig. 5 show that one 7264B exhibits a slightly positive (+1.5 g) only shows data from the first of five reactor pulses, the data offset after the reactor shot, whereas the second 7264B has a for the four other reactor shots are similar and indicate slightly negative (–0.9 g) offset. The output of each sensor satisfactory operation of the three MEMS-type piezoresistive changes over the first few seconds after the reactor shot due to devices. heating of the sensor. Note that although the Wheatstone bridge compensates for identical resistance changes in each Kulite Piezoresistive Pressure Transducers bridge leg, the individual piezoresistors are not of identical 1.5 35 resistance (R), thereby causing differences in ∆R in each leg

1 30 from temperatures changes.

) 25 Power (GW) 0.5 Solenoid impulses for qualitative sensor 20 degradation evaluation immediately after pulse 0 XTE-190-25A Radiation-induced effect 15 from reactor pulse -0.5 XCE-062-25A Pressure (psig 10 10 Reactor Power 8 -1 Accel 7264B-500T 5 6

. Accel 7264B-500T -1.5 0 4 2 +1.5g 0 0.02 0.04 0.06 0.08 0.1 0 Time (sec) -2 -4 –0.9g Acceleration (g) Fig. 4. Kulite piezoresistive pressure transducer outputs vs. time after a 285- -6 Control rod chain-drive action MJ ACRR pulse. The initial prompt jump and drop, respectively, by the -8 XTE-190 and XCE-062 outputs are a radiation-induced effect. After the -10 reactor pulse, the XCE-062 exhibits anomalous behavior in terms of a non- 0 5 10 15 20 constant steady-state output. Time (sec)

Fig. 6. Endevco 7264B piezoresistive accelerometer outputs following an 87- 50 13 MJ ACRR pulse at t=2.5 sec. Both accelerometers exhibit a slightly biased output because of the temperature increase. 40 Thermistor 44031 12.8

r Accel 7264B-500T 12.6 30 Accel 7264B-500T 5) Experiments 5, 6 and 7 Pressure XTE-190-25A 12.4 20 These three experiments were carried out in the ACRR 12.2 central cavity during September 2003. Three instrumented Pressure (psia) Acceleration (g) Acceleration 10 canisters were placed in the reactor central cavity and Temperature (°C) o 12 subjected to three or four reactor pulses as outlined in Table 0 11.8 IV. Two Kulite XTE-190 series pressure transducers were -10 11.6 located on the top flange of each aluminum test canister. 0 5 10 15 20 Time (sec) TABLE IV REACTOR PULSES IN EXPERIMENTS 5, 6 AND 7 Fig. 5. Sensor outputs from reactor pulse (shot) 1 of Experiment 4. The 87- MJ ACRR pulse occurs at t=2.5 sec, after which temperature and pressure increases are recorded by the instruments. Experiment Reactor Pulse Energies 5 22 MJ, 78 MJ, 272 MJ 6 28 MJ, 95 MJ, 158 MJ, 273 MJ For Experiment 4, a solenoid with a spring-loaded piston 7 38 MJ, 81 MJ, 151 MJ, 277 MJ was mounted inside the test package to perturb the accelerometers while they were in the reactor. Energizing or Eventually all but one of the six XTE-190 pressure de-energizing the solenoid produced a single impulse. transducers degraded or failed from the total combined gamma Solenoid operation consisted of energizing the device, and dose and neutron fluence, that is, the sensors gradually and then waiting about a second, followed by de-energizing the systematically deteriorate as the total exposure is increased. solenoid. This arrangement allowed non-zero stimulation of For example, Fig. 7 shows that for the first two pulses, the the accelerometers, but the arrangement was subject to pressure transducer exhibits a normal response to the reactor variability and the results should be viewed as qualitative in shots; however, after the third pulse, the sensor begins to nature. Solenoid operation is reflected in intermittent peaks in display an erratic output, and after the fourth pulse, the the accelerometer data of Fig. 6. The peaks associated with magnitude of the erratic behavior has increased noticeably. energizing the solenoid are smaller than those associated with Other Kulite XTE-190s catastrophically failed after multiple

pulses in these experiments. Noteworthy is that the total dose (see Table III). For comparison, the XTE-190s were found to and fluence to the XTE-190s from these experiments are fail in a pure gamma environment at doses on the order of 100 larger than those experiments reported earlier in this paper kGy [36].

0.02 0.05 0 0 -0.02 28 MJ -0.05 -0.04 95 MJ -0.1 -0.06 -0.15 -0.08 -0.2

-0.1 Pressure (psia) Pressure (psia) -0.12 -0.25 -0.14 -0.3 -0.16 -0.35 -100 0 100 200 300 400 500 600 -100 0 100 200 300 400 500 600 Time (sec) Time (sec)

0.3 12 158 MJ 273 MJ 0.2 10 8 0.1 6 0 4 -0.1 Pressure (psia) Pressure (psia) 2

-0.2 0

-0.3 -2 -100 0 100 200 300 400 500 600 -100 0 100 200 300 400 500 600 Time (sec) Time (sec)

Fig. 7. Degradation of a Kulite XTE-190-25A MEMS pressure transducer for four successively larger ACRR pulses during Experiment 6.

four pulses from the SPR-III. In addition, a CT-190 pressure IV. DISCUSSION OF TESTING RESULTS transducer (which is similar to the XTE-190 pressure sensor, This section examines the pulsed reactor testing results with except that the CT-190 is designed for cryogenic applications) respect to the two different sensor types. The piezoresistive was exposed to a single SPR-III pulse. These three pressure sensors tested consist of three different Kulite Semiconductor transducers survived those reactor pulses without observable Products, Inc. pressure transducers (models CT-190, XCE-062 degradation. Subsequent tests at the ACRR demonstrated and XTE-190) and two Endevco Corporation accelerometers another XTE-190 to survive seven pulses (Experiments 3 and (models 7264 and 7270A). The Kulite pressure transducers 4); however, an XCE-062 exhibited anomalous behavior from are micromachined silicon-on-insulator (SOI) devices with a single ACRR pulse. The main difference between the two sensors is their mass: the XCE-062 weighs 0.2 g whereas the layers of SiO2 sandwiched between adjacent piezoresistive segments, as seen in Fig. 1. The Endevco accelerometers are XTE-190 has a mass of 4 g [37]. Further exposure to a bulk silicon devices in which the piezoresistive elements sustained gamma field resulted in complete failure of the extend over an etched hinge for force measurement (see Fig. XCE-062 sensor, whereas the XTE-190 continued to function properly, indicating that the XCE-062 is more gamma 2) and are protected by a thin SiO2 layer. These sensors are small devices with the piezoresistive elements placed on two sensitive. Consequently, the XCE-062 was removed from or four legs of a Wheatstone bridge. The pressure transducers further consideration. employ an off-chip thin-film resistive network for temperature Six additional XTE-190 transducers were exposed to compensation whereas the accelerometers do not. multiple ACRR pulses in the last three experiments, which showed that for total combined dose and fluence of more than A. MEMS Pressure Transducers 15 to 25 kGy and 3×1015 to 5×1015 n/cm2, respectively, that The pressure transducers received the greatest attention most sensor outputs become erratic. Fig. 8 shows a summary during this project with at least one pressure transducer tested of the pressure transducer performance from all seven in each of the seven experiments. The initial testing in the experiments. This graph provides users with the capability to SPR-III provided a smaller ratio of gamma to neutron predict the survivability of a sensor for an expected dose and radiation as compared to the ACRR. An XCE-062 pressure fluence in future pulsed reactor experiments. transducer and an XTE-190 pressure sensor were subjected to

interface trapped hole charges, which reduce current flow Kulite Pressure Transducers 1.4×1016 through the piezoresistors due to the creation of a depletion

1.2×1016 region about the periphery of the gage resistors [36]. This mechanism ultimately leads to sensor offset-voltage drift and a 16 1.0×10 slight sensitivity increase. Referring to Fig. 6, however, the 8.0×1015 bias observed in the accelerometer outputs after the pulse is CT-190 Survived 15 from thermal heating of the sensors. In particular, the 7264B 6.0×10 XCE-062 Survived accelerometers can have a thermal shift in the zero measurand 4.0×1015 XCE-062 Failed

Neutron Fluence(n/cm²) XTE-190 Survived output of ±30 g over a –18° to 66°C range [38]. A peak 15 2.0×10 XTE-190 Failed temperature of about 46°C temperature rise was recorded by 0 the thermistor present in the shot depicted by Fig. 6, which 0 10203040506070means the –1g and +2g biased readings were well within the Gamma Dose (kGy) manufacturer specifications. Fig. 8. Post reactor pulse performance of Kulite piezoresistive MEMS pressure transducers. No failures of the XTE-190 are observed below a V. CONCLUSIONS 15 2 combined gamma dose of 20 kGy and neutron fluence of 3×10 n/cm . Various COTS MEMS sensors being considered for use in a pulsed reactor core were operated in several different radiation Endevco Piezoresistive Accelerometers environments. The performance of the Kulite pressure 50 35 transducers was graphically summarized in Fig. 8, as a 0 30 function of total neutron fluence and gamma dose. From Fig. -50 25 8, one can more easily observe that for neutron irradiation and . -100 (GW) Power lower gamma doses (< ~20 kGy), these sensors perform -150 20 reasonably well. Only one sensor (an XCE-062 model) shows -200 15 noticeable degradation below those levels. Otherwise, the 7264C-2000 -250 Acceleration (g) (g) Acceleration 7270A-2000 10 results show promise for use of these devices (particularly, the -300 Reactor Power 5 XTE-190) in a pulsed neutron-gamma radiation environment. -350 Survival of the Endevco piezoresistive MEMS accelerometers -400 0 is observed at high neutron fluences, with the exception of a 0 0.02 0.04 0.06 0.08 0.1 single sensor anomaly (i.e., the 7270A) at a neutron fluence of Time (sec) 1.6×1015 n/cm2. As compared to the Kulite pressure Fig. 9. Endevco piezoresistive accelerometer output after a 285-MJ ACRR transducers, these accelerometers did not show signs of pulse. The initial prompt drops by the accelerometer outputs are a radiation catastrophic failure. induced effect. The 7270A-2000 (where ‘-2000’ denotes a 0–2000 g range) exhibits a negatively biased output after the reactor pulse. We conclude that some COTS piezoresistive MEMS sensors are viable candidates for measurements in a pulsed B. MEMS Accelerometers reactor environment. We find the Kulite XTE-190 pressure 15 2 The Endevco piezoresistive MEMS accelerometers were transducer useable to a fluence and dose of 4×10 n/cm and 20 kGy, respectively. The Endevco 7264 accelerometers subjected to pulses from the ACRR only. Fig. 9 shows that operate to a radiation exposure of more than twice the XTE- the sensors demonstrate a negative pulse coincident with the 190. Noteworthy is that the research from this project has reactor pulse. The negative pulse is a radiation effect within originated the first reported results from nuclear radiation the sensing elements and/or lead wires versus a physical acceleration. The 7270A shows substantial bias (about –107g) effects testing of piezoresistive MEMS accelerometers and pressure transducers [39], [40]. immediately following exposure to a single ACRR pulse; Although some researchers are advocating the use of therefore, it was eliminated for use in future pulsed reactor MEMS devices in harsh radiation environments, we experiments. In contrast, during Experiments 3 and 4, one nevertheless find it necessary to perform hardness assurance Endevco 7264C and two 7264B accelerometers were exposed testing of such sensors as is common with other to two and five pulses, respectively, without any noticeable semiconductor components. The differences in response by degradation. The 7264C is virtually identical to the 7264B, sensors from same manufacturer have been noted herein, for except that the seismic mass of the 7264C extends from the end of the sensor housing; the resulting difference is that the example, the softness of the Endevco 7270A accelerometer versus the 7264, and similarly, the softness of the Kulite XCE- 7264B has a mounted resonance frequency of 28 kHz and a 062 pressure transducer compared to the XTE-190. damping ratio of 0.005, whereas for the 7264C these specifications are 26 kHz and 0.05, respectively. Such VI. REFERENCES comparative values appear to make the 7274B more suitable for the measurement of short duration shocks. [1] J. E. Ramus, “Radiation induced electrical transients in strain gage and temperature transducer circuits in a pulsed reactor environment,” IEEE In a prior work, we found that gamma irradiation of these Trans. on Nuclear Science, vol. 11, no. 5, Nov. 1964, pp. 111-122. MEMS accelerometers causes the formation of oxide and

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Radiation Hardness Characterization of a 130nm ASIC Library Technology

Radu Dumitru, Member, IEEE, Craig Hafer, Member, IEEE, Tzu-Wen Wu, Member, IEEE, Rob Rominger, Harry Gardner, Member, IEEE, Peter Milliken, Member, IEEE, Kevin Bruno, Member, IEEE, Teresa Farris, Member, IEEE

complex I/O structures, PLL’s, various configurations of Abstract--Radiation hardness characterization has been SRAM’s and other macros. performed on a RadHard-by-Design ASIC Library designed using a 130nm commercial fab process. Test chip results are II. TEST CHIP CONFIGURATION presented illustrating the ASIC library performance and radiation hardness response. Test chip WX26A was fabricated at Taiwan Semiconductor Manufacturing Company’s (TSMC’s) wafer ® I. INTRODUCTION fab using their CyberShuttle . The devices were manufactured using their general purpose CL013G 130nm S higher density and increased electrical performance A are required for radiation-hardened integrated circuits logic 1P8M salicide silicon process. The nominal power (ICs), smaller geometry wafer fabrication processes must be supply voltages used are 1.2V for core (thin oxide transistors) characterized for both electrical performance and radiation and 3.3V for I/O (thick oxide transistors). effects. To achieve this goal, a test chip was developed to Both thick and thin gate oxide transistors are represented characterize the capabilities of a 130nm process technology. in the WX26A and were TID tested. Also, intrinsic (field Future test chips are underway to validate the design and edged) transistors and annular RHBD transistors are tested on characterization of a robust RadHard-by-Design (RHBD) the WX26A. The thin oxide transistors are built with three ASIC library. For the initial chip, radiation-hardened flip- threshold voltage options, varying between standard flops have been developed for operation in the harsh threshold voltage (VT), low VT and high VT. Several radiation environment of space using a 130nm wafer structures were laid out to test various elements of SEE fabrication process. hardness (SEU, SEL, etc.), while two capacitor structures In this paper, total ionizing dose (TID) data for both were evaluated for radiation induced leakage current [1]. commercial layout and annular RadHard-by-Design discrete TABLE I transistors will be reviewed along with single event effects RADIATION EFFECTS TEST CONDITIONS (SEE) data, namely single event latch-up (SEL) and single Power Supplies Temperature Test Radiation Source Test Notes event upset (SEU), under a set of conditions listed in Table I. Core, I/O (V) (°C) Characterization of electrical performance and SEE response TID Co60 gamma cell 1.35, 3.6 25 Static, 185 rd(Si)/s Dose Rate from shift registers built with a variety of RHBD flip-flop SEL LBNL 1.35, 3.6 125 115 MeV-cm²/mg (max LET) structures will also be the focus of this paper. Future test chip Xe, Kr, Cu, Ar, and Ne heavy ions SEU LBNL 1.1, 3.0 25 work includes development and characterization of more (LET range 4 to 115 Mev-cm²/mg)

III. TEST CHIP RESULTS Manuscript received July 29, 2010. R. Dumitru is with Aeroflex Colorado Springs, Colorado Springs, CO A. Library Performance 80907, USA (telephone: 719-594-8188, email: [email protected]) The 130nm technology node allows improved timing and C. Hafer is with Aeroflex Colorado Springs, Colorado Springs, CO 80907, USA (telephone: 719-594-8319, email: [email protected]) power performance over an existing 0.25µ RHBD ASIC T. Wu is with Aeroflex Colorado Springs, Colorado Springs, CO 80907, offering, while preserving the radiation hardness required for USA (telephone: 719-594-8413, email: [email protected]) space applications. Table II below illustrates typical data R. Rominger is with Aeroflex Colorado Springs, Colorado Springs, CO 80907, USA (telephone: 719-594-8183, email: [email protected]) extracted from post layout simulations. H. Gardner is with Aeroflex Colorado Springs, Colorado Springs, CO 80907, USA (telephone: 719-594-8078, email: [email protected]) TABLE II P. Milliken is with Aeroflex Colorado Springs, Colorado Springs, CO 130NM RHBD ASIC LIBRARY ELECTRICAL PERFORMANCE DATA 80907,USA (telephone: 719-594-8382, email: [email protected]) K. Bruno is with Aeroflex Colorado Springs, Colorado Springs, CO Quiescent Current (nA) 80907, USA (telephone: 719-594-8086, email: [email protected]) Max Toggle Max Core Dynamic Power (nW/gate- Rate (GHz) Frequecy (MHz) MHz) (na02nd1) T. Farris is with Aeroflex Colorado Springs, Colorado Springs, CO -55oC25oC125oC

80907, USA (telephone: 719-594-8035, email: [email protected]) 1.4 570 18.5 0.2 1 115

B. TID Results 1.E+00 TID testing with a J.L. Shepherd model 81-22 Co60 cell 1.E-01 1.E-02

was performed on a variety of discrete N-channel transistors. 1.E-03 During irradiation, the transistors were statically biased in a 1.E-04 worst case configuration with maximum specified power 1.E-05 supply voltage applied to the gate as described in Table III. Ids 1.E-06 1.E-07

The source, drain and substrate were grounded. Irradiation 1.E-08 Low Dose Rate (0k, 50k, 100k, 200k) was done at 25°C with a dose rate of 185 rd/s. 1.E-09 High Dose Rate (300k, 500k, 1M) 1.E-10 Transistors drain current versus gate voltage IDS (A) vs. 1.E-11 VGS (V) curves were generated pre-irradiation and at each -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 post-irradiation level using a HP4145 Parametric Analyzer. Vgs Fig. 3. IDS (A) vs. VGS (V) at various TID (rd) levels for Standard TABLE III N-channel 10 µm / 0.13 µm SVT transistor. TRANSISTORS EVALUATED FOR TID IN THE 130NM TECHNOLOGY

1.E+00

N-channel Standard/ Irradiation 1.E-01 # W/L (µm) Oxide VT Transistor Annular VGATE (V) 1.E-02 1 A 10/0.13 Thin LVT Std 1.35 1.E-03 2 B 10/0.13 Thin LVT Annular 1.35 1.E-04 3 C 10/0.13 Thin SVT Std 1.35 1.E-05 4 D 10/0.13 Thin SVT Annular 1.35 Ids 1.E-06 5 E 10/0.13 Thin HVT Std 1.35 1.E-07 6 F 10/0.13 Thin HVT Annular 1.35 1.E-08 1.E-09 Low and High Dose Rate (0k through 1M)

As can be discerned from the six plots (Figs. 1 to 6), the 1.E-10 annular transistors are TID hard to greater than 1 Mrd. The 1.E-11 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 TID performance of the intrinsic standard VT thin oxide Vgs transistor is 200 krd while the TID of intrinsic low and high Fig. 4. IDS (A) vs. VGS (V) at various TID (rd) levels for Annular VT thin oxide transistor is 100 krd and 300 krd respectively. N-channel 10 µm / 0.13 µm SVT transistor.

1.E+00 1.E+00 1.E-01 1.E-01 1.E-02 1.E-02 1.E-03 1.E-03 1.E-04 1.E-04 1.E-05

1.E-05 Ids

Ids 1.E-06

1.E-06 1.E-07

1.E-07 1.E-08 Low Dose Rate (0k, 50k, 100k) Low Dose Rate (0k, 50k, 100k, 200k, 1.E-08 1.E-09 300k) High Dose Rate (200k, 300k, 500k, 1M) High Dose Rate (500k, 1M) 1.E-10 1.E-09 1.E-11 1.E-10 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 Vgs Vgs Fig. 1. IDS (A) vs. VGS (V) at various TID (rd) levels for Standard Fig. 5. IDS (A) vs. VGS (V) at various TID (rd) levels for Standard N-channel 10 µm / 0.13 µm LVT transistor. N-channel 10 µm / 0.13 µm HVT transistor.

1.E+00 1.E+00 1.E-01 1.E-01 1.E-02 1.E-02 1.E-03 1.E-03 1.E-04 1.E-04 1.E-05

1.E-05 Ids

Ids 1.E-06

1.E-06 1.E-07

1.E-07 1.E-08

1.E-08 Low and High Dose Rate (0k through 1M) 1.E-09 Low and High Dose Rate (0k through 1M)

1.E-09 1.E-10

1.E-10 1.E-11 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 Vgs Vgs Fig. 6. I (A) vs. V (V) at various TID (rd) levels for Annular Fig. 2. IDS (A) vs. VGS (V) at various TID (rd) levels for Annular DS GS N-channel 10 µm / 0.13 µm LVT transistor. N-channel 10 µm / 0.13 µm HVT transistor.

C. SEE results SEE characterization was performed at Lawrence Berkeley 25 National Laboratory (LBNL) using Xe, Kr, Cu, Ar, and Ne heavy ions at an angle of incidence from normal (0°) to a 20 maximum of 60° producing an effective Linear Energy 2 15 Transfer (LET) range of 4 to 115 MeV-cm /mg. I/O The parts were tested under worst-case test temperature Core 10 and specified operating voltages for inducing single event Current (mA) upset (SEU) and single event latch-up (SEL). SEU was 5 performed at 25°C with the power supply voltages at 1.1V core/3.0V I/O. SEL immunity verification was done with the 0 device temperature at 125°C and the power supply voltages 0 200 400 600 800 1000 at 1.35V core/3.6V I/O. Time During Irradiation (s)

For SEU testing, a one/zero pattern was shifted into the Fig. 7. Run 1 (serial number 22) power supply currents versus time. 512-bit memory chain. The clock was held in a DC state during irradiation with heavy ions. After irradiation, the data 25 were read-out of each chain to determine the number of upset cells (cells with a changed or flipped logic state). The errors 20 were recorded by a JD Instruments tester as a function of heavy ion effective LET and effective fluence. The 15 characterization test board contained one socket to I/O accommodate the WX26A die in a delidded 144-PGA 10 Core

package. Because this TSMC 130 nm process uses eight (mA) Current levels of copper interconnect metal, the overlayer thickness 5 was approximated to be 15 µm of equivalent silicon thickness for LET correction due to ion beam energy loss through the 0 overlayer [2]. 0 50 100 150 200 250 1) SEL results Time During Irradiation

Four WX26A devices were tested for SEL immunity by Fig. 8. Run 2 (serial number 12) power supply currents versus time. monitoring power supplies during irradiation to detect shifts in measured currents as a function of time, as shown in Fig. 7 2) SEU results and Fig. 8. The summary in Table IV indicates that no single A preliminary SEU test was performed on a 512-stage shift event induced latch-up was observed to an effective LET of register structure. A variety of flip-flop storage cells were 115 MeV-cm2/mg (maximum possible with the available test designed into the WX26A test chip. Table V contains the setup) when exposed to Xenon ions at LBNL to an effective associated Weibull fit parameters and error rate calculations fluence of 1 x 107 ions/cm2. for the 512-cell flip-flop memory chains. Figs. 9 to 14 contains plots of cross-section versus LET for TABLE IV six of the latches instantiated on the chip. SEL DATA FOR FOUR DEVICES

Pre-Irradiation Current Post-Irradiation Current Serial Number Latch-up (Y/N) IO/Core (mA) IO/Core (mA) 22 18.5/4.7 18.8/5.6 N 12 18.2/5.2 18.3/5.4 N 6 17.0/4.6 17.7/5.0 N 3 17.3/4.8 17.7/5.0 N

TABLE V SEU WEIBULL DATA AND ERROR RATE PREDICTION

Flip - Flop Type Saturated Cross-section (cm²/bit) Onset LET (MeV-cm²/mg) Error-Rate (Errors/bit-day) Features

SDFFN0D2 2.0x10-7 6 5.2x10-8 1x drive single clock, comercial design SDFFN1D2 1.0x10-7 19 4.7x10-9 2x drive single clock SDFFN5D2 Immune to LET=115 MeV-cm2/mg fluence of 1x107 ions/cm2 Temporal (200ps) filter on clock SDFFN4D2 5.0x10-7 88 9.4x10-10 10x drive single clock SDFFACN1D2 9.0x10-8 21 4.5x10-9 Split clock (3µ separation) and 10x drive on AC SDFFN6D2 3.0x10-8 83 5.4x10-11 Split clock (3µ separation) -7 -9 SDFFDUAL 2.0x10 79 1.1x10 DICE Flop

1E-6 1E-7 / bit)

1E-7 / bit) 2 2

1E-8 1E-8 Weibull 3 Weibull 1E-9 10 3

Cross Section (cm Section Cross 10

22 (cm Section Cross 12 22 12 1E-10 1E-9 0 20 40 60 80 100 120 2 0 20406080100120 LET (MeV-cm /mg) 2 LET (MeV-cm /mg)

Fig. 9. SDFFN0D2 flip-flop cross-section versus LET. Fig. 12. SDFFACN1D2 flip-flop cross-section versus LET.

1E-6 1E-7

Weibull 3 / bit) / bit)

10 2 2 1E-7 22 1E-8 12

Weibull 1E-8 1E-9 3 10 Cross Section (cm Cross Section Cross Section (cm Section Cross 22 12 1E-9 1E-10 0 20 40 60 80 100 120 0 20 40 60 80 100 120 LET (MeV-cm2/mg) LET (MeV-cm2/mg)

Fig. 10. SDFFN1D2 flip-flop cross-section versus LET. Fig. 13. SDFFN6D2 flip-flop cross-section versus LET.

1E-7 1E-6 Weibull 3 / bit) / bit)

2 10 2 1E-8 1E-7 22 12

Weibull 1E-9 1E-8 3 10 Cross Section (cm Section Cross Cross Section (cm Cross Section 22 12 1E-10 1E-9 0 20406080100120 0 20 40 60 80 100 120 LET (MeV-cm2/mg) LET (MeV-cm2/mg)

Fig. 11. SDFFN4D2 flip-flop cross-section versus LET. Fig. 14. SDFFDUAL flip-flop cross-section versus LET.

IV. SUMMARY The WX26A test chip was designed using a commercially available 1P8M 130nm EPI substrate process. Test structures were designed to evaluate electrical performance, SEL, SEU and TID on this 130nm technology. The devices were irradiated with heavy ions at LBNL to test SEL and SEU effects. None of the hardened SEL structures exhibited SEL to a maximum LET of 115 MeV-cm2/mg at 125°C and effective fluence of 1x107 ions/cm2 under a 1.35V operating voltage. Preliminary SEU data were taken from shift register chains on the WX26A. The SEU onset LET for the commercial design practices DFF shift register chain is 6 MeV-cm2/mg. The RadHard-by-Design shift register chain exhibits a large improvement in SEU onset LET of about 80 MeV-cm2/mg. The 130nm process technology node proves to be very suitable for the development of RadHard-by-Design ASIC applications.

V. REFERENCES [1] F. W. Sexton, "Destructive single-event effects in semiconductor devices and ICs", IEEE Trans. on Nucl. Sci., vol. 50, no. 3, June 2003. [2] J. L. Wert, E. Normand, C. Hafer, "The effects of device metal interconnect overlayers on SEE Testing", NSREC IEEE Radiation Effects Data Workshop, 2005. Radiation Performance of Commercial SiGe HBT BiCMOS High Speed Operational Amplifiers

Dakai Chen, Member, IEEE, Jonathan Pellish, Member, IEEE, Anthony Phan, Hak Kim, Sam Burns, Rafi Albarian, Bruce Holcombe, Bradley Little, James Salzman, Paul Marshall, Member, IEEE, and Kenneth LaBel, Member, IEEE

Abstract—We present results on heavy-ion and proton SiGe HBT technology is attractive for space applications due irradiations for commercial SiGe BiCMOS differential to its intrinsic tolerance to both ionizing and non-ionizing amplifiers: LTC6400-20 from Linear Technology and THS4304 irradiation effects [1]–[3]. However SiGe HBT-based circuits from Texas Instruments. We found that the devices are are sensitive to single event effects (SEE), such as single susceptible to heavy-ion-induced SETs, with relatively low LET event upsets (SEU) and transients (SET) [4]. Additionally, thresholds (LETth). The LTC6400 exhibits a LETth < 7.4 MeV·cm2/mg for frequencies ranging from 10 to 1000 MHz. The since SiGe HBT technology is often designed for high speed 2 applications, the high operating frequency further enhances THS4304 exhibits a LETth < 4.4 MeV·cm /mg at 200 MHz; the LETth decreases with increasing frequency. The SET cross- the significance of the SEUs and SETs [5], [6]. sections increase with increasing operating frequency. The Furthermore, these high speed devices typically have low significance of the SETs also increases with frequency. The linear energy transfer (LET) upset thresholds, which can lead SETs at 1000 MHz erase several signal cycles. We also found to vulnerability to proton irradiations [7]. Proton-induced that the LTC6400 is relatively robust against 198 and 54 MeV SEEs can be a concern for orbits in proton rich environments, protons. We did not observe angular sensitivity from the proton like the Van Allen Belt. The SEUs/SETs from protons can irradiations. also exhibit angular dependence, which increases in

significance as geometries become smaller [8]. I. INTRODUCTION Here we investigate the SEE sensitivities of commercial

SiGe HBT BiCMOS operational amplifiers from different ilicon-germanium (SiGe) heterojunction-bipolar- manufacturers with heavy-ion and proton irradiations. transistors (HBTs) are well suited for high speed S microelectronic applications. SiGe HBTs utilize band gap II. DEVICE DESCRIPTION engineering to achieve similar performance as III-V compound semiconductors, while maintaining the same Si The devices in this experiment include the LTC6400 CMOS fabrication processes. Therefore we benefit from the differential output amplifier from Linear Technology and the high performance, while keeping the manufacturing costs THS4304 wideband amplifier from Texas Instruments. Table down. I. shows the device information, including the process Although flight systems desire radiation hardened parts, technology, lot date code, and part function. these components are often more expensive and remain The LTC6400 is fabricated with the JAZZ-TOWER several technology generations behind their commercial 0.35 µm SiGe BiCMOS process. The process includes 3.3 V counterparts. As a result, space systems are utilizing more CMOS with deep trench isolations, and lateral PNP commercial-off-the-shelf (COTS) parts, especially in transistors. Additional options include a 5 V CMOS, vertical missions with relatively lower radiation requirements. The PNP transistor, and triple-well isolation. The THS4304 is developed in Texas Instrument’s BiCom3 Silicon-Germanium BiCMOS process. The process ______contains complementary SiGe PNP and NPN transistors, 5 V 0.35 µm SOI CMOS logic, and trench isolation. Manuscript received on July 15, 2010. This work is supported in part by the NASA Electronics Parts and Packaging program (NEPP) and the Defense Threat Reduction Agency TABLE I. (DTRA) under IACRO#09-4587I. DEVICE INFORMATION. Dakai Chen, Anthony Phan, and Hak Kim are with MEI Technologies Inc., in support of NASA/GSFC, Greenbelt, MD, USA 20771 (phone: 301- LTC6400 THS4304 286-8595, e-mail: [email protected]). Linear Texas Manufacturer Jonathan Pellish and Kenneth LaBel are with NASA/GSFC, Greenbelt, Technology Instrument MD, USA 20771 (email: [email protected], JAZZ-TOWER [email protected]). TI BiCom3SiGe Sam Burns and Rafi Albarian are with Linear Technology Corp., Process 0.35 µm SiGe BiCMOS Milpitas, CA, USA 95035 (email: [email protected], BiCMOS [email protected]). Bruce Holcombe, Bradley Little, and James Salzman are with Texas Lot date code 0746 and 0705 October, 2004 Instruments, Inc., 6412 Highway 75 South, Sherman, Texas, USA75090 (email: [email protected]). P. Marshall is a consultant and is at Brookneal, VA 24528 USA (e-mail: [email protected]).

Fig. 1. Heavy-ion-induced SET error cross-sections vs. effective LET for Fig. 2. Heavy-ion-induced SET characteristics for the LTC6400 operating 2 the LTC6400 with VIN = 140 mVpp and frequencies of 10, 100, and 1000 with VIN = 140 mVpp, frequency = 100 MHz, at LET = 49 MeV·cm /mg. MHz.

Figure 4. Heavy-ion-induced SET cross-sections vs. effective LET for the LTC6400 with VIN = 2 mV at 10, 100, and 1000 MHz. Fig. 3. Heavy-ion-induced SET characteristics for the LTC6400 operating Fig. 4. Heavy-ion-induced SET error cross-sections vs. effective LET for 2 with VIN = 140 mVpp, frequency = 1000 MHz, at LET = 49 MeV·cm /mg. the LTC6400 with VIN = 2 mVpp and frequencies of 10 and 1000 MHz.

III. EXPERIMENTAL DETAILS TABLE II. We conducted the heavy-ion irradiations at the Texas HEAVY-ION SPECIFICATIONS.

A&M Cyclotron SEE Test Facility. The beam energy was 15 4 5 -2 -1 Peak Energy LET Range in Si MeV/amu. The flux varied from 1 × 10 to 1 × 10 cm s . Ion 2 · (MeV) (MeV·cm /mg) (µm) Table II lists the ion species used in the experiments, with Ne 300 2.5 316 their respective values for energy, linear energy transfer, and Ar 29 7.4 229 penetration range in silicon. The heavy-ion irradiations were carried out until 100 transients are observed and acquired, or Cu 944 17.8 172 up to a fluence of 2 × 107 cm-2. The proton experiment was Kr 152 24.8 170 conducted at the Indiana University Cyclotron Test Facility. Ag 1634 38.5 156 The beam energy was 198 MeV/amu. Various angles were used during the irradiations. IV. HEAVY-IONS During the irradiation runs, an RF generator provides a high frequency sinusoidal signal to the device input. A digital A. LTC6400 oscilloscope monitors the output. A computer controls the test setup, including the device operating conditions and We tested the LTC6400-20 for single-ended operation. transient trigger levels, via LabVIEW program. Two LTC6400 parts were irradiated at room temperature with

FigureFig. 5.2. Heavy-ion-inducedSET characteristics SETof the characteristics LTC6400 operating for the LTC6400with frequency operating = 100 Fig. 6. Heavy-ion-induced SET cross-sections vs. effective LET for the 2 2 with VIN = 2 mVpp, frequency = 10 MHz, at LET = 49 MeV·cm /mg. THS4304 at various operating conditions. MHz for LETeff = 49 MeV·cm /mg.

Fig. 7. Heavy-ion-induced SET characteristics for the THS4304 operating Fig. 8. Heavy-ion-induced SET cross-sections vs. effective LET for the 2 with VIN = 800 mVpp, frequency = 100 MHz, at LET = 67 MeV·cm /mg. LTC6400 and THS4304 operating at 100 MHz.

the devices operating at VCC = 3 V, VCM = 1.25 V, sinusoidal SETs at 1000 MHz erases several signal cycles, which can inputs of 140 mVpp (large signal) or 2 mVpp (small signal), at significantly impact device performance. frequencies of 10, 100, and 1000 MHz. Two ion species were We also evaluated the small signal performance. Unlike used for this experiment: Ar and Kr. the large signal response, the SET cross-sections are similar Fig. 1. shows the SET cross-sections from large signals for different frequencies, as shown in Fig. 4. The SET at 10, 100, and 1000 MHz. We observed SET LETth < 7.4 characteristics are also similar for the different frequencies. MeV·cm2/mg for all frequencies of operation. The SET cross- Fig. 5. shows a worst case SET at 1000 MHz. The SET has a section increases linearly with increasing frequency, partly voltage spike of ~ 110 mV, which is approximately 20× the due to reduced noise-margins and an increasing proportion of output’s amplitude. The signal recovers from the large clock edges [4]–[6]. The SET LET threshold may also exhibit voltage spike after 1 cycle, but remains unstable for several frequency dependence at smaller LET values. cycles. The SET characteristics also depend on the device’s We did not observe any destructive event, such as single operating frequency. SETs at 10 MHz appeared as small event latchup, during the irradiations at room temperature up glitches. The majority of SETs at 100 MHz are positive- or to fluencies of 2 × 107 cm-2. The supply current remained negative-going voltage spikes, which disrupt 1 to 2 bits of the relatively unchanged, at ~ 85 − 90 mA, throughout signal, as shown in FiG. 2. Fig. 3. shows a typical SET at irradiation. The parts were exposed to approximately 100 1000 MHz. A few of the SETs at 100 MHz and most of the krad(Si) total ionizing dose for the duration of the heavy-ion TABLE III. PROTON IRRADIATION INFORMATION AND SET RESULTS.

Beam Incident Angle Avg Flux Fluence Cross-section Run DUT Energy TID (krad) SETs (degrees) (#/(cm2·s)) (#/cm-2) σ (cm2) (MeV) 31 3 0 198 5.20E+08 1.00E+11 18.57 0 0 32 3 0 198 2.81E+09 1.00E+12 78.37 3 3.00E-12 33 3 60 198 2.98E+09 1.00E+12 138.17 8 8.00E-12 34 3 90 198 2.62E+09 1.00E+12 197.97 8 8.00E-12 35 3 0 198 2.91E+09 1.00E+12 257.77 15 1.50E-11 1 4 0 198 6.40E+08 1.00E+11 5.98 1 1.00E-11 2 4 0 198 2.97E+09 1.00E+12 60.00 3 3.00E-12 3 4 0 198 3.02E+09 4.00E+12 239.00 4 1.00E-12 4 4 0 198 3.00E+09 4.90E+11 3.34 1 2.04E-12 5 4 0 198 2.90E+09 2.00E+12 120.00 9 4.50E-12 6 4 0 198 3.03E+09 6.20E+11 37.00 3 4.84E-12 7 4 0 198 3.25E+09 2.00E+12 129.00 5 2.50E-12 8 4 0 198 3.10E+09 5.00E+12 300.00 19 3.80E-12 9 4 0 198 2.96E+09 5.00E+12 300.00 20 4.00E-12 10 4 0 198 3.10E+09 1.50E+11 1.20 0 0 11 4 0 198 3.04E+09 5.00E+12 300.00 16 3.20E-12 13 5 0 54 1.66E+09 1.00E+12 150.00 1 1.00E-12 14 5 0 54 1.69E+09 1.00E+12 300.00 0 0 15 5 60 54 1.69E+09 2.00E+12 600.00 1 5.00E-13 16 5 90 54 1.64E+09 2.00E+12 900.00 0 0 17 5 0 198 1.46E+00 2.00E+12 1020.00 5 2.50E-12

irradiation, with no significant effect on the SET cross- application circuits were VIN = 140 mVpp, 20 dB and VIN = section. 800 mVpp, 6 dB for the LTC6400 and THS4304, respectively. The SET cross-section for the LTC6400 is about half of B. THS4304 one magnitude larger than that of the THS4304. The SET 2 LETth for the THS4304 (< 15.6 MeV·cm /mg) is also higher Two THS4304 parts were irradiated with the devices than that of the LTC6400 (< 7.4 MeV·cm2/mg) at 100 MHz. operating with VCC+ = 2.5 V, VCC- = -2.5 V, sinusoidal Vin = Fig. 8. offers a quick comparison of the relative SEE 800 mVpp or 100 mVpp, 10, 100, and 200 MHz. Three ion performances of the state-of-the-art SiGe operational species were used for this experiment: Ne, Cu, and Ag. Fig. amplifiers of similar technology node. The LTC6400 and the 6. shows the SET cross-sections vs. LET, with the devices THS4304 have considerable differences in their processes, operating in various conditions. The SET LETth and error designs, and functions, which may lead to the differences in cross-sections vary with the LET, the operating frequency, their radiation performance. For example the THS4304 and the input signal. utilizes SOI CMOS, which is known to be more robust The SET LETth decreased while the SET cross-section against SEEs relative to Bulk CMOS. The SET susceptibility increased, with increasing frequency for large signals (1 Vpp). also depends on many other elements. As described The SET LETth and cross-sections for the small signal (100 previously, the different operation conditions for the input mVpp) showed negligible frequency dependence, similar to signals may also influence the SEE sensitivity. the LTC6400 part. The SET LETth is less than 4.4 2 MeV·cm /mg at 200 MHz. Fig. 7. shows a typical SET from V. PROTONS a large signal at 100 MHz. Approximately 1 − 2 data bits are affected by an SET at this frequency, similar to the LTC6400. We also examined the SEE susceptibility of the We did not observe any destructive event. LTC6400 with high energy protons. We tested 3 parts Fig. 8. shows the SET cross-sections for the THS4304 throughout two separate proton tests. The parts operated with and LTC6400, with both devices operating at 100 MHz. We VIN = 140 mVpp sinusoidal input signal and various note that there are differences in the operation conditions. frequencies. We observed SETs only at 200 MHz. We The magnitudes of the input signals and signal gains from the irradiated the first part (DUT3) with 198 MeV protons, at 0o, 60o, 90o, and again at 0o incident angles, up to a total proton low LET thresholds. The SET cross-sections increased with increasing frequency, similar to previous studies [5], [6]. The significance of the SETs also increased with increasing frequency. The most significant transients at 1 GHz for the LTC6400 erased several cycles of the output signal. The small signal response did not exhibit frequency dependence for either of the devices. Additionally the LTC6400 was robust against high energy protons, with relatively low SET cross-sections. We observed sharp increases in the cross-section at early stages of irradiation for each of the two parts. The increase in cross- section may be due to the increase in degradation from accumulated TID/DD. However the significant scatter in the dataset suggests that the SET cross-sections more likely follow a Poisson distribution, and do not correlate strongly with accumulated dose. The significant difference in the SET cross-sections for the two parts is also consistent with the large data scatter. In addition the different lot date codes of Fig. 9. Proton-induced SET cross-sections vs. accumulated proton fluence the parts may also contribute to the variability of their for the LTC6400 operating with VIN =140 mVpp and 200 MHz. radiation response. fluence of ~ 4.3 × 1012 cm-2. The proton fluence for each run was 1 × 1012 cm-2. The initial 0o incident run produced 3 VII. ACKNOWLEDGEMENT SETs. The following runs at 60o and 90o produced 8 SETs o This work was supported in part by the NASA Electronic Parts and each. The final run at 0 produced 15 SETs. Fig. 9. shows the Packaging Program (NEPP) and the Defense Threat Reduction Agency cross-sections vs. accumulated proton fluence, with noted (DTRA) under IACRO# 10-4977I. incident angles. The authors would like to thank Ray Ladbury for his insights on The increase in SET error cross-sections from 0o to 60o is statistical analysis. unlikely due to angular effects that can result from nuclear elastic scattering or spallation reactions [7], since the final 0o VIII. REFERENCES incident run produced a larger cross-section than the angular irradiations and the initial normal incident run. The data trend [1] J. A. Babcock, J. D. Cressler, L. S. Vempati, S. D. Clark, R. C. Jaeger, and D. L. Harame, “Ionizing radiation tolerance of high- suggests that the increase in error cross-section is possibly performance SiGe HBT’s grown by UHV/CVD,” IEEE Trans. Nucl. due to increases in accumulated TID and/or displacement Sci., vol. 42, Dec. 1995, pp. 1558 – 1566. damage. [2] J. Roldán, W. E. Ansley, J. D. Cressler, S. D. Clark, and D. Nguyen- We irradiated a second part (DUT4) with 198 MeV Ngoc, “Neutral radiation tolerance of advanced UHV/CVD SiGe protons at normal incidence up to a total fluence of 2.5 × 1013 NBTs,” IEEE Trans. Nucl. Sci., vol. 44, Dec. 1997, pp. 1965 – 1973. -2 [3] J. D. Cressler, “On the potential of SiGe HBTs for extreme cm to examine the effect of increasing proton dose. As environment electronics,” Proceedings of IEEE, vol. 93, Sep. 2005, shown in Fig. 9., the cross-section increases notably from a pp 1559 – 1582. proton fluence of approximately 5 × 1013 cm-2 to 8.2 × 1013 [4] P. W. Marshall, M. A. Carts, A. Campbell, R. Ladbury, R. A. Reed, -2 C. J. Marshall, S. Currie, D. McMorrow, S. Buchner, C. Seidleck, P. cm , but then decreases. There is significant scatter in the Riggs, K. Fritz, B. Randall, and B. Gilbert, “A comparative study of SET cross-sections. Therefore the dataset here is consistent heavy-ion and proton-induced bit-error sensitivity and complex with a Poisson distribution with allowable error deviations. burst-error modes in commercially available high-speed SiGe For example the first data point is based on 1 SET. BiCMOS,” IEEE Trans. Nucl. Sci., vol. 51, Dec. 2004, pp. 3457 – 3463. The notable difference in the magnitudes of the SET [5] P. W. Marshall, M. A. Carts, A. Campbell, D. McMorrow, S. cross-sections between the two parts may also be the result of Buchner, R. Stewart, B. Randall, B. Gilbert, and R. A. Reed, “Single the error deviations and/or part-to-part variations, as the parts event effects in circuit-hardened SiGe HBT logic at gigabit per have different lot-date-codes. second data rates,” IEEE Trans. Nucl. Sci., vol. 47, Dec. 2000, pp. We also irradiated a third part with 54 MeV protons at 2669 – 2674. o o o [6] R. A. Reed, M. A. Carts, P. W. Marshall, C. J. Marshall, S. Buchner, 0 , 60 and 90 incident angles. We observed a maximum of 1 M. La Macchia, B. Mathes, and D. McMorrow, “Single event upset SET up to 2 × 1012 cm-2 proton fluence at each angle. So the cross sections at various data rates,” IEEE Trans. Nucl. Sci., vol. 43, part is very robust against 54 MeV protons, with no signature Dec. 1996, pp. 2862 – 2867. [7] P. E. Marshall and C. J. Marshall, “Proton effects and test issues for of angular sensitivity. satellite designers,” in Proceedings IEEE NSREC – Short Course, 1999. VI. CONCLUSION [8] R. A. Reed, P.W. Marshall, H. S. Kim, P. J. McNulty, B. Fodness, T. M. Jordan, R. Reedy, C. Tabbert, M. S. T. Liu, W. Heikkila, S. Buchner, R. Ladbury, and K. LaBel, “Evidence of angular effects in We have evaluated the performance of two state-of-the- proton-induced single-event upsets,” IEEE Trans. Nucl. Sci., vol. 49, art commercial SiGe HBT-based operational amplifiers in Dec. 2002, pp. 3038 – 3043. heavy-ion and proton radiation environments. The devices were sensitive to heavy-ion-induced SETs, with relatively Radiation Testing a Very Low-Noise RHBD ASIC Electrometer Andrew R. Jones, Member, IEEE, Darren O’Connor, Edward Thiemann, Virginia A. Drake, Gregory Newcomb, Member, IEEE, Neil White, Dean D. Aalami, Henry L. Clark, Raymond L. Ladbury, Barbara von Przewoski, Sharon Dooley, Seth Finkelstein, Porter Haskins, Vicki Wei Hsu, Brian Kirby, Tom Reese, and Patricia Soto Hoffmann

Abstract—We report the results of Single Event Effect (SEE) between the two devices. The ASIC is fabricated using the and Total Integrated Dose (TID) testing of a very-low-noise ON Semiconducter C5N process through the MOSIS service. six-channel electrometer Application Specific Integrated Circuit A custom package was developed for the ASIC. The pack- (ASIC) constructed through the MOSIS service using the ON Semiconductor C5N process. The ASICs were designed using age provides a very small footprint, and has been optimized to Radiation Hard By Design (RHBD) layout rules, and TID reduce leakage currents and capacitance at the analog inputs. mitigation strategies. This testing provides a verification that the The package was built by Kyocera America Inc. (KAI) who device does not show latch-up behavior, and that performance is also installed the ASIC die into the package. Parts were not unduly compromised by TID. The SEE testing, using heavy delivered from KAI for testing in two configurations: loosely ions, took place at the Single Event Effects Facility at Texas A&M University using the 24.8 MeV/u beam with ions Ar, Kr, lidded parts (so that the lid could be removed, for SEE testing) and Xe giving a range of Linear Energy Transfer (LET) at the and brazed, hermetically sealed parts for all other tests. No device of 7.5–63.5 MeV cm2/mg. No latch-ups were seen even performance difference was observed between the parts with ◦ at an elevated temperature (30 C). TID testing using protons hermetic or loose lids. was conducted at the Indiana University Cyclotron Facility on the Radiation Effects Research Program RERS2 beamline. Parts were tested to a total dose of 300 krad(Si). As these ASICs are II. ASIC FUNCTION AND MODES constructed using CMOS technology there will be no Enhanced A. Principle of Operation Low Dose Rate Sensitivity (ELDRS). The ASIC comprises six nearly identical channels. Fig. 1 shows a block diagram of a single channel. This is a preci- I. INTRODUCTION sion synchronous current-to-frequency converter with a 20-bit E have developed a mixed-signal ASIC electrometer counter and shift register to read out the integrated current. W (digital electrometer) in a collaboration between the Laboratory for Atmospheric and Space Physics (LASP) and Space Instruments [1]. The ASIC is optimized to digitize fA level currents from EUV photodiode arrays, replacing the traditional electrometer-VFC-counter system with a multi- channel, single-chip solution. An iterative approach was taken to the ASIC design. The first device (Test Chip 1 — TC1) was used to characterize the transistor geometries. TC2 had the full analog and digital sections in a 4-channel device. TC3 implemented the RHBD rules. TC4 and TC5 were the full 6-channel 20-bit devices with RHBD, and are the devices described in this paper. There are slight clocking differences between TC4 and TC5, but most of the design is common

Manuscript received July 28, 2010. This work was carried out under NASA contract: NNG07HW00C. Fig. 1. Block diagram of a single electrometer channel. The precision current A. Jones, D. O’Connor, E. Thiemann, V. Drake, G. Newcomb, N. White, source, comparator reference voltage (Vref) and clocking signals are shared S. Dooley, S. Finkelstein, P. Haskins, V. Wei Hsu, B. Kirby, T. Reese, and P. between all six channels. The shift registers for both the data and control Soto Hoffmann are with the Laboratory for Atmospheric and Space Physics, registers are daisy-chained internally, so the digital signals act on the entire University of Colorado at Boulder, 1234 Innovation Dr., Boulder, CO 80303- chip. The analog inputs (pins iIn and Ref ) of all channels are isolated from 7814 USA e-mail: ([email protected]). each other. D. Aalami is with Space Instruments, 19 Hammond #508, Irvine, CA92618- 1636 USA . H. Clark is with the Cyclotron Institute, Texas A&M University, College The input current is integrated, and when the voltage on Station, TX 77843 USA. CInt exceeds the reference voltage (Vref ), the state of the R. Ladbury is with the Radiation Effects and Analysis Group, comparator will change. When the next sample clock goes NASA/Goddard Space Flight Center, Greenbelt, MD 20771 USA. B. von Przewoski is with the Indiana University Cyclotron Facility, Bloom- high, a precision charge packet is switched to the summing ington, IN 47405 USA. node of the integrator, and this continues until the incoming

978-1-4244-8404-1/10/$26.00 ©2010 IEEE current is balanced. Thus, the number of charge packets is SEE testing was performed in both the normal and calibra- proportional to the input current. The difference between TC4 tion modes, and the effects of TID on the calibration capacitor and TC5 is that the charge bucket is formed based on the clock were investigated. period in TC5, rather than being defined by the pulse width in TC4 and earlier versions. This reduces the sensitivity of the III. EXPERIMENTAL SETUP system to clock jitter. A. Pre-test Characterization At these small charge levels, extreme care has been taken to balance the switching transients, as the charge is formed Before shipping to the beam lines, the electrical perfor- and delivered to the summing node. To further reduce noise, mance of the ASICs was characterized. The laboratory setup the digital side of the ASIC is switched off during integrations is computer controlled and uses a Keithley 4200-SCS with and only the sample clock is running. remote low-noise preamplifiers to drive the ASIC electrometer The ASICs we are testing use a sample clock frequency inputs. The electronics to control and read data from the ASIC of up to 1 MHz. The precision current source is externally comprises three main parts: programmed using an external resistor connected to Rext,to 1) The ‘APGSE’ is the computer interface and ASIC digital provide charge packets: timing section. An 8051 microcontroller is used to (1.5 V ) handle the computer interface as either RS232 or USB. I = F × × k An FPGA is programmed to provide the clocks needed max SampleClock R (1) ext to control the ASIC. (Imax/FSampleClock) IDN = (2) 2) A ‘mother board’ connected by a ribbon cable to the Tint APGSE buffers the digital signals to and from the ASIC Where: and also regulates and filters the power supplies needed by the ASIC. Imax is the maximum input current to be measured k is constant related to the current divider in the 3) An ASIC ‘baby board’ holds the ASICs themselves. ASIC = 1.667×10−8 It is built of very low-leakage Rogers 4000 material. Individual ASICs are soldered to their own baby boards. Rext is the external current programming resistor FSampleClock is the frequency of the sample clock A recirculating chiller/heater under computer control is used IDN is the ASIC’s current resolution to stabilize the temperature of the ASIC under test. The set- (Current per DN) point temperature and the PID control is set by the control 1.5 V is the voltage across Rext computer. A block diagram of the setup is shown in Fig. 2.

B. Offset and Calibration A control register is used to set up the operation of each channel. This comprises a 14-bit register and latch. Twelve of these bits set a DAC that is used to balance the input of the integrator ampliﬁer. In operation, the offset is set so that, with 0 A input, a small count (approximately 10 DN) is counted on the output. This will allow for any possible negative drift in the baseline. The DAC has 12 bits; two bit pairs carry the same nominal weight. This allows for some manufacturing tolerance in the divider networks so that a good balance can always be achieved. An additional feature built into the ASIC is the ability to perform ‘in circuit’ calibration of each channel. Two bits of the control register set switches to setup the calibration. A reference capacitor (nominally 1 pF) is switched into the summing node. A ramped voltage applied to the CALin pin Fig. 2. ASIC characterization setup showing the interconnection of the results in a known current at the input: control computer, APGSE, mother board, baby board (with ASIC) and temperature control.

ical = CCAL × dV/dt (3) When making measurements at the fA level, great care By varying the ramp rate, each electrometer channel can be needs to be taken in the grounding schemes to prevent stray calibrated at different points over its range. During offset and currents from overwhelming the measurement. This is impor- calibration modes, the input signal is not switched out of the tant not only at the inputs — that are all fully guarded — circuit. As the shunt resistance of the detector forms an integral but in the entire setup. The scheme we used is also shown in part of the offset circuit, it can not be removed from the input Fig. 2. to perform calibrations. Therefore, a shutter or other means A full characterization test for all six channels of a single should be used to interrupt the light path during calibrations. ASIC takes about 22 hours. The test measures gain, linearity, TABLE I gain calibration and offset for each channel. The leakage cur- LET AT DEVICE FOR DIFFERENT IONS AND ANGLES.INALLCASESTHE rents between the calibration pin and input are measured. The BEAM WAS TUNED TO 24.8 MeV/u tests also check for any crosstalk between channels at various Ion Angle of Incidence Effective LET (MeV cm2/mg) current inputs. These tests are performed at two temperatures, ◦ ◦ ◦ Xe 45 63.5 nominally 0 C and 10 C. The test runs completely auto- Xe 0◦ 44.9 ◦ matically. For each test, 812 ASIC performance parameters Kr 45 33.1 Kr 30◦ 27.0 are calculated. The only human intervention necessary in the Kr 0◦ 23.4 process is to swap ASIC chips by removing one ‘baby board’ Ar 45◦ 10.6 ◦ and replacing it with another, and then starting both the test Ar 0 7.5 and data analysis programs.

be changed out. The ASIC test data is taken at 0◦,30◦ and B. Single Event Effects Testing Setup 45◦ to sample the range of LETs shown in Table I. All SEE testing was conducted the Cyclotron Institute at During heavy ion testing, the parts were operated in their Texas A&M University at the Radiation Effects Facility. Parts normal and calibration modes. The power to the voltage for the SEE testing were delivered from Kyocera America Inc. regulators was supplied by a Keithley 2636 dual-channel (KAI) with the lids loosely attached. Once the ASIC boards source meter. The compliance (current limit) was set on each were mechanically mounted in the beam fixture the lids were output voltage of the Keithley, and the current and compliance removed to expose the Si. The parts were then bagged in a recorded during a beam exposure. Data from the device under TM 3M SCC 1000 antistatic bag and GN2 flowed into the bag test was also continuously recorded. to prevent condensation on the ASIC or support electronics. To look for Single Event Upsets (SEUs) in the digital The 79 µm thickness of the bagging material and the air gap sections, data loaded into both the command and data shift to the part were taken into account in the LET calculations. registers were compared on a second-by-second basis before During SEE testing, the device has to be operating and and after each measurement integration. The number of bit returning data. The standard support electronics described errors was automatically recorded. above were used to control the ASIC except that the inputs At the end of each individual test run, the total number of were not driven. Rather, each input was terminated with a errors over that run was also recorded in a master spreadsheet 1GΩ resistor that simulates the detector impedance. The containing information about the beam conditions during the control computer and drive electronics were located with the run. device at the end of the beamline. To operate the system, a The results of Xe and Kr beam runs are shown in Fig. 5. No second computer was used with remote desktop software to SEUs were seen in any of the Ar beam data. However, there monitor the setup from the safety of the control room. were definite data ‘spikes’ during the Ar beam runs. These can be explained as energy from the incoming ion being deposited in the analog portions of the ASIC.

C. Total Integrated Dose Testing Setup All TID testing took place at the Indiana University Cy- clotron Facility on the Radiation Effects Research Program (RERP) RERS2 beamline. For all the tests 198 MeV protons were used. The TC4 and TC5 ASICs used for the TID testing were packaged in the same custom KAI ceramic package used for the SEE testing, but this time they had a standard hermetic lid. The ASIC baby boards were mounted onto a biasing board as operation is not required during testing. The bias board provided +5 VDigital and ground to the supply pins. The digital clock pins were held at 0 V through a 1 kΩ resistor. All digital outputs are terminated in 10 kΩ loads. The analog side biasing Fig. 3. ASIC setup at the end of the SEE beamline at Texas A&M. During was held at 0 V using 10 kΩ resistors to ground. The analog testing, the ASIC board is enclosed in a thin bag and purged with GN2 inputs were terminated in a 1 GΩ resistor that matches the to prevent condensation on the device or test ﬁxture which are temperature controlled. The photograph shows the ASIC with the cover taped on with shunt resistance of the detectors that will be used with the Kapton tape. Before exposure the cover is removed (inset) to expose the die. ASIC. The calibration input pins are also taken to ground through a 1 kΩ resistor. Devices were irradiated to the levels The ASIC mother board and baby board were mounted on a shown in Table II. computer controlled X-Y-Z-Θ stage at the exit of the beam port Between irradiations a limited performance test is conducted (Fig. 3). The stage is under computer control and a positioning to measure the offset, gain and linearity of the ASIC at a camera is used to align the device under test with the beam. single ﬁxed temperature. It is not possible to perform a full The stage is moved back from the beam port to allow parts to characterization of the part in the 1 hour period required by Fig. 4. ASIC setup at the end of the RERS2 beamline. The ASIC is mounted on a bias board described in Section III-C. For these tests the ASIC is in a lidded KAI package. The ASIC is centered on the beamline using a laser cross hair (seen in the inset). The ASIC is mounted 12 from the beam exit port, as this is where the dosimetry is performed.

MIL-STD-833, Method 1019. All parts survived irradiation functioning, except for part TC4-26 taken to 5 ×1012 p/cm2, whose counts were saturated immediately after irradiation. All parts undergo a full characterization after they are returned to LASP, however, they were not kept cold, so it is possible that some annealing took place. Furthermore, some of the parts were re-characterized after spending 1000 hours at 125◦Cto look for trap migration effects.

TABLE II Fig. 5. SEE test data for Test chips 4 and 5. Cross Section is defined as the number of single event effects / fluence (SEEs / particle / cm2). In this case IRRADIATION LEVELS FOR THE TC4 AND TC5 ASICS.LEVELS IN BOLD × FACE WERE THE TOTAL DOSE FOR THAT DEVICE, AND THUS THE LEVELS the number of SEUs is 2 the number recorded by the software as explained AVAILABLE FOR THE FULL CHARACTERIZATION TESTS AT LASP in Section IV-A. It can be seen that for both devices the threshold LET is about 22 MeV cm2/mg and that saturation occurs at a cross section of about 2 × 10−4, which is equivalent to about 4 upset events during 15 year mission Part Serial Fluence 2 in geostationary orbit at a 90% confidence level. Type # (protons / cm ) TC4 18 5.03×1010,6.26×1011, 2.68 × 1012 TC4 20 6.26×1011 11 12 12 TC4 26 6.26×10 ,2.68×10 , 5.02×10 B. Total Integrated Dose Effects TC4 35 1.26×1010, 2.52×1010 10 11 11 TC5 31 5.00×10 ,1.67×10 ,2.85×10 , The parameters that we are most concerned about are shifts 7.88×1011, 1.63×1012 TC5 36 5.02×1010 in the offset current, changes in device gain (counts / fA) and TC5 38 3.38×1011 nonlinearity. The results of TID on these parameters is shown in Fig. 6. The parameters are all obtained by performing a weighted least-squares fit to recorded counts vs. known input It should be noted that these devices are CMOS technology currents measured using exactly the same testing setup de- parts so there is no susceptibility to Enhanced Low Dose Rate scribed in Section III-A. All parts functioned after irradiation Sensitivity (ELDRS). to 2.68×1012 p/cm2 (160 krad (Si)). However, the single part exposed to 5.02×1012 p/cm2 (300 krad (Si)) showed IV. RESULTS all channels at maximum counts when tested immediately A. Single Event Effects after irradiation. On return to LASP, some of the channels The experimental design allowed us to look for SEU events of TC4-26 had returned to less than saturation, but the part in both the 20-bit data output shift register and the 14-bit was essentially uncharacterizable. command shift register. However, events in the data counters As mentioned in Section II-B, each channel of the ASIC and command register can not be directly measured. The provides an internal capacitor that can provide an in-circuit circuitry for the shift registers and counters is almost identical, calibration. This works by switching a known capacitor into so it is not unreasonable to assume an error rate in these the input. It is thus important to know if this capacitance circuits to be the same as that in the shift registers so the changes under dose (as this can be used to correct for any actual error count reported by the software is doubled to get gain changes). Fig. 7 shows that the capacitance (formed the true bit error rate. between poly1 and poly2 layers) is essentially unchanged by proton irradiation. These data were taken immediately after irradiation.

Fig. 7. Change in calibration capacitor vs. irradiation. There is essentially no change in the value of the calibration capacitor (Ccal) at these dose levels. The error bars represent the 1σ spread in the measured data.

To look for any effects of trap migration some of the irradiated parts were included in a separate accelerated life test. The results for the change in RMS noise are shown in Fig. 8.

Fig. 6. Changes in device parameters for Test chips 4 and 5 after proton exposure. The data from TC4 and TC5 were combined as there was no statistical difference between them. The offset and gain are calculated from the slope and crossing point of a weighted least-squares fit to the data for various imposed input currents. The offset current change reported is the averaged |(Offsetdose -Offset0dose)|.The percentage gain change is calculated as the average over all channels for a given exposure of|((Gdose -G0dose)/ G0dose)|. The fractional linearity difference is calculated as averaged |[1-(IEST dose/IMEAS dose)]| - |[1-(IEST 0 dose)/IMEAS 0 dose)]|. Fig. 8. Measured average RMS noise for three of the irradiated devices The diamond points represent data taken at IUCF as soon after irradiation during a 1000 hour accelerated life test at 125◦C. The ASIC that had been as was possible. The bars represent the 1σ variations in the measurements. irradiated to 5.02×1010 (300 krad(Si)) was so unstable that no measurement The open circles are the results obtained using the full device characterization could be made at the 0 hours point. However, all devices show a reduction after the devices were returned to LASP. in noise at the first sample time and a slight increase towards the end of the test. V. C ONCLUSION We have characterized two versions of a RHBD very low- noise digital electrometer for both SEE and TID effects. We have demonstrated that in this case the RHBD rules that prevent parasitic SCR structures have produced a chip that is not susceptible to latch-up, at least to an LET of 63.5 MeV cm2/mg, even at elevated temperature. As expected, no significant difference was seen in any of the data between Test Chip 4 and Test Chip 5 as there were no significant differences in the device geometries. Furthermore, we have characterized a device working in the fA regime and have seen that by careful choice of transistor geometries and layout and the use of edgeless transistor geometries, leakage current from TID can be maintained at low levels. There is possibly some slight annealing effect in the offset current, which drops by a factor of almost two when retested at LASP, though this might just have been a radiation induced current in the amplifier. The gain and offset of the electrometer appear to show a slow function of dose. However, as there seems to be no change in the capacitor used for the internal calibration, the gain change can be measured. Dark measurements will allow any changes in the offset to be removed. Changes in linearity are very small. Finally, as part of a parallel effort to assess the reliability of the ASIC some parts have undergone a 1000 hr 125◦C accelerated life test. Three of the TID test parts were included in this test to see if there were any trap migration effects in the irradiated parts. In fact, it looks like annealing takes place in these parts with a reduction in measured RMS noise. Indeed, the part that had been exposed to the highest dose actually recovered and behaved like all the other parts.

ACKNOWLEDGMENT The development would not have been possible without the dedication and expertise of many skilled engineers, scientists, and managers at LASP and Space Instruments. We would like to thank them all for the long hours they have put into this project already and for those to come. We would especially like to recognize the major contribution to this work by the undergraduate and REU students Vicki, Porter and Brian, who did a lot of the testing and data analysis presented in this paper. We would like to thank the beam operators and support staff at both TAMU and IUCF. Their professionalism, helpfulness, and knowledge makes our jobs much easier.

REFERENCES [1] Aalami, D. D. and Jones, A. R., “A low-noise ASIC electrometer for precision low-current measurements,” in [Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series], Fineschi, S. and Fennelly, J. A., eds., Solar Physics and Space Weather Instrumentation III 7438 (September 2009).

Hardening of Texas Instruments’ VC33 DSP

Robert Fuller, Wesley Morris, David Gifford, Rex Lowther, Jon Gwin, James Salzman, David Alexander and Ken Hunt

SST’s HardSIL™ process modules. Radiation testing has Abstract—A hardened version of Texas Instruments’ VC33 shown that TID, DR and SEE performance are significantly Digital Signal Processor was created without any mask changes. improved in the VC33 DSP manufactured with the The commercial mask set was processed using Silicon Space HardSIL™ modified process. Technology’s HardSIL™ process variant to produce the hardened version. Radiation testing of the resulting hardened circuit demonstrated significant improvement in performance.

I. INTRODUCTION ILICON Space Technology (SST) was awarded a SBIR SPhase II contract by MDA in April 2008 to manufacture a hardened version of Texas Instruments’ (TI) VC33 Digital Signal Processor (DSP). The approach for producing a radiation-hardened 250nm VC33 incorporates SST’s proprietary HardSIL™ techniques for improving circuit performance in extreme environments. In the HardSIL™ approach, radiation-hardening process modules were introduced into TI’s commercial 250nm (VC33) CMOS process flow. This approach, depicted in Fig. 1, allows existing off-the-shelf commercial circuits to be radiation hardened without circuit redesign. Additionally this approach Fig. 1. SST manufacturing model at a commercial foundry with enables the design and production of custom ASIC’s using HardSIL™™ process enhancements added to create a radiation-hardened the same layout rules and standard cell libraries used in silicon process – the “RH Client Process.” commercial circuits. Hardening is achieved by manufacturing the ASIC with the HardSIL™ modified process. This II. DESCRIPTION OF THE VC33 DSP manufacturing approach allows maximum circuit packing The TMS320VC33 DSP is a 32-bit, floating-point density and low power; and it minimizes the circuit area, processor manufactured in TI’s 250nm four-level-metal power, performance and cost penalties normally associated CMOS technology. The TMS320VC33 is part of the with a Radiation Hardened-by-Design approach. Key to the TMS320C3x generation of DSPs from Texas Instruments. HardSIL™ approach is that it provides a solution for all The TMS320C3x’s internal busing and special digital-signal- radiation environments both natural and man-made. processing instruction set have the speed and flexibility to HardSIL™’s minimally invasive hardening methods [1], [2]; execute up to 150 million floating-point operations per previously shown to address Total Ionizing Dose (TID), second (MFLOPS). The TMS320VC33 optimizes speed by Single-Event Effects (SEE), and Dose Rate (DR); are implementing functions in hardware that other processors demonstrated again in the VC33 catalog DSP COTS part implement through software or microcode. The manufactured by TI. No circuit design, layout, or package TMS320VC33 can perform parallel multiply and ALU changes were made to achieve radiation hardening of the operations on integer or floating-point data in a single cycle. VC33. The exact same standard commercial design was Each processor also possesses a general-purpose register file, simply run through TI’s 250nm CMOS process augmented by a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and

Manuscript received Match 10, 2010. This work was supported in part by a short machine-cycle time. General-purpose applications are the U.S. Missile Defense Agency under SBIR Phase II contract W9113M-08- greatly enhanced by the large address space, multiprocessor C-0163 interface, internally and externally generated wait states, one R. Fuller, W. Morris, D. Gifford, R. Lowther and J. Gwin are with Silicon external interface port, two timers, one serial port, and Space Technology, Austin, TX 78738 USA (telephone: 512-347-1803, e- mail: [email protected]). multiple-interrupt structure. The TMS320C3x supports a J. Salzman is with Texas Instruments, Sherman, TX 75090 USA. wide variety of system applications from host processor to (telephone: 214-538-5086, e-mail: [email protected]). dedicated coprocessor. High-level-language support is easily D. Alexander was with the Air Force Research Laboratory, Albuquerque, implemented through a register-based architecture, large NM 87117 USA, now retired). K. Hunt is with the Air Force Research Laboratory, Albuquerque, NM address space, powerful addressing modes, flexible 87117 USA

instruction set, and well-supported floating-point arithmetic. assembly level “instruction set” can be programmed directly The TMS320VC33 has 1 Mb of on-chip SRAM. in the ATV environment.

III. TEST PROCEDURE A. Test Hardware A J/D Instruments ATV tester was used to evaluate device performance during radiation tests. J/D Instruments was also contracted to build the test board and develop the test program for the tests. The J/D Instruments tester connects via three meter cables to a test head. A test board to hold the device under test (DUT) is then either plugged directly into the test head, or extension cables (up to one meter in length) can be used to separate the test board from the test head. The test-head-to- test-board extension cables limit the frequency at which the DUT can be operated, so these extender cables were only used when the test environment required the test board and Fig. 2. Typical radiation test set up test head to be physically separated. In all tests, the tester was placed behind appropriate In this way a program was created to isolate the DSPs major shielding to protect the sensitive electronics in the tester from subsystems for independent test (to the extent possible). irradiation. In tests where the directionality of the radiation In general, the approach was to first create a test where was not controllable (i.e. TID and dose-rate tests) extender only the Program Control circuitry (PC) of the DSP is cables were used between the test board and test head to exercised. Since the PC is involved in operating other allow shielding of electronics within the test head. subsystems, its failure levels provide a “baseline” for the part. The J/D Instruments tester is controlled using a laptop In other words, the radiation sensitivity of other subsystems computer connected to the tester through USB. USB distance can only be differentiated if they are more susceptible to limitations combined with long distances between control and radiation than the PC portion. Based on previous experience source/target rooms at the test facilities required additional it was expected that the PC circuitry would be the most hardware to allow the controller computer to interface with radiation resistant portion of the parts because its circuitry is the tester over the required distances. A Black Box Remote usually fairly simple, being composed mainly of control Port USB 2.0 → CAT5 Port Extender was employed to circuitry and registers. increase maximum allowable distance between the tester and After the PC failure level was established, separate test computer controller to 50 meters. Most radiation test facilities programs were exercised to test other individual subsystems provide CAT5 Ethernet cables between the control and including: source/target chamber; so the USB → CAT5 port extender embedded RAM, was a perfect solution. A diagram of the hardware set up is embedded registers, shown in Fig. 2. ALU, and B. Test Software CPU. Testing DSPs and microprocessors using general IC testers IV. TOTAL DOSE TESTING RESULTS has been problematic in the past due to the complexity of these devices. DSPs are actually integrated systems and Testing was performed using the Cobalt 60 gamma-ray subsystems with many additional IC technology types system at the Air Force Research Laboratory facility on embedded as internal “peripherals.” Previously the Kirtland AFB, NM. The test boards were constructed so specialized requirements of these parts has led to testing multiple samples could be irradiated and measured in situ. approaches that made dynamic upset and some in-situ testing Samples from two process splits were measured: control parts abstract – potentially missing many failures. Often design or which were not processed through the hardened steps and the application programs and vectors were run during test to hardened parts which included the hardened process steps. create a pass/fail type test, rather than create programs that The parts were irradiated with a checkerboard (CB) pattern specifically separate out and test the various sub-system stored in the internal memory and the standby current was components. This did not give insight into the processor measured with the checkerboard pattern and the inverse failure levels, mechanisms, and modes [3], [4]. checkerboard pattern in memory after irradiation. The devices For testing of the VC33 DSP, the ATV test software was were also tested for PC (basic function), CPU, and ALU enhanced to make testing of microprocessors and DSPs a functionality. The control parts exhibited a rapid increase in single step, completely inclusive solution. Specifically, the standby current for TID > 50 krd(Si). After TID = 100 ATV technology was advanced so that a processor’s krd(Si), the worst-case standby current for the controls was 500 mA. The controls also exhibited memory failures starting

at 75 krd(Si) and memory plus functional fails at 100 krd(Si). In contrast the hardened split significantly outperformed the control parts. Hardened parts exhibited a much slower increase in standby current. After TID = 1 Mrd(Si), the worst- case standby current was 70 mA for the hardened process with the checkerboard (CB) pattern stored in the array. Fig. 3 shows the control and hardened Device-Under-Test (DUT) standby current vs. TID curves with CB patterns. No functional or memory fails were observed for the hardened part. It should be noted that the standby currents for the checkerboard and inverse checkerboard patterns were similar when measured after irradiation for all samples.

Fig. 4. Standby current vs. TID as a function of dose rate for control and hardened samples. The standby current for the hardened samples decrease with dose rate. The current is unaffected by the dose rate for the control samples.

Fig. 3. Standby current as a function of total dose for the hardened and the control samples. The hardened sample showed no functional failures after 1 Mrd(Si) where the control sample failed after less than 100 krd(Si).

A second set of tests was performed in the gamma cell to determine the effect of gamma cell dose rate on total dose Fig. 5. Standby current after 200 krd(Si) vs. TID dose rate for the performance. These results are shown in Fig. 4. The post- hardened parts. The increase in current post radiation decreases linearly with irradiation standby currents for the control parts show no the dose rate, suggesting little or no change at the dose rates in most orbits. direct correlation to the gamma cell dose rate. The hardened parts show a clear correlation with reduced standby current In contrast, neither single bit upsets nor CPU errors were after 200 krd(Si) as the dose rate is reduced. Fig. 5 shows the observed for the hardened samples up to the highest dose rate 10 relationship between the current after 200 krd(Si) and dose achievable in the flash X-Ray system (1.73 × 10 rd(Si)/s). rate is approximately linear and suggests that the standby As expected the hardened parts also did not latch up at the current for the hardened samples will not shift at the dose highest dose rate. As shown in Fig. 6, the hardened parts rates encountered in most orbits. showed an improvement of over five times in dose rate hardness from the commercial parts. V. DOSE RATE TESTING RESULTS VI. SINGLE EVENT TEST RESULTS Testing was performed using the flash x-ray system at the Air Force Research Laboratory facility on Kirtland AFB, A. Single Event Upset NM. Commercial grade VC33 DSPs (control samples) Testing was performed using the cyclotron at Texas A & 9 exhibited single bit memory upset at 3.57 × 10 rd/s and CPU M University (TAMU). Many tests were run to test the 9 dynamic upsets at 7.77 × 10 rd/s. However, no latch-up was various components of the DSP. As would be expected the observed for the commercial VC33 at the highest dose rate. on-chip memory showed the most sensitive and largest cross- section. Figure 7 shows a linear Weibull fit of the memory upsets vs. LET. While the onset LET is similar for both samples, the plot shows that the hardened parts have lower native cross-section at higher LETs.

B. Single Event Latch-up Test Results The samples were tested for single-event latch-up by exposing the sample to a fluence of 1×107 ions/cm2. The supply current was monitored to determine if latch-up had occurred. Table II shows a summary of the observed latch-up behavior. At temperatures above 85⁰ C the control parts latched at an LET of 21.5 MeV-cm2/mg. At room temperature the control samples latched at LET’s of 74 MeV- cm2/mg and above. In contrast the hardened VC33 DSPs did not show any latch-up even at an LET = 125 MeV-cm2/mg while operating at a temperature of 150˚C and an overvoltage of 10% (1.98 V).

TABLE I SUMMARY OF ERROR RATES FOR VC33 SUB-CIRCUITS

Fig. 6. Dose rate testing results showing no errors for the hardened part at the maximum achievable dose rate.

This has previously been shown to be due to the charge coupling effect leading to the higher occurrences of large MBUs (multiple-bit upsets) with control parts vs. the hardened parts [5].

TABLE II SUMMARY OF LATCH-UP TEST RESULTS

Fig. 7. Device cross sections and Weibull fits as a function of effective LET for the VC33 DSP memory. While the onset for both samples is similar, the saturation cross section is lower for the hardened device. The cross section for both parts deviated significantly from the Weibull fit at high LET’s.

Multiple tests were conducted; similar curves were derived for the various other DSP subcircuits; and each curve was fitted with a Weibull function. The resulting coefficients were entered into the CRÈME96 software and the error rates for a The 25MHZ CPU test was the most sensitive to latch-up, geosynchronous orbit at a solar minimum were calculated. especially at the higher temperatures. Latch-up was observed These results are summarized in Table I. The hardened part’s for others tests on the control part. No latch-up was observed memory error rate is improved by over 25% from the control for the memory test. parts; and these errors are many times more frequent than are the errors in the other DSP subcircuits

VII. SUMMARY SST has demonstrated hardening of a commercial DSP without any design or mask changes. TI’s commercial 250nm VC33 DSP was hardened using SST’s HardSIL™ techniques. The circuit demonstrated robust die yield at first silicon. The hardened VC33, radiation tested for DR, TID, and SEE, shows the following achievements: • DR threshold exceeding 1.7×1010 rads(Si) • TID performance of ~1Mrad(Si) with no bit or functional fails and < 70mA post radiation ISB. • A 2x improvement (reduction) in SEU cross-section at high LET • Complete elimination of SEL at LET> 125 MeV- cm2/mg while the circuit was operating at 150˚C and at 10% over voltage.

VIII. ACKNOWLEDGMENT Silicon Space Technology thanks David Sleeter and Jake Tausch of J/D Instruments for their considerable effort in developing test hardware and software for this project. We also thank Jake Tausch for his assistance in the testing of the parts.

IX. REFERENCES [1] W. Morris, R. Lowther, D. Alexander, J. Gwin, “Buried Guard Rings as a Solution to Single-Event Effects,” Hardened Electronics And Radiation Technology (HEART) Conference, March, 2007. [2] W. Morris, R. Lowther, J. Gwin, “Application of the Parasitic Isolation Device (PID) into a 180nm Commercial CMOS Process to Achieve Megarad TID Hardening,” Hardened Electronics And Radiation Technology (HEART) Conference, March, 2007. [3] Kinnison, J.D.; Maurer, R.H.; Carkhuff, B.G.; Conde, R.F.; Buchner, S.P.; Kang, K.; Stapor, W.J.; Campbell, A.B.; Herlich, G.A.; Moore, H.C., “Radiation characterization of the ADSP2100A digital signal processor,” IEEE Trans. on Nucl. Sci., vol. 39, no. 3, , pp. 1398 - 1402, Dec. 1991. [4] Harboe-Sorensen, R.; Seran, H.; Armbruster, P.; Adams, L., “The single event upset response of the Analog Devices, ADSP2100A, digital signal processor,” IEEE Trans. on Nucl. Sci., vol. 38, no. 6, , pp. 441 - 445, June. 1992. [5] Robert Fuller, Wes Morris, Jon Gwin, Rex Lowther, Dave Gifford, Paul Young, “Performance of SST 16Mb SRAM,” Hardened Electronics and Radiation Technology (HEART) Conference, April, 2009.

SEU Testing of SiGe Bipolar and BiCMOS Circuits

David L. Hansen, Anthony Le, Kay Chesnut, Eric Miller, Steven Pong, Sichul Sung, John Truong

two divide-by-8 circuits designed by Boeing and fabricated in Abstract— Bipolar and BiCMOS divider circuits were tested IBM’s SiGe 7HP process,. The first is a multiplexing digital to using heavy ions to determine their sensitivity to single-event analog converter (MUX-DAC), tested to determine the effects (SEE) in terms of differences in cross-section and upset susceptibility of the MUX-DAC to SEL and SEU sensitivity duration. No single-event latchups (SEL) were observed under any conditions. A triple-mode-redundant (TMR) design was of the clock divider sub-circuit. SEL is primarily a concern for found to be effective in reducing the SEE cross section and the CMOS circuitry within the MUX-DAC. The fact that this preventing phase-shift upsets which were the dominant upset type is a BiCMOS circuit allows us to test for additional upset in the non-hardened design. characteristics associated with the integration of bipolar and Index Terms— Silicon Germanium, SiGe HBT, Single Event CMOS transistors in this technology. The second circuit tested Upset, Heavy Ion. was a TMR divider designed with HBTs only. We present results showing the changes in the SEU sensitivity due to the

I. INTRODUCTION TMR circuitry, the device bias and input signal strength. PACE provides a particularly hostile environment for the Soperation of communications systems. Environmental II. EXPERIMENTAL SETUP irradiation can interact with the semiconductor material depositing energy and causing a variety of deleterious effects. A. MUX-DAC Description Single event upsets (SEU) can vary from transients (SET) The first device under test is a 10-bit monolithic high-speed, which cause a temporary corruption of data and may have little MUX-DAC (Fig. 1). It is capable of receiving multiple, 10-bit or no system level impact; to more damaging failures such as data streams at a nominal rate of 384 Mbps. In normal single-event latchup (SEL) which can, in some cases, result in operation, the DAC simultaneously clocks in up to six, 10-bit the catastrophic failure of the operating part and mission data channels. At each rising clock of the DAC clock, the failure. Thus it is necessary to show that that any circuit used MUX-DAC sequences through each data port, to perform the in an on orbit application will be sufficiently robust to conversion. The process is repeated at the completion of all radiation effects. ports. During testing, the input ports were hardwired to SiGe based heterojunction bipolar transistors have gained represent four discrete voltage levels within the analog-voltage prominence for their performance in high-speed applications. output range of the MUX-DAC, starting from low to high. The SiGe technology has a fairly mature processing base with high converted analog output gives a staircase waveform covering production yields. In addition, the combination of CMOS HBT heterojunction-bipolar transistor (HBT) and CMOS processes to form BiCMOS technology produces a high level of integration [1]-[2] that is one of the great advantages of the BiCMOS process. Consequently, it is desirable to use SiGe 40 10 circuits in on-orbit applications. However, while there have DAC been several experimental [3]-[12] studies of the SEU 4:1 Mux Aout performance of circuits fabricated using SiGe HBTs, less Data information is available on the SEU performance of CMOS circuits in the BiCMOS technologies. Such information is essential for space-based applications, especially since CMOS transistors can be susceptible to SEL. In this paper, we will present the results of SEE testing on Div 4 Div 2 Clock Manuscript received Feb. 1, 2009. This work was supported in part by the U.S. NAVY (SPAWAR) under Contract # : N00039-04-C-2009 / MUOS-001 Authors are with Boeing Space and Intelligence Systems, Los Angeles, CA Fig. 1. MUX-DAC simplified block diagram. 90009 USA (telephone: 310-364-6990, e-mail: [email protected]).

the full analog range as the MUX-DAC cycles through the four output of the DAC was monitored visually on the oscilloscope data ports. This enables visual inspection of the analog output (Fig. 2). Visual inspection of the scope allows immediate for any abnormal behavior as the result of a circuit SEL. identification of a functional interrupt, and enables the The MUX-DAC contains a divide by eight sub-circuit that identification of changes in the output levels with an accuracy was tested to determine its upset rate. This ripple divider- of 10-50 mV (50Ω load) depending on the amount of noise in circuit consists of a bipolar divide-by-2 in series with a CMOS the environment. This allowed us to monitor for SEL in the divide-by-4. Thus the circuit operates at a nominal input entire MUX-DAC circuit. frequency of 3 GHz while still maintaining the power savings SEU detection was performed only in the dividers (Fig. 2). associated with CMOS designs. An HP bit error rate tester (BERT) was set to feed a 3 GHz square wave into the input of the divide-by-8 circuitry. The B. HBT Divider Description divider output was fed back to the BERT error detector (ED) The all HBT divide-by-eight circuit is functionally identical which had been set to monitor a 3 GHz 11110000 pattern. to the BiCMOS divider that is part of the MUX-DAC. With no upsets, the 50% duty-cycle divide-by-8 output was However, it incorporates two major differences. First, while identical to that generated by the BERT pattern generator (PG) the MUX-DAC incorporates a CMOS-divide-by-4 circuit, the so the BERT was able to synch to the divided output (Fig. 3). HBT divider uses only SiGe 7HP HBT transistors in the Any permanent functional disruptions would have been circuitry. Additionally, the HBT divider was designed for an recorded as a continuous synch loss by the BERT. The setup application requiring a lower upset rate. As such, it was capable of resolving transients at least 333 ps long, incorporates triple-mode redundancy (TMR) within the circuit equivalent to one period of the 3 GHz clock. In cases where and in some cases uses buffers with larger transistors to reduce upsets caused a phase shift in the output of the DUT the BERT the upset cross section. must “re-synch” to the BERT data output, and all bits to the C. Test Setup ED are counted as errors. This is recorded by the PC as an Heavy-ion tests were performed at the Cyclotron Institute event with more than 1 million errors and is easily identified in Radiation Effects Facility (IREF) at Texas A&M University. the data record as a synch-loss error. Ion beams of various energies in combination with device A laptop PC connected to the BERT by GPIB interface under test (DUT) angle, and degrader foils were chosen to recorded the number of bits corrupted every 400 ms. Each collect test data over a wide range of linear energy transfer incremental increase in the number of bits corrupted during a (LET) values. In the case of the angled data we use standard 400 ms interval was recorded as a single upset event, or cosθ scaling [13] to correct the LET. We note that that in SiGe interaction between the circuit and a single ion. The PC HBT technologies this may misrepresent the charge collected software then allowed us to analyze the number of bits [14], however it is a reasonable approximation for the CMOS corrupted during each upset event. The cross section was transistors. Each DUT was assembled in a test fixture with calculated by dividing the number of upset events (regardless provisions for bias sources and high-speed input and output of the number of bits corrupted during an event) by the signals. In the case of the MUX-DAC, decoupling capacitors fluence. Error bars were calculated by first taking the square were added to ensure a stable voltage in case of a large current root of the number of events (the Poisson statistical increase that might accompany a SEL event. The entire test uncertainty), and then dividing by the fluence. fixture was mounted on a heating block. A thermocouple is installed near the DUT to provide a feedback to the automatic BERT temperature controller. Prior to each run, the temperature was Clock Out allowed to stabilize within ±1°C and recorded in the log sheet. DUT Clock D Out to ED DAC TDS Scope Pattern Divider Generator C 0 0 1 1 1 1 0 0 0 0 PG / ED Pattern

C Analog Out Error Single Bits Measured by ED Detector D Fig. 3. Timing diagram for the detection scheme.

Fig. 2. Test Setup for the divider circuitry in the MUX-DAC. Setup for Typically, the beam flux was adjusted so that events BiCMOS divider was the same with the “analog out” portion removed occurred at a rate of about 1 Hz. The data was manually

Monitoring for SEL in the MUX-DAC divider was examined to determine the time between upsets and ensure that performed by monitoring the CMOS current for the DAC the upset rate was slow enough that multiple errors in the during irradiation, and it was recorded before and after each sample window were unlikely. Because of the limited beam test run; this allowed us to measure increases in the CMOS time available, some runs had to be performed at a higher flux current greater than 2 mA. Additionally the analog and clock so that SEL testing up to higher total fluences could be

accomplished in a shorter time period. In those few cases, the upset rate was close to the rate at which the software queried the BERT, which resulted in the measured cross-section being about 30% less than the cross-section measured at lower fluxes. These points were ignored in analyzing the cross- section of the device. Because only one output of the divider-chain differential pair was required to be fed into the BERT, the other was connected to a TDS digital oscilloscope for comparison to the pattern generated by the BERT. The oscilloscope internal subtracting function was used to detect the difference between data signal from the BERT and the divided clock signal from the DUT. Under normal circumstance, the difference was zero as the two patterns were identical. When a phase shift occurred due to upset, the result of the comparison would be a square wave whose duty cycle reflected the phase differences between Fig. 4 Test conditions for the MUX-DAC, each data point represents the LET, temperature and CMOS voltage used when the cross section was the waveforms until the BERT re-synched. This was used to measured. confirm that phase changes in the output were being captured by the BERT. TABLE I: TEST CONDITIONS FOR THE MUX-DAC

The test setup used for the bipolar divider is nearly identical Parameter Min. Max. to the setup used for testing the divide-by-8 circuit that is part LET 2.7 172 of the BiCMOS MUX-DAC. The primary difference between (MeV.cm2/mg) the two is that the bipolar divider is a “triplicate and vote” Ion, angle Ne, 0 Au, 60 TMR design. Thus in order to ensure correct operation of the TMR, the bipolar divider includes pins that when shorted to CMOS Voltage (V) 1.65 2.7 ground turn off the different legs of the TMR. Prior to testing, each of the legs was turned off individually and in pairs to Bipolar Voltage (V) 3.14 3.46 show that the TMR was functioning properly. In addition, to 33 Temperature (˚C) 125 determine the benefit of the TMR circuitry, the bipolar divider (ambient) was tested under select conditions with the TMR disabled by Fluence (ion/cm2) 1×107 turning one of the legs off during irradiation. Since the TMR is a triplicate and vote hardening scheme, when one leg is disabled, upsets in either of the other two legs corrupt data. 1.E-03 9L29MUX-DAC Divide-by-8 III. RESULTS ) 2 1.E-04 A. Results BiCMOS MUX-DAC A summary of the test conditions is given in Fig. 4 and Table I. High temperature and high voltage are worst case for Vcc = 3.3V Vdd=1.65V 1.E-05

SEL, and it is primarily a concern for CMOS transistors. No Cross-Section (cm S/N 2 evidence of SEL was seen during any test of the BiCMOS S/N 3 MUX-DAC. In Fig. 4 the parameters relevant to SEL Weibull sensitivity (LET, CMOS voltage and temperature) for each run 1.E-06 are plotted and different symbols are used to indicate which 0 50 100 150 200 Effective LET (MeV cm2 / mg) part was tested under each of the conditions. Parts were also tested under different bipolar bias conditions however this is Fig. 5 Cross section for the MUX-DAC at nominal conditions (3.3 V bipolar and 1.65 V CMOS bias.). excluded from Fig. 4 since SEL performance is expected to be independent of bipolar bias. Both DUTs were tested at the Device cross-section measured under nominal, CMOS worst-case SEL conditions with a temperature of 125˚ C, voltage (1.65 V) and bipolar voltage (3.3 V) is shown as a CMOS voltage of 2.6 V, an effective LET of 172 MeV 2 7 2 function of LET during heavy-ion irradiation in Fig. 5. All cm /mg, and with a fluence of 1×10 ions/cm . Achieving this temperatures for these bias conditions were included in Fig. 5 LET required the DUT to be at a 60˚ angle with respect to the since temperature was seen to have negligible effect on cross beam. As can be seen in Fig. 4, the test plan concentrated section. The divide-by-8 circuitry in the MUX-DAC shows testing on the nominal and worst case conditions, since no behavior typical of unhardened semiconductor devices in that latchup was seen at the worst case conditions, it was deemed the cross section increases rapidly from a low value at L0 and unnecessary to fully map the parameter space.

then levels off to the saturated cross section (σSAT) value at divider is a ripple divider, we see that most upsets involved -4 2 higher LET. Our data shows σSAT = 1.7×10 cm and a phase changes. This is as expected since upsets to the clock 2 -1 threshold LET L0 =1 MeV cm mg . We note that the low buffers or the flip-flops in the divider cause them to change state, thus changing the phase of the output signal. Previous value for L0 may reflect the sensitivity of the bipolar circuitry at low LET. This has been seen in previously published results microbeam studies of SiGe shift registers indicate that these are the most sensitive parts of the circuit [7]. Below an LET of for bipolar circuits [10]. 2 -1 75 MeV cm mg , most of the errors corrupting bits last for less than 10 ns. Above 110 MeV cm2/mg, most of the upsets 100% MUX-DAC recorded are longer than 10 ns. We also note that below an 90% Divide-by-8 LET of 17 MeV cm2/mg no upsets longer than 10 ns were 80% Vcc=3.3V recorded. The longest transient recorded was less than 83 ns. 70% The MUX-DAC was also tested at different bipolar (Vcc) 60% and CMOS (Vdd) bias conditions to look for variations in 0.32 - 2.9 ns 50% sensitivity [15]. In comparing the cross section for the MUX- 2.9 - 10 ns Percent 40% >10 ns DAC in the saturated cross section portion of the LET 30% Phase Shifts spectrum with the different bias conditions (Figs. 7-8) we see

20% that within the calculated error bars. The cross section is unchanged regardless of the bipolar and CMOS biases. 10% 0% B. Results Bipolar Divider 0 50 100 150 200 The bipolar divider was tested at nominal bias (Vcc = 3.3V) Effective LET (MeV cm2/mg) and at reduced bias (Vcc = 3.17). The results for testing at Fig. 6 Percentage of upsets as a function of effective LET for transient both bias conditions are shown in Fig. 9. The data indicates errors. All runs at an identical LET were averaged in this figure. that there is no measurable difference between the cross 4.0E-04 sections for the two bias conditions. Therefore both sets of 9L29MUX-DAC 3.5E-04 data were used for the Weibull fit. We measure a saturated Vcc = 3.14V; Vdd = 2.6V -6 2 2 -1 Vcc = 3.14V; Vdd = 1.9V cross section of 3.9×10 cm and a L0 of 2.8 MeV cm mg ) 3.0E-04 2 Vcc = 3.14V; Vdd = 1.65V from the Weibull fit. Again the low value for L0 is consistent 2.5E-04 Vcc = 3.3V; Vdd = 1.65 V with the results previously seen for this technology [10]. Fig. 2.0E-04 10 shows the durations of the upsets recorded during

1.5E-04 irradiation. Most importantly, we note that unlike the MUX- DAC, no phase shifts were recorded during irradiation under Cross-Section (cm Cross-Section 1.0E-04 both bias conditions with a 0 dBm input signal. The longest 5.0E-05 transient recorded was less than 5 ns, and the majority of the 0.0E+00 upsets were less than 1 ns. Unlike the unhardened divider, no 40 60 80 100 120 140 160 180 phase shifts were recorded, showing the TMR to be effective. Effective LET (MeV cm2 / mg) 1E-05 Fig. 7. Effect of bipolar bias on cross section for the MUX-DAC. Data is Bipolar Divide -by- 8 plotted as a function of Effective LET and represents the portion of the curve 0 dBm Input where the cross section has saturated.

) 1E-06 2 4.E-04 9L29MUX-DAC 3.E-04 Vcc= 3.3 V; Vdd = 1.65 V Vcc = 3.3V; Vdd = 2.6V 1E-07 ) 2 3.E-04 Vcc = 3.3V; Vdd = 1.9V

2.E-04 Vcc = 3.3 V Cross- Section(cm 1E-08 2.E-04 Vcc = 3.17 V

Cross-Section (cm 1.E-04 Weibull Fit 1E-09 5.E-05 020406080 0.E+00 Effective LET(MeV cm 2/mg) 50 60 70 80 90 100 110 Fig. 9. Cross section for the bipolar divider at nominal input power with Effective LET (MeV cm2 / mg) nominal and reduced bipolar bias. The solid line represents a Weibull fit to Fig. 8. CMOS bias effect on cross section for the MUX-DAC the data. Under nominal conditions, the bipolar divider operates Fig. 6 shows the upset characteristics for the MUX-DAC with a 3 GHz clock at 0 dBm. Testing the bipolar divider with divider in terms of the proportion of upsets involving -10 dBm input power (Fig. 11) the data indicate that the device corrupted bits and phase shifts. Because the MUX-DAC has a similar sensitivity at low LET and a slightly higher σSAT,

with the values of σSAT measured under both conditions being The bipolar divider was also tested with the TMR circuitry identical within the error bars of the measurement. However at disabled. These tests provide a means to check the higher values of LET (≥ 29.5 MeV cm2 mg-1) upsets are no improvement in cross section gained by the TMR scheme. The longer limited to corrupted bits (Fig. 12), and phase shifts are results are shown in Fig. 13. The data collected during recorded. irradiation under nominal operating conditions as well as with TMR disabled both show similar, low values for L0. However 1 Bipolar Divider with the TMR circuitry disabled, the value for σSAT is an order Nominal Conditions of magnitude higher thus showing the effectiveness of the 3.3 V, 0dBm Input 0.75 0.32 - 1.6 ns TMR implementation. With the TMR enabled, only the voter 1.6 - 2.9 ns and the output buffers are vulnerable to upset. These are 2.9 - 5.2 ns typically less sensitive to SEU upset than the flip-flops and 0.5 > 5.2 ns clock buffers in the circuit [7]. This improvement is smaller Fraction Phase Shift than that seen in previous testing of a 16-bit shift register with 0.25 TMR [4]. We note that the divide-by-8 circuit is implemented with only 3 flip-flops instead of 16 and less associated circuitry for the clocks and voters is present in the divider than 0 0 20 40 60 80 100 120 the shift register. Thus the smaller improvement is expected. Effective LET (MeV cm2/mg) 1E-03 Bipolar Divide-by-8 3.3 V Bias Fig. 10. Transient duration for the bipolar divider during irradiation with 1E-04 nominal bias conditions. No phase shifts were recorded during irradiation ) with 0 dBm input power. 2 1E-05 1E-05 1E-06 Bipolar9L30 Divide-by-8 3.3 V Bias 1E-07 TMR Operating Cross- Section(cm

) 1E-06 Weibull Fit 2

cm Weibull Fit ( 1E-08 TMR Disabled

1E-07 1E-09 020406080 2

Cross- Section Effective LET(MeV cm /mg) 0 dBm Input 1E-08 Fig. 13. Cross section for phase shifts in the bipolar divide-by-8 circuit -10 dBm Input Bias with the TMR disabled and during normal operation. The lines represent a Weibull fit to the data. Weibull Fit

1E-09 1 0 1020304050607080 Bipolar Divide-by-8 Effective LET(MeV cm2/mg) TMR Disabled Fig. 11. Cross section for the bipolar at low input power with nominal 0.75 bipolar bias and the cross section under nominal conditions. The lines 0.32 - 1.6 ns represent a Weibull fit to the data. 2.9 - 5.2 ns 0.5 2.9 - 5.2 ns

Fraction > 5.2 ns 1 Phase Shift 9L30 0.25 -10dBm Input Vcc = 3.3 V 0.75 0.32 - 1.6 ns 0 1.6 - 2.9 ns 0 102030405060 2.9 - 5.2 ns 0.5 Effective LET (MeV cm2/mg) > 5.2 ns Fraction Phase Shift Fig. 14. Upset characteristics for the bipolar divider-by-8 circuit with the 0.25 TMR disabled.

Fig. 14 shows the proportion for the different duration 0 upsets observed with the TMR disabled. The data shows 0 102030405060 similar trends to those seen during testing of the MUX-DAC Effective LET (MeV cm2/mg) divider (Fig. 6). At all values of LET, most upsets result in Fig. 12. Transient duration for the bipolar divider during irradiation with - phase shifts. Again the explanation is the same as in the case of 10 dBm input power. Phase shifts were recorded at higher LETs under these conditions. the MUX-DAC divider: the upsets in the flip-flops and clock buffers result in phase-shift upsets. At higher LET values, SET

in the less sensitive circuitry such as the output buffers become heterojunction bipolar transistors and circuits," IEEE Trans. Nucl. Sci. more an appreciable fraction of the upsets measured. In vol. 50, p. 2184-2190, 2003. [9] D.L. Hansen, P. Chu, K. Jobe, A.L. Mc Kay, H.P. Warren, “SEU Cross contrast when the TMR is enabled, the flip-flops and clock Sections of Hardened and Unhardened SiGe Circuits,” IEEE Trans. circuitry is protected and the phase shift cross section becomes Nucl. Sci. vol. 53f, no. 6, p. 3579 – 3585, Dec. 2006. negligible (Fig. 11). [10] P. Marshall, M. Carts, A. Campbell, R. Ladbury, R. Reed, C. Marshall, S. Currie, D. McMorrow, S. Buchner, C. Seidleck, P. Riggs, K. Fritz, B. Randall, and B. Gilbert, “A comparative study of heavy ion and proton IV. CONCLUSION induced bit error sensitivity and complex burst error modes in commercially available high speed SiGe BiCMOS,” IEEE Trans. Nucl. Two circuits designed by Boeing Space and Intelligence Sci., vol. 51, p. 3457-3463, 2004. Systems, El Segundo were tested to determine their SEU [11] G. Niu, J. D. Cressler, M. Shoga, K. Jobe, P. Chu, D. L. Harame, sensitivity. The divider circuitry in a SiGe 7HP BiCMOS “Simulation of SEE-induced charge collection in UHV/CVD SiGe MUX-DAC showed no evidence for SEL even during testing HBTs,” IEEE Trans. Nucl. Sci. vol. 47, p. 2682, 2000. [12] G. Niu, R Krithivasan, J. D. Cressler, P. Marshall, C. Marshall, R. Reed, at worst case: high LET, high bias and high temperature D. L. Harame, “Modeling of single-event effects in circuit-hardened conditions. This is significant since SEL can be a concern for high-speed SiGe HBT logic,” IEEE Trans. Nucl. Sci. vol. 48, p. 1849- CMOS circuitry. The cross section showed no dependence on 1854, 2001. bias during testing at biases representing the operational range [13] E.J. Montes, R.A. Reed, J.A. Pellish, M.L. Alles, R.D. Schrimpf, R.A. Weller, M. Varadharajaperumal, G. Niu, A.K. Sutton, R. Diestelhorst, of the device. Testing of a TMR hardened bipolar divide-by-8 G. Espinel, R. Krithivasan, J.P. Comeau, J.D. Cressler, P.W. Marshall, circuit showed that the implementation of the TMR circuitry G Vizkelethy, “Single Event Upset Mechanisms for Low-Energy- improved the cross section by about an order of magnitude, Deposition Events in SiGe HBTs” IEEE Trans. Nucl. Sci. vol. 55, p. and was effective in preventing phase shifts. 1581 – 1586, June 2008 [14] D. L. Oberg, J. L. Wert, E. Normand, J. D. Ness, P. P. Majewski, R. A. Kennerud, “Measurement Of Single Event Effects In The 87c51 V. ACKNOWLEDGMENT Microcontroller,” IEEE Radiation Effects Data Workshop, 1993., p.43 – The authors would like to thank P. Marshall, A. Bogorad, 50, July 1993. [15] D.R. Roth et al, “Monitoring SEU parameters at reduced bias,” IEEE M. Bustamante, J. Heide, A. McKay, B. Paine, L. Rubio, A. Trans. Nucl. Sci., vol. 40, 1993, p. 1721-1724. Sweeney, M. Weaver, and the staffs at IBM and Texas A&M IREF for their involvement in making this research possible.

VI. REFERENCES [1] J. M. Roldán, W. E. Ansley, J. D. Cressler, S. D. Clark, D. Nguyen- Ngoc, “Neutron radiation tolerance of advanced UHV/CVD SiGe HBT BiCMOS technology,” IEEE Trans. Nucl. Sci. vol44, p. 1965-1973, 1997. [2] D. L. Harame, D.C. Ahlgren, D. D. Coolbaugh, J. S. Dunn, G. G. Freeman, J. D. Gillis, R. A. Groves, G. N. Hendersen, R. A. Johnson, A. J. Joseph, S. Subbanna, A. M. Victor, K.M. Watson, C. S. Webster, P. J. Zampardi, “Current Status and Future Trends of SiGe BiCMOS Technology,” IEEE Trans. Elec. Dev., vol. 48,p. 2575-2594, Nov. 2001 [3] P. W. Marshall, M. A. Carts, A. Campbell, D. McMorrow, S. Buchner, R. Stewart, R. Randall, B. Gilbert, R. A. Reed, “Single event effects in circuit-hardened SiGe HBT logic at gigabit per second data rates,” IEEE Trans. Nucl. Sci. vol. 47, p. 2669-2674, 2000. [4] R. Krithivasan, P.W. Marshall, M. Nayeem, A.K. Sutton, W. Kuo, , B.M. Haugerud,L. Najafizadeh, J. D. Cressler, M.A. Carts, C J. Marshall, D L. Hansen, K. M. Jobe, A.L. McKay, G. Niu, R. Reed, B. A. Randall, C. A. Burfield, M.Daun-Lindberg, B. Gilbert, E. Daniel, ”Application of RHBD Techniques to SEU Hardening of Third- Generation SiGe HBT Logic Circuits,” IEEE Trans. Nucl. Sci, vol. 53, no. 6, p. 3400-3407, Dec. 2006. [5] R. A. Reed, P. W. Marshall, H. Ainspan, C. J. Marshall, H. S. Kim, J. D. Cressler, G. Niu, K. A. LaBel, “Single event upset test results on a prescalar fabricated in IBM’s 5HP silicon germanium heterojunction bipolar transistors BiCMOS technology,” 2001 IEEE Rad Effects Data Workshop, p. 172, 2001. [6] D. L. Hansen, P. W. Marshall, K. Jobe, M. A. Carts, C. J. Marshall, Peter Chu, S. F. Meyers, “A Study of the SEU Performance of InP and SiGe Circuits,” IEEE Trans. Nucl. Sci. vol. 52, p. 1140-1147, 2005.. [7] P. Chu, D.L. Hansen, B.L. Doyle, K. Jobe, R. Lopez-Aguado, M. Shoga, D.S. Walsh, “Ion-Microbeam Probe of High-Speed Shift Registers for SEE Analysis; Part 1: SiGe,” IEEE Trans. Nucl. Sci. vol. 53, p. 1574- 1582, 2006. [8] R. Reed, K. LaBel, P. Marshall, J. Pickel, M. Carts, G. Niu, K. Fritz, P. Riggs, J. Prarie, B. Randall, B. Gilbert, G. Vizkelethy, P. Dodd, T. Irwin, J. Cressler, R. Krithivasan, "Broad-beam and ion microprobe studies of single-event upsets in high speed 0.20 μm Silicon-germanium

Single Event Transient and ELDRS Characterization Test Results for LM4050QML 2.5V Precision Reference

Kirby Kruckmeyer, Member, IEEE, Elisa Morozumi, Member, IEEE, Robert Eddy, Thang Trinh, Tom Santiago and Pierre Maillard, Student Member, IEEE

functions of the products are significantly different which may Abstract—National Semiconductor’s 100 krad(Si) low dose result in significantly different radiation responses. SET test rate qualified, 2.5V precision reference, LM4050WG2.5RLQV, results under different operating conditions and TID test was put through heavy ion testing and an enhanced low dose rate results at both high dose rate (HDR) and low dose rate (LDR) sensitivity (ELDRS) characterization. The results are presented here. for the LM4050WG2.5RLQV will be presented here.

I. INTRODUCTION ATIONAL Semiconductor’s LM4050WG2.5RLQV (DSCC 2.5 V NSMD 5962R0923561VZA) is a precision shunt voltage reference with a 2.5 V fixed reverse breakdown voltage (Fig. 1) [1]. It has an accuracy of 0.1% at 25ºC and an operating temperature range of -55ºC to +125ºC. It has an operating Fig. 1. LM4050WG2.5RLQV application diagram. current range of 60 µA to 15mA, which is set by the resistor Rs in Fig. 1. A functional block diagram of the part is shown in Fig. 2. The LM4050WG2.5RLQV is manufactured using National Semiconductor’s LFAST process, which is a standard, junction isolated bipolar structure on a lightly doped substrate. Many bipolar references have been shown to degrade when exposed to ionizing radiation. Many bipolar products experience Enhanced Low Dose Rate Sensitivity (ELDRS), where the product performance degrades more when exposed at a low dose rate (LDR), similar to the dose rates seen in a space application, than when exposed at a high dose (HDR), Fig. 2. LM4050WG2.5RLQV block diagram. for the same total ionizing dose (TID) [2]-[5]. In addition, a reference can experience a single event transient (SET) where II. TEST METHOD the output is disturbed by a single ion strike from a cosmic A. ELDRS Characterization ray. It has been shown that the SET performance of a bipolar product can be highly dependent upon the operating TID testing was done using the ELDRS characterization in conditions of the product [6]. MIL-STD-883, Test Method 1019.7 section 3.13.1.1 as a The LFAST process is also used for National guide [9]. A four way split was run with units biased and Semiconductor’s DS16F95QML RS-485 transceiver [7], unbiased during irradiation at low dose rate (LDR) and high which will have single event transient (SET) and total ionizing dose rate (HDR). HDR irradiation was run at 152 rad(Si)/s at dose (TID) data presented at the NSREC 2010 Data Workshop National Semiconductor’s radiation facility in Santa Clara, [8]. Although the products share the same process, the California. The LDR irradiation was done at 10 mrad(Si)/s at Radiation Assured Devices (RAD) in Colorado Springs, Colorado. The unbiased units had all pins grounded during Manuscript received July 14, 2010. irradiation. For the biased units, the negative pin was Kirby Kruckmeyer is with National Semiconductor, 2900 Semiconductor connected to ground and the positive pin (V ) was connected Drive, Santa Clara, California 95052-8090, phone: (408) 721-3548, email: S [email protected] to 15 V though an 866 Ω resistor for a supply current of 15 Elisa Morozumi, Robert Eddy, Thang Trinh and Tom Santiago are with mA. National Semiconductor, Santa Clara, CA 95052 Electrical testing was done with an Eagle ETS500 test Pierre Maillard is with Vanderbilt University, Nashville, TN 37235

system at National Semiconductor’s Santa Clara radiation DUTs. RF was shorted and RL was open for all testing and the facility. All datasheet parameters were tested. For the HDR CF value and ion linear energy transfer (LET) were the only legs testing was done at 0, 3, 10, 30, 50, 80, 100 and 150 variables. At TAMU, the operating current for DUT 1 was set krad(Si) levels. The LDR legs were pulled at close to the at 14.3 mA and for DUT 2 at 0.89 mA. All testing was done 2 same levels, but not always exactly at those levels. For the with the Au ion for an LET of 87.1 MeV-cm /mg. HDR legs, electrical testing was completed within an hour of Each DUT was decapped to expose it to the ion beam. For being removed from the gamma radiation. The LDR legs the flatpack package, the lid seal is on the same plane as the were shipped overnight from the test facility at RAD to bottom of the die, making decapping a challenge. It took National for testing, and shipped back overnight to RAD to several attempts to remove the lid without damaging the leadframe or bond wires. For DUT 1 tested at LBNL, the resume irradiation. Testing time limits were in accordance leadframe was damaged during decapping (Fig. 4). The “no with MIL-STD-883G, TM1019.7. connect” leads (Fig. 2) were broken off. The two active leads B. SET Testing were epoxied to hold them in place. Due to the limited SET testing was done under several different biasing number of samples available at test time, this damaged part conditions and at two different heavy ion facilities. The first was used in the testing. round of testing was conducted at Lawrence Berkeley National Laboratory (LBNL) using the 10 MeeV/nucleon beam with a minimum ion penetration of 90 µm [10]. The second round of testing was conducted at the at the RRadiation Effects Facility at the Texas A & M University Cyclotron Institute (TAMU), using the 15 A MeV beam withh a minimum ion penetration of 106 µm [11]. At LBNL, heavy ion exposure is done inside a vacuum chamber. All testing was performed with the beam at a 0º incident angle. Test boards were designed to accommodate two devices under test (DUT 1 and DUT 2 in Fig. 3) and several different operating conditions. For a clean input, each DUT was supplied by an LM4050WG5.0RLQV 5 V reference. The 5 V output of the LM4050WG5.0RLQV was connected to the input of the DUT through a resistor to set the operating current. The 5V references were powered by an external 7.5 V supply through a 100 Ω resistor and using an RC network to reduce the input noise. The output of DUT could be connected to different filters consisting of a filter resistor (RF) and capacitor (CF) by switching jumpers on the board (see Fig. 4). All capacitors are tantalum unless otherwise noted. The output load (RL) was controlled by an external decade resistor box. The output was monitored by connecting it directly to a Tekttronix DPO 7354 oscilloscope. The scope termination was 1 MΩ, so that if RL was open, the load current would be 2.5 µA and most of the operating current would be dissipated through the DUT. At LBNL, the scope capture window was set to 8 µs with the Fig. 3. SET test board. This configuration was used for the testing at trigger set at 0.8 µs. The maximum length of a transient LBNL. At TAMU, the board was modified so that DUT 1 operating current was 14.3 mA and DUT 2 was 0.89 mA. The capacitor values were changed, recorded was 7.2 µs and if a transient was longer than that, the and an optional resistor was added between the DUT and the capacitors. total length of the transient is unknown. 500 data points were collected at each scope capture, for a time ressolution of 16 ns. The DUT output was relatively noisy due to feeding the signals through a vacuum chamber wall. The scope trigger limits were set at 2.35 to 2.75 V. At TAMU, the scope capture window was increased to 20 µs, with the trigger set at 2 µs for a maximum transient capture of 18 µs. 1000 data points were collected at each scope capture, keeping the resolution at 16 ns. A cleaner output was achieved at TAMU and the scope trigger limits were tightened to 2.44 to 2.60 V. To be consistent, data analysis on the TAMU data was done with limits widen to 2.35 to 2.75 V. For testing at LBNL, the board set up waas as depicted in Fig. 3. The operating current was set at 12.0 mA for both Fig. 4. Schematic of the filter and load options.

qualified to 100 krad(Si), it must pass qualification testing to 150 krad(Si) at a dose rate of 10 mrad(Si)/s with all parameters inside the post irradiation test limits. The post irradiation drift limit for reference voltage is 1.5%. Fig. 5 shows a plot of the median parametric drift, along with the post irradiation limit for the reference voltage with a 15 mA load. The maximum, average, minimum and the standard deviations of the drift are shown in Table II.

1.6%

Fig. 4. DUT 1 (bottom part) was damaged during decapping but was used 1.4% for the testing due to the lack of available units at the time of the testing. 1.2% LDR Biased LDR Unbiased III. ELDRS CHARACTERIZATION RESULTS 1.0% HDR Biased The parametric drift between 0 rad and 100 krad(Si) was HDR Unbiased analyzed for each of the test splits. The LM4050WG2.5RLQV 0.8% 100 krad(Si) Spec Limit is a simple shunt reference and there are only 2 parametric 0.6% tests: minimum operating current and reference voltage at 0.4% various current loads (Table I). The minimum operation DriftReference (%) Voltage current, which has a specification limit of 60 µA did not show any significant drift through irradiation. For TID 0.2% qualification, the reference voltage is expressed in terms of 0.0% percentage drift from the 0 rad reading. Measureable drift was 0 20406080100120140160 detected on this parameter through irradiation (Table I and Radiation (krad(Si)) Fig. 5). As the load current increased there was a slight amount of increase in the parametric drift, with the 15 mA Fig. 5. Reference voltage parametric drift with the load current at 15 mA, load current being the worst case. The worst case irradiation which was the worst case showing the most amount of parametric drift. condition resulting in the most parametric drift was at LDR with the units biased during irradiation. The condition with TABLE II the least amount of drift was HDR biased. REFERENCE VOLTAGE DRIFT AT LDR WITH LOAD CURRENT AT 15 MA. Per the ELDRS characterization method in MIL-STD- UNITS ARE % DRIFT FROM 0 RAD READING 883G, TM1019.7, section 3.13.1.1, the median parametric TID Level krad(Si) 30.6 52.3 102 151.7 drift for each test condition was compared (Table I). If any Biased parameters show significant drift and the ratio of the median Maximum 0.167 0.316 0.712 1.138 LDR drift to the median HDR drift is greater than 1.5, the Average 0.149 0.288 0.656 1.060 “part is considered to be ELDRS susceptible”. With the units Minimum 0.129 0.252 0.577 0.945 biased during irradiation, the reference voltage LDR/HDR Standard Deviation 0.00018 0.00030 0.00061 0.00087 drift ratio was 1.8, indicating that the LM4050WG2.5RLQV has ELDRS under the definition in MIL-STD-883. Unbiased To qualify a part defined as having ELDRS for low dose Maximum 0.150 0.286 0.654 1.082 rate environments, MIL-STD-883 TM1019 requires that the Average 0.144 0.270 0.615 1.022 part is tested at a dose rate of 10 mrad(Si)/s and an overtest Minimum 0.137 0.257 0.589 0.975 factor of 1.5X is used. For the LM4050WG2.5RLQV to be Standard Deviation 0.00006 0.00012 0.00025 0.00041

TABLE I ELDRS CHARACTERIZATION TABLE LISTING THE MEDIAN PARAMETRIC DRIFT

Median Drift LDR/HDR Parameter Conditions LDR HDR Drift Ratio Units Bias Unbias Bias Unbias Bias Unbias Minium Operating Current µA -0.802 -0.989 -0.709 -0.758 1.13 1.31

Reference Voltage IL=60 µA % drift 0.671 0.591 0.366 0.436 1.83 1.36

Reference Voltage IL=100 µA % drift 0.672 0.592 0.367 0.437 1.83 1.35

Reference Voltage IL=1 mA % drift 0.672 0.592 0.368 0.441 1.83 1.34

Reference Voltage IL=10 mA % drift 0.675 0.601 0.373 0.448 1.81 1.34

Reference Voltage IL=15 mA % drift 0.678 0.605 0.375 0.453 1.81 1.33

IEEE RADIATION EFFECTS DATA WORKSHOP 1992–2008 CUMULATIVE INDEX

1992 Workshop Record 1993 Workshop Record

Editor: H. Eisen Editor: M. DeLaus IEEE Catalog Number 92TH0507-4 IEEE Catalog Number 93TH0657-7 ISBN 0-7803-0930-8 ISBN 0-7803-1906-0

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Rate Response of Low Dropout Voltage Regulators,” pp.85- [27] M.W. Savage, J.E. Seiler, G.W. Dunham, D. Platterer, 93 (2006). “Analog Transients In The National VIP-10 and VIP-50 [15] M. Hartwell, K. Ryan, S. Netherton, P. Milliken, D. Process,” pp.160-164 (2006). Kerwin, “Total Ionizing Dose Testing of a RadHard-by- Design FET Driver in a 0.35µm Triple Well Process,” pp.94- [28] S. Liu, M. Boden, H. Cao, E. Sanchez, J. Titus, 100 (2006). “Evaluation of Worst-Case Test Conditions for SEE on Power DMOSFETs,” pp.165-171 (2006). [16] J.J. Wang, G. Kuganesan, N. Charest, and B. Cronquist, “Biased-Irradiation Characteristics of the Floating Gate [29] R. Edwards, J. Woodhouse, “Determination of High Switch in FPGA,” pp.101-104 (2006). Energy Neutron Voltage Stress Margins for High Voltage IGBT and Diode Pairs from Two Manufacturers using [17] D.M. Hiemstra, F. Chayab, Z. Mohammed, “Single Energetic Particle Induced Charge Spectroscopy, EPICS,” Event Upset Characterization of the Virtex-4 Field pp.172-176 (2006). Programmable Gate Array Using Proton Irradiation,” pp.105- 108 (2006). [30] E.W. Cascio, “The Use of the Compensated Contoured Double Scatterer in the Radiation Test Beamline at the [18] J. George, R. Koga, G. Swift, G. Allen, C. Carmichael, Francis H. Burr Proton Therapy Center,” pp.177-182 (2006). C.W. Tseng, “Single Event Upsets in Xilinx Virtex-4 FPGA Devices,” pp.109-114 (2006). [31] M.B. Johnson, M.A. McMahan, T.L. Gimpel, W.S.

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[19] D. Chen, J. D. Forney, A. M. Phan, M. A. Carts, [24] D. Chen, A. Phan, H. Kim, MEI/NASA-GSFC ; J. MEI/NASA-GSFC; Ronald L. Pease, RLP Research; S. R. Pellish, K. LaBel , NASA-GSFC ; S. Burns, R. Albarian, Cox, K. LaBel , NASA-GSFC; K. Kruckmeyer, National Linear Technology; B. Holcombe, B. Little, J. Salzman, Semiconductor; S. Burns, R. Albarian, Linear Technology; B. Texas Instruments; P. Marshall, Consultant, “Radiation Holcombe, B. Little, J. Salzman, Texas Instruments; G. Performance of Commercial SiGe HBT BiCMOS High Chaumont, H. Duperray, A. Ouellet, ST Microelectronics, Speed Operational Amplifiers,” pp. 142-146 (2010). “The Effects of ELDRS at Ultra-Low Dose Rates,” pp. 111- 116 (2010). [25] A. R. Jones, D. O'Connor, E. Thiemann, V. A. Drake, G. Newcomb, N. White, S. Dooley, S. Finkelstein, P. [20] D. J. Cochran, D. Chen, H. S. Kim, M. J. Campola, M. Haskins, V. Wei Hsu, B. Kirby, T. Reese and P. Soto V. O'Bryan, MEI Technologies, Inc.; T. R. Oldham, Dell Hoffmann, University of Colorado; Dean D. Aalami, Space Perot Systems ; A. B. Sanders, K. A. LaBel, C. J. Marshall, J. Instruments; Henry L. Clark, Texas A&M University; A. Pellish, M. A. Carts, NASA/GSFC ; S. P. Buchner, Global Raymond L. Ladbury, NASA; Barbara von Przewoski, Defense Technology and Systems, Inc., “Total Ionizing Dose Indiana University, “Radiation Testing a Very Low-Noise and Displacement Damage Compendium of Candidate RHBD ASIC Electrometer,” pp. 147-152 (2010). Spacecraft Electronics for NASA,” pp. 117-124 (2010). [26] R. Fuller, W. Morris, D. Gifford, R. Lowther, J. Gwin, [21] D. N. Nguyen, F. Irom, NASA/CalTech/Jet Propulsion Silicon Space Technology; J. Salzman, Texas Instruments; Lab, “Comparison of TID Response of Micron Technology D. Alexander, K. Hunt, AFRL, “Hardening of Texas Single-Level Cell High Density NAND Flash Memories,” pp. Instruments' VC33 DSP,” pp. 153-157 (2010). 125-128 (2010). [27] D. L. Hansen, A. Le, K. Chesnut, E. Miller, S. Pong, S. [22] K. E. Holbert, Arizona State University ; A. Sharif Sung, J. Truong, Boeing, “SEU Testing of SiGe Bipolar and Heger, S. S. McCready, Los Alamos National Laboratory, BiCMOS Circuits,” pp. 158-163 (2010). “Performance of Commercial Off-the-Shelf Microelectromechanical Systems Sensors in a Pulsed Reactor [28] K. Kruckmeyer, E. Morozumi, R. Eddy, T. Trinh, T. Environment,” pp. 129-136 (2010). Santiago, National Semiconductor; P. Maillard, Vanderbilt University, “Single Event Transient and ELDRS [23] R. Dumitru, C. Hafer, T.-W. Wu, R. Rominger, H. Characterization Test Results for LM4050QML 2.5V Gardner, P. Milliken, K. Bruno, T. Farris, Aeroflex Colorado Precision Reference,” pp. 164-169 (2010). Springs, “Radiation Hardness Characterization of a 130nm ASIC Library Technology,” pp. 137-141 (2010).

Author Index

A Gifford, D...... 153 Gill, J. S...... 80

Gill, P...... 13 Aalami, D. D...... 147 Guertin, S. M...... 5 Adell, P. C...... 44 Gwin, J...... 153 Albarian, R. S...... 32, 111, 142

Alexander, D...... 153 Allen, G. R...... 44, 71 H

B Hafer, C...... 28, 58, 137 Hansen, D. L...... 158

Harris, R. D...... 104 Baranski, B...... 28 Haskins, P...... 147 Battiston, G...... 13 Heger, A. S...... 129 Berg, M. D...... 32 Heidecker, J...... 71 Bernard, T. M...... 32, 88 Hiemstra, D. M...... 1, 13 Bielat, S...... 17 Holbert, K. E...... 129 Brown, B...... 63 Holcombe, B...... 111, 142 Brown, R. D...... 94 Hood, R...... 88 Bruno, K...... 137 Hunt, K...... 153 Buchner, S. P...... 32, 117

Burns, S...... 32, 111, 142 I C Irom, F...... 5, 32, 44, 125

Campola, M. J...... 117 Carts, M. A...... 32, 111, 117 J Chaumont, G...... 75, 111 Chen, D...... 32, 111, 117, 142 Jones, A. R...... 147 Chesley, P. J...... 80, 88 Jordan, A...... 28, 58 Chesnut, K...... 158 Clark, H. L...... 147 K Clark, K. B...... 104 Cochran, D. J...... 117 Kelly, A. T...... 94 Cox, S. R...... 111 Kenna, A. J...... 104 Kim, H. S...... 32, 117, 142 D Kirby, B...... 147 Koga, R...... 17 Daniel, C...... 100 Kruckmeyer, K...... 63, 111, 164 Dominik, L...... 50 Dooley, S...... 147 L Drake, V. A...... 147 Dumitru, R...... 137 LaBel, K...... 32, 111, 117, 142 Duperray, H...... 111 Ladbury, R. L...... 32, 147 Larsen, J...... 28 E Lauenstein, J.-M...... 32 Lawrence, R. K...... 23 Eddy, R...... 63, 164 Le, A...... 158 Leslie, M...... 58 F Little, B...... 111, 142 Lowther, R...... 153

Farris, T...... 137 Finkelstein, S...... 147 M Fleming, P. R...... 94 Fobes, T. E...... 80 Maillard, P...... 164 Forney, J. D...... 111 Malou, F...... 75 Fuller, R...... 153 Marshall, C. J...... 32, 117 Marshall, P. W...... 32, 142 G McClure, S. S...... 44, 104 McCready, S. S...... 129

Miller, E...... 158 Gardner, H...... 137 Milliken, P...... 137 George, J...... 17 Miyahira, T. F...... 44 Soto Hoffmann, P...... 147 Morozumi, E...... 164 Sung, S...... 158 Morris, W...... 153 Szczapa, A...... 63

N T

Newcomb, G...... 147 Thiemann, E...... 147 Nguyen, D. N...... 125 Thomson, E. J...... 88 Normand, E...... 50 Thomson, E. T...... 32, 80 Thornbourn, D. O...... 104 O Trinh, T...... 164 Truong, J...... 158 O'Bryan, M. V...... 32, 117 O'Connor, D...... 147 U Oldham, T. R...... 32, 117 Ouellet, A...... 111 Uguen, A...... 75

P V

Pearce, L. G...... 32, 80, 88 van Vonno, N. W...... 32, 80, 88 Pease, R. L...... 111 von Przewoski, B...... 147 Pellish, J. A...... 32, 117, 142 Von Thun, M...... 58 Phan, A. M...... 32, 111, 142 Pong, S...... 158 W Prugne, C...... 75 Wei Hsu, V...... 147 R White, J. D...... 88 White, N...... 147 Rakers, S...... 100 Williams, A. P...... 32, 80 Rax, B. G...... 104 Wong, F...... 94 Reese, T...... 147 Wood, G. M...... 88 Rominger, R...... 137 Wood, N. E...... 23 Ross, J. F...... 23 Wu, T.-W...... 137

S X

Salzman, J...... 32, 111, 142, 153 Xapsos, M. A...... 32 Sanders, A. B...... 32, 117 Santiago, T...... 63, 164 Y Satterfield, H. W...... 32, 80 Scheick, L. Z...... 44 Yan, T.-Y...... 104 Schüttauf, A...... 100 Yu, P...... 17 Sheldon, D...... 71 Sievert, F...... 28, 58

IV. SET TEST RESULTS Both positive-going and negative-going SETs were The maximum SET amplitude and duration and the SET detected. For larger amplitude transients, the recovery could cross section were dependent upon operating conditions. The take several microseconds and overshoot the nominal output TAMU data are summarized in Table III. The cross section is up to two times before settling (Figs. 6 and 7). No oscillation a relative indication of the probability of an SET. It is or ringing was seen. calculated by dividing the number of SETs by the fluence from the ion runs at a specific LET. With no load on the 5 output, a higher operating current resulted in as slight shift upward on the SET amplitude (Fig. 8). The maximum duration of the negative transients was 9.8 µs at the high 4 operating current but was greater than 18 µs at the lower operating current (the actual maximum duration is unknown as the scope could only capture 18 µs). 3 3 Operating Current = 0.89 mA 2 Operating Current = 14.3 mA 2 Reference Voltage (V) Reference Voltage

1 1

0 0 -1012345678 Time (µs) (V) Amplitude -1 Fig. 6. Example of a negative-going SET. 5 -2

4 -3 0 5 10 15 20 Time (µs) 3 Fig. 8. SET amplitude vs. pulse width with a 2.5 µA load current. Data are from TAMU with an LET of 87.1 MeV-cm2/mg.

2 Increasing the load current had a significant impact on

Reference Voltage (V) Reference Voltage reducing the SET amplitude. With the operating current at 1 14.3 mA and the load current at 10 mA, the maximum SET amplitude was 0.5V, while it was 2.6 V when the load was just the 2.5 µA from the scope termination (Fig. 9 and Table III). 0 The output filters may attenuate the SETs, depending upon -1012345678the size of the filter capacitor. The output filters using a Time (µs) capacitor value of 220 pF or lower had little impact at high

Fig. 7. Example of a positive-going SET. operating currents (Table III), but had a minor impact at the lower operating current (Table III and Fig. 10). These data are

TABLE III SET RESULTS FROM TAMU, LET=87.1 MEV-CM2/MG

Operating Conditions SET Results Operating Load Filter Filter Max Min Max Cross Current Current Resistor Capacitor Amplitude Amplitude Duration Section (mA) (mA) (Ω)(pF)(V)(V)(µs)(cm2) 14.3 0 None None 2.62 -1.69 9.8 1.27E-03 14.3 10 None None 0.49 -1.80 14.3 8.35E-04 14.3 0 50 80 2.54 -1.52 9.5 1.33E-03 14.3 0 50 220 2.65 -1.50 9.8 1.48E-03 14.3 0 100 220 2.62 -1.49 9.9 1.49E-03 14.3 10 100 220 0.52 -1.55 13.6 9.12E-04 0.89 0 None None 1.94 -2.31 18+ 1.29E-03 0.89 0 50 220 1.29 -1.68 18+ 8.80E-04 0.89 0 100 200 1.36 -1.77 18+ 9.74E-04

from TAMU testing, using the gold ion beam with an LET of testing at TAMU with an operating current of 14.3 mA. Some 87.1 MeV-cm2/mg. A 30 µF capacitor had a significant of the increase in the amplitude may also be due to the impact attenuating the SETs and no SETs were detected when increased operating current. The maximum duration of the a 60 uF capacitor was used (Table IV). There was one SETs increases with LET up to at least 30 MeV-cm2/mg (Fig. anomaly in that DUT 1, which was damaged during 12). These data are from LBNL. Since the scope window decapping, had some SETs with 120 µF output capacitance could only capture 7.2 µs, the relation between duration and using a 20 µF tantalum capacitor and a 100 µF aluminum LET is unknown beyond this point. capacitor, while it did not have any SETs with a 60 µF tantalum capacitor. DUT 2 did not have any SETs with either TABLE IV TEST RESULTS FROM LBNL, LET=58.8 MEV-CM2/MG, 60 or 120 µF output capacitance. These data are from the OPERATING CURRENT=12.0 MA, LOAD CURRENT=2.5µA LBNL testing using the xenon ion beam with an LET of 58 MeV-cm2/mg. No filter resistor was used, the operating Cross Maximum SET Amplitude Maximum Output Section Positive Negative SET Duration current was 12.0 mA and the load current was 2.5 µA. Capacitor (cm2)(V)(V)(µs) No Cap 1.0E-03 1.76 -1.72 7.2+ 3 Load Current = 0.0025 mA 30 µF 1.4E-05 0.33 -0.44 0.06 60 µF None None None None Load Current = 10 mA 2

3.0 1 2.5 2.0 0 1.5

Amplitude (V) Amplitude -1 1.0 0.5 -2 0.0 -0.5 -3

Maximum Error Amplitude (V) Amplitude Error Maximum -1.0 0246810121416 Time (µs) -1.5 Fig. 9. SET amplitude vs. pulse width with the operating current set at -2.0 14.3 mA. Data are from TAMU with an LET of 87.1 MeV-cm2/mg. 0 20406080100 LET (MeV-cm2/mg)

3 Fig. 11. SET amplitude vs. LET. Data are from LBNL, with an operating current of 12.0 mA, except for the last points at 87.1 MeV-cm2/mg, which 2 came from the testing at TAMU with an operating current of 14.3 mA.

8 1 No Filter 7 Filter s)

0 µ 6

Amplitude (V) Amplitude 5 -1 4 -2 3

-3 2 0 5 10 15 20 ( Duration Error Maximum 1 Time (µs) 0 Fig. 10. SET amplitude vs. pulse width with the operating current set at 0.89 mA and a load current of 2.5 µA. Data are from TAMU with an LET of 0 5 10 15 20 25 30 35 87.1 MeV-cm2/mg. LET (MeV-cm2/mg)

With no load on the output and a high operating current, the Fig. 12. SET duration vs. LET. Data are from LBNL. magnitude of the negative-going SETs was dependent upon LET up to 30 MeV-cm2/mg (Fig. 11). The magnitude of the A threshold LET (LETth) was not determined, as 1 event positive-going SET continued to increase with LET. The data was detected at a fluence of 1 x 107 ions/cm2 at the lowest plotted are from LBNL, with a 12.0 mA operating current, LET tested (0.89 MeV-cm2/mg). A saturated cross section of except the point at 87.1 MeV-cm2/mg, which comes from the 1 x 10-3 cm2 was determined during the testing at LBNL. The

SET cross section versus LET to 58.8 MeV-cm2/mg for the [4] D. J. Cochran, et al, “Compendium of total ionizing dose results and LBNL data is plotted in Fig. 13. This testing was done with displacement damage results for candidate spacecraft electronics for NASA”, 2006 IEEE Radiation Effects Data Workshop Record, pp. 6-12 the operating current at 12.0 mA. Also plotted on Fig. 13 at [5] UNiSYS test report. May 17, 1995 2 an LET of 87.1 MeV-cm /mg is the cross section data from http://radhome.gsfc.nasa.gov/radhome/papers/tid/PPM-95-152.pdf TAMU with an operating current of 14.3 mA. The increase in [6] R. Koga, S. H. Crawford, W. R. Crain, S. C. Moss, S. D. Pinkerton, S. cross section may be due to the operating current. A Weibull D. LaLunondiere, M. C. Maher, “Single event upset (SEU) sensitivity dependence of linear integrated circuits (ICs) on bias conditions”, IEEE fit [12] based on the LBNL data only is also plotted. The Trans. Nucl. Sci, vol. 44, no. 6, pp 2325-2332, Dec. 1997 Weibull parameters are listed in Table V. [7] “DS16F95QML EIA-485/EIA-422A Differential Bus Transceiver”, September 2005, National Semiconductor, Santa Clara, California http://www.national.com/opf/DS/DS16F95.html#Overview 1.0E-02 [8] “A. T. Kelly, R. D. Brown, F. Wong, and P. R. Fleming, “Single event and ELDRS effects in the DS16F95 RS-485 transceiver”, 2010 Nuclear and Space Radiation Effects Conference brochure, 1.0E-03 http://nsrec.com/brochure.htm [9] MIL-STD-883 Test Method Standard, Microcircuits, Department of ) 2 Defense, Defense Supply Center Columbus, Columbus, OH, June18, 1.0E-04 2004 Data http://www.dscc.dla.mil/Downloads/MilSpec/Docs/MIL-STD- Weibull Fit 883/std883.pdf. 1.0E-05 [10] Lawrence Berkeley National Laboratory website http://cyclotron.lbl.gov/ [11] Radiation Effects Facility, The Cyclotron Institute, Texas A&M Cross Section(cm 1.0E-06 University, http://cyclotron.tamu.edu/ref/ [12] ”Reliability and Risk Analysis”, N. J. McCormick Academic Press, NY, NY 1981 1.0E-07 0 20406080100 LET (MeV-cm2/mg) Fig. 13. SET cross section vs. LET. Data for 0.89 to 58.8 MeV-cm2/mg are from the testing at LBNL with an operating current of 12.0 mA. The point at 87.1 MeV-cm2/mg is from the testing at TAMU with an operating current of 14.3 mA.

TABLE V WEIBULL FIT PARAMETERS FOR THE LBNL DATA ALoW s 1.00E-03 0 16 2.8

V. CONCLUSION The LM4050WG2.5RLQV is considered to have ELDRS under the strict definition in MIL-STD-883 TM1019. To qualify the product at 100 krad(Si) for low dose rate environments, the part is tested at a dose rate of 10 mrad(Si)/s to a TID of 150 krad(Si), with all parameters inside the specification limits at 150 krad(Si). SET performance of the LM4050WG2.5RLQV is dependent upon operating conditions. Positive-going SETs can be greatly mitigated by carefully matching the operating current close to the load current. An output filter capacitor can attenuate or eliminate SETs.

VI. REFERENCES [1] “LM4050QML Precision Micropower Shunt Voltage Reference”, June 30, 2010, National Semiconductor, Santa Clara, California http://www.national.com/pf/LM/LM4050QML.html#Overview [2] S. S. McClure, J. L. Gorelick, C. C. Yui, B. G. Rax, M. C. Wiedeman, “Continuing evaluation of bipolar linear devices for total dose bias dependency and ELDRS effects”, 2003 IEEE Radiation Effects Data Workshop Record, pp. 1-5 [3] R. M. Rivas, A. H. Johnston, T. F. Miyahira, B. G. Rax, M. D. Wiedeman, “Test results of total ionizing dose conducted a the Jet Propulsion Laboratory”, 2004 IEEE Radiation Effects Data Workshop Record, pp. 36-41