Comparative Analysis of Space-Grade Processors

Total Page:16

File Type:pdf, Size:1020Kb

Comparative Analysis of Space-Grade Processors COMPARATIVE ANALYSIS OF SPACE-GRADE PROCESSORS By TYLER MICHAEL LOVELLY A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2017 © 2017 Tyler Michael Lovelly To my country ACKNOWLEDGMENTS This work was supported in part by the Industry/University Cooperative Research Center Program of the National Science Foundation under grant nos. IIP-1161022 and CNS-1738783, by the industry and government members of the NSF Center for High- Performance Reconfigurable Computing and the NSF Center for Space, High- Performance, and Resilient Computing, by the University of Southern California Information Sciences Institute for remote access to their systems, and by Xilinx and Microsemi for provided hardware and software. 4 TABLE OF CONTENTS page ACKNOWLEDGMENTS .................................................................................................. 4 LIST OF TABLES ............................................................................................................ 7 LIST OF FIGURES .......................................................................................................... 8 ABSTRACT ..................................................................................................................... 9 CHAPTER 1 INTRODUCTION .................................................................................................... 11 2 BACKGROUND AND RELATED RESEARCH ....................................................... 14 Metrics and Benchmarking Analysis ....................................................................... 15 Computational Dwarfs and Taxonomies ................................................................. 18 3 METRICS AND BENCHMARKING METHODOLOGIES ........................................ 20 Metrics Calculations for Fixed-Logic and Reconfigurable-Logic Processors........... 20 Benchmark Development, Optimization, and Testing for CPUs and FPGAs .......... 24 4 METRICS EXPERIMENTS, RESULTS, AND ANALYSIS ....................................... 27 Metrics Comparisons of Space-Grade CPUs, DSPs, and FPGAs .......................... 27 Performance Variations in Space-Grade CPUs, DSPs, and FPGAs ...................... 29 Overheads Incurred from Radiation Hardening of CPUs, DSPs, and FPGAs ......... 36 Projected Future Space-Grade CPUs, DSPs, FPGAs, and GPUs .......................... 39 5 BENCHMARKING EXPERIMENTS, RESULTS, AND ANALYSIS ......................... 44 Space-Computing Taxonomy and Benchmarks ...................................................... 44 Performance Analysis of Space-Grade CPUs ........................................................ 48 Performance Analysis of Space-Grade FPGAs ...................................................... 51 Benchmarking Comparisons of Space-Grade CPUs and FPGAs ........................... 53 Expanded Analysis of Space-Grade CPUs ............................................................. 55 6 CONCLUSIONS ..................................................................................................... 58 APPENDIX A METRICS DATA ..................................................................................................... 62 B BENCHMARKING DATA ........................................................................................ 65 5 LIST OF REFERENCES ............................................................................................... 68 BIOGRAPHICAL SKETCH ............................................................................................ 84 6 LIST OF TABLES Table page 2-1 UCB computational dwarfs. ................................................................................ 18 5-1 Space-computing taxonomy. .............................................................................. 45 5-2 Space-computing benchmarks. .......................................................................... 47 A-1 Metrics data for space-grade CPUs, DSPs, and FPGAs. ................................... 62 A-2 Performance variations in space-grade CPUs, DSPs, and FPGAs. ................... 62 A-3 Metrics data for closest COTS counterparts to space-grade CPUs, DSPs, and FPGAs. ........................................................................................................ 62 A-4 Radiation-hardening outcomes for space-grade CPUs, DSPs, and FPGAs. ...... 63 A-5 Percentages achieved by space-grade CPUs, DSPs, and FPGAs after radiation hardening. ............................................................................................ 63 A-6 Metrics data for low-power COTS CPUs, DSPs, FPGAs, and GPUs. ................ 64 A-7 Metrics data for projected future space-grade CPUs, DSPs, FPGAs, and GPUs (worst case). ............................................................................................ 64 A-8 Metrics data for projected future space-grade CPUs, DSPs, FPGAs, and GPUs (best case). .............................................................................................. 64 B-1 Parallelization data for space-grade CPUs. ........................................................ 65 B-2 Resource usage data for space-grade FPGAs. .................................................. 66 B-3 Benchmarking data for matrix multiplication on space-grade CPUs and FPGAs. ............................................................................................................... 66 B-4 Benchmarking data for Kepler’s equation on space-grade CPUs and FPGAs. .. 66 B-5 Performance data for additional benchmarks on space-grade CPUs. ................ 67 7 LIST OF FIGURES Figure page 4-1 Metrics data for space-grade CPUs, DSPs, and FPGAs. ................................... 28 4-2 Operations mixes of intensive computations. ..................................................... 30 4-3 Performance variations in space-grade CPUs, DSPs, and FPGAs. ................... 31 4-4 Metrics data for closest COTS counterparts to space-grade CPUs, DSPs, and FPGAs. ........................................................................................................ 37 4-5 Percentages achieved by space-grade CPUs, DSPs, and FPGAs after radiation hardening. ............................................................................................ 38 4-6 Metrics data for low-power COTS CPUs, DSPs, FPGAs, and GPUs. ................ 40 4-7 Metrics data for current and projected future space-grade CPUs, DSPs, FPGAs, and GPUs. ............................................................................................ 42 5-1 Parallelization data for matrix multiplication on space-grade CPUs. ................... 49 5-2 Parallelization data for Kepler’s equation on space-grade CPUs. ...................... 50 5-3 Resource usage data for matrix multiplication on space-grade FPGAs. ............. 51 5-4 Resource usage data for Kepler’s equation on space-grade FPGAs. ................ 52 5-5 Benchmarking data for matrix multiplication on space-grade CPUs and FPGAs. ............................................................................................................... 54 5-6 Benchmarking data for Kepler’s equation on space-grade CPUs and FPGAs. .. 54 5-7 Performance data for additional benchmarks on space-grade CPUs. ................ 56 8 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy COMPARATIVE ANALYSIS OF SPACE-GRADE PROCESSORS By Tyler Michael Lovelly December 2017 Chair: Alan Dale George Major: Electrical and Computer Engineering Onboard computing demands for space missions are continually increasing due to the need for real-time sensor and autonomous processing combined with limited communication bandwidth to ground stations. However, creating space-grade processors that can operate reliably in environments that are highly susceptible to radiation hazards is a lengthy, complex, and costly process, resulting in limited processor options for space missions. Therefore, research is conducted into current, upcoming, and potential future space-grade processors to provide critical insights for progressively more advanced architectures that can better meet the increasing demands for onboard computing. Metrics and benchmarking data are generated and analyzed for various processors in terms of performance, power efficiency, memory bandwidth, and input/output bandwidth. Metrics are used to measure and compare the theoretical capabilities of a broad range of processors. Results demonstrate how onboard computing capabilities are increasing due to processors with architectures that support high levels of parallelism in terms of computational units, internal memories, and input/output resources; and how performance varies between applications, depending on the intensive computations 9 used. Furthermore, the overheads incurred by radiation hardening are quantified and used to analyze low-power commercial processors for potential use as future space- grade processors. Once the top-performing processors are identified using metrics, benchmarking is used to measure and compare their realizable capabilities. Computational dwarfs are established and a taxonomy is formulated to characterize the space-computing domain and identify computations for benchmark development, optimization, and testing. Results demonstrate how to optimize for the architectures of space-grade processors and how they compare to one another
Recommended publications
  • Wind River Vxworks Platforms 3.8
    Wind River VxWorks Platforms 3.8 The market for secure, intelligent, Table of Contents Build System ................................ 24 connected devices is constantly expand- Command-Line Project Platforms Available in ing. Embedded devices are becoming and Build System .......................... 24 VxWorks Edition .................................2 more complex to meet market demands. Workbench Debugger .................. 24 New in VxWorks Platforms 3.8 ............2 Internet connectivity allows new levels of VxWorks Simulator ....................... 24 remote management but also calls for VxWorks Platforms Features ...............3 Workbench VxWorks Source increased levels of security. VxWorks Real-Time Operating Build Configuration ...................... 25 System ...........................................3 More powerful processors are being VxWorks 6.x Kernel Compatibility .............................3 considered to drive intelligence and Configurator ................................. 25 higher functionality into devices. Because State-of-the-Art Memory Host Shell ..................................... 25 Protection ..................................3 real-time and performance requirements Kernel Shell .................................. 25 are nonnegotiable, manufacturers are VxBus Framework ......................4 Run-Time Analysis Tools ............... 26 cautious about incorporating new Core Dump File Generation technologies into proven systems. To and Analysis ...............................4 System Viewer ........................
    [Show full text]
  • RAD750 at Our Website: Click HERE RAD750• Board
    Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the BAE Systems RAD750 at our website: Click HERE RAD750 Board Hardware Specification Document Number 234A524 Release Date August 1, 2000 Copyright by BAE SYSTEMS All Rights Reserved Document Number: 234A524 RAD750 CompactPCI Hardware Specification Notices Before using this information and the product it supports, be sure to read the general information on the back cover of this book. Trademarks The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM IBM Logo PowerPC PowerPC 750 The following are trademarks of BAE SYSTEMS in the United States, or other countries, or both: RAD750 The following are registered trademarks of PCI Industrial Computer Manufacturing Group in the United States, or other countries, or both: PICMG CompactPCI Other company, product, and service names may be trademarks or service marks of others. Preliminary Edition (Version 4.0, 8/1/2000) This unpublished document is the preliminary edition of RAD750 3U CompactPCI board Hardware Specification.
    [Show full text]
  • Schedule 14A Employee Slides Supertex Sunnyvale
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 SCHEDULE 14A Proxy Statement Pursuant to Section 14(a) of the Securities Exchange Act of 1934 Filed by the Registrant Filed by a Party other than the Registrant Check the appropriate box: Preliminary Proxy Statement Confidential, for Use of the Commission Only (as permitted by Rule 14a-6(e)(2)) Definitive Proxy Statement Definitive Additional Materials Soliciting Material Pursuant to §240.14a-12 Supertex, Inc. (Name of Registrant as Specified In Its Charter) Microchip Technology Incorporated (Name of Person(s) Filing Proxy Statement, if other than the Registrant) Payment of Filing Fee (Check the appropriate box): No fee required. Fee computed on table below per Exchange Act Rules 14a-6(i)(1) and 0-11. (1) Title of each class of securities to which transaction applies: (2) Aggregate number of securities to which transaction applies: (3) Per unit price or other underlying value of transaction computed pursuant to Exchange Act Rule 0-11 (set forth the amount on which the filing fee is calculated and state how it was determined): (4) Proposed maximum aggregate value of transaction: (5) Total fee paid: Fee paid previously with preliminary materials. Check box if any part of the fee is offset as provided by Exchange Act Rule 0-11(a)(2) and identify the filing for which the offsetting fee was paid previously. Identify the previous filing by registration statement number, or the Form or Schedule and the date of its filing. (1) Amount Previously Paid: (2) Form, Schedule or Registration Statement No.: (3) Filing Party: (4) Date Filed: Filed by Microchip Technology Incorporated Pursuant to Rule 14a-12 of the Securities Exchange Act of 1934 Subject Company: Supertex, Inc.
    [Show full text]
  • Microkernel Mechanisms for Improving the Trustworthiness of Commodity Hardware
    Microkernel Mechanisms for Improving the Trustworthiness of Commodity Hardware Yanyan Shen Submitted in fulfilment of the requirements for the degree of Doctor of Philosophy School of Computer Science and Engineering Faculty of Engineering March 2019 Thesis/Dissertation Sheet Surname/Family Name : Shen Given Name/s : Yanyan Abbreviation for degree as give in the University calendar : PhD Faculty : Faculty of Engineering School : School of Computer Science and Engineering Microkernel Mechanisms for Improving the Trustworthiness of Commodity Thesis Title : Hardware Abstract 350 words maximum: (PLEASE TYPE) The thesis presents microkernel-based software-implemented mechanisms for improving the trustworthiness of computer systems based on commercial off-the-shelf (COTS) hardware that can malfunction when the hardware is impacted by transient hardware faults. The hardware anomalies, if undetected, can cause data corruptions, system crashes, and security vulnerabilities, significantly undermining system dependability. Specifically, we adopt the single event upset (SEU) fault model and address transient CPU or memory faults. We take advantage of the functional correctness and isolation guarantee provided by the formally verified seL4 microkernel and hardware redundancy provided by multicore processors, design the redundant co-execution (RCoE) architecture that replicates a whole software system (including the microkernel) onto different CPU cores, and implement two variants, loosely-coupled redundant co-execution (LC-RCoE) and closely-coupled redundant co-execution (CC-RCoE), for the ARM and x86 architectures. RCoE treats each replica of the software system as a state machine and ensures that the replicas start from the same initial state, observe consistent inputs, perform equivalent state transitions, and thus produce consistent outputs during error-free executions.
    [Show full text]
  • Qoriq: High End Industrial and Networking Processing
    TM TechDays 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, Ready Play, Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, trademarks of Freescale Semiconductor, Inc. All other product or service names are the BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, TM property of their respective owners. © 2012 Freescale Semiconductor, Inc. 1 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All . other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. 2013 2011 QorIQ Qonverge QorIQ next-generation platform launch platform based T series 28nm on Layerscape architecture 2008 QorIQ Multicore Platform launch (P series) Accelerating the P series 45nm Network’s IQ 2004 Dual-core
    [Show full text]
  • SEWIP Program Leverages COTS P 36 P 28 an Interview with Deon Viergutz, Vice President of Cyber Solutions at Lockheed Martin Information Systems & Global Solutions
    @military_cots John McHale Obsolescence trends 8 Special Report Shipboard displays 44 Mil Tech Trends Predictive analytics 52 Industry Spotlight Aging avionics software 56 MIL-EMBEDDED.COM September 2015 | Volume 11 | Number 6 RESOURCE GUIDE 2015 P 62 Navy SEWIP program leverages COTS P 36 P 28 An interview with Deon Viergutz, Vice President of Cyber Solutions at Lockheed Martin Information Systems & Global Solutions Military electronics market overview P 14 Volume 11 Number 6 www.mil-embedded.com September 2015 COLUMNS BONUS – MARKET OVERVIEW Editor’s Perspective 14 C4ISR funding a bright spot in military 8 Tech mergers & military electronics electronics market obsolescence By John McHale, Editorial Director By John McHale Q&A EXECUTIVE OUTLOOK Field Intelligence 10 Metadata: When target video 28 Defending DoD from cyberattacks, getting to data is not enough the left of the boom By Charlotte Adams 14 An interview with Deon Viergutz, Vice President of Cyber Solutions at Lockheed Martin Information Mil Tech Insider Systems & Global Solutions 12 Broadwell chip boosts GPU performance for COTS SBCs 32 RF and microwave innovation drives military By Aaron Frank radar and electronic warfare applications An interview with Bryan Goldstein, DEPARTMENTS General Manager of the Aerospace and Defense, Analog Devices 22 Defense Tech Wire By Mariana Iriarte SPECIAL REPORT 60 Editor’s Choice Products Shipboard Electronics 112 University Update 36 U.S. Navy’s electronic warfare modernization On DARPA’s cybersecurity radar: 36 effort centers on COTS Algorithmic and side-channel attacks By Sally Cole, Senior Editor By Sally Cole 114 Connecting with Mil Embedded 44 Key to military display technologies: Blog – The fascinating world of System integration By Tom Whinfrey, IEE Inc.
    [Show full text]
  • Application Support for Agilent Logic Analyzers
    Application Support for Agilent Logic Analyzers Configuration Guide May 1, 2005 Configuring a logic analyzer for your Table of Contents specific application is as easy as one, two, three. To configure a system Agilent Logic Analyzer Family Selection Guide. 2 select the combination of products and capabilities that will 1 connect Designed In Probing . 4 1 connect Connectorless . 4 Connector. 5 General Purpose Probing . 6 Create the physical and electrical Flying-Lead Sets . 6 connection between the logic analyzer Wedge Probe Adapter . 6 and your device under test. IC Package Adapters . 7 Device Specific (Processor/Bus) Real-Time Trace Probes . 8 Processor, DSP and FPGA Solutions . 10 - 17 2 acquire Bus Interconnect Solutions. 18 - 24 2 acquire Provide accurate and reliable measurements, with power to cover Modular Logic Analysis Systems – 16900 Series Mainframes and future technology trends. Logic Analyzer Modules. 25 Modular Logic Analysis Systems – Pattern Generator Module and Oscilloscopes . 27 1680 Series Standalone Logic Analyzers . 28 3 view & analyze 1690 Series PC-Hosted Logic Analyzers. 28 Consolidate large amounts of data 3 view & analyze rapidly into displays that provide Post-Processing Analysis Tools . 29 insight into your system’s behavior in Pattern Generator Analysis Tools. 29 a format you understand. Third Party Contact Information . 30 Support, Services, and Assistance . 31 Use information in each of the sections listed to help you configure a system that will meet your specific measurement needs. Agilent Logic Analyzer
    [Show full text]
  • Dual-Core ARM Cortex-A7 • 2 X ARM Cortex A7 Cpus, up to 1.0Ghz
    Технологии QNX и КПДА в России Москва, 13 апреля 2017 Микропроцессоры NXP c с поддержкой технологий QNX для промышленных, сетевых, автомобильных приложений. Семейства QorIQ, i.MX и S32V. Александр Акименко, Группа компаний Симметрон Программа презентации • i.MX 6QuadPlus/6DualPlus – флагман линейки i.MX • i.MX 7 – энергоэффективное решение для IoT • Анонс процессоров i.MX 8 – взгляд в будущее линейки i.MX • LS1012A – самый маленький и самый энергоэффективный 64- битный процессор • LS1020A/21A/22A – двухъядерные процессоры с широким набором периферии для IoT и промышленных приложений • LS1023A/43A – 64-разрядные процессоры с поддержкой 10Gbps Ethernet • S32V – процессоры для реализации функций ADAS в автомобильной электронике 1 i.MX 6QuadPlus/6DualPlus (upgraded i.MX 6Quad/6Dual) QNX SDP 7.0 Specifications: BSP available • CPU: i.MX 6QuadPlus: 4x Cortex-A9 @ 800MHz/852MHz/1GHz/1.2GHz i.MX 6DualPlus: 2x Cortex-A9 @ 800MHz/852MHz/1GHz/1.2GHz • Process: 40nm • Package: 21x21 0.8mm Flip-chip BGA • Temp Range (Tj): • Auto -40 to 125C • Industrial -40 to 105C • Extended Commercial -20 to 105C • Qual Tiers: Commercial, Automotive, Industrial • Pin compatible with i.MX 6Quad and i.MX 6Dual • Up to 10,000 DMIPS 2 i.MX Processor Roadmap 6QuadPlus i.MX 8 family 6Quad Advanced Graphics and Performance ARM ® v8-A (32-bit/ 64-bit) 6DualPlus i.MX 8M family pin Compatible pin 6Dual - Advanced Audio and Video to - ARM ® v8-A 6DualLite (32-bit/ 64-bit) Pin 6Solo i.MX 8X family Safety Critical & Efficient Performance 6SoloX ® ARM v8-A (32-bit/ 64-bit) Software Compatible Software 6SoloLite 6UltraLite i.MX 7 Power Efficiency & BOM Cost Optimizations ® 6ULL ARM v7-A (32-bit) ® ARM v7-A 3 i.MX 7Dual/7Solo QNX SDP 7.0 BSP Specifications: available .
    [Show full text]
  • IBM Systems Group
    IBM STG Deep Computing IBM Systems Group Deep Computing with IBM Systems Barry Bolding, Ph.D. IBM Deep Computing SciComp 2005 Confidential | Systems Group 2004 © 2004 IBM Corporation IBM Systems and Technology Group Deep Computing Components High Performance Computing Leadership Research and Innovation Systems Expertise – pSeries – xSeries – Storage – Networking Innovative Systems © 2004 IBM Corporation IBM Systems and Technology Group Deep Computing Focus Government Research Labs – Energy and Defense Weather/Environmental – Weather Forecasting Centers – Climate Modeling Higher Education/Research Universities Life Sciences – Pharma, BioTech, Chemical Aero/Auto Petroleum Business Intelligence, Digital Media, Financial Services, On Demand HPC © 2004 IBM Corporation IBM STG Deep Computing Deep Computing Teams and Organization Confidential | Systems Group 2004 © 2004 IBM Corporation IBM Systems and Technology Group Deep Computing Technical Team Kent Winchell Technical Team Deep Computing Barry Bolding Jeff Zais Technical Manager Technical Manager Public Sector Industrial Sector Farid Parpia John Bauer Martin Feyereisen Doug Petesch HPC Applications HPC Storage Auto/Aero Auto/Aero Life Sciences Government, HPC Business Intelligence “Suga” Sugavanam Wei Chen Charles Grassl Guangye Li EDA Government HPC Applications Auto/Aero Asia Pacific HPC HIgher Ed. BlueGene/L Stephen Behling Ray Paden Si MacAlester Harry Young Higher Ed GPFS CFD HPC Storage Digitial Media Digital Media Joseph Skovira James Abeles Scott Denham Janet Shiu Schedulers
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Freescale Qoriq P4080 DMA-DDR Performance Analysis
    TM Wai Chee Wong Sr.Member of Technical Staff Freescale Semiconductor Raghu Binnamangalam Sr.Technical Marketing Engineer Cadence Design Systems Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. DAC 2013, Austin, TX • Company Overview • Use of emulation at Freescale • Palladium usage for emulation model under test • Performance case studies • Experiences using Palladium system • Summary Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 2 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. • Global leader in embedded
    [Show full text]
  • Vybrid Controllers Technical Overview
    TM June 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. • Overview of Vybrid Family • Vybrid Tower Board • Vybrid System Modules • QuadSPI Flash • Vybrid Clock System • Vybrid Power System • Vybrid Boot Operation • High Assurance Boot • Vybrid Trusted Execution • LinuxLink and MQX Embedded Software • DS-5 compiler TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. 2 Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, SafeAssure, the SafeAssure logo, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg.
    [Show full text]