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I0186d Latticesemi.Com OPEN SOURCE SOFT CORE MICROPROCESSOR LatticeMico32 Soft Core 32-Bit Microprocessor Optimized for Lattice Programmable Devices The LatticeMico32™ is a highly configurable 32-bit Harvard architecture “soft” microprocessor core for Lattice FPGA devices. LatticeMico32 combines a 32-bit wide instruction set with 32 general purpose registers, to provide the performance and flexibility suitable for a wide variety of markets. Using a Reduced Instruction Set Computer (RISC) architecture, the core consumes minimal device resources, while maintaining the performance required for a broad application set. The associated LatticeMico™ System Development Tools provide a fast and easy way to implement microprocessor designs. The tools coordinate processor platform definition, software development and debug. Additionally, the LatticeMico32 is available as source code under Key Features and Benefits the Lattice open IP core license, thereby providing visibility, Optimized for Lattice FPGA Devices flexibility and portability – all free of charge. Innovative Open IP Core License LatticeMico32 Block Diagram Performance Enhanced Feature Set • RISC architecture PC • 32-bit data path Instruction • 32-bit instructions WISHBONE Instruction Cache Memory • 32 general purpose registers • Handles up to 32 external interrupts Instruction Register • Optional instruction cache Branch Predictor Instruction Decoder Register File • Optional data cache • Optional inline data memory • Optional inline instruction memory User Adder CSRs Logical • WISHBONE memory interfaces (Instruction and Data) Logic Easy to Use Development Tools Bypass & Interlock Shifter • LatticeMico System for: Multiply - Platform definition & WISHBONE Data Data - C/C++ Software development Cache Memory Divide - Debug • LatticeMico System operates with Lattice Diamond® • Includes support for: Align - Standard Make - Non-volatile memory deployment Peripheral Components (WISHBONE) • Memory controllers: DDR, DDR2 and DDR3 SDRAM Build a Complete Embedded System controllers, asynchronous SRAM, on-chip block memory, SDRAM controller, on-chip dual port memory, SPI Flash, parallel Flash Lattice FPGA LatticeMico32 IP Core User Logic • I/O: 32-bit timer, Tri-Speed Ethernet MAC, DMA controller, GPIO, I2C master controller, SPI, UART, PCI Target 32-bit Timer WISHBONE Arbiter On-chip Memory Flash Memory SRAM Controller UARTGPIO Controller SRAM Flash Memory LATTICESEMI.COM Development Tools Open IP Core Licensing The LatticeMico System is used to implement the LatticeMico32 The generated LatticeMico32 core and selected peripheral soft microprocessor and attached peripheral components in a component HDL codes are available through a unique open IP core Lattice FPGA. It is based on the Eclipse C/C++ Development Tools licensing agreement, while the GNU-based compiler, assembler, (CDT) environment, which is an industry open-source development linker and debugger are licensed under the GNU GPL agreement. and application framework for building software. The LatticeMico The main benefits of open source IP are: System contains two integrated tools (detailed below) that combine Visibility with Diamond to coordinate the building of an embedded processor • Allows complete understanding of the detailed operation of system on an FPGA device and to write the software that drives it. the core Mico System Builder (MSB) Flexibility • Choose peripheral components to attach to the LatticeMico32 • User can develop alternate micro-architectures or • Specify connectivity between peripheral components implementations • Generate platform description and associated HDL for Portability hardware implementation • Architecture independence C/C++ Software Project Environment (SPE) and • Migrate to an ASIC or an SoC Debugger Free of Charge • Develop the code that runs on platforms created with MSB • Interfaces to compiler, assembler, linker, and debugger tools Resource Utilization/Performance* Lattice FPGA Family LUTs Max. Clock Frequency LatticeECP3™ 2370 115 MHz LatticeXP2™ 2406 85 MHz LatticeECP2/M 2497 110 MHz * Standard configuration with 8K instruction cache. LatticeMico System Development Flow Platform Development Software Development Hardware Platform C/C++ Software Project Environment (SPE) Mico System Builder and Debugger (MSB) (C/C++ SPE & Debugger supported for LatticeMico32, C SPE supported for LatticeMico8) HDL ELF FPGA Design Rest of User Design Implementation in HDL Debug Target Board LATTICE DIAMOND DESIGN SOFTWARE ispVM™ or Programmer Program Applications Support LATTICE 1-800-LATTICE (528-8423) 503-268-8001 DIAMOND [email protected] DESIGN SOFTWARE Copyright © 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), ispLEVER, ispVM, Lattice Diamond, LatticeMico8, MachXO2, MachXO, sysCLOCK, sysIO, sysMEM, TraceID, and TransFR are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. July 2012 Order #: I0186D LATTICESEMI.COM.
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