MICROCONTROLLER-BASED,
DUAL-CHANNEL WIRELESS NEURAL
RECORDER/ STIMULATOR
by
Christopher Dorr
Submitted in partial fulfillment of the requirements
for the degree of Master of Science
Thesis Advisor: Dr. Steven L. Garverick
Department of Electrical Engineering and Computer Science
CASE WESTERN RESERVE UNIVERSITY
January 2009 CASE WESTERN RESERVE UNIVERSITY
SCHOOL OF GRADUATE STUDIES
We hereby approve the thesis/dissertation of
______
candidate for the ______degree *.
(signed)______(chair of the committee)
______
______
______
______
______
(date) ______
*We also certify that written approval has been obtained for any proprietary material contained therein. Table of Contents
List of Tables ...... iv List of Figures...... v Acknowledgements...... x Abstract...... xi 1. Introduction...... 1 1.1 Motivation...... 1 1.2 Background...... 2 1.2.1 Previous Work at CWRU...... 4 1.2.2 Other Related Work ...... 6 1.3 Objectives ...... 15 2. Architecture for Wireless Neural Recording and Stimulation...... 16 2.1 Basic Version...... 16 2.1.1 Neural Recording...... 17 2.1.2 Data Transmission ...... 18 2.1.3 Neural Stimulus...... 19 2.1.4 Command Reception...... 20 2.1.5 Control ...... 20 2.1.6 Power ...... 21 2.2 Advanced Version...... 21 2.2.1 Neural Recording...... 22 2.2.2 Data Transmission ...... 22 2.2.3 Neural Stimulus...... 23 2.2.4 Command Reception...... 23 2.2.5 Control ...... 23 2.2.6 Power ...... 23 3. Detailed Design of the Implantable Neural Recording and Stimulation Device...... 25 3.1 Basic Implant Device...... 25 3.1.1 Neural Amplifiers ...... 26 3.1.2 Multiplexer...... 29 3.1.3 Analog-to-Digital Converter...... 30 3.1.4 FSK Transmitter...... 31 3.1.5 Neural Stimulator...... 32 3.1.6 OOK Receiver...... 34 3.1.7 Microcontroller ...... 37 3.1.8 Power ...... 44 3.1.9 Implementation ...... 45 3.2 Advanced Implant Prototype ...... 46 3.2.1 Neural Amplifiers ...... 47 3.2.2 Multiplexer...... 48 3.2.3 Analog-to Digital Converter ...... 48 3.2.4 FSK Transmitter...... 49 3.2.5 Neural Stimulator...... 49 3.2.6 OOK Receiver...... 50 3.2.7 Microcontroller ...... 50
ii 3.2.8 Power ...... 55 3.2.9 Implementation ...... 56 4. Test Results...... 58 4.1 Basic Device Test Results...... 58 4.1.1 Microcontroller Start-up...... 58 4.1.2 Multiplexer...... 60 4.1.3 Second-Stage Amplifier...... 62 4.1.4 OOK Receiver...... 63 4.1.5 ASIC ...... 65 4.1.6 Power ...... 75 4.2 Tests with Aplysia...... 76 4.2.1 In Vitro Tests...... 77 4.2.2 Immersion Tests...... 87 4.2.3 In Vivo Tests ...... 89 4.3 Advanced Prototype Test Results ...... 91 4.3.1 Data Processing...... 92 4.3.2 OOK Receiver...... 92 4.3.3 ASIC ...... 93 4.3.4 Supply Current...... 99 5. Conclusion ...... 101 5.1 Achievements...... 101 5.2 Future Work...... 104 Appendix A: Basic 2-Channel Implant Schematic ...... 105 Appendix B: Basic 2-Channel Implant PCB Layout ...... 106 Appendix C: Advanced 2-Channel Prototype Schematic...... 109 Appendix D: Advanced 2-Channel Prototype Layout...... 110 Bibliography ...... 114
iii List of Tables
3-1 MAX4544 logic table (from [49])...... 29
3-2 Microcontroller input/output signals table...... 38
3-3 Command packet format (from [3-4, 56])...... 39
3-4 Trigger & Channel Set command data bits (from [3-4, 57])...... 40
3-5 Summary of T&C command data bit functions...... 41
3-6 Stimulation Parameter 1 command data bits (from [3-4, 57])...... 41
3-7 Stimulation Parameter 2 command data bits (from [3-4, 57])...... 42
3-8 Advanced prototype microcontroller input/output table...... 51
3-9 Advanced prototype Stimulation Parameter 1 command data bits (from [3-4, 57]).52
3-10 Other Parameters command data bits (from [3-4, 57])...... 52
4-1 Measured microcontroller default output levels...... 60
4-2 Microcontroller signal output levels before and after SP1 and T&C commands were sent...... 65
4-3 Voltage regulator output at different input voltages...... 66
4-4 Measured reference generator voltage levels...... 74
4-5 Measured current drawn by components of the implant unit...... 75
4-6 Enhanced voltage regulator output for different supply voltages...... 94
4-7 Advanced prototype reference generator output for various supply voltages...... 99
4-8 Advanced prototype current draw by component...... 100
5-1 Comparison of similar neural recording and stimulation technology research...... 103
iv List of Figures
1.1 Common sea slug, Aplysia californica...... 2
1.2 Wireless recording unit (from [32])...... 4
1.3 TinyOS-based neural recording unit developed at UCLA (from [34])...... 7
1.4 TinyOS-based neural recording unit schematic (from [34])...... 7
1.5 15-channel wireless neural recording chip block diagram, developed at NCSU (from [36])...... 9
1.6 Complete integrated neural interface assembly, developed at University of Utah (from [38])...... 10
1.7 Integrated neural interface block diagram, developed at University of Utah (from [38])...... 10
1.8 Block diagram of neural recoding system developed at the University of Michigan (from [40])...... 12
1.9 Block diagram of the NPU-32, developed at the University of Michigan (from [40])...... 12
1.10 Block diagram of the Interstim-2B, developed at the University of Michigan (from [42])...... 14
2.1 Block diagram of basic version. Shaded blocks represent hardware external to the ASIC (from [3-4])...... 17
2.2 An illustrative example of frequency-shift keying modulation (from [45])...... 18
2.3 An illustrative example of on-off keying modulation (after [45])...... 20
2.4 Block diagram of advanced version. Lightly shaded blocks represent hardware external to the ASIC. Darkly shaded blocks represent hardware that is contained in the ASIC, but not presently utilized...... 22
3.1 Block diagram of the basic version ASIC (from [3-4]) ...... 26
3.2 Neural preamplifier schematic (from [1]). Pin names and numbers match those of channel A of the basic 2-channel ASIC...... 27
v 3.3 Second-stage amplifier schematic. Component names and pin numbers match those used for recording channel A in the basic 2-channel schematic...... 28
3.4 Block diagram of MAX4544 multiplexer chip (from [50])...... 29
3.5 Schematic of the ADC and accompanying circuitry (from [2]). Pin names and numbers match those of the basic 2-channel ASIC...... 30
3.6 FSK transmitter schematic. Pin names and numbers match those of the basic 2- channel ASIC...... 31
3.7 Neural stimulator schematic (from [1]). Pin names and numbers match those of the basic 2-channel ASIC...... 33
3.8 OOK receiver schematic in the basic 2-channel device...... 35
3.9 An illustrative example of Manchester encoding (from [53])...... 36
3.10 Power management circuitry schematic. Pin names and numbers match those of the basic 2-channel ASIC. Dashed lines indicated hand-wired connections...... 44
3.11 Block diagram of the advanced 2-channel ASIC (from [3-6])...... 47
3.12 Compressed data transmission format (from [47])...... 54
3.13 Advanced prototype power management circuit schematic. Pin names and numbers match those of the advanced 2-channel ASIC...... 55
4.1 Fully assembled 2-channel implant device (top and bottom view). A penny is shown for comparison...... 58
4.2 Measured system clock waveform...... 59
4.3 Measured multiplexer turn-on waveform with inputs set to 0 V (channel A) and 2.61 V (channel B)...... 61
4.4 Measured multiplexer turn-off waveform with inputs set to 0 V (channel A) and 2.61 V (channel B)...... 61
4.5 Measured second-stage amplifier gain vs. frequency graph...... 62
4.6 Oscillation on command antenna while OOK receiver is idle...... 63
4.7 125-kHz OOK receiver interference on the ADC output (left) and the multiplexer output (right) while the receiver is idle. Multiplexer inputs are as in Figure 4.3 and 4.4...... 64
vi
4.8 Neural preamplifier gain vs. frequency graph...... 67
4.9 Measured analog-to-digital converter output for 60-Hz square-wave input...... 68
4.10 Test setup used to measure the resonant frequency of the FSK antenna...... 69
4.11 Measured frequency response of the un-tuned FSK antenna...... 69
4.12 Basic implant unit with tuning wire on transmission antenna...... 70
4.13 Measured VCO spectrum at resonance. A marker has been placed at the center frequency of 53.54 MHz...... 71
4.14 Data transmitter spectrum...... 72
4.15 Interleaved hyperpolarized stimulation with 300-μA amplitude pulses that are 2 ms wide being output at a frequency of 10 Hz...... 73
4.16 Interleaved depolarized stimulation with 100-μA amplitude pulses that are 5 ms wide being output at a frequency of 20 Hz...... 73
4.17 Basic 2-channel implant unit with dipole antenna...... 76
4.18 In vitro test setup...... 77
4.19 In vitro (a) wireless vs. (b) wired recording ...... 78
4.20 In vitro (a) wired vs. (b) wireless recording with digital values shown for wireless data...... 79
4.21 In vitro wireless recording, zoom view of action potential...... 79
4.22 (a) Hyperpolarized stimulation with small amplitude creating (b) artifacts on wired recording...... 80
4.23 (a) Hyperolarized stimulation with large amplitude creating (b) artifacts on wired recording...... 81
4.24 (a) Wireless vs. (b) wired recording during and after (c) hyperpolarized stimulation...... 82
4.25 (a) Wired recording over an extended time period during and after (b) hyperpolarized stimulation...... 83
vii 4.26 (a) Wired recording of artifacts from (b) depolarized stimulation, indicated amongst other action potentials generated by the stimulation...... 84
4.27 (a) Wireless vs. (b) wired recording during and after (c) depolarized stimulation...85
4.28 Wired recording over an extended period of time during and after depolarized stimulation...... 86
4.29 (a) Wireless vs. (b) wired recording with (c) depolarized then hyperpolarized stimulation...... 87
4.30 Immersion test setup...... 88
4.31 In vivo test setup...... 89
4.32 In vivo wireless recording. System gain is ~7950...... 90
4.33 In vivo wireless recording, zoom view of action potential...... 91
4.34 Fully assembled advanced 2-channel prototype (top view). A penny is shown for comparison...... 92
4.35 Integrated second-stage amplifier output response to test waveform...... 95
4.36 ADC output (top trace) with byte synchronization signal (Byte_Syn, bottom trace). ...96
4.37 ADC output (top trace) with bit synchronization signal (Bit_Syn, bottom trace)....96
4.38 Channel select signal (top trace) toggling on each high-to-low transition of the Byte_Syn signal (bottom trace) during interleaved recording...... 97
4.39 Advanced prototype VCO spectrum at resonance...... 98
A.1 Basic 2-channel implant schematic...... 105
B.1 Basic 2-channel implant PCB layout, top and bottom layer...... 106
B.2 Basic 2-channel implant PCB layout, top layer...... 107
B.3 Basic 2-channel implant PCB layout, bottom layer...... 108
C.1 Advanced 2-channel prototype schematic...... 109
D.1 Advanced 2-channel prototype PCB layout, silkscreen, top, and bottom layers....110
D.2 Advanced 2-channel prototype PCB layout, silkscreen layer...... 111
viii
D.3 Advanced 2-channel prototype PCB layout, top layer...... 112
D.4 Advanced 2-channel prototype PCB layout, bottom layer...... 113
ix Acknowledgements
I am extremely grateful to my thesis advisor, Dr. Steven L. Garverick, for the
opportunity to carry out this research. It has been an honor to work with such a
knowledgeable individual. I truly appreciate his guidance and patience throughout my
research. I would also like to thank Dr. Hillel J. Chiel for his leadership and continuous
input on the development of this work.
I am grateful to Paras Samsukha and Miranda Cullins, whom I worked very
closely with throughout my research. Paras was always available to answer all my
questions, and there certainly were a lot. Miranda worked tirelessly and patiently with
the two of us on our experiments. I would also like to thank Paras for his work in the
development of both the basic 2-channel ASIC and the enhanced 2-channel ASIC.
I am grateful to Steve Majerus and Ming-Hsuan Hsu, who developed the
telemetry circuitry and the second-stage amplifier and multiplexer circuitry of the
enhanced 2-channel ASIC, respectively. I would like to thank Dan Howe for developing
the GUI for our external transceiver. I would also like to thank the members of the
Mixed-Signal Integrated Circuits Group for their help and support throughout my
research.
I am forever grateful to my family for their love and support throughout my time at Case. I would also like to extend my deepest love and thanks to my wonderful fiancée,
Laura Juengst. She was always there to support me and has been my biggest fan. I could
not have done this without her by my side.
x Microcontroller-Based, Dual-Channel Wireless Neural Recorder/Stimulator
Abstract
by
CHRISTOPHER DORR
Two, dual-channel wireless neural recording and stimulation devices are
presented. The basic version has a neural preamplifier in series with a second amplifier
to provide a signal gain of 4000. A multiplexer selects the recording channel. An 8-bit
ADC converts the analog neural data into a digital stream, which is Manchester-encoded and frequency-shift-key (FSK) modulated at 27.12 MHz, before being transmitted to the host transceiver. The device receives 125-kHz on-off-keyed (OOK) commands, allowing the user to change record channels, program stimulation parameters, and trigger stimulus.
The electrical performance of the basic version has been measured and compared to theoretical results. In vitro and in vivo animal experiments are reported. A comparison of wired and wireless data is in good agreement. Commands are properly received.
The advanced version has additional integration, circuit revisions, and provides support for on-board digital data processing. Basic functionality of the advanced prototype has been verified.
xi 1. Introduction
Two versions of a multi-channel neural recording and stimulation system have
been developed. The systems have been developed specifically for use in neurodynamic
studies of the common sea slug, Aplysia californica, though they can be easily
customized for other applications. The embedded hardware of each device is based on an
application specific integrated circuit [1-6]. Schematics and printed circuit board layouts
have been created, and the fabricated boards have been assembled, tested in a lab
environment, and also used in animal tests.
1.1 Motivation
Researchers are continually gaining insight into the function of the nervous
system through the complex interaction of neurons, muscles, and other tissue. There is
much to be gained from the study of neural activity with implantable recording and
stimulation devices. A greater understanding of this interaction is not only clinically and
medically relevant, but it could also lead to improved neural simulators and to new circuit and algorithm design methods based on biological principles [7-8]. Studies of organisms with simpler nervous systems, such as Aplysia, can serve as a gateway to understanding more complex neural networks.
In addition to being a powerful learning tool, implantable neural recording and stimulation devices could have medical application. Functional neural stimulation can be used to assist patients in simple motor tasks, such as grasping and standing, and for other non-motor muscles, such as those involved in urination [9-12]. Such stimulation systems are also the basis for developing advanced prosthetic limbs for amputees [13-16] and for
1 neural prostheses for treating deafness [17-18] and blindness [19-20]. Long-term
recording of patient electroencephalography (EEG) data is being studied and used to
predict seizures in epileptic patients [21], and deep brain stimulation has been shown to
be successful in combating Parkinson’s disease [22-23].
1.2 Background
The common sea slug, Aplysia californica, pictured in Figure 1.1, is a saltwater
invertebrate that inhabits the coastal waters of California and northern Mexico [24]. The average adult sea slug grows to be about 10-15 inches in length. These creatures are herbivorous, feeding on red and brown seaweed. The sea slug moves by gliding on hard surfaces using its foot, which covers most of the underside of it body. It has two chemical sensors which protrude from its head and appear as antennae or rabbit ears. The mouth of the Aplysia is located at the front of its head. The animal can release a reddish- purple ink from a gland in the mantle cavity when it feels threatened.
Figure 1.1. Common sea slug, Aplysia californica.
2 Aplysia contain approximately 20,000 large and easily-identifiable neurons [25].
Neural action potentials in Aplysia range in amplitude from 10-300 µV at frequencies primarily between 100-500 Hz.
The relative simplicity of the Aplysia nervous system makes it fairly easy to
correlate specific neural activity to its behavior. Aplysia has shown a capacity for
distinguishing if a material is edible or not based on taste [26]. Researchers have even
been able to predict digestive or egestive feeding behavior from its neural activity alone
[27-28]. Other learning tasks, such as habituation, sensitization, and conditioning, have
also been demonstrated in Aplysia [24].
As a physical specimen, Aplysia provides a good model for neurodynamic studies
[29-31]. The large neurons of Aplysia are similar to human peripheral nerves in size and
behavior. Additionally, wireless transmission of data through a saline (saltwater)
environment is often used as a model for data transmission through human tissue, which
is a side benefit of Aplysia experimentation, considering that human peripheral nerves are
buried deep within the body.
The use of Aplysia in neurodynamic studies presents a host of challenges to
researchers. Most obvious is the need to operate electronic devices in a saltwater
environment. Special care must be taken to protect these devices from potential damage
and to ensure proper function. Testing should be non-invasive to the extent possible to
enable the animal to move freely and behave genuinely. This is not only important in
obtaining accurate data, but also because an annoyed animal will release ink and make
observation difficult to impossible. Data acquisition equipment must have low-noise
3 performance in view of the small amplitude of the action potentials, and care must be
taken to limit 60-Hz interference and other low-frequency noise.
1.2.1 Previous Work at CWRU
This work is a continuation of work in a joint effort between the departments of
Electrical Engineering and Computer Science, Biology, Neurosciences, and Biomedical
Engineering at CWRU. Chestek et al [32] designed a previous bio-compatible implantable neural recording unit for studies of Aplysia californica. The device is pictured in Figure 1.2.
Figure 1.2. Wireless recording unit (from [32]).
This device was capable of neural recording on as many as 8 channels, but
channel change required more than one second. Data was acquired with high-
performance, low-power, low-noise preamplifiers [33]. They were packaged in an
application specific integrated circuit (ASIC) with an 8-channel multiplexer provided by
4 Professor R. Harrison of the University of Utah. The multiplexer was controlled using a
PIC18F1320 microcontroller, which could select between sampling a single channel of data or a pre-programmed subset of the 8 channels, although the band pass amplifiers required very large settling times when switching from channel to channel. The microcontroller mode was determined by the position of a contactless magnetic reed switch. The system had a measured noise of 2.8 µVrms and experienced a DC drift up to
260 µV.
Neural data was digitized in the microcontroller’s 8-bit analog-to-digital converter. Twelve frame alignment bits were grouped with a 4-bit channel number to form a frame alignment word (FAW), which was added to the end of each sample and used to align the data in the host transceiver.
Digitized data was transmitted to a host transceiver using 27.12-MHz frequency- shift keyed (FSK) telemetry at a 5-kbps bit rate. The FSK telemetry was provided using a commercially available integrated circuit, the Tricome T86. The telemetry utilized an
8- cm electric dipole antenna made from 26-gauge copper wire. The antenna was matched to 50 Ω by exposing the ends of the antenna wires to the saltwater. Wireless data could be transmitted through a maximum of 18 cm of saltwater.
Digitized data could also be transmitted via a wired RS-232 interface. RS-232 encoding was done within the microcontroller and could be sent from of the microcontroller’s RS-232 port to a PC. This interface was used to operate the unit without the host transceiver and aided in debugging the host transceiver during its initial development.
5 The unit was powered by a 3-V lithium ion battery (160 mAh) which provided 16 hours of recording. The FSK transmitter consumed the most power of the components at
30 mW. The microcontroller consumed 450 µW of power.
The CWRU effort was continued by Samsukha, et al, who developed a new ASIC and an early version of the implantable device described here, as detailed in Chapter 2.
1.2.2 Other Related Work
Considerable research and development has been devoted to implantable neural devices. Key issues include improved component integration, reduced device size, reduced power consumption, reduced system noise, and increased wireless data throughput.
Researchers at the University of California in Los Angeles have designed a multi- channel neural recording system based on the TinyOS-based MICA2DOT mote [34-35].
The device schematic is pictured in Figure 1.3, and the device itself is pictured in Figure
1.4. The MICA2DOT mote is commercially available from Crossbow Technologies, Inc.
It is an all-inclusive sensor device that possesses sensing, communication, and data processing capabilities. The MICA2DOT mote is interfaced with a custom discrete neural preamplifier circuit consisting of an OPA234, manufactured by Texas Instruments, an AD627 instrumentation amplifier, manufactured by Analog Devices, and a few additional passive components per channel. The MICA2DOT mote transmits wireless data to a MIB510 gateway, which is also commercially available from Crossbow
Technology Inc. This gateway receives and relays neural data and commands to a client
PC via an RS-232 serial connection. The MICA2 system operates with custom developed software for signal acquisition, data transmission, data archiving, and hosting.
6
Figure 1.3. TinyOS-based neural recording unit developed at UCLA (from [34]).
Figure 1.4. TinyOS-based neural recording unit schematic (from [34]).
The system is capable of amplifying, sampling, transmitting, and reconstructing input neural signals at a rate of 1,200 8-bit samples per second. This data rate allows for the reliable transmission of up to 6 EEG data channels with a sampling rate of 200 Hz per channel. The device can measure signals ranging from 0.06-15 mV and transmit at a
7 distance of up to 9 meters. It consumes less than 66 mW of power from a 3-V supply.
The device measures 2.5 cm x 2.5 cm x 1 cm in size.
Researchers at North Carolina State University have developed a 15-channel wireless implantable neural recording (WINeR) system based on time division multiplexing of pulse width modulated signals [36-37]. The PWM technique provides three benefits: lower power consumption, improve noise performance, and reduce system complexity by eliminating the need for an ADC and its associated circuitry. The WINeR system is based on a 3-mm by 3-mm application specific integrated circuit shown in
Figure 1.5. The chip was fabricated in the MOSIS AMI 3M3P n-well standard CMOS process.
The WINeR ASIC contains 15 low-noise amplifier/filters (one dedicated to each channel), a time division multiplexer (for channel switching), a sample-and-hold pulse width modulator (PWM), an on-chip clock generator, a 32-bit register for control commands, a voltage-controlled oscillator (VCO) transmitter, a reference generator, and inductive power management circuitry.
8
Figure 1.5. 15-channel wireless neural recording chip block diagram, developed at NCSU (from [36]).
The chip can measure neural signals between greater than 500 µV in amplitude at
a frequency range of 0.1 Hz to 10 kHz. It can acquire and wirelessly transmit up to 20
ksps to an external receiver with 75-MHz bandwidth at 8-bit resolution using a carrier frequency of 400 MHz and FSK modulation. The chip consumes 1.5 mA when supplied at ±1.5 V.
Researchers at the University of Utah have developed a wireless 100-electrode neural recording system for cortex measurements [38-39]. The neural recording system is depicted in Figure 1.6 and a block diagram of the system is shown in Figure 1.7.
9
Figure 1.6. Complete integrated neural interface assembly, developed at University of Utah (from [38]).
Figure 1.7. Integrated neural interface block diagram, developed at University of Utah (from [38]).
10
The system is based on a 4.7-mm by 5.9-mm ASIC fabricated using the 0.5-µm
3M2P CMOS process. The chip fits onto a PCB with a 10-by-10 fixed electrode grid,
through which neural data is acquired from the cortex of a subject. Twelve of the
electrodes serve as references. The chip contains dedicated amplifiers for each channel, a
multiplexer for selecting channels, a low-power 10-bit ADC, a 433-MHz FSK data
transmitter, a voltage regulator, and a 2.64-MHz amplitude-shift keyed (ASK) link for
receiving power and commands. The system also contains spike detection and data
compression circuitry to support such a large number of channels.
The system is capable of measuring neural signals between greater than 500 µV in magnitude. It consumes 13.5 mW of power from a minimum supply voltage of 3.55 V.
Commands can be sent to the device at a data rate of 6.5 kbps, and neural data can be transmitted from the device at a rate of 330 kbps.
Researchers at the University of Michigan have developed separate ASICs for wireless neural recording and wireless neural stimulation devices [40-43]. A block diagram of the wireless neural recording system is shown in Figure 1.8. The system is based on the NPU-32 (neural processing unit), a block diagram of which is shown in
Figure 1.9. The NPU-32 processor was fabricated using the AMI 0.5-µm 3M2P standard n-well CMOS process. The die size measures 3.5 mm by 2.7 mm.
11
Figure 1.8. Block diagram of neural recoding system developed at the University of Michigan (from [40]).
Figure 1.9. Block diagram of the NPU-32, developed at the University of Michigan (from [40]).
12 The NPU-32 neural processing units use a modular design style. The processor
itself is made up of four smaller SD-8 signal processing modules grouped together. Two
NPU-32 processors can be joined in a master-slave configuration for a maximum of up to
64 channels of data acquisition.
The NPU-32 has two different modes of operation, scan mode and monitor mode.
In scan mode, the processor scans all 32 channels waiting to detect a spike, which is then
recorded, tagged with a channel number, and sent serially to the wireless data transmitter.
In monitor mode, the processor records all neural data from two selected channels and
sends either the analog data or 8-bit digital data to the wireless data transmitter.
The NPU-32 processor consumes 197 µW of power per channel at a supply of
1.8V. It operates from a 2-MHz system clock. The processor has a channel scan rate of
62.5 ksps and an output bit rate of 2 Mbps. The sample rate per channel is 7.8 ksps.
The wireless neural stimulation system from the University of Michigan is based on the Interstim-2B, a block diagram of which is shown in Figure 1.10. It was designed for cortex stimulation to help combat blindness, deafness, and severe epilepsy. The
Interstim-2B was fabricated in the MOSIS 1.5-µm 2M2P standard CMOS process. The die size is 4.6 mm by 4.6 mm.
13
Figure 1.10. Block diagram of the Interstim-2B, developed at the University of Michigan (from [42]).
The Interstim-2B also uses a modular design. Each chip can support up to 32 stimulation sites, and as many as 64 of these chips can be connected in parallel to a single
5/10-MHz FSK command and power link, providing a maximum of 2,048 stimulation sites.
The stimulation patterns are customizable through the command link. Stimulation amplitude can be set to ±270 µA with 5-bit resolution, and timing can be set with a resolution of 7.6 µs. The chip provides 8 different stimulation styles, e.g. rail-to-rail swings, rail-to-bias swings, etc. At full capacity, the chip can deliver 65,800 stimulation pulses per second.
Each stimulation module consumes 8.25 mW of power from a 5-V supply.
Command data is sent at a data rate of 2.5 Mbps.
14 1.3 Objectives
This work features the development of two versions of a wireless neural recording and stimulation device which aim to improve on previous technology developed at
CWRU. A basic version and an advanced version were developed with the following goals in mind.
1. Provide two channels of neural data recording and neural stimulus.
2. Establish a command protocol to allow the user to select the channels to record
from, including simultaneous readout from both channels, and customize
stimulation patterns.
3. Implement the command interpreter within the microcontroller.
4. Improve the wireless transmission distance and data rate.
5. Improve the noise performance.
6. Decrease the overall power consumption.
7. Reduce the physical size.
The following goals were set specifically for the advanced device in addition to the above requirements.
8. Implement neural data processing, including data compression and spike detection
within the microcontroller.
9. Improve the blanking operation during multiplexed stimulation and recording.
10. Reduce size further using an ASIC with increased integration of functionality.
15 2. Architecture for Wireless Neural Recording and Stimulation
Two versions of a dual-channel wireless neural recording and stimulus system are
outlined in this chapter, a basic version and an advanced version. The advanced version
provides additional features not included in the basic version, such as neural spike
detection and data compression. More importantly, though, the advanced version uses
fewer components than the basic version, since the advanced version is based upon a later
generation application specific integrated circuit (ASIC). The detailed hardware differences are explored in Chapter 3.
2.1 Basic Version
A block diagram of the implantable device is shown in Figure 2.1. This basic
version, originally prototyped by Samsukha and Garverick [1-4], provides two channels
that can be used for neural recording or neural stimulus. All system commands are
executed within the microcontroller. The system is completely wireless and has separate
communication interfaces for transmitting recorded neural data and receiving recording
and stimulus commands and parameters. The system uses a battery for powering.
16
Figure 2.1. Block diagram of the basic version. Shaded blocks represent hardware external to the ASIC (from [3-4]).
2.1.1 Neural Recording
The basic version provides two recording channels, allowing for neural data to be measured from two different neurons. Differential electrodes, consisting of a pair of insulated stainless steel wires with exposed ends, are glued directly to the neurons [44] and measure action potentials in the range of 1-330 µV, more than adequate for neurodynamic studies of Aplysia. Data is continuously read from both channels, except during stimulation. This neural data is multiplexed according to the desired record setting: record from channel A or record from channel B. The desired data is digitized and sent to the data transmitter.
17 2.1.2 Data Transmission
Digitized neural data is modulated and transmitted wirelessly using frequency-
shift keying (FSK) at 27.12 MHz. This is an industrial, scientific, and medical (ISM)
radio frequency band, and use of this band by a medically implantable device for neural
data transmission is permitted by FCC regulations. FSK modulation utilizes discrete
changes in the frequency of the carrier wave to transmit binary 1’s and 0’s [45], as
illustrated in Figure 2.2.
Figure 2.2. An illustrative example of frequency-shift keying modulation (from [45]).
The bandwidth of this ISM channel is 326 kHz, meaning that the mark (“1”) and space (“0”) spectrums must fit within an antenna bandwidth of 326 kHz centered at 27.12
MHz. We have designed for a nominal frequency deviation of 160 kHz, which allows
18 non-overlapping main lobes of ±80 kHz within a total bandwidth of 320 kHz. This design supports a maximum bit rate of 80 kbps.
2.1.3 Neural Stimulus
The basic version provides the ability to stimulate neurons on both of its recording channels. The user can stimulate on channel A only, channel B only, or interleaved on both channels. Stimulus is manually triggered using a command sent from the host transceiver. Recording on a given channel is disabled (blanked) during its stimulation. Stimulus consists of series of electrical current pulses. The pulses are generated by momentarily creating a potential difference across the two exposed ends of the recording electrodes attached to the neurons.
The stimulus patterns are customizable and were chosen specifically for neurodynamic studies of Aplysia, but they can be easily modified to suit other applications.. Parameters can be selected from a list [3-4] stored in the on-board microcontroller. The amplitude, duration, and polarity of the electrical current pulses can be adjusted, as well as the frequency and number of pulses generated in a stimulus pattern, and the delay from trigger to stimulus. During interleaved stimulation, both channels will output the same pulse pattern.
The amplitude of electrical current pulses can range from 0-300 µA and can be adjusted in 100 µA increments, and the polarity of this current can be set as hyperpolarizing (source) or depolarizing (sink). The pulse duration can range from 500
µs - 8 ms and can be adjusted in 500 µs increments. Current pulses can be generated at frequencies ranging from 2.5-20 Hz, adjusted in 2.5 Hz increments. A single pattern may contain 1 or 5-35 pulses, adjustable in multiples of five. A 0-30 ms pattern delay,
19 adjustable in 10 ms increments, can be added between when stimulus is triggered and current pulses are actually generated.
2.1.4 Command Reception
Stimulus/record commands and parameters are modulated and sent to the system from a host transceiver using On-Off Keying (OOK) at 125 kHz. OOK modulation uses the presence or absence of a carrier wave to transmit binary 1’s and 0’s [46], as illustrated in Figure 2.3. Following demodulation, received bits are sent to the on-board microcontroller for command decoding.
Figure 2.3. An illustrative example of on-off keying modulation (after [45]).
2.1.5 Control
All control functions are handled by the microcontroller, which decodes all the
OOK commands received by the system and sets the necessary internal parameters. The
20 record channel, stimulus channel, and stimulus pattern parameters are stored within the
microcontroller, which provides the necessary control signals to the rest of the system. It
also provides the 500-kHz system clock. The microcontroller is field programmable so
new commands and features may be added after assembly. This also allows the stimulus
parameter values to be modified for applications other than neurodynamic studies of
Aplysia.
2.1.6 Power
The system requires a battery for power, which is regulated down to 2.7 V to be
used by the components of the system. A latching magnetic reed switch is used to turn
the system on and off in a non-contact manner, e.g. across the transcutaneous boundary
of the animal.
2.2 Advanced Version
The block diagram of the advanced version is shown in Figure 2.4. As before, the advanced version provides two channels that can be used for neural recording or neural stimulus, all system commands are executed within the microcontroller, and the system is completely wireless with separate communication interfaces for transmitting recorded neural data and receiving stimulus/record commands and parameters. In the advanced version, however, neural data is processed by the microcontroller before being transmitted. The advanced version also requires a battery for powering.
21
Figure 2.4. Block diagram of advanced version. Lightly shaded blocks represent hardware external to the ASIC. Darkly shaded blocks represent hardware that is contained in the ASIC, but not presently utilized.
2.2.1 Neural Recording
The advanced version provides two recording channels, as in the basic version, but 1) the advanced version can record interleaved neural data from both channels and 2) neural data is processed in the microcontroller prior to transmission.
2.2.2 Data Transmission
Data communication employs the same 27.12-MHz FSK technique, bandwidth, and bit rate described previously.
22 2.2.3 Neural Stimulus
The neural stimulus capability of the advanced version is identical to the basic
version, with one exception. The stimulus pulse amplitude in this version can range from
0-350 µA and can be adjusted in 50 µA increments.
2.2.4 Command Reception
The advanced version of the ASIC has a prototype OOK receiver with integrated
sleep mode circuitry. These circuits do not function properly on the ASIC that is
presently available and, are therefore not used.
2.2.5 Control
In the advanced version, the microcontroller intercepts and processes neural data,
identifying spikes in the neural data and providing data compression using code provided
by Hsu [47]. The processed data is relayed to the FSK data transmitter. The spike
detection algorithm enables advanced functions such as “trigger stimulus on spike detect”
and other modes in which the implant responds to neural activity. The data compression
algorithm will enable future channel counts as high as 64 within the constraint of 80 kbps
communication [47].
2.2.6 Power
The advanced version of the ASIC contains prototype circuits to implement a
system sleep mode. The latching magnetic switch is sufficient for work with Aplysia, but for applications where deep implantation is required, direct access to the system will be even more limited, negating the usefulness of the magnetic switch. Instead, these
prototype circuits would allow the user to send an OOK sleep command to the system,
23 which the prototype OOK receiver would decode. The receiver would then send a control signal disengaging the main voltage regulator to shut off all other system components.
The prototype OOK receiver is powered from a secondary voltage regulator which never shuts off, but since the OOK receiver draws very little power, battery life will be very long, even though the receiver always remains on.
Unfortunately, these circuits do not function properly on the presently available
ASIC and were not used, but will be incorporated in a future version of the wireless neural recording and stimulus system.
24 3. Detailed Design of the Implantable Neural Recording and Stimulation Device
Two wireless neural recording and stimulation devices were created based on the architectures outlined in Chapter 2. A basic version has been developed for implantation.
An advanced version was implemented on a larger, development board. The advanced version utilizes an enhanced 2-channel ASIC containing several previously untested prototype circuits.
3.1 Basic Implant Device
The basic implant device consists of five integrated circuits (IC’s): the microcontroller, an application specific integrated circuit (ASIC), a multiplexer, a dual operational-amplifier, and an OOK receiver, as well as several passive components.
With the exception of the ASIC, all the IC’s are off-the-shelf (OTS) components.
A block diagram of the ASIC [3-4] is shown is Figure 3.1. It contains biasing circuitry, the neural preamplifiers, the analog-to-digital converter, the voltage-controlled oscillator, the FSK transmitter, and the neural stimulators. The following sections provide a closer examination of the individual circuits and components used in the basic implant device, on and off the ASIC.
25
Figure 3.1. Block diagram of the basic 2-channel ASIC (from [3-4]).
3.1.1 Neural Amplifiers
When neural data is acquired via the device electrodes, it is passed through a cascade of two differential amplifiers. Each recording channel has an identical set of neural amplifiers. These amplifiers provide a total signal gain of 4000, which magnifies
the small signals from the nerve cells to full rail-to-rail voltage levels (0-2.7 V). The
amplifiers have very low input-referred noise to prevent corruption of the neural signals.
3.1.1.1 Neural Preamplifier
The neural preamplifier is part of the 2-channel ASIC [1]. A simplified schematic
of the preamplifier is shown in Figure 3.2.
26
Figure 3.2. Neural preamplifier schematic (from [1]). Pin names and numbers match those of channel A of the basic 2-channel ASIC.
The positive terminal of the amplifier is the reference terminal and is biased to the common mode level of 1.2 V, i.e. the voltage swing of the recordings is maximized by setting the DC-voltage level between the supply rails. The ratio C1/C2 internally sets the passband gain of the preamplifier to -100. The gain is negative, because the amplifier is in the inverting configuration. The capacitive input C1 blocks the DC drift common in biological recording in a saline environment. The parallel combination of the small signal resistance of M1-M2 and the feedback capacitance of C2 set the low-frequency cutoff below 1 Hz. The amplifier transconductance and load capacitance determine the high-frequency cutoff, which is about 100 kHz.
3.1.1.2 Second-Stage Amplifier
A second stage of amplification is provided by the TLV2382, an OTS opamp manufactured by Texas Instruments, as shown in Figure 3.3.
27
Figure 3.3. Second-stage amplifier schematic. Component names and pin numbers match those used for recording channel A in the basic 2-channel schematic.
The pseudo differential outputs of the neural preamplifiers are supplied to the input of the second stage. The positive input of the amplifiers is the reference terminal and is biased at biased same 1.2-V level used by the neural preamplifiers. The off-chip capacitor ratio
CC11/CCf1 sets the passband gain of the amplifiers to -40. The gain is negative, because the amplifiers are inverting.
The parallel feedback resistance and capacitance set the low-frequency cutoff at
100 Hz based on Equation 3.1.
1 fl = (3.1) 2π CR ff 11
The 40-nF input capacitance and 1st-stage output resistance set the high-frequency cutoff to 4 kHz.
The TLV2382 is a dual, micropower, rail-to-rail (input and output), operational amplifier [48]. Each of its operational amplifiers is devoted to a single channel of neural data. The second-stage amplifiers have an input referred noise of about 90 nV/√Hz, which yields an in-band noise far below the level of the neural signals. Each amplifier
28 draws at most 7 µA of supply current, meaning the TLV2382 consumes at most 37.8 µW
of power. The 8-pin SOIC version of the part is used.
3.1.2 Multiplexer
The two channels of neural data are multiplexed using the MAX4544, an OTS component manufactured by MAXIM Integrated Circuits, as illustrated in Figure 3.4.
Figure 3.4. Block diagram of MAX4544 multiplexer chip (from [49]).
The amplified channel A neural data is connected to the normally-closed (NC) pin of the
multiplexer, and the amplified channel B neural data is connected to the normally-open
(NO) pin. The selection input (IN) is connected to the microcontroller and is operated
based on the logic in Table 3-1.
Table 3-1. MAX4544 logic table (from [49]).
The MAX4544 is a low-voltage, single-supply, 2-to-1 multiplexer [49]. The multiplexer
is fast switching, with a turn-on time typically around 80 ns and a turn-off time typically
29 around 50ns. It uses very little power, consuming less than 5 µW. The 6-pin SOT23
package of the chip is used.
3.1.3 Analog-to-Digital Converter
The analog-to-digital converter (ADC) and its accompanying circuitry are part of
the 2-channel ASIC [2]. The ADC schematic is shown in Figure 3.5.
Figure 3.5. Schematic of the ADC and accompanying circuitry (from [2]). Pin names and numbers match those of the basic 2-channel ASIC.
Multiplexed neural data is passed through the ADC circuitry to produce a 1-bit
serial data stream. The ADC uses a switched-capacitor, 1st-order Σ-Δ architecture to produce a digital output. A decimation filter is included to remove the out-of-band noise and reduce the bit rate. From the decimation filter, the data is passed to a parallel-to- serial converter, where it is serialized. Alternate samples are discarded and replaced with a header containing frame alignment bits “10101” and a 3-bit channel number, which is not used in this design. The serialized data is passed to the voltage-controlled oscillator
(VCO) and the FSK transmitter, and the header is used for clock recovery in the host
transceiver.
The ADC provides an effective resolution of about 8 bits using a sampling rate of
500 kHz (system clock rate) and an oversampling rate of 64, i.e. output sample rate is about 7.8 ksps. Since the serial-to-parallel converter discards alternate samples to insert
30 the header, the transmitted sample rate is only 3.9 ksps. Each channel will have a sample
rate of 1.95 ksps during interleaved recording.
3.1.4 FSK Transmitter
The FSK transmitter is part of the 2-channel ASIC [1-2]. The transmitter
schematic is shown in Figure 3.6. Serialized data from the ADC is passed to the FSK
transmitter, from which it is transmitted to the host transceiver.
Figure 3.6. FSK transmitter schematic. Pin names and numbers match those of the basic 2-channel ASIC.
The carrier wave for the FSK transmitter is generated by a voltage-controlled
oscillator (VCO). The VCO requires an off-chip inductor and capacitor to set the
oscillation frequency, as per Equation 3.2.
1 f = (3.2) O 2π LC
The VCO frequency must be set at twice the transmission frequency, since an internal clock divider is used to in sure a 50% duty cycle. Thus, to achieve the desired 27.12-
MHz transmission frequency, the oscillator must be tuned to 54.24 MHz. For an oscillation frequency of 54.24 MHz, an inductance of 220 nH and a capacitance of 39 pF were chosen.
31 An off-chip resistor that is connected to the regulator output sets the bias current of the VCO. A value of 270 kΩ was chosen so as to provide 10 µA of bias current. This guarantees that the VCO will consume very little power (around 27 µW).
The serialized output from the ADC is passed into the FSK modulator for modulation by the carrier waveform, and then the modulated data is then sent to the antenna driver. The antenna driver consists of two CMOS inverters with output coupling capacitors that form capacitive dividers when combined with PCB parasitics. The capacitive dividers are coupled to the 10-µH inductive antenna (Q=69) which is resonant at 27.12 MHz, and the CMOS inverters provide the necessary complementary FSK outputs for driving the antenna. The capacitive dividers have been set to deliver roughly
1 mW from the 2.7 V supply into the 27.12-MHz frequency band. The inverters were sized to minimize power losses through on-resistance and output parasitic capacitance.
3.1.5 Neural Stimulator
The neural stimulators are part of the 2-channel ASIC [1]. The schematic is shown in Figure 3.7. Each channel of the device has an identical neural stimulator.
32
Figure 3.7. Neural stimulator schematic (from [1]). Pin names and numbers match those of the basic 2-channel ASIC.
The reference currents for the neural stimulators are generated using off-chip bias resistors, R_Ref0 and R_Ref1 (for channels A and B respectively). Each current reference is mirrored and magnified by 0x to 7x, and these current mirrors are connected to a digital logic block with 3-bit control (ICt2-ICt0) provided by the microcontroller. A value of 30 kΩ was chosen for the off-chip bias resistors, and when combined with the internal voltage drop of the current mirrors, a reference current of 50 μA is generated. If all three mirrors are engaged, the reference current can be magnified a maximum of 7x.
Therefore, the maximum output current of the device is 350 μA. In this basic design, the least significant bit, ICt0, was tied to ground, so the output current can only be adjusted in 100-μA increments.
The digital logic block of each channel is enabled or disabled using the Chan signal. This signal is provided by the microcontroller and is used for channel selection.
33 When the Chan signal is high, channel A is enabled, and channel B is disabled. When the
Chan signal is low, channel A is disabled, and channel B is enabled.
The polarity of the output current can be toggled using the Pos signal. The Pos
signal is provided by the microcontroller and controls a switch that can internally swap
the connections to the differential electrodes. When the Pos signal is high, the polarity is
set to depolarizing or current sinking from E0M, and when the Pos signal is low, the
polarity is set to hyperpolarizing or current sourcing from E0M.
The actual outputting of current is timed by the Stim signal, provided by the microcontroller. Through the use of a transmission gate switch, the Stim signal simultaneously enables output current while disconnecting the preamplifier on the selected channel, to prevent saturation of the preamplifiers. The microcontroller toggles the Stim signal to produce the proper pattern based upon the user selected trigger method, current pulse width, pulse frequency, number of pulses, and delay before stimulation.
3.1.6 OOK Receiver
The reception of recording and stimulation commands and parameters is handled by the MLX90109, an off-the-shelf IC manufactured by Melexis [50], as shown in Figure
3.8. The OOK receiver utilizes the MLX90125, a 73.7-μH, 52-turn, 17-mm, inductive antenna manufactured by Melexis specifically for use with the MLX90109 [51]. The
MLX90125 has a quality factor of 25. Coupled with a 22-nF capacitor, the reception
frequency is set at 125 kHz as per Equation 3.2.
34
Figure 3.8. OOK receiver schematic in the basic 2-channel device.
The MLX90109 is a 125-kHz RFID transceiver designed for minimum system cost and minimum power consumption. The 8-pin SOIC version of the part is used.
The MLX90109 receives Manchester-encoded, OOK-modulated commands and parameters from the host transceiver and decodes them, as illustrated in Figure 3.9. In
Manchester coding, each bit of data is represented with a fixed time window and at least one transition, so that it is self-clocking [52]. A binary “1” is represented by a low-to- high transition, and a binary “0” is represented by a high-to-low transition.
35
Figure 3.9. An illustrative example of Manchester encoding (from [52]).
The MODE pin of the MLX90109 is connected to VDD to set the receiver to internally decode Manchester data, and the SPEED pin is connected to VDD to set the data decoding speed to 2 kbps. The decoded commands and parameters are sent to the microcontroller via a 2-wire serial interface, consisting of a CLOCK signal and a DATA signal. The CLOCK and DATA outputs of the MLX90109 are open drain outputs, so they require 100-kΩ pull-up resistors.
The MODU pin of the MLX90109 is used to adjust the lower limit of the antenna voltage (COIL pin). The antenna voltage amplitude, Vant, is determined by Equation
3.3, where VDD is 2.7 V and Vot is roughly 300 mV.
Vant = VDD – VMODU + Vot (3.3)
The MODU pin is connected to the microcontroller through a resistive divider. When the microcontroller outputs a high voltage to the MODU pin, the antenna voltage amplitude is 1.3 V, as per Equation 3.3. During normal operation, VMODU is always kept high by the microcontroller, keeping the MLX90109 powered-on.
The MLX90109 is designed for receiving ASK (amplitude-shift-key) modulated commands and to operate as an OOK transmitter using this MODU pin as the serial data input. The transmission capability of the MLX90109 is the reason the receiver is
36 intended to oscillate when in idle mode. This method of operation allows the MLX90109 to run at low power levels.
3.1.7 Microcontroller
The microcontroller used in the basic 2-channel device is the PIC18F1320 manufactured by Microchip Technology Inc. The PIC18F1320 is a high performance, enhanced Flash MCU with 10-bit A/D and nanoWatt technology [53]. It operates at a frequency of 8 MHz, generated by an internal oscillator. It has two I/O ports, 8192 bytes of program memory, 256 bytes of SRAM data memory, and 256 bytes of EEPROM data memory.
Table 3-2 summarizes the microcontroller pin numbers, signal names, I/O usage, and their functions. The microcontroller can be programmed in-circuit via a 5-pin header using the MPLAB® ICD 2 [54]. The 20-pin SSOP version of the part is used. This package of the PIC18F1320 has separate connections for analog and digital power and analog and digital ground for better noise performance.
37 Signal Pin Name μC Usage Used With Function Signal for adjusting voltage across OOK 1 Vmod Output OOK Receiver receiver antenna 2 Sel Output Multiplexer Selects recording channel Neural 3 Pos Output Stimulator Selects stimulus polarity 4 MCLR System Microcontroller Master reset, for programming 5 DVSS System Microcontroller Digital ground 6 AVSS System Microcontroller Analog ground FSK Processed data output to FSK transmitter, 7 VCO Output Transmitter bypassed on this device 8 Data Input OOK Receiver Data signal from OOK receiver 9
Table 3-2. Microcontroller input/output table.
3.1.7.1 Microcontroller Programming Pins and Clock
The microcontroller has three pins that are used for in-circuit programming, each connected to the programming header. (The remaining two pins of the 5-pin programming header are connected to power and ground.)
The MCLR pin serves as the master reset. It is held low by the MPLAB® ICD during programming. The MCLR pin is held high during normal operation using a 1-kΩ pull-up resistor.
38 The PGC and PGD pins are the programming clock and data pins, respectively.
They form a two-wire serial interface for writing to the microcontroller’s program memory. The programming interface is only enabled when the master reset is low.
During normal operation, these pins are used for amplitude control of the neural stimulator.
The microcontroller provides a 500-kHz system clock, Clk_slug, to the ASIC.
Outputs from the ASIC are synchronized to the clock.
3.1.7.2 OOK Receiver Command Interpretation
The microcontroller receives commands from the OOK receiver using a serial interface consisting of the CClk and Data pins. The commands arrive in the form of packets and are then interpreted before the appropriate control signals are sent to the rest of the components.
The command packets are organized by the host transceiver in the format shown in Table 3-3 [3-4, 55].
Number of Command Command Tone Preamble Bytes Codes Data
Table 3-3. Command packet format (from [3-4, 55]).
The tone consists of all 1’s followed by the sequence 1010. The preamble consists of six bytes of 0x46h, followed by two additional bytes of 0x69h and 0x96h, respectively. This identifies the packet as a command packet and is also used for synchronization. The third section of the packet contains the number of remaining bytes to be sent. This value is the sum of both the command code bytes and the command data bytes which are contained in the next section of the packet. Each command has a unique identifying code. In the case
39 of multiple commands, command code bytes and data bytes are alternated during
transmission.
The basic 2-channel device supports three different commands: Trigger &
Channel Set (T&C), Stimulation Parameter 1 (SP1), and Stimulation Parameter 2 (SP2).
They are identified by the command codes 0x12h, 0x21h, and 0x52h, respectively [3-4,
55].
The T&C command is used to select the channels for stimulation and recording,
and the trigger mode for stimulus. The T&C command bits are organized as shown in
Table 3-4 [3-4, 56]. The functionality of the T&C command bits is summarized in Table
3-5. The last two bits are not used.
Trig1 Trig0 RA RB SA SB x X
Table 3-4. Trigger & Channel Set command data bits (from [3-4, 56]).
The first two bits, Trig0-Trig1, set the trigger mode for stimulus. When both bits are low, the trigger mode is single, and the unit will only stimulate the appropriate channels when the device receives a T&C command. If both bits are high, the trigger mode is continuous, and the device will continually output stimulus current patterns until another T&C command changes the trigger mode back to single. The device defaults to single mode.
The RA and RB bits are used to set which channels from which to record. When the RA bit is high, recording on channel A is enabled. When the RB bit is high, recording on channel B is enabled. When both bits are high or both bits are low, the
command is ignored. The unit will continually record from at least one channel unless it
40 is stimulating on both channels in continuous mode, blanking out both preamplifiers.
The device defaults to recording from channel B.
The SA and SB bits are used to select which channels to stimulate. When the SA bit is high, stimulation on channel A is enabled. When the SB bit is high, stimulation on channel B is enabled. When both bits are high, interleaved stimulation on both channels is enabled. When both bits are low, neither channel will stimulate. The device defaults to stimulating on channel A.
Trigger & Channel Set commands are summarized in Table 3-5. “No implemented” means that the codes are ignored if received.
Trigger & Channel Set Trigger Record Stimulate Trig1 Trig0 RA RB SA SB
Continuous Not Implemented A,B
1 1 1 1 1 1
Not implemented A A
1 0 1 0 1 0
Not implemented B B
0 1 0 1 0 1
Single Not Implemented None
0 0 0 0 0 0
Table 3-5. Summary of T&C command data bit functions.
The SP1 command is used to set the amplitude, polarity, and pulse width of the stimulation current pulses. The SP1 command bits are organized as shown in Table 3-6
[3-4, 56].
A2 A1 x Polarity PW3 PW2 PW1 PW0
Table 3-6. Stimulation Parameter 1 command data bits (from [3-4, 56]).
41 The first two bits, A2-A1, are used to control the amplitude of the stimulus
current. The amplitude can range from 0-300 μA, adjusted in 100-μA increments using
A2 and A1. A1 is the least significant bit in this design. (The “x” bit adjacent to A1 is
reserved for future use as a 50-μA LSB, which hardware did not permit in this version.)
The stimulus amplitude defaults to zero.
The Polarity bit is used to set the polarity of the stimulus current. When the
polarity bit is low, the stimulus current is set to hyperpolarizing or source current. When
the polarity bit is high, the stimulus current is set to depolarizing or sink current. The
polarity defaults to hyperpolarizing.
The PW3-PW0 bits are used to set the pulse width of the current pulses in the
stimulus patterns. The pulse width can range from 500 μs to 8 ms, adjusted in 500 μs
increments using PW3-PW0. PW0 is the least significant bit. The pulse width defaults
to 500 μs.
The SP2 command is used to select the number and frequency of pulses per
stimulus and the delay after trigger of stimulation. The SP2 command bits are organized
as shown in Table 3-7 [3-4, 56].
NP2 NP1 NP0 FS2 FS1 FS0 DT1 DT0
Table 3-7. Stimulation Parameter 2 command data bits (from [3-4, 56]).
The first three bits, NP2-NP0, are used to set the number of current pulses per
stimulus pattern. The number of pulses ranges from 1-35 pulses, adjusted in multiples of five using NP2-NP0, where NP0 is the least significant bit. The zero case outputs one pulse instead of no pulses. The number of pulses defaults to 20.
42 The FS2-FS0 bits are used to set the output frequency of current pulses in a
stimulus pattern. The frequency of pulses ranges from 2.5-20 Hz, adjusted in 2.5 Hz
increments using FS2-FS0. The pulse output frequency defaults to 20 Hz.
The DT1 and DT0 bits are used to set the delay after trigger of stimulus patterns.
In continuous mode, this serves as the delay between successive stimulus patterns. The
delay after trigger ranges from 0-30 ms, adjusted in 10 ms increments using DT1 and
DT0. DT0 is the least significant bit. The delay after trigger defaults to zero.
3.1.7.3 Neural Stimulator Control
The microcontroller provides the control signals needed to operate the neural
stimulator, using the I/O indicated in Table 3-2.
The StimChan output is used to select the stimulation channel using the “Chan”
input of the ASIC, as per Figure 3.7. When StimChan is high, channel A is selected for
stimulation. When StimChan is low, channel B is selected for stimulation. During
interleaved stimulation on both channels, the StimChan output is toggled after each
stimulus pulse is completed.
The ICt2 and ICt1 outputs are used to set the amplitude select bits in the digital
logic blocks of the neural stimulator using the corresponding ASIC inputs. Likewise, the
Pos output is used to select the polarity of the stimulus current by controlling the switch
that swaps the polarity of the electrode connections inside the neural stimulator.
Finally, the Stim output is used to create the actual stimulus pulse patterns by engaging the output of the neural stimulator appropriately. During stimulation, the microcontroller toggles the Stim signal in a pattern according to the number of pulses, frequency of pulses, and delay after trigger set by the user.
43 3.1.7.4 Multiplexer Control
The microcontroller provides the Sel output to the multiplexer chip to select the recording channel. When the Sel output is high, channel A is selected for recording.
When the Sel output is low, channel B is selected for recording.
3.1.8 Power
The schematic of the power management circuitry in the basic device is shown in
Figure 3.10. The voltage regulator and reference generators are contained within the 2- channel ASIC [2], though an external battery and magnetic reed switch are required.
Figure 3.10. Power management circuitry schematic. Pin names and numbers match those of the basic 2-channel ASIC. Dashed lines indicate hand-wired connections.
3.1.8.1 Battery
The battery used in the basic device is the CR1/3N manufactured by Sanyo
Electric Co., Ltd. The CR1/3N is a 3-V lithium battery with a capacity of 160 mAh at a standard discharge current of 2 mA [57]. The battery measures 10.8 mm in height and
11.6 mm in diameter.
44 3.1.8.2 Magnetic Reed Switch
The magnetic reed switch used with the basic implant is the MK6-10-E manufactured by MEDER Electronic [58]. The MK6-10-E is a latching magnetic reed switch for PCB mounting that can tolerate voltages as high as 200 V and currents as high as 0.5 A in combinations not exceeding 10 W. The switch can resist 20 g of shock vibration and 50 g of shock without breaking or functioning improperly.
3.1.8.3 Voltage Regulator
The voltage regulator on the ASIC is designed to output a steady 2.7-V level with a 50-mV dropout voltage at a load of up to 3 mA of current.
3.1.8.4 Reference Generator
The reference generator on the ASIC produces three additional voltage levels. It generates a common-mode voltage of ~1.2 V, which is used to bias the preamplifiers, centering the neural data recordings between the supply rails. It also generates the Vr+ and Vr- voltages of ~1.8 V and ~0.6 V. The differential voltage (Vr+ - Vr-) is a precision bandgap voltage of 1.2 V that serves as the ADC reference.
3.1.9 Implementation
The schematic of the basic 2-channel implant device is shown in Appendix A and was created using ExpressPCB software [59]. The ASIC is packaged in a 40-pin ceramic leadless chip carrier with gold contacts and a soldered-on gold lid. The package measures 1.22 cm by 1.22 cm, but the die only measures 1.5 mm by 1.5 mm.
The layout of the basic implant device is shown in Appendix B and was created using ExpressPCB software [59]. The components were laid out on a small, 4-layer printed circuit board (PCB) measuring 1.6 cm by 3 cm. The top and bottom layers are
45 used for routing traces, and the internal layers are using for connecting power and
ground.
Due to the small size of the board, several components and traces did not fit onto the layout. The reed switch and the battery holder must be wired to the board, and
although the microcontroller programming header is placed on the board, its signal traces
are not routed. The remaining header connections are made by hand wiring. After
development, a few additional wire modifications, shown on the schematic, were deemed
necessary.
3.2 Advanced Implant Prototype
The advanced 2-channel prototype consists of three integrated circuits: the
microcontroller, an application specific integrated circuit (ASIC), and an OOK receiver.
With the exception of the ASIC, all the IC’s are off-the-shelf components.
A block diagram of the enhanced 2-channel ASIC [3-6] is shown is Figure 3.11.
In addition to the functionality of the basic 2-channel ASIC, the enhanced ASIC contains the 2nd-stage amplifiers, channel multiplexer, and OOK receiver with sleep enable and
secondary voltage regulator. Additionally, the main voltage regulator, FSK transmitter,
and neural stimulator have been improved from the basic version.
46
Figure 3.11. Block diagram of the advanced 2-channel ASIC (from [3-6]).
The following sections provide a closer look at the individual circuits and components used in the advanced 2-channel prototype, on and off the ASIC.
3.2.1 Neural Amplifiers
As in the basic device, acquired neural data is passed through a cascade of two differential neural amplifiers that together provide a signal gain of 4000. The amplifiers have very low input-referred noise to prevent corruption of the neural signals, and each recording channel has an identical set of neural amplifiers.
47 3.2.1.1 Neural Preamplifier
The neural preamplifier circuitry is part of the advanced 2-channel ASIC. The preamplifier circuitry is identical to that contained within the basic 2-channel ASIC, as shown Figure 3.2, but that the circuit is now interfaced through pins 3 and 4 (channel A) and pins 5 and 7 (channel B).
3.2.1.2 Second-Stage Amplifier
The second-stage amplifier circuitry [6] is contained within the enhanced 2- channel ASIC. The schematic design is identical to that presented in Figure 3.3, but the opamp is now integrated on the ASIC and interfaced through pins 18 (preamp output), 16
(inverting input), and 19 (opamp output) for channel A and pins 20 (preamp output), 21
(inverting input), and 22 (opamp output) for channel B.
3.2.2 Multiplexer
The multiplexer is part of the enhanced 2-channel ASIC. As in the basic device selects, it switches between the outputs of the 2nd-stage amplifiers of the two channels of neural data and provides a single analog input to the analog-to-digital converter. Instead of having a dedicated control signal, as in the basic version, the multiplexer is operated using the same channel select signal as the neural stimulator. This control signal is generated by the microcontroller.
3.2.3 Analog-to Digital Converter
The architecture and operation are of the ASIC are identical to the ADC in the basic 2-channel ASIC, except that the serial output SoutB (pin 42) is now accompanied by synchronization signals Bit_syn (pin 43) and Byte_syn (pin 41). Also, the analog
48 neural data need not be routed to the ADC from outside the ASIC, since the neural amplifiers and multiplexer have been integrated inside the ASIC. Finally, digital data is sent to the microcontroller for processing before being transmitted to the host transceiver, instead of directly to the FSK transmitter.
3.2.4 FSK Transmitter
The FSK transmitter is identical to that of the basic version, but the ASIC circuitry of the modulator and antenna driver circuit blocks have been redesigned to improve reliability and transmission distance. Data to be transmitted now comes from the microcontroller, where it has been processed first, instead of directly from the ADC on the ASIC.
3.2.5 Neural Stimulator
In the advanced design, a 15-kΩ bias resistor (RRef) generates a bias current of
100 μA, which is shared by the two channels so that each channel has a reference current of 50 μA, as in the basic device. All three amplitude control bits (ICt0-ICt2), pins 9-11, are used in this version, however, so that the amplitude can be adjusted in 50-μA increments. The maximum output current amplitude is 350 μA.
The control signals generated by the microcontroller have identical functionality to the neural stimulators of the basic 2-channel device. The transmission gate switches on the ASIC used to disconnect the neural preamplifiers during stimulation have been resized to minimize leakage current and improve blanking.
49 3.2.6 OOK Receiver
The reception of recording and stimulation commands and parameters is handled by the MLX90109, as before. The enhanced 2-channel ASIC contains a prototype OOK receiver with integrated sleep mode circuitry, but this circuit did not function properly and is not used. PCB components meant for use with the ASIC OOK receiver, i.e. the antenna inductor (L_OOK) and capacitors (C_OOK, Cex3-Cex5), are not populated, and jumper resistors RA30 and RA31 are removed to disconnect the serial communication traces from the microcontroller.
3.2.7 Microcontroller
The microcontroller used in the advanced 2-channel prototype is the PIC18F1320, described previously. Table 3-8 summarizes the microcontroller pin numbers, signal names, I/O usage, and their functions. The microcontroller can be programmed in-circuit via a 5-pin header using the MPLAB® ICD 2. The 18-pin SOIC version of the part is used in the advanced prototype. This package of the PIC18F1320 has a single power connection and a single ground connection. The following sections will explore these interactions in greater detail.
50
Signal Pin Name μC Usage Used With Function Signal for adjusting voltage across OOK 1 Vmod Output OOK Receiver receiver antenna 2
Table 3-8. Advanced prototype microcontroller input/output signals table.
3.2.7.1 Microcontroller Programming Pins and Clock
The microcontroller programming pins are identical in connection and functionality to those of the basic 2-channel device.
As before, the microcontroller provides a 500-kHz system clock, Clk_slug, to the
ADC. In addition, the microcontroller receives two clock signals from the ADC, Bit_Syn
51 and Byte_Syn. These signals are used for synchronization during data compression, and
Byte_Syn is also used to determine when to toggle the Chan (channel select) signal during interleaved recording from both channels.
3.2.7.2 OOK Receiver Command Interpretation
The T&C, SP1, and SP2 commands in the advanced 2-channel prototype function as in the basic 2-channel device, except that the T&C command, which is used to select the trigger mode for stimulus, now supports two additional trigger modes [3-4, 57].
Stimulus can be triggered when a neural spike is detected on either channel A or channel
B by the microcontroller. Also, interleaved recording from both channels is enabled by
setting both RA and RB high.
Also, the SP1 command has all three amplitude select bits enabled, as shown in
Table 3-10. A0 is the least significant bit, and the stimulus current amplitude can be adjusted in 50-μA increments.
A2 A1 A0 Polarity PW3 PW2 PW1 PW0
Table 3-9. Advanced prototype Stimulation Parameter 1 command data bits (from [3-4, 57]).
A new command, OP1, has been added. The OP1 command is used to enable
data compression. The OP1 command bits are organized as shown in Table 3-11 [3-4,
57].
x x CompA CompB x x x x
Table 3-10. Other Parameters command data bits (from [3-4, 57]).
The CompA and CompB bits are used to enable data compression, CompA for channel A and CompB for channel B. Data compression is enabled when the bits are
52 high and disabled when the bits are low. No data compression or data compression of both channels are the only modes supported. Data compression defaults as disabled.
3.2.7.3 Neural Stimulator and Multiplexer Control
The microcontroller provides the control signals needed to operate the neural stimulator using the I/O indicated in Table 3-8. The Chan output is used to select both the record and stimulation channel using the “Chan” input of the enhanced ASIC. During interleaved recording from both channels, the microcontroller toggles the Chan output every time the Byte_Syn input transitions low so that samples will come from alternate channels. During interleaved stimulation, the microcontroller toggles the Chan output after each stimulus pulse is complete.
The Chan signal can be shared by the multiplexer and the neural stimulator, since recording on a given channel is stopped during stimulation due to preamplifier blanking.
Recording on both channels is halted during stimulation. The microcontroller cannot switch channels until a stimulation pattern is complete.
3.2.7.4 Data Processing
The microcontroller in the advanced version performs two different types of data processing, neural spike detection and data compression, using algorithms developed by
Hsu [47]. The spike detector passes the data through a first-order recursive low pass filter with a cutoff frequency of 46 Hz. The filter is used to calculate the mean-square value of the input signal, which is scaled and used as a spike threshold. A spike is detected if the threshold is exceeded by an input sample.
If a spike is detected, the data compressor is invoked. The data compressor records the maximum amplitude and duration of a spike. A spike is considered to begin
53 when the threshold is exceeded and end when the signal falls below the threshold or the
polarity of the signal changes. The time between detected spikes, referred to as “runs,” is
also recorded. The compression algorithm achieves an average compression ratio of
20:1.
Spike and run data are transmitted according to Figure 3.12. The spike and run
data are each allocated an 11-bit data slot. Spikes are allotted 1 bit to signify that the data
slot is a spike, 3 bits to represent the duration of the spike, and 7 bits to represent the
amplitude of the spike in 2’s-compliment. Runs are allotted 1 bit to signify the data slot
is a run and 10 bits for to represent the duration of the run.
Figure 3.12. Compressed data transmission format (from [47]).
Every 5 data slots are combined with a synchronization bit to form a data frame. Every
12 data frames form a super frame with the synchronization bits forming the frame alignment word.
Special actions are taken by the microcontroller when a spike or run exceeds the parameters allowed for in the encoding format. A run with duration greater than 1024
54 samples is transmitted using multiple data slots whose durations sum to give the correct
total duration. A spike with duration greater than 8 samples is transmitted using multiple
data slots whose durations sum to give the correct total duration. In this case, the spike
amplitude is recorded as zero in all but the last of the data slots. A spike with amplitude
greater than 64 is transmitted using multiple data slots whose amplitudes sum to give the
correct total amplitude. In this case, the spike duration is repeated in each of the data
slots.
3.2.8 Power
The schematic of the power management circuitry in the advanced prototype is
shown in Figure 3.13. The voltage regulator and reference generators are part of the
advanced 2-channel ASIC, though an external battery and power switch are required.
Figure 3.13. Power management circuit schematic. Pin names and numbers match those of the advanced 2-channel ASIC.
3.2.8.1 Battery
The battery used in the advanced prototype is the CR1/3N from Sanyo Electric
Co., Ltd, described previously.
55 3.2.8.2 Power Header
The advanced prototype is equipped with a 3-pin header for powering the board from a lab bench supply. PowerIn+ and PowerIn- connect to the power and ground traces, and the third pin connects the board’s ground plane to earth ground. CPow should be populated with a 10-μF capacitor when a bench supply is used.
3.2.8.3 Power Switch
A simple on-off switch is used in the advanced prototype. A magnetic reed switch is not necessary, since this is only a prototype and will not be implanted.
3.2.8.4 Voltage Regulator
The voltage regulator in the enhanced ASIC was adjusted to output a more reliable 2.7-V level with a 50-mV dropout voltage at a load of more than 10 mA of current. The regulator is internally connected to power the ASIC circuits. The regulator is not used to power the external components (The microcontroller and OOK receiver are powered directly from the battery), though it could easily be connected if desired.
External biasing of any ASIC circuits, such as the neural stimulator, is done by connection to the analog supply pin.
3.2.8.5 Reference Generator
The reference generator is identical to the basic version.
3.2.9 Implementation
The schematic of the advanced 2-channel prototype was created using
ExpressPCB software [59] and is shown in Appendix C.
Several additional elements have been added to this device for use during development. Each signal trace and each power trace can be connected or disconnected
56 using a 0-ohm jumper resistor. This makes it easy to rewire traces or disable
components. Each component pin is connected a test point, so it can be probed easily or
connected to an oscilloscope. A power header was added, so that the board can be connected to a lab bench supply. Additional pads and variable capacitors were added to
antenna circuits to make tuning easier.
The enhanced ASIC is packaged in a 44-pin ceramic leadless chip carrier with
gold contacts and a taped-on gold lid. The package measures 1.65 cm by 1.65 cm, but
the die is only 1.5 mm by 1.5 mm.
The layout of the advanced 2-channel prototype is shown in Appendix D and was
created using ExpressPCB software [59]. The components were laid out on a 2-layer
printed circuit board (PCB) measuring 9.65 cm by 6.35 cm. For ease in assembly, all
components were placed on the top layer of the board. The top and bottom layers are
used for routing signal, power, and ground traces. An earth ground plane was added to
the bottom of the board to decrease noise. Star grounding and star powering techniques
were also used during layout to improve noise performance.
57 4. Test Results
The basic implant device was assembled using a combination of hand and reflow
soldering. The fully assembled unit is 4.5 cm by 1.8 cm by 1.8 cm and has a mass of
21.9 grams when fully encapsulated in silicone. A photograph of the fully assembled
device is shown in Figure 4.1. After each major component was mounted to the PCB, the
functionality of the component and the implant, as a whole, was verified.
Figure 4.1. Fully assembled 2-channel implant device (top and bottom view). A penny is shown for comparison.
4.1 Basic Device Test Results
4.1.1 Microcontroller Start-up
The measured clock output from the microcontroller is shown in Figure 4.2, and the default levels at the remaining microcontroller output pins are shown in Table 4-1.
These tests were performed after the microcontroller had been successfully programmed
58 in order to verify the default configuration. All output levels are well defined and within
1 mV of the 2.61-V supply produced by the regulator on the ASIC. (The regulator is
discussed in Section 4.1.5.1.)
Figure 4.2. Measured system clock waveform.
The measured frequency of the system clock was 490.2 kHz, which is less than the desired 500 kHz clock. The slight difference is likely due to an error in the microcontroller's internal 8-MHz reference oscillator, which is divided by 16 to produce the system clock. A 1.96% error in the reference oscillator would account for the inconsistency measured here, which is within the ±2% error specified for the internal oscillator [53].
59 Signal Default Measured Name Level Voltage Vmod High 2.611 V Sel Low 0 V Pos Low 0.001 V Stim Low 0 V MCLR High 2.610 V StimChan High 2.611 V ICt2 Low 0 V ICt1 Low 0 V
Table 4-1. Measured microcontroller default output levels.
The default voltage values measured on the microcontroller output pins are consistent with the expected levels. The high voltage levels are not quite 2.7 V, because the voltage regulator is overloaded.
4.1.2 Multiplexer
The measured multiplexer turn-on and turn-off waveforms are shown in Figure
4.3 and Figure 4.4. These tests were performed to verify that the multiplexer switches correctly. The normally closed input of the multiplexer was shorted to ground, and the normally open input was shorted to Vdd. The selection input of the multiplexer was toggled manually.
60
Figure 4.3. Measured multiplexer turn-on waveform with inputs set to 0 V (channel A) and 2.61 V (channel B).
Figure 4.4 Measured multiplexer turn-off waveform with inputs set to 0 V (channel A) and 2.61 V (channel B).
61 The turn-on time of the multiplexer was measured to be 85 ns, and the turn-off
time was measured to be 58 ns. These values are consistent with the 80 ns turn-on and 50
ns turn-off times specified in the multiplexer datasheet [49].
4.1.3 Second-Stage Amplifier
The measured second-stage amplifier gain vs. frequency characteristics are shown
in Figure 4.5. The gain vs. frequency was measured at supply voltages of 2.7 V and 3.0
V to account for the range of battery voltages at which the unit may operate.
Figure 4.5. Measured second-stage amplifier gain vs. frequency graph.
The gain vs. frequency characteristics are nearly identical for the different supply voltages. The maximum gain achieved by the second-stage amplifier was measured to be
33 dB, which equates to a gain of 45. The low frequency cutoff, defined as -3 dB from
33 dB was measured to be 110 Hz, and the high frequency cutoff, also defined as -3 dB from 33 dB, was measured to be 4.9 kHz. These results are very close to the expected
62 values of 100 Hz and 4 kHz, and are within the expected tolerance of the external
components used.
4.1.4 OOK Receiver
The waveform measured at the antenna of the OOK receiver when idle is shown
in Figure 4.6. The antenna has been tuned to a frequency of 125 kHz by adjusting the
value of the capacitor, Ccntr. The waveform appears as a 125-kHz sine wave centered on
the supply rail with a peak-to-peak voltage of 1.2 V. The signal is centered at the supply
rail, because one side of the antenna is tied to the supply rail.
Figure 4.6. Oscillation on command antenna while OOK receiver is idle.
These oscillations disturb of the supply of the OOK receiver IC. The supply rail
for the OOK receiver IC is not isolated from the supply rails of the other components,
and as a result, tiny 125-kHz perturbations occur on the supply voltages of the other components. When the OOK receiver is disabled, this 125-kHz interference disappears.
Figure 4.7 shows the output of the ADC (left) and the output of the multiplexer
(right) with 125-kHz interference on the high-level voltage. The interference has a peak-
63 to-peak voltage of 50 mV. Although this is not large enough to cause a false logic transition, this interference could affect the performance of the system.
Figure 4.7. 125-kHz OOK receiver interference on the ADC output (left) and the multiplexer output (right) while the receiver is idle. Multiplexer inputs are as in Figure 4.3 and 4.4.
Table 4-2 shows the default microcontroller signal values and their new values after an SP1 command was transmitted to 1) change the stimulation amplitude to maximum (350 μV) and 2) reverse the polarity of stimulation from hyperpolarize to depolarize. This first command was followed by a T&C command to toggle the record and stimulation channels. The microcontroller's output signal levels were measured after the commands were sent. All levels correctly changed.
64 Voltage Signal Default After Name Level Command Vmod High High Sel Low High Pos Low High Stim Low Low MCLR High High StimChan High Low ICt2 Low High ICt1 Low High
Table 4-2. Microcontroller signal output levels before and after SP1 and T&C commands were sent.
4.1.5 ASIC
The results of testing the individual circuits contained in the basic 2-channel
ASIC are summarized in the following sections.
4.1.5.1 Voltage Regulator
Table 4-3 shows the measured output voltage of the voltage regulator for different input voltages. The output of the regulator was loaded with the full burden of the implant unit.
65 Input Voltage Regulator (V) Output (V) 3.300 2.643 3.250 2.638 3.200 2.632 3.150 2.626 3.100 2.620 3.050 2.613 3.000 2.607 2.950 2.600 2.900 2.591 2.850 2.582 2.800 2.571 2.750 2.550 2.700 2.518 2.650 2.478 2.600 2.440 2.550 2.399 2.500 2.356 2.450 2.313 2.400 2.269
Table 4-3. Voltage regulator output at different input voltages.
The regulator fails to output the full 2.7 V it is expected to deliver, and supply sensitivity is poor, about 20% for inputs less than 2.9 V, because the implant unit draws more than the anticipated 3 mA of current. The regulator was able to output at least 2.7
V for input voltages greater than 2.75 V during previous tests without a load [2].
4.1.5.2 Neural Preamplifier
The gain vs. frequency characteristic of the neural preamplifier is shown in Figure
4.8. Measurements were taken using supply voltages of 2.7 V and 3.0 V to account for the range of battery voltages at which the unit may operate.
66
Figure 4.8. Neural preamplifier gain vs. frequency graph.
The gain vs. frequency characteristics were slightly different for the different supply voltages, with the high-frequency cutoff being slightly less at a supply of 2.7 V.
The maximum gain achieved by the preamplifier was measured to be 39.6 dB, which equates to a gain of 95.5, very close to the expected gain of 100.
The high-frequency cutoff, defined as -3 dB from 39.6 dB was measured to be 35 kHz at 2.7 V and 46 kHz at 3.0 V. These results are close to the expected value of 100 kHz. The low-frequency cutoff could not be measured with the spectrum analyzer since it is below 10 Hz.
4.1.5.3 Analog-to-Digital Converter
The output of the analog-to-digital converter for a 60-Hz square-wave input is shown in Figure 4.9. By design, the bits are inverted when they exit the ADC. The measured data rate is 62.5 kHz, as designed, and the frame alignment bits can easily be seen.
67
Figure 4.9. Measured analog-to-digital converter output for 60-Hz square-wave input.
4.1.5.4 FSK Transmitter
The setup used to find the resonant frequency of the FSK data antenna is shown in
Figure 4.10. The VCO inductor and capacitor of the completed implant were removed from the unit and replaced by a 180-Ω resistor to suppress oscillation. The VCO was then driven through a 22-nF capacitor using a signal generator with a 1-Vpp sine wave.
The output power of the antenna was measured using a magnetic loop probe connected to a spectrum analyzer. The implant unit was positioned directly in the center of the magnetic loop probe with axes aligned to achieve maximum signal strength. The discrete frequency of the signal generator was varied in small increments, and the output power at each frequency was recorded.
68
Figure 4.10. Test setup used to measure the resonant frequency of the FSK antenna.
The results of the frequency sweep before tuning are shown in Figure 4.11. The transmission power was at a maximum at 26.75 MHz, i.e. the un-tuned antenna is resonant at 26.75 MHz.
Figure 4.11. Measured frequency response of the un-tuned FSK antenna.
69 Unfortunately, this is less than the desired 27.12-MHz transmission frequency. It
would be difficult to decrease the inductance of the antenna without degrading the quality factor, so the unit was used as is. The external unit was instead tuned to receive 26.75-
MHz FSK data.
If the antenna had been tuned to a frequency greater than 27.12 MHz, the
capacitance of the antenna could be increased very slightly using a piece of wire glued to
the outside of the inductor, as shown in Figure 4.12. The length of this wire could be
varied to achieve precise tuning, and this concept was verified on a preliminary version
of the implant unit. In future implant designs, parasitics should be reduced to ensure
untuned resonance is greater than 27.12 MHz.
Figure 4.12. Basic implant unit with tuning wire on transmission antenna.
The VCO spectrum at resonance was measured using an active probe connected to a spectrum analyzer and is shown in Figure 4.13. The probe was connected directly to
70 the LC-tank of the VCO. The VCO was tuned to a center frequency of 53.54 MHz to correspond with the antenna frequency (26.75 MHz x 2) by adjusting the capacitor, Cvco, in the VCO tuning circuit.
Figure 4.13. Measured VCO spectrum at resonance. A marker has been placed at the center frequency (between the two peaks) of 53.54 MHz.
The spectral output of FSK data antenna with tuned VCO was measured using a magnetic loop probe connected to a spectrum analyzer and is shown in Figure 4.14. The implant unit was positioned directly in the center of the magnetic loop probe with axes aligned. The center frequency was measured to be 26.74 MHz, and the mark and space frequencies were measured to be 26.56 MHz and 26.93 MHz, respectively. The frequency deviation is 370 kHz, which is higher than desired 320 kHz, but acceptable.
The measured amplitudes were -38 dBm/Hz and -42 dBm/Hz, respectively.
In both cases, VCO and data transmitter, the measured amplitude is highly dependent upon antenna details, including spacing and orientation. In order to determine the true voltage amplitude of the data transmitter output, an identical transmit inductor
71 was driven directly by a signal generator using frequencies of 26.56 MHz and 26.93 MHz
with 1 VRMS, which was measured using a calibrated probe. The orientation and spacing of the transmit inductor and pickup coil were precisely the same as used in tests of the implant unit. The amplitudes measured using the spectrum analyzer were -50 dBm/Hz and -50 dBm/Hz, respectively. Thus, the previously measured amplitudes of -38 dBm/Hz and -42 dBm/Hz are 12 dB and 8 dB higher than that for the 1 VRMS excitation, implying
4 VRMS and 2.5 VRMS amplitudes across the transmit inductor.
Figure 4.14. Data transmitter spectrum.
4.1.5.5 Neural Stimulator
Figures 4.15 and 4.16 show the output of the neural stimulator for hyperpolarized
(positive) and depolarized (negative) stimulation through a 1-kΩ load resistor.
Stimulation was triggered by wirelessly sending commands to the implant unit. Both
channels were exercised to demonstrate the interleaved stimulation feature.
72
Figure 4.15. Interleaved hyperpolarized stimulation with 300-μA amplitude pulses that are 2 ms wide being output at a frequency of 10 Hz.
Figure 4.16. Interleaved depolarized stimulation with 100-μA amplitude pulses that are 5 ms wide being output at a frequency of 20 Hz.
73 4.1.5.6 Reference Generator
The output voltages of the reference generator for various supply voltages are
listed in Table 4-4. The measured voltages are significantly higher than the simulated values of 0.6, 1.2, and 1.8 V respectively [3-4], due to an inaccurate diode model.
However, the outputs vary only slightly over a wide range of input voltages, thanks to the
on-chip regulator.
It is important to note that all recorded signals are biased to a common mode level of Vcmref ~ 1.5 V, and not the expected 1.2-V level, but this has little effect on the implant performance since signals are measured differentially. The ADC reference voltage ΔVr = (Vr+) – (Vr-) is close to simulation and varies by only 0.010 V for a
supply variation from 2.75 V to 3.3 V, corresponding to an ADC gain variation of 0.78%.
Supply Voltage (V) Vr- (V) Vcmref (V) Vr+ (V) ΔVr (V) 3.30 0.767 1.508 2.062 1.295 3.25 0.767 1.506 2.061 1.294 3.20 0.766 1.506 2.060 1.294 3.15 0.766 1.506 2.060 1.294 3.10 0.766 1.506 2.059 1.293 3.05 0.766 1.506 2.058 1.292 3.00 0.767 1.507 2.058 1.291 2.95 0.767 1.506 2.058 1.291 2.90 0.767 1.507 2.056 1.289 2.85 0.767 1.507 2.056 1.289 2.80 0.767 1.507 2.055 1.288 2.75 0.767 1.506 2.052 1.285 2.70 0.767 1.506 2.049 1.282 2.65 0.767 1.506 2.045 1.278 2.60 0.767 1.506 2.040 1.273 2.55 0.766 1.506 2.034 1.268 2.50 0.766 1.505 2.025 1.259 2.45 0.766 1.505 2.013 1.247 2.40 0.765 1.503 1.995 1.230
Table 4-4. Measured reference generator voltage levels.
74 4.1.6 Power
4.1.6.1 Supply Current
Table 4-5 shows the current drawn by major components of the implant unit. The unit draws 7.09 mA of total current from the battery, which is more than twice the load for which the voltage regulator was designed, due to the inclusion of test and system features not originally anticipated. As expected, the ASIC’s the most power hungry component, with all its integrated circuitry, especially the FSK transmitter.
Component Current Draw (mA) PIC, Mux, 2nd-Stage Amp 1.42 OOK Receiver 1.62 ASIC 4.05 Total 7.09
Table 4-5. Measured current drawn by components of the implant unit.
4.1.6.2 Battery Life
The CR1/N3 lithium ion battery has a nominal capacity of 160 mA-hours, determined by discharging to a end voltage of 2 V at the standard discharge level of 2 mA [57]. This is much less than the 7.09-mA current draw of the implant unit, and the implant performance will degrade when battery voltage drops below the minimum required by the voltage regulator, 2.75 V.
The standard discharge curve provided by the CR1-N3 datasheet was used to determine a more relevant capacity, discharging to an end voltage of 2.75 V. From the curve, it was determined that the battery would discharge to 2.75 V after 36 hours, yielding a nominal capacity of (2 mA)*(36 hours) = 72 mA-hours. Given this capacity, the battery lifetime of the implant unit was calculated to be (72 mA-hours)/(7.09 mA) =
10.2 hours.
75 4.2 Tests with Aplysia
An early, but otherwise identical, version of the basic implant that used a electric dipole antenna similar to [32] was used in animal tests in conjunction with Miranda
Cullins and Dr. Hillel J. Chiel in the Department of Biology at Case Western Reserve
University and with the assistance of Paras Samsukha. Tests were performed in vitro while immersed in salt water, then in vivo. This progression was followed in an effort to verify the implant unit's performance after each step before moving to an in vivo test.
The animal tests and their results are summarized in the following sections.
All animal testing was done with a dipole antenna using 6.8-μH inductors for
FSK transmission. The dipole antenna was made from two pieces of 22 AWG wire with the ends stripped approximately 0.25 inches and is pictured in Figure 4.17. The dipole antenna was tuned using series inductors. The external transceiver used a dipole antenna to receive data in these tests, which has since been replaced by a large coil antenna for use with the newer inductive antenna.
Figure 4.17. Basic 2-channel implant unit with dipole antenna.
76 4.2.1 In Vitro Tests
The setup for the in vitro tests is shown in Figure 4.18. A few ganglia from the sea slug Buccal mass (a grouping of nerves and muscles from the Aplysia mouth) were isolated in a small Petri dish of nutrient saline solution. The nutrients preserve the ganglia life when removed from the animal. One pair of exposed electrode ends was glued to an isolated ganglion with the reference of the pair left immersed nearby. The connector ends of the electrodes were plugged into the implant unit. A second set of electrodes were also attached to the ganglion and plugged into a laboratory amplifier to give wired recordings for direct comparison to wireless data.
Figure 4.18. In vitro test setup.
The implant unit and external receiver dipole antennas were placed in a beaker of
10% saline solution to test the telemetry link. Commands were sent to the implant unit
77 from the external transceiver's OOK antenna, which was mounted on the end of a long
wooden wand. Both the laboratory amplifier and the external transceiver were connected
to a PC to log and display the wired and wireless data.
Figure 4.19 shows a direct comparison of wired vs. wireless data acquired from
the in vitro ganglion. A clear 1:1 correspondence between action potentials (spikes) can be seen. The wireless data is biased near 2.5 V due to the transceiver DAC, and the wireless system gain is Amp_Gain*DACLSB/ADCLSB = 45*95.5*0.625/0.338 = 7946.
Figure 4.19. In vitro (a) wireless vs. (b) wired recording.
Figure 4.20 shows a direct comparison of wired vs. wireless data acquired from the in vitro ganglion with the digital values scale also present, and Figure 4.21 shows a zoom view of one of the action potentials.
78
Figure 4.20. In vitro (a) wired vs. (b) wireless recording with digital values shown for wireless data.
Figure 4.21. In vitro wireless recording, zoom view of action potential.
Correlation was calculated using Equation 4.2. The calculated correlation coefficient between the wired and wireless data of individual action potentials was as high as 0.85, and the average correlation between wired and wireless data over a longer period of time ranged from 0.50 to 0.70. This is due to the noise on the wireless recording.
79 (4.2)
The input-referred RMS (root-mean-square) noise of the wired and wireless in vitro data from Figure 4.20 was calculated to be 1.6 μV and 3.4 μV, respectively.
4.2.1.1 Hyperpolarized Stimulation
In the following set of tests, hyperpolarized stimulation was employed to examine its affects on neural activity. Stimulation was triggered manually with wireless commands from the external transceiver. In this early device, stimulation parameters vary slightly from the revised command set described in sections 2.1.3 and 3.1.7.2.
Figure 4.22 shows hyperpolarized stimulation artifacts on the wired recording
along with the actual stimulation pulses from the implant unit. The stimulation pulses
were set to an amplitude of 100 µA and a pulse width of 700 µs at a frequency of 25 Hz.
The PC was sampling at a rate of 2 kHz, so stimulation pulses are distorted and amplitude is not meaningful.
Figure 4.22. (a) Hyperpolarized stimulation with small amplitude creating (b) artifacts on wired recording.
80 Figure 4.23 shows the effect of increased amplitude and duration on the
hyperpolarized stimulation artifacts in the wired recording. The stimulation pulses were
set to an amplitude of 300 µA and a pulse width of 8.4 ms output at a frequency of 25 Hz.
The amplitude of the pulses during this stimulation was three times that of the previous
stimulation, and the artifacts appearing on the wired recording were also roughly three
times larger. Based on the amplitude of the stimulation pulses, the impedance of the
ganglion interface is calculated to be 7.5 Ω.
Figure 4.23. (a) Hyperolarized stimulation with large amplitude creating (b) artifacts on wired recording.
Figure 4.24 shows both the wired and wireless recordings with hyperpolarized stimulation. The stimulation pulses were set to an amplitude of 100 µA and a pulse width of 700 µs at a frequency of 25 Hz. The wireless recording blanks for a short period before stimulation begins, because the external transceiver exits record mode to send commands to the implant unit. Wireless recording continues to be blanked during the
81 stimulation period and resumes when stimulation is completed. The wired and wireless
recordings continue to show a 1:1 correspondence in action potentials.
Figure 4.24. (a) Wireless vs. (b) wired recording during and after (c) hyperpolarized stimulation.
Figure 4.25 shows wired recording over an extended period of time with
hyperpolarized stimulation from the implant unit. The stimulation pulses were set to an amplitude of 200 µA and a pulse width of 2.8 ms at a frequency of 25 Hz. There are four
stimulation groups, three of which are in immediate succession. They appear as the large
shaded areas, which are in fact the artifacts on the ganglion closely grouped together on the recording. As indicated on the figure, hyperpolarized stimulation leads to reduced neural activity.
82
Figure 4.25. (a) Wired recording over an extended time period during and after (b) hyperpolarized stimulation.
4.2.1.2 Depolarized Stimulation
The following set of tests employ depolarized stimulation to examine its affects on neural activity. Stimulation was triggered manually with wireless commands from the external transceiver. Stimulation parameters may not match the current command set.
Figure 4.26 shows depolarized stimulation artifacts on the wired recording along with the actual stimulation pulses from the implant unit. The stimulation pulses were set to an amplitude of 100 µA and a pulse width of 700 µs at a frequency of 25 Hz. Once again, the pulses amplitudes are not accurately measured, because the PC was sampling at a rate of 2 kHz.
83
Figure 4.26. (a) Wired recording of artifacts from (b) depolarized stimulation, indicated amongst other action potentials generated by the stimulation.
Figure 4.27 shows both the wired and wireless recordings with depolarized stimulation. The stimulation pulses were set to an amplitude of 300 µA and a pulse width of 8.4 ms at a frequency of 25 Hz. The wireless recording blanks for a short period before stimulation begins, because the external transceiver exits record mode to send commands to the implant unit. Wireless recording continues to be blanked during the stimulation period and resumes when stimulation is completed. The stimulation period is immediately followed by a grouping of large action potentials, much larger in size than the artifacts of the stimulus pulses.
84
Figure 4.27. (a) Wireless vs. (b) wired recording during and after (c) depolarized stimulation.
Figure 4.28 shows wired recording over an extended period of time with depolarized stimulation. The stimulation pulses were set to an amplitude of 300 µA and a pulse width of 8.4 ms at a frequency of 25 Hz. There is one burst of stimulation which produces large artifacts followed by large bursts of neural activity on the ganglion.
85
Figure 4.28. Wired recording over an extended period of time during and after depolarized stimulation.
4.2.1.3 Mixed Depolarized and Hyperpolarized Stimulation
The final in vitro test employs depolarized stimulation followed by hyperpolarized stimulation. Stimulation was triggered manually with wireless commands from the external transceiver.
Figure 4.29 shows both wired and wireless recordings with depolarized stimulation follow by hyperpolarized stimulation. As in previous depolarized stimulations, the pulse artifacts are immediately followed by a group of large action potentials. The hyperpolarized stimulation is also followed by sizeable action potentials, but they are much smaller in amplitude than the previous group and not as long in duration.
86
Figure 4.29. (a) Wireless vs. (b) wired recording with (c) depolarized then hyperpolarized stimulation.
4.2.2 Immersion Tests
The next test performed with the implant unit was an immersion test. This test was used to verify the integrity of the silicone encapsulation and the performance of the unit while encapsulated and immersed in saline.
The implant unit was encapsulated in clear RTV silicone adhesive (MED ADH
4100 RTV), an implant grade silicone manufactured by Rhodia Silicones. The encapsulation was done using a rectangular plastic mold. Only the ends of the dipole antenna and the electrode wires were left exposed. The silicone was poured into the mold and allowed 24-48 hours to cure before testing began.
The setup of an immersion test is shown in Figure 4.30. The entire Buccal mass was removed from the animal. One pair of exposed electrode ends was glued to an isolated ganglion with the reference of the pair left immersed nearby. The connector
87 ends of the electrodes were plugged into the implant unit. A second set of electrodes
were also attached to the ganglion and plugged into a laboratory amplifier to give wired recordings for direct comparison to wireless data.
Figure 4.30. Immersion test setup.
The encapsulated implant unit and isolated Buccal mass were placed in a large beaker of 10% saline solution, along with the dipole antenna of the external transceiver.
Commands were sent to the implant unit from the external transceiver's OOK antenna.
Both the laboratory amplifier and the external transceiver were connected to a PC to display and log the wired and wireless data.
The implant unit recorded perfectly for 3 hours during the immersion test, but the command link was unreliable. Commands were only received (roughly) 10% of the time and only if the encapsulated unit and the external transceiver command antenna were pressed flush against the sides of the beaker. The external transceiver was not powerful
88 enough to send commands through the combination of the beaker, the saline solution, and
the encapsulation of the implant unit. In fact, the external transceiver was only just
powerful enough to send commands through the encapsulation alone. A colleague is
working to improve the command signal strength.
4.2.3 In Vivo Tests
The final test performed with the implant unit was done in vivo. The setup of the
in vivo test is shown in Figure 4.31. The unit was encapsulated as previously described and implanted into the foot of the animal. The electrodes were routed through the
animal's body to the Buccal mass, and one of each pair of exposed electrode ends was
glued to a ganglion within the mass with the other half of the pair left immersed nearby,
serving as a reference.
Figure 4.31. In vivo test setup.
89 The animal was placed in a large beaker of 10% saline solution along with the
dipole antenna of the external transceiver. Commands were sent to the implant unit from the OOK antenna of the external transceiver. The external transceiver was connected to a
PC to log and display the wireless data.
Figure 4.32 shows the wirelessly recorded in vivo data, and Figure 4.33 shows a zoom view of one of the action potentials. The transceiver dipole antenna had to be placed very close to the animal in order to receive data. The new inductive antenna described in section 3.1.4 is expected to provide better performance. As in the immersion tests, the external transceiver was not powerful enough to send commands to the implanted unit, even if the command antenna was placed inside the beaker against the slug.
Figure 4.32. In vivo wireless recording. System gain is ~7950.
90
Figure 4.33. In vivo wireless recording, zoom view of action potential.
The action potentials can clearly be seen in the figure, even though the noise level
was higher than during the in vitro. The input-referred RMS (root-mean-square) noise of the in vivo data from Figure 4.31 was calculated to be 5 μV.
4.3 Advanced Prototype Test Results
The advanced prototype was assembled using hand soldering. The fully
assembled advanced prototype is shown in Figure 4.34. The components were mounted
on the PCB all at once, and then the functionality of the prototype was verified at the
completion of construction.
91
Figure 4.34. Fully assembled advanced 2-channel prototype (top view). A penny is shown for comparison.
Basic functionality of the advanced prototype has been verified and the results provided here. Continued development and testing will be performed by a colleague.
4.3.1 Data Processing
A microprocessor compatible spike detection and data compression algorithm has been simulated by Hsu [47] and functions properly, but has not yet been adapted to the
PIC18F1320 platform. The framework of the OP1 command has been implemented in preparation for the completion of the data processing algorithm.
4.3.2 OOK Receiver
Thanks to the star layout technique used on the power lines of the advanced 2- channel prototype, the 125-kHz noise from the OOK receiver is no longer observed on
92 the supply lines of the other components on the board. As a result, the digital outputs of these components no longer have 125-kHz interference on their high-level voltage levels
(see Figures 4.36-4.37, ADC outputs).
4.3.3 ASIC
The following sections examine the results of testing the individual circuits provided by the enhanced 2-channel ASIC.
4.3.3.1 Voltage Regulator
Table 4-6 shows the measured output voltage of the voltage regulator for different input voltages. The output of the regulator was loaded with only the ASIC circuits. The regulator successfully outputs at least 2.7 V on both the analog and digital power lines for supply voltages greater than 2.75 V. The slight difference between AVDD and DVDD is due to the fact that DVDD bears a greater load, i.e. most of the ASIC circuits are supplied by DVDD. Supply sensitivity is ~14% for supply voltage greater than 2.85 V. The improved regulator performance is due to its internal redesign, i.e. increased size of the output transistor.
93 Supply Voltage (V) AVDD (V) DVDD (V) 3.30 2.825 2.815 3.25 2.820 2.811 3.20 2.813 2.805 3.15 2.807 2.798 3.10 2.800 2.792 3.05 2.793 2.785 3.00 2.786 2.777 2.95 2.779 2.771 2.90 2.772 2.763 2.85 2.761 2.753 2.80 2.748 2.740 2.75 2.713 2.705 2.70 2.665 2.657 2.65 2.616 2.609 2.60 2.568 2.562 2.55 2.520 2.514 2.50 2.472 2.467 2.45 2.423 2.419 2.40 2.375 2.371
Table 4-6. Enhanced voltage regulator output for different supply voltages.
4.3.3.2 Second-Stage Amplifier
Figure 4.35 shows the integrated second-stage amplifier response to a test waveform sinusoid of 10 mVpp, 500 Hz produced by a signal generator. The output of the amplifier is an inverted 400 mVpp, 500 Hz sine wave. The gain is thus -40, as designed.
94
Figure 4.35. Integrated second-stage amplifier output response to test waveform.
The output waveform is not biased at 1.5 V (common-mode level), however, and is instead biased at 2.2 V. This is an unusual result, and the cause of the problem has not yet been discovered. Also, the raised bias level and the strong 60-Hz interference in the setup has thus far made it impossible to obtain an accurate gain vs. frequency or noise vs. frequency characteristic curve.
4.3.3.3 Analog-to-Digital Converter
The output of the analog-to-digital converter (top trace) is shown with the byte synchronization signal (Byte_Syn, bottom trace) in Figure 4.36 and with the bit synchronization signal (Bit_Syn, bottom trace) in Figure 4.37. By design, the bits are inverted when they exit the ADC. The measured data rate is 62.5 kHz, as designed, and the frame alignment bits can easily be seen. As expected, Byte_Syn is low when the
ADC is outputting the frame alignment header and high when the ADC is outputting data, and Bit_Syn toggles has one period for each data bit that is output by the ADC.
95
Figure 4.36. ADC output (top trace) with byte synchronization signal (Byte_Syn, bottom trace).
Figure 4.37. ADC output (top trace) with bit synchronization signal (Bit_Syn, bottom trace).
96 4.3.3.4 Interleaved Recording
Figure 4.38 shows the channel select signal from the microcontroller toggling
each time the byte synchronization signal (Byte_Syn) transitions from high to low during
interleaved recording. This ensures that the analog input for alternate samples of the
ADC is properly synchronized.
Figure 4.38. Channel select signal (top trace) toggling on each high-to-low transition of the Byte_Syn signal (bottom trace) during interleaved recording.
The external transceiver is not yet ready to receive data from two channels. The present transceiver does not convert a single data stream into two separate data streams, one for each channel. The advanced prototype does not provide a marker to differentiate data from channel A and channel B, but channel A is always first following blanking.
4.3.3.5 FSK Transmitter
The VCO spectrum of the advanced prototype is shown in Figure 4.39. The VCO was tuned to a center frequency of 54.24 MHz to correspond with the 27.12-MHz frequency band. This was done by adjusting the variable capacitors, Ctrim and Cfine,
97 accordingly. Given the same antenna orientation as in the tests of the basic device, the spectrum is much more powerful than that of the basic implant device, so the VCO inductor could potentially be used as the FSK antenna if tuned to 27.12 MHz. The bandwidth is greater than the expected 640 kHz and might be too wide for the host transceiver to properly receive data. The excess bandwidth may be due to improper sizing of the internal capacitor used to generate the mark and space frequencies.
Figure 4.39. Advanced prototype VCO spectrum at resonance.
4.3.3.6 Reference Generator
The output voltages of the advanced prototype reference generator for various supply voltages are listed in Table 4-7. The measured voltages are slightly higher than the simulated values for nominal supply voltages of 2.75-3.30 V, as in the basic 2- channel ASIC. The ADC reference voltage is also slightly higher, about 1.35 V, but
98 variation over the supply range is just 8 mV, corresponding to an ADC gain variation of
0.6%.
Supply Voltage (V) Vr- (V) Vcmref (V) Vr+ (V) ΔVr (V) 3.30 0.774 1.519 2.128 1.354 3.25 0.773 1.518 2.127 1.354 3.20 0.773 1.518 2.126 1.353 3.15 0.773 1.517 2.126 1.353 3.10 0.772 1.517 2.125 1.353 3.05 0.772 1.517 2.125 1.353 3.00 0.772 1.517 2.124 1.352 2.95 0.772 1.516 2.123 1.351 2.90 0.772 1.516 2.123 1.351 2.85 0.772 1.516 2.122 1.350 2.80 0.772 1.516 2.121 1.349 2.75 0.772 1.516 2.118 1.346 2.70 0.772 1.515 2.114 1.342 2.65 0.771 1.515 2.109 1.338 2.60 0.771 1.514 2.105 1.334 2.55 0.771 1.514 2.099 1.328 2.50 0.770 1.513 2.093 1.323 2.45 0.770 1.512 2.085 1.315 2.40 0.769 1.512 2.075 1.306
Table 4-7. Advanced prototype reference generator output for various supply voltages.
4.3.4 Supply Current
Table 4-8 shows the current drawn by each component of the advanced prototype.
The prototype draws 5.32 mA of total current from the battery, which is much less than the 10-mA load for which the voltage regulator is designed. As expected, the ASIC is the most power hungry component again, though the enhanced ASIC draws significantly less power (almost half) than the basic version. The PIC draws more current in the advanced prototype than in the basic version due to the larger package size used.
99 Component Current Draw (mA) PIC 1.67 OOK Receiver 1.40 ASIC 2.25 Total 5.32
Table 4-8. Advanced prototype current draw by component.
100 5. Conclusion
5.1 Achievements
In this work, two dual-channel wireless neural recording and stimulation devices
are presented, a basic implantable version and an advanced prototype. This research is
based upon previous work done at CWRU by Chestek, et al.
The basic implant has two channels for neural recording and stimulation. It is
capable of recording neural signals with magnitudes as large as 330 uV, and the system
has a calculated input-referred noise of 3.4 µVrms. An integrated 8-bit ADC converts the
analog neural data into a digital stream, which is then Manchester encoded and frequency-shift-key (FSK) modulated at 27.12 MHz, before being transmitted to the host transceiver.
The implant receives 125-kHz on-off-keyed (OOK) commands from the host transceiver, which allow the user to change record channels, program stimulation parameters, and trigger stimulus. The user may select the magnitude, polarity, duration, frequency, number of pulses, and delay after trigger of the stimulus.
The basic implant is implemented using a basic 2-channel ASIC having a die size of 1.5 mm x 1.5 mm, and four other major components on a small printed circuit board.
The encapsulated device measures 4.5 cm x 1.8 cm x 1.8 cm. It is powered by a 3-V
lithium ion battery and consumes 21.3 mW of power.
The advanced prototype also has two channels for neural recording and
stimulation. Along with several circuit improvements, the advanced prototype has
integrated second-stage amplifiers and record channel multiplexer, and provides support
for on-board data processing, i.e. spike detection and data compression. It is
101 implemented using an enhanced 2-channel ASIC, also with die size 1.5 mm x 1.5 mm, and two other major components on a larger prototype printed circuit board, measuring
9.65 cm x 6.35 cm. It is powered by a 3-V lithium ion battery and consumes 16 mW of
power.
The electrical performance of the basic version has been measured and compared
to calculations and simulation results. In vitro and in vivo animal experiments are
reported. Basic functionality of the advanced prototype has been tested.
Table 5-1 compares the achievements of this work to other research in wireless
neural recording and stimulation technology. Despite the low channel count, this work is
the only effort to combine neural recording and stimulation capabilities into one device,
and does it so without consuming large amounts of power. The tradeoff is lesser noise
performance.
102
Table 5-1. Comparison of similar neural recording and stimulation technology research.
103
5.2 Future Work
The following improvements for future work on the basic 2-channel implant are suggested.
1. A better magnetic reed switch must be found. The current magnetic switch is not
very reliable, and has a high failure rate.
2. Additional animal testing should be performed with the new inductive data
antenna. An improvement in transmission distance should be seen.
The following improvements for future work on the advanced 2-channel prototype are suggested.
3. The data compression and spike detection algorithm should be implemented in the
microcontroller.
4. The source of the noise on the FSK spectrum (not presented) should be
discovered and the underlying cause resolved.
5. The cause of the raised bias level at the output of integrated second stage
amplifiers should be discovered and the underlying problem resolved.
6. An implantable version of the advanced 2-channel prototype should be developed.
The following improvements for general future work are suggested.
7. The error with the internal OOK receiver circuit on the enhanced ASIC has been
fixed, and the updated design should be incorporated into future ASIC revisions.
8. A battery recharge circuit should be developed in order to allow for long term
implantations.
104 Appendix A: Basic 2-Channel Implant Schematic
Figure A.1. Basic 2-channel implant schematic.
105 Appendix B: Basic 2-Channel Implant PCB Layout
Plus signs and minus signs indicate connections to the internal power and ground layers, respectively. The silkscreen is not shown. It clutters the layout, and no silkscreen
appears on the actual PCB.
Figure B.1. Basic 2-channel implant PCB layout, top and bottom layer.
106
Figure B.2. Basic 2-channel implant PCB layout, top layer.
107
Figure B.3. Basic 2-channel implant PCB layout, bottom layer.
108 Appendix C: Advanced 2-Channel Prototype Schematic
Figure C.1. Advanced 2-channel prototype schematic.
109 Appendix D: Advanced 2-Channel Prototype Layout
No silkscreen appears on the actual PCB.
Figure D.1. Advanced 2-channel prototype PCB layout, silkscreen, top, and bottom layers.
110
Figure D.2. Advanced 2-channel prototype PCB layout, silkscreen layer.
111
Figure D.3. Advanced 2-channel prototype PCB layout, top layer.
112
Figure D.4. Advanced 2-channel prototype PCB layout, bottom layer.
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[51] MLX90125 Datasheet, Melexis NV, 2002.
[52] “Manchester code,” Wikipedia. 2008. Wikimedia Foundation, Inc. 28 April 2008.
[53] PIC18F1220/PIC18F1320 Datasheet, Microchip Technology Inc., Chandler, AZ, 2002.
[54] MPLAB® ICD In-Circuit Debugger User’s Guide, Microchip Technology Inc, Chandler, AZ, 2007.
[55] Private communications with Daniel Howe
[56] Private communications with Dr. Hillel J. Chiel and Miranda Cullins
[57] CR1/3N Datasheet, Sanyo Electric Co., Ltd., 2008.
[58] MK6 Series Datasheet, MEDER Electronic, Germany, 2008.
[59] ExpressPCB, 2008.
[60] MPLAB® IDE User’s Guide, Microchip Technology Inc, Chandler, AZ, 2006.
[61] MPLAB® C18 C Compiler User’s Guide, Microchip Technology Inc, Chandler, AZ, 2005.
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