Fully Reused VLSI Architecture of Differential Manchester Encoding Using SOLS Technique for DSRC Application B

ISSN 2319-8885 Vol.06,Issue.24 July-2017,

Pages:4770-4773

www.ijsetr.com

Fully Reused VLSI Architecture of Differential Manchester Encoding Using SOLS Technique for DSRC Application B. TEJASWINI1, B. VAMSI KRISHNA2 1PG Scholar, Dept of ECE, Gudlavalleru Engineering College, Gudlavalleru, AP, India, Email: [email protected]. 2Assistant Professor, Dept of ECE, 2Gudlavalleru Engineering College, Gudlavalleru, AP, India, Email: [email protected].

Abstract: The Encoding techniques has received great attention in last few years due to their ability to reduce the power dissipation which is the main requirement in low power VLSI design. The dedicated short-range communication (DSRC) is an emerging technique to push the intelligent transportation system into our daily life. This paper proposes a Differential Manchester encoding using Similarity Oriented logic Simplification(SOLS) technique. This SOLS technique is based on two core methods 1)Area compact retiming 2)Balance logic operation sharing .The designed encoding technique has high hardware utilization rate. In addition to that the designed technique is better than the existing counterparts in terms of power consumption, delay. The designed technique is modeled using Verilog HDL and functionality is verified with Xilinx ISE 13.1.

Keywords: DSRC, SOLS, VLSI, Manchester, Encoding.

I. INTRODUCTION II. FM0 AND DIFFERENTIAL MANCHESTER Differential Manchester encoding is a line code in CODING PRINCIPLES which data and clock signals are combined to form a self A. FM0 Encoding synchronizing data stream. In various specific applications, The coding principle of FM0 is listed as the following this line code is also called by various other names, three rules. including BiphaseMark Code(BMC), Frequency Modulation  If X is the logic-0, the FM0 code must exhibit a (FM).This SOLS consists of two core methods, area compact transition between A and B. retiming and Balance logic operation sharing. The dedicated  If X is the logic-1, no transition is allowed between A short-range communication (DSRC) is a protocol for one- or and B. two-way medium range communication especially for  The transition is allocated among each FM0 code no intelligent transportation systems. The DSRC can be briefly matter what the X. classified into two categories: automobile-to-automobile and automobile-to-roadside. In automobile-to-automobile. This paper proposes Differential Manchester encoding using SOLS technique designed with no.of logic gates. This SOLS technique based on two core methods 1)area compact retiming 2)Balance logic operation sharing. The area- compact retiming relocates the hardware resource to reduce Fig.1. code word structure of FM0 22 transistors.The balance logic-operation sharing efficiently combines FM0 and Manchester encodings with the fully A FM0 coding example is shown in Fig. 2. At cycle 1, the reused hardware architecture. With SOLS technique, this X is logic-0; therefore, a transition occurs on its FM0 code, paper constructs a fully reused VLSI architecture of according to rule 1. For simplicity, this transition is initially Manchester and FM0 encodings for DSRC application. In set from logic-0 to -1. According to rule 3, a transition is the proposed technique different types of logic gates, flip allocated. flops, multiplexers are used.. This paper is organized as follows. Section II deals with the FM0 and Differential Manchester encoding principles, Section III shows the proposed designs of Differential Manchester encoding with SOLS and without SOLS techniques respectively. Section IV deals with results and Finally, conclusion is presented in Section V.

Fig2. Illustration of FM0 encoding example.

B. TEJASWINI, B. VAMSI KRISHNA B. Differential Manchester encoding  If the high and low signal levels have the same The Differential Manchester encoding example is shown magnitude with opposite polarity, the average voltage in fig.3 which represents the data are represented not by around each unconditional transition is zero. Zero DC logic 1 or 0 but with transitions. bias reduces the necessary transmitting power,  A logic ‘0’ is represented by a transition from HIGH- minimizes the amount of electromagnetic noise LOW. produced by the transmission line, and eases the use of  A logic ‘1’ is represented by a transition from LOW- isolating transformers. HIGH.

Fig.3. Illustration of Differential Manchester encoding example.

III. DIFFERENTIAL MANCHESTER ENCODING TECHNIQUES 1. Design of Differential Manchester encoding without Fig.4. Hardware architecture for Differential Manchester SOLS technique. encoding without SOLS technique. 2. Design of Diffrential Manchester encoding with SOLS technique. Fig.4 represents the Hardware architecture for Differential Manchester encoder without SOLS technique. The upper Differential Manchester encoding is a line code in which part in the architecture represents FM0 logic and the bottom data and clock signals are combined to form a single 2-level part of architecture represents Differential Manchester logic. self-synchronizing data stream. In various specific Here two logics are performed depends on mode selection. If applications, this line code is also called by various other mode is ‘0’ then FM0 logic is activated otherwise names, including Biphase Mark Code (BMC), Frequency Differential Manchester logic is activated. if one logic is in Modulation (FM), F2F (frequency/double frequency), active state then rest of the logic is in deactivate state, so AikenBiphase, and Conditioned diphase. It is a differential some of the components is not in active mode so here the encoding, using the presence or absence of transitions to HUR rate only 60%. Flip flop here are used to store the state indicate logical value. It is not necessary to know the code of FM0 code, mux1 acts as switch through the selection polarity of the sent signal since the information is not of clock signal and mux2 determines which code is adopted represented by the absolute voltage levels but in their depends on “mode” selection. changes: in other words it does not matter which of the two voltage levels is received, but only whether it is the same or different from the previous one; this makes synchronization easier.

Differential Manchester encoding has the following advantages over some other line codes:  A transition is guaranteed at least once every bit, for robust clock recovery.  In a noisy environment, detecting transitions is less error-prone than comparing signal levels against a . threshold. Fig5. Hardware architecture for Differential Manchester  Unlike with Manchester encoding, only the presence of encoding with SOLS technique. a transition is important, not the polarity. Differential coding schemes will work exactly the same if the signal Fig.5 represents the Hardware architecture for Differential is inverted (e.g. wires swapped). Other line codes with manchester encoder with SOLS technique. Here also two this property include NRZI, bipolar encoding, coded logic operations performed depends on mode selection but in mark inversion, and MLT-3 encoding. this operation all the components are in active state during International Journal of Scientific Engineering and Technology Research Volume.06, IssueNo.24, July-2017, Pages: 4770-4773 Fully Reused VLSI Architecture of Differential Manchester Encoding Using SOLS Technique for DSRC Application both logic operations. So here the HUR rate is 100%, so this The fig.8 shows the Simulation results for the Differential is the drawback overcome here compared to above design. Manchester encoding with SOLS technique . here inputs like Xin, clock, reset, and mode which produces output as out.

if mode is ‘0’ then FM0 logic performes and if mode is ‘1’ the Differential Manchester logic performs.

IV. RESULTS AND DISCUSSION The designed encoding techniques are designed using verilog HDL. The functionality is using Xilinx ISE 13.1. The simulated wave forms of Differential Manchester encoding with SOLS technique and without SOLS technique are shown below. The fig.6 shows the Simulation results for Differential Manchester encoding without SOLS technique. Here inputs like x, mode, reset and clock produces an output as out. Fig8. Simulation waveforms of Differential Manchester encoding with SOLS technique.

The Fig.9 shows the RTL view of Differential Manchester encoding with SOLS technique which has the logic gates acts as major elements with better output.

Fig.6. Simulation waveforms of Differential Manchester encoding without SOLS technique.

The fig.7 shows the RTL view of Differential Manchester encoding without SOLS technique which has the major elements are logic gates, flip flops and multiplexers.

Fig9. RTL schematic for Differential Manchester encoding with SOLS technique.

Table.1: Comparison table for Differential Manchester encoding using without and with SOLS technique with parameters like HUR, Power and Delay.

Fig7. RTL schematic for Differential Manchester encoding without SOLS technique. International Journal of Scientific Engineering and Technology Research Volume.06, IssueNo.24, July-2017, Pages: 4770-4773

B. TEJASWINI, B. VAMSI KRISHNA V. CONCLUSION transactions on very large scale integration (vlsi) systems, By this Differential Manchester encoding technique using vol. 23, no. 1, january 2015. SOLS technique the Parameters like Power and Delay are [13]H. Zhou and A. Aziz, “Buffer minimization in pass reduced and in addition to that Hardware Utilization rate transistor logic,” IEEE Trans. Comput. Aided Des. Integr. increases, by this SOLS technique the architecture is fully Circuits Syst. , vol. 20, no. 5, pp. 693–697, May 2. reused, and the logic gates used in architecture which improves the performance. The designed encoding techniques are designed using verilog HDL.

VI. REFERENCES [1] Yu-Hsuan Lee, Member, IEEE, and Cheng-Wei Pan “Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications” Yu-Hsuan Lee, Member, IEEE, and Cheng-Wei Pan, January 2015. [2] F. Ahmed-Zaid, F. Bai, S. Bai, C. Basnayake, B. Bellur, S. Brovold,et al., “Vehicle safety communicate on Applications (VSC-A) final report,” U.S. Dept. Trans., Nat. Highway Traffic Safety Admin., Wash- ington, DC, USA, Rep. DOT HS 810 591, Sep. 2011. [3] J. B. Kenney, “Dedicated short-range communications (DSRC) standards in the United States,” Proc. IEEE , vol. 99, no. 7, pp. 1162–1182, Jul. 2011. [4]J. Daniel, V. Taliwal, A. Meier, W. Holfelder, and R. Herrtwich, “Design of 5.9 GHz DSRC-based vehicular safety communication,” IEEE Wireless Commun. Mag. , vol. 13, no. 5, pp. 36–43, Oct. 2006 [5]P. Benabes, A. Gauthier, and J. Oksman, “A Manchester code generator running at 1 GHz,” in Proc. IEEE, Int. Conf. Electron., Circuits Syst. , vol. 3. Dec. 2003, pp. 1156–1159. [6]A. Karagounis, A. Polyzos, B. Kotsos, and N. Assimakis, “A 90nm Manchester code generator with CMOS switches running at 2.4 GHz and 5 GHz,” in Proc. 16th Int. Conf. Syst., Signals Image Process. , Jun. 2009, pp. 1–4. [7]Y.-C. Hung, M.-M. Kuo, C.-K. Tung, and S.-H. Shieh, “High-speed CMOS chip design for Manchester and Miller encoder,” in Proc. Intell. Inf. Hiding Multimedia Signal Process. , Sep. 2009, pp. 538–541. [8]M. A. Khan, M. Sharma, and P. R. Brahmanandha, “FSM based Manchester encoder for UHF RFID tag emulator,” in Proc. Int. Conf. Comput., Commun. Netw. , Dec. 2008, pp. 1–6. [9]M. A. Khan, M. Sharma, and P. R. Brahmanandha, “FSM based FM0 and Miller encoder for UHF RFID tag emulator,” in Proc. IEEE Adv. Comput. Conf. , Mar. 2009, pp. 1317– 1322. [10]J.-H. Deng, F.-C. Hsiao, and Y.-H. Lin, “Top down design of joint MODEM and CODEC detection schemes for DSRC coded-FSK systems over high mobility fading channels,” in Proc. Adv. Commun. Technol.Jan. 2013, pp. 98–103. [11]I.-M. Liu, T.-H. Liu, H. Zhou, and A. Aziz, “Simultaneous PTL buffer insertion and sizing for minimizing Elmore delay,” in Proc. Int. Workshop Logic Synth. , May 1998, pp. 162–168. [12] Hsuan Lee, Member, IEEE, and Cheng-Wei Pan “Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications” ieee

International Journal of Scientific Engineering and Technology Research Volume.06, IssueNo.24, July-2017, Pages: 4770-4773