Lecture 14

FET Current and Voltage Sources and Current Mirrors

The Building Blocks of Analog Circuits - IV

In this lecture you will learn:

• Current and voltage sources using FETs • FET current mirrors • Cascode current mirror • Double Wilson current mirror • Active biasing schemes

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Motivation Questions:

• Are there better ways to realize on-chip current sources to bias circuits? • Are there good ways to generate on-chip voltage levels to bias circuits?

VDD VDD

VB1 IBIAS Using large resistors too often is not a good idea VB2 in integrated chips

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

1 Characteristics of Ideal Current Sources and Sinks

Ideal Current Sources: IOUT IOUT roc=∞ + I VOUT I I roc - VOUT

One can have any voltage at the at the output terminals of an ideal current source and the current delivered will remain constant The output resistance of an ideal current source is infinity

Ideal Current Sinks: IOUT IOUT roc=∞ + I VOUT I I roc - VOUT

One can have any voltage at the at the output terminals of an ideal current sink and the current sinked will remain constant The output resistance of an ideal current sink is infinity

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Characteristics of Ideal Voltage Sources

Ideal Voltage Sources: IOUT rov=0

IOUT + r V ov VOUT V V - V OUT

One can draw any current from an ideal voltage source and the voltage at the output terminals will remain constant

The output resistance of an ideal voltage source is zero

Non-Ideal Voltage Sources: IOUT r ≠ 0 ov 1 slope =  IOUT rov + r V ov VOUT V V - V OUT

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

2 A FET Voltage Source: Large Signal Analysis

• Assume for the moment that we have a current source IREF

VDD If VOUT > VTN : k I  I  I  n V V 2 1  V  I REF D OUT 2 OUT TN n OUT OUT I REF 2IREF  IOUT  VOUT  VTN  if nVOUT  1 kn Slope ID IOUT I dI OUT OUT  g  k V V dV m n OUT TN + IREF OUT VOUT -

VTN VOUT Non-Ideal Voltage Source IOUT • The line can be made more vertical and the voltage 1 slope =  source more ideal by increasing the value of gm rov

V VOUT

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

A FET Voltage Source: Large Signal Analysis VDD 2IREF  IOUT VOUT  VTN  W L nCox

IREF dIOUT W  gm   nCox VOUT VTN dVOUT L

ID IOUT IOUT + V Increasing (W/L) OUT IREF -

VOUT VTN

• If the (W/L) ratio of the FET is made very large, the output voltage VOUT is fixed at approximately VTN for all values of the current IOUT drawn from the source (provided IOUT < IREF)

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

3 A FET Voltage Source: Small Signal Analysis

VDD roc Small signal I REF roc roc (Ideal) + -

Need to find the resistance rov looking into from the output terminals Small signal model

rov

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

A FET Voltage Source: Small Signal Analysis

ig Gate Drain id 0 roc + v gs r r g v o oc - m gs gmbvbs Source + - - vbs Base +

Small signal model Need to find the resistance rov looking into from the output terminals

rov

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

4 A FET Voltage Source: Small Signal Analysis

ig Gate Drain id

roc gm ro roc

Source + - - vbs Base Small signal resistance looking into the voltage + source is: 1 r  1 g || r || r  Generally small ov m o oc g rov m if gm is large

We have a voltage source that:

• Gives a DC voltage VOUT adjustable by changing the value of IREF , and • Has an incremental or small signal resistance rov approximately equal to 1/gm (which can be pretty small)

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

A FET Voltage Source: Simplest Implementation of IREF V DD If VOUT > VTN : V V k DD OUT  I  I  n V V 2  I R D OUT 2 OUT TN OUT R 1 2V V R  I 1  V  V   DD TN OUT  OUT TN 2 2 knR kn knR ID I OUT Slope when R is much larger than 1/gm IOUT dIOUT  gm  kn VOUT VTN VOUT VDD dVOUT R

Slope VOUT dIOUT 1   VTN dVOUT R

• If the (W/L) ratio of the FET is made very large and R is much larger than 1/gm , the output voltage VOUT is fixed at approximately VTN for all values of the current IOUT drawn from the source - provided IOUT < (VDD - VTN)/R

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

5 FET Voltage Sources One can produce multiple voltage levels from the same structure using NMOS FETs, PMOS FETs, and combination of both NMOS and PMOS FETs

VDD VDD VDD

IREF

V1 V1

I M1 1 V1 V2 V2

I2 M2 V2 IREF V3

IREF 2IREF  I1 V1  V2 VTN1  kn1

2IREF  I1  I2 But ………need to be careful about the small signal V2  VTN2  resistances associated with each voltage output! kn2

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

FET Voltage Sources: Small Signal Analysis

Gate Drain id1 roc + v gs1 ro1 roc - gm1v gs1 Source rov1

Gate Drain id 2 rov 2 + vgs2 ro2 - gm2vgs2 Source

Find the resistance looking into the first voltage source assuming the second one is incrementally open (why?)

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

6 FET Voltage Sources: Small Signal Analysis

Gate Drain id1 r oc g m1 ro1 roc

Source rov1

Gate Drain rov 2

gm2 ro2

Source

Find the resistance looking into the first voltage source assuming the second one is incrementally open (why?)

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

FET Voltage Sources: Small Signal Analysis

Gate Drain id1 roc gm1 ro1 roc

Source rov1 gm2

rov 2

1 1 rov1   Small gm1 gm2

Find the resistance looking into the first voltage source assuming the second one is incrementally open (why?)

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

7 FET Voltage Sources: Small Signal Analysis

Gate Drain id1 roc + v gs1 ro1 roc - gm1v gs1 Source rov1

Gate Drain id 2 rov 2 + vgs2 ro2 - gm2vgs2 Source Then find the resistance looking into the second voltage source assuming the first one is incrementally open (why?) 1 rov 2  Small gm2

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

A FET Current Sink: Large Signal Analysis

• Assume that we have a single current source IREF - but we want more………

VDD VGS2  VGS1 kn2 W L 2 Assuming  ID2  ID1  ID1 I k W L M2 is in IREF OUT n1 1 saturation W L 2 +  IOUT  IREF W L 1 ID1 I D2 Slope V OUT dI 1 IOUT OUT  dVOUT ro2 M1 M2 - W L 2 IREF W L 1

In saturation: k VOUT I  n V V 2 1  V D 2 GS TN n DS W Small kn  nCox • Not exactly the horizontal line of an ideal L current source but good enough for many practical applications

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

8 A FET Current Mirror • A ideal current mirror duplicates the current: IOUT  IREF VGS2  VGS1

VDD Matched W L 2  W L 1 Transistors I IREF OUT  IOUT  IREF + I D1 ID2 Slope VOUT I dI 1 OUT OUT  dVOUT ro2 M1 M2 - IREF

A matched transistor pair

VOUT VGS1

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

A FET Current Sink: Small Signal Analysis i rocref Gate Drain d 2 + + vgs2 ro2 - gm2vgs2 Source -

Gate Drain id1 + r v oc gs1 ro1 rocref - gm1v gs1

1 Source roc  ro2  go2 We have a current sink that:

• Provides a DC current IOUT adjustable by changing the value of IREF , and • Has an incremental or small signal resistance roc approximately equal to ro2 (which can be pretty large)

• The resistance roc will become small if M2 goes into the linear region

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

9 Multiple NFET Current Sinks VDD

V VOUT 3 V V IREF OUT 2 OUT 4 OUT 5

I D1 ID2 ID3 ID4 ID5

M1 M2 M3 M4 M5

One can realize multiple current sinks for biasing applications from the same structure using NMOS devices with different (W/L) ratios:

W L k IDk  IREF W L 1

Note that VOUTk needs to be always large enough such that Mk remains in saturation

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

A PFET Current Source and Current Mirror • A current mirror duplicates the current:

IOUT  IREF VGS2  VGS1

V V Matched DD DD W L 2  W L 1 Transistors

M1 M2  IOUT  IREF

Slope ID1 ID2 VOUT + I dI 1 OUT OUT   dVOUT ro2 IOUT IREF IREF

A matched transistor pair VOUT VSG1  VGS1 VDD

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

10 Multiple PFET Current Sources VDD VDD VDD VDD VDD

M1 M2 M3 M4 M5

ID1 ID2 ID3 ID4 ID5

I I OUT 2 OUT 3 IOUT 4 IOUT 5 IREF VOUT 2 VOUT 3 VOUT 4 VOUT 5

One can realize multiple current sources for biasing applications from the same structure using PMOS devices with different (W/L) ratios:

W L k IOUTk  IREF W L 1

Note that VOUTk needs to be always small enough such that Mk remains in saturation

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

A Current Sink with Large Output Resistance: The Cascode Design

VDD VDD

I I IREF OUT IREF OUT

+ + I I D1 ID2 D1 ID3 VOUT

V M1 M2 - M1 M3 OUT I D2 ID4

1 roc  ro2  M2 M4 go2 -

roc  ro3  ro4 1 gm3ro3   gm3ro3ro4

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

11 A Current Sink with Large Output Resistance: The Cascode Design

VDD

I Usually the substrate contact of all IREF OUT NFETs in the stack are tied to the ground in CMOS technologies in + which all NFETs share the same I D1 ID3 substrate

Need to account for the body effect V (due to non-zero VSB) in M3 M1 M3 OUT I D2 ID4

M2 M4 -

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

The Double Wilson Current Mirror

VDD

More immune to systemic errors in I IOUT the fabrication process than the REF cascode design + I D1 ID3

M1 M3 VOUT I D2 ID4

M2 M4 -

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

12 A PFET Current Source: The Cascode Design

VDD VDD VDD VDD

M1 M2 M2 M4

ID1 ID2 V OUT I I + D1 D4 M1 M3 IOUT IREF

VOUT ID1 ID3 + 1 r  r  I oc o2 g OUT o2 IREF

roc  ro3  ro4 1 gm3ro3   gm3ro3ro4

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

A PFET Current Source: The Cascode Design

VDD VDD

Usually the substrate contact of all M2 M4

PFETs in the stack are tied to VDD in CMOS technologies in which all PFETs share the same substrate ID1 ID4 Need to account for the body effect M1 M3 (due to non-zero VSB) in M3

ID1 ID3 VOUT +

IOUT IREF

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

13 Biasing the PFET Loaded NFET CS Amplifier

VDD VDD

PFET cascode Current source load VB3 IBIAS

VB2

ID ID RS RS + + + + V  v V  v v s OUT out v s OUT out - - + - + - VBIAS VBIAS - -

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Biasing the PFET Loaded NFET CS Amplifier V VDD DD

Voltage biasing network Matched pairs PFET cascode If M4 and M5 are M4 M5 load identical and M3 and M6 are Matched pairs identical (matched

pairs) then ID7 will equal IREF and the M3 M6 gate voltages needed for M5 and M6 will be automatically ID7 RS generated on the IREF + chip without exact + V  v knowledge of the v s OUT out k and V of the - M7 p TP + - PFETs VBIAS -

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

14 Biasing the PFET Loaded NFET CS Amplifier V VDD DD

Matched pairs PFET cascode V DD M4 M5 load Matched pairs IREF

M3 M6

ID1 ID2  ID7 ID7 RS + + V  v v s OUT out M1 M2 - M7 + - VBIAS -

NFET current sink

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Biasing the PFET Loaded NFET CS Amplifier V VDD DD

Matched pairs

VDD PFET cascode M4 M5 load Matched pairs R M3 M6

ID1 ID7 RS + + V  v v s OUT out M1 M2 - M7 + - VBIAS -

NFET current sink

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

15 Biasing the PFET Loaded NFET CS Amplifier

V VDD PFET cascode DD current source

Matched pairs

M4 M5

Matched pairs

M3 M6

ID7 RS I  I + REF D7 + V  v v s OUT out - M7 + - VBIAS -

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Biasing the PFET Loaded NFET CS Amplifier

VDD So we implemented a current source load using the PFETs in a cascode configuration Current source

IBIAS

ID7 RS + + V  v v s OUT out - M7 + - VBIAS -

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

16 ECE 315 – Spring 2007 – Farhan Rana – Cornell University

17