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Intel® Quick Sync Video Technology Guide
WP80 Superguide 3: THE CLOUD VIDEO SUPERGUIDE JANUARY/FEBRUARY 2015 SPONSORED CONTENT Intel® Quick Sync Video Technology and Intel® Xeon® Processor Based Servers— Flexible Transcode Performance and Quality Video transcoding involves converting provides enterprise-quality HEVC and and boost image quality. Some key one compressed video format to audio codecs, Intel® VTune™ Amplifier improvements include the following: another. In the past this process has XE performance analysis tools and Video • Additional JPEG/MJPEG decode in been a compute-intensive task which Quality Caliper stream quality analyzer. the multi-format codec engine. This demanded a large amount of precious Additionally, product family members, support is on top of existing energy- CPU resources. Intel® Quick Synch Video Intel® Video Pro Analyzer and Intel® efficient, high-performance AVC (QSV) can enable hardware-accelerated Stress Bitstreams and Encoder bundles encode/decode that sustains multiple transcoding to deliver better performance enable production–scale validation and 4K and Ultra HD video streams. than transcoding on the CPU without debug of encode, transcode, and decode • A dedicated new video quality engine sacrificing quality. and playback applications. to provide extensive video processing First introduced in 2011, Intel Quick Intel Media Server Studio SDK at low power consumption Sync technology is available in the Intel® implements many codec and tools • Programmable and media-optimized Xeon® Processor E3-1200 v3 with Intel components initially in software, and EU (execution units)/samplers for HD Graphics P4600/4700 and Iris™ Pro later as hybrid (software and hardware) high quality P5200. (From here on, we’ll simply refer to or entirely in hardware. -
GPU Developments 2018
GPU Developments 2018 2018 GPU Developments 2018 © Copyright Jon Peddie Research 2019. All rights reserved. Reproduction in whole or in part is prohibited without written permission from Jon Peddie Research. This report is the property of Jon Peddie Research (JPR) and made available to a restricted number of clients only upon these terms and conditions. Agreement not to copy or disclose. This report and all future reports or other materials provided by JPR pursuant to this subscription (collectively, “Reports”) are protected by: (i) federal copyright, pursuant to the Copyright Act of 1976; and (ii) the nondisclosure provisions set forth immediately following. License, exclusive use, and agreement not to disclose. Reports are the trade secret property exclusively of JPR and are made available to a restricted number of clients, for their exclusive use and only upon the following terms and conditions. JPR grants site-wide license to read and utilize the information in the Reports, exclusively to the initial subscriber to the Reports, its subsidiaries, divisions, and employees (collectively, “Subscriber”). The Reports shall, at all times, be treated by Subscriber as proprietary and confidential documents, for internal use only. Subscriber agrees that it will not reproduce for or share any of the material in the Reports (“Material”) with any entity or individual other than Subscriber (“Shared Third Party”) (collectively, “Share” or “Sharing”), without the advance written permission of JPR. Subscriber shall be liable for any breach of this agreement and shall be subject to cancellation of its subscription to Reports. Without limiting this liability, Subscriber shall be liable for any damages suffered by JPR as a result of any Sharing of any Material, without advance written permission of JPR. -
Keepixo’S Genova Live:Speed Is the Latest Addition to Genova Virtualizable Software Family of Products
High Density Video Transcoding Keepixo’s Genova Live:Speed is the latest addition to Genova Virtualizable Software family of products. It runs on the Kontron SYMKLOUD platform and leverages Intel’s Quick Sync Video (QSV) technology to dramatically increase transcoding density; minimize power consumption while meeting professional service grade levels. Media Processing Acceleration Genova Live:Speed The explosive growth of Internet video traffic has put Keepixo worked with Kontron to leverage the Kontron pressure on video transcoding infrastructures to SYMKLOUD Converged Infrastructure platform and optimize bandwidth, power consumption and cost of developed a comprehensive package that optimizes the operations. High density transcoding solutions such as performance of QSV and allows smooth deployment of Intel’s Quick Sync Video technology have emerged to highly dense transcoding infrastructures comprising of address these challenges. They introduce various levels hundreds of services. of HW acceleration to off-load computationally intensive tasks. Initially targeted at consumer Keepixo selected the Kontron SymKloud MS2910 applications, high density transcoding has become a platform to implement its high density transcoding viable option for professional transcoding solution. The MS2910 platform comes in a 2U (21” infrastructures when included in suitable packages that depth) chassis, dual hot-swappable 10GbE switches, address the requirements of professional applications. and can accommodate up to 9 modular compute servers, each hosting 2 independent CPUs for a total of Intel Quick Sync Video (QSV) is available on a range of up to 18 CPUs per chassis. The SymKloud compute Intel i7 and Xeon E3 processors fitted with on-chip nodes can be of different mix-and-match processor graphics. -
SIMD Extensions
SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel. -
Rethinking Visual Cloud Workload Distribution
WHITE PAPER Media and Communications Content Creation and Distribution RethinkingVisualCloud WorkloadDistribution Creating a New Model With visual computing workloads growing at an accelerating pace, cloud service providers (CSPs), communications service providers (CoSPs), and enterprises are rethinking the physical and virtual distribution of compute resources to more effectively balance cost and deployment efficiency while achieving exceptional performance. Visual cloud deployments accommodate a diverse range of streaming workloads, encompassing media processing and delivery, cloud graphics, cloud gaming, media analytics, and immersive media. Contending with the onslaught of new visual workloads will require more nimble, scalable, virtualized infrastructures; the capability of shifting workloads to the network edge when appropriate; and a collection of tools, software, and hardware components to support individual use cases fluidly. Advanced network technologies and cloud architectures are essential for agile distribution of visual cloud workloads. A 2017 report, Cisco Visual Networking Index: Forecast and Methodology, 2016–2021, projected strong growth in all Internet and managed IP video- related sectors. Compound annual growth rate (CAGR) figures during this time span, calculated in petabytes per month, included these predictions: • Content delivery network (CDN) traffic: 44 percent increase globally • Consumer-managed IP video traffic: 19,619 petabytes per month (14 percent increase) by 2021 • Consumer Internet video: 27 percent increase for fixed, 55 percent increase for mobile The impact of this media growth on cloud-based data centers will produce a burden on those CSPs, CoSPs, and enterprises that are not equipped to deal with TableofContents large-scale media workloads dynamically. Solutions to this challenge include: Creating a New Model . 1 • Increasingflexibilityandoptimizingprocessing: Virtualization and software- defined infrastructure (SDI) make it easier to balance workloads on available OpenSourceSoftware resources. -
Intel® Quick Sync Video and Ffmpeg Installation and Validation Guide
White paper Intel® Quick Sync Video and FFmpeg Installation and Validation Guide Introduction Intel® Quick Sync Video technology on Intel® Iris™ Pro Graphics and Intel® HD graphics provides transcode acceleration on Linux* systems in FFmpeg* 2.8 and later editions. This paper is a detailed step-by-step guide to enabling h264_qsv, mpeg2_qsv, and hevc_qsv hardware accelerated codecs in the FFmpeg framework. For a quicker overview, please see this article. Performance note: The *_qsv implementations are intended to provide easy access to Intel hardware capabilities for FFmpeg users, but are less efficient than custom applications optimized for Intel® Media Server Studio. Document note: Monospace type = command line inputs/outputs. Pink = highlights to call special attention to important command line I/O details. Getting Started 1. Install Intel Media Server Studio for Linux. Download from software.intel.com/intel-media-server- studio. This is a prerequisite for the *_qsv codecs as it provides the foundation for encode acceleration. See the next chapter for more info on edition choices. Note: Professional edition install is required for hevc_qsv. 2. Get the latest FFmpeg source from https://www.FFmpeg.org/download.html. Intel Quick Sync Video support is available in FFmpeg 2.8 and later editions. The install steps outlined below were verified with ffmpeg release 3.2.2 3. Configure FFmpeg with “--enable –libmfx –enable-nonfree”, build, and install. This requires copying include files to /opt/intel/mediasdk/include/mfx and adding a libmfx.pc file. More details below. 4. Test transcode with an accelerated codec such as “-vcodec h264_qsv” on the FFmpeg command line. -
Liečba Firmy Krízovým Manažérom
SEPTEMBER- OKTÓBER 2016 Ročník VIII. Magazín o ekonomike, biznise a spoločnosti Cena: 2,20 € LIEČBA FIRMY KRÍZOVÝM MANAŽÉROM Neľahká cesta z červených do čiernych čísel Trendy a výzvy európskej logistiky Firemný blog: robte ho poriadne alebo vôbec Stalo sa, opravíte s naším poistením majetku. Poistenie majetku MÔJ DOMOV Postavte sa s odvahou všetkým nepred- vídaným situáciám, ktoré ohrozujú váš domov. Najoceňovanejšie poistenie majetku Môj domov ich za vás vyrieši rýchlo a fér. allianzsp.sk Infolinka 0800 122 222 VZDELÁVANIE Podchyťme všetky talenty, Magazín o ekonomike, biznise a spoločnosti lebo Európa ich potrebuje V deťoch sa ukrýva veľký potenciál, príliš často však zostáva nevyužitý. Registrované ako periodická tlač Ministerstvom kultúry Slovenskej To je niečo, čo si Európska únia jednoducho nemôže dovoliť: plytvanie republiky pod registračným číslom EV 3451/09, ISSN 1337-9798 ľudskými zdrojmi, ktoré robí ľudí nešťastnými a je takisto kolektívnym Vydanie september – október 2015 zlyhaním. Vydáva: Nemám pritom na mysli len nadanie na štúdium. Je načase uznať ši- Goodwill Publishing, s. r. o. rokú škálu talentu a zručností. Známe sú práce amerického výskumní- IČO: 44 635 770 LB)PXBSEB(BSEOFSB LUPSâJEFOUJmLPWBMWFĔBESVIPWJOUFMJHFODJFPE interpersonálnej po muzikálnu, od priestorovej po jazykovú, logickú Adresa redakcie: alebo intrapersonálnu. Azda všetci súhlasia s tým, že až príliš často sa GOODWILL, Nevädzová 5, 821 01 Bratislava talent hodnotí na základe pevných kritérií, ktoré neodrážajú jeho boha- UFMGBYtHPPEXJMM!HPPEXJMMFVTL tosť ani zložitosť. Musíme sa otvoriť koncepcii talentu a vidieť ďalej, za Ing. Juraj Filin študijné výsledky. Žiaľ, školy majú stále sklon sústrediť sa na úzku ideu šéfredaktor a konateľ spôsobilosti – na akademickú prácu. mMJO!HPPEXJMMFVTLtSFEBLDJB!HPPEXJMMFVTL Potrebujeme talenty pre vyššie vzdelávanie, ale aj pre oblasti odbor- tel.: 0907 78 91 64 ného vzdelávania a prípravy. -
The Economic Impact of Moore's Law: Evidence from When It Faltered
The Economic Impact of Moore’s Law: Evidence from when it faltered Neil Thompson Sloan School of Management, MIT1 Abstract “Computing performance doubles every couple of years” is the popular re- phrasing of Moore’s Law, which describes the 500,000-fold increase in the number of transistors on modern computer chips. But what impact has this 50- year expansion of the technological frontier of computing had on the productivity of firms? This paper focuses on the surprise change in chip design in the mid-2000s, when Moore’s Law faltered. No longer could it provide ever-faster processors, but instead it provided multicore ones with stagnant speeds. Using the asymmetric impacts from the changeover to multicore, this paper shows that firms that were ill-suited to this change because of their software usage were much less advantaged by later improvements from Moore’s Law. Each standard deviation in this mismatch between firm software and multicore chips cost them 0.5-0.7pp in yearly total factor productivity growth. These losses are permanent, and without adaptation would reflect a lower long-term growth rate for these firms. These findings may help explain larger observed declines in the productivity growth of users of information technology. 1 I would like to thank my PhD advisors David Mowery, Lee Fleming, Brian Wright and Bronwyn Hall for excellent support and advice over the years. Thanks also to Philip Stark for his statistical guidance. This work would not have been possible without the help of computer scientists Horst Simon (Lawrence Berkeley National Lab) and Jim Demmel, Kurt Keutzer, and Dave Patterson in the Berkeley Parallel Computing Lab, I gratefully acknowledge their overall guidance, their help with the Berkeley Software Parallelism Survey and their hospitality in letting me be part of their lab. -
Curtiss-Wright to Display Rugged COTS Modules and System Solutions at Intel Developer Forum 2016
NEWS RELEASE FOR IMMEDIATE RELEASE Contact: John Wranovics (925) 640-6402 Curtiss-Wright to Display Rugged COTS Modules and System Solutions at Intel Developer Forum 2016 INTEL DEVELOPER FORUM 2016 (IDF16) – SAN FRANCISCO, Calif. (Booth #329) – August 16-18, 2016 – Curtiss-Wright’s Defense Solutions division will highlight its industry-leading open architecture rugged commercial-off-the-shelf (COTS) processing modules and subsystems along with its OpenHPEC™ Accelerator Suite of High Performance Embedded Computing (HPEC) software development tools for the aerospace and defense market at Intel Developer Forum 2016 San Francisco (IDF16: Booth #329). Featured will be demonstrations of glass cockpit applications running on rugged Intel processing modules and the industry’s first VITA 48.8-compliant Air Flow Through (AFT) rugged OpenVPX™ chassis. Curtiss-Wright will also display its Intel® Xeon® processor D-based 3U VPX CHAMP-XD1 and 6U VPX CHAMP-XD2 Digital Signal Processor (DSP) modules, which bring supercomputing-class processing to very compute-intensive C4ISR aerospace and defense applications such as radar processing, Signal Intelligence (SIGINT), and Electronic Warfare (EW). The broad range of Intel-based rugged COTS solutions displayed will include: Rugged Single Board Computer and DSP Modules: 3U VPX and XMC Mobile Xeon processor E3 v5 Modules: At IDF16 Curtiss-Wright is introducing two new small form factor COTS Single Board Computers (SBCs) based on Intel’s latest generation Mobile Xeon processor E3 v5 (formerly known as “Skylake-H”). The new rugged modules, the 3U OpenVPX™ VPX3-1220 and XMC-121 XMC processor mezzanine card, feature a low-power version of the Xeon processor to provide high performance quad-core x86 processing with integrated graphics at typically 50% the power levels of previous solutions. -
System Design for Telecommunication Gateways
P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come SYSTEM DESIGN FOR TELECOMMUNICATION GATEWAYS Alexander Bachmutsky Nokia Siemens Networks, USA A John Wiley and Sons, Ltd., Publication P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come SYSTEM DESIGN FOR TELECOMMUNICATION GATEWAYS P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come SYSTEM DESIGN FOR TELECOMMUNICATION GATEWAYS Alexander Bachmutsky Nokia Siemens Networks, USA A John Wiley and Sons, Ltd., Publication P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come This edition first published 2011 C 2011 John Wiley & Sons, Ltd Registered office John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, United Kingdom For details of our global editorial offices, for customer services and for information about how to apply for permission to reuse the copyright material in this book please see our website at www.wiley.com. The right of the author to be identified as the author of this work has been asserted in accordance with the Copyright, Designs and Patents Act 1988. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, except as permitted by the UK Copyright, Designs and Patents Act 1988, without the prior permission of the publisher. -
H P Intel® Quick Sync Video Tec Nology on Intel® Iris™ Graphics
WHITE PAPER Intel Quick Sync Video Intel® Quick Sync Video Tech n ology on Intel® Iris™ Graphics and Intel® HD Grap h ics family—Flexible Transcode Performance an d Quality The 4th generation Intel® Core™ Processor introduces Intel® Iris™ Pro Graphics, Intel® Iris™ Graphics and Intel® HD Graphics (4200+ Series), featuring the newest iteration of Intel® Quick Sync Video technology. In addition, Intel Quick Sync technology is also available in the Intel Xeon® Processor E3-1200 v3 product family with Intel HD Graphics P4600/P4700. For the purposes of this whitepaper, we will refer simply to Intel Quick Sync technology. This advanced graphics solution sets a milestone in performance by delivering a blazingly fast transcode experience, and balances image quality and performance through a series of optimized user targets for easy adoption. This paper explains the changes in Intel Quick Sync Video transcode target usages, describes the new high-performance hardware acceleration engine, and sets performance and quality expectations for each target usage. Introduction In the past, transcoding has been a Video transcoding involves converting one compute-intensive task that demanded a compressed video format to another. The large amount of precious CPU resources. process can apply changes to the format, With multiple cores and more powerful such as moving from MPEG2 to H.264, or processors driving today’s systems, transcoding can change the properties of transcoding happens faster, and is a given format, like bit rate or resolution. commonly used to support the format Conversions cannot generally happen in a requirements of a whole range of video single step; rather, a series of transitions consumption devices. -
Processing Multimedia Workloads on Heterogeneous Multicore Architectures
Doctoral Dissertation Processing Multimedia Workloads on Heterogeneous Multicore Architectures H˚akon Kvale Stensland February 2015 Submitted to the Faculty of Mathematics and Natural Sciences at the University of Oslo in partial fulfilment of the requirements for the degree of Philosophiae Doctor © Håkon Kvale Stensland, 2015 Series of dissertations submitted to the Faculty of Mathematics and Natural Sciences, University of Oslo No. 1601 ISSN 1501-7710 All rights reserved. No part of this publication may be reproduced or transmitted, in any form or by any means, without permission. Cover: Hanne Baadsgaard Utigard. Printed in Norway: AIT Oslo AS. Produced in co-operation with Akademika Publishing. The thesis is produced by Akademika Publishing merely in connection with the thesis defence. Kindly direct all inquiries regarding the thesis to the copyright holder or the unit which grants the doctorate. Abstract Processor architectures have been evolving quickly since the introduction of the central processing unit. For a very long time, one of the important means of increasing per- formance was to increase the clock frequency. However, in the last decade, processor manufacturers have hit the so-called power wall, with high heat dissipation. To overcome this problem, processors were designed with reduced clock frequencies but with multiple cores and, later, heterogeneous processing elements. This shift introduced a new challenge for programmers: Legacy applications, written without parallelization in mind, gain no benefits from moving to multicore and heterogeneous architectures. Another challenge for the programmers is that heterogeneous architecture designs are very different with respect to caches, memory types, execution unit organization, and so forth and, in the worst case, a programmer must completely rewrite the application to obtain the best performance on the new architecture.