Techniques for Lowering Power Consumption in Design Utilizing the EP80579
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Techniques for Lowering Power Consumption in Design Utilizing the Intel® EP80579 Integrated Processor Product Line Application Note February 2010 Order Number: 320180-003US INFORMATIONLegal Lines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. 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Techniques for Lowering Power Consumption in Design Utilizing the Intel® EP80579 Integrated Processor Product Line Application Note February 2010 2 Order Number: 320180-003US Techniques for Lowering Power Consumption Contents 1.0 Introduction ..............................................................................................................5 1.1 Related Documents .............................................................................................5 2.0 Overview ...................................................................................................................5 3.0 Device Disabling ........................................................................................................6 4.0 IA-32 core Throttling.................................................................................................7 4.1 IA-32 core Throttling Implementation and Effects ....................................................8 4.2 Benefits of Throttling ...........................................................................................9 4.2.1 Throttling Power Savings...........................................................................9 5.0 Power Management................................................................................................. 11 5.1 Supported System Power States.......................................................................... 11 5.2 BIOS Support for Power Management .................................................................. 11 6.0 Conclusions ............................................................................................................. 11 Figures 1 Clocks Relationship for 50% Throttling Ratio..................................................................8 Tables 1 Related Documents ....................................................................................................5 2 Configurable Devices That Can be Disabled....................................................................6 3 Throttling Configuration with FORCE_THLT ....................................................................7 4 Throttling Power Savings (All Interface Device Units Enabled) ..........................................9 5 Throttling Power Savings with Devices Enabled/Disabled ............................................... 10 Techniques for Lowering Power Consumption in Design Utilizing the Intel® EP80579 Integrated Processor Product Line February 2010 Application Note Order Number: 320180-003US 3 Techniques for Lowering Power Consumption Revision History Date Revision Description February 2010 003 Updated Table 5 May 2009 002 Update content in Tab le 1, Table 4, and Tab le 5 August 2008 001 Initial Release. Techniques for Lowering Power Consumption in Design Utilizing the Intel® EP80579 Integrated Processor Product Line Application Note February 2010 4 Order Number: 320180-003US Techniques for Lowering Power Consumption 1.0 Introduction This application note discusses techniques that are used to conserve power when using the Intel® EP80579 Integrated Processor Product Line (EP80579) in system platform designs. 1.1 Related Documents Table 1. Related Documents Document Document Title Number Intel® EP80579 Integrated Processor Product Line Datasheet 320066 Intel® EP80579 Integrated Processor Product Line Platform Design Guide 320068 Note: Intel® EP80579 Integrated Processor Product Line BIOS Writers Guide Contact your Intel Field Representative to obtain document 2.0 Overview The EP80579 architecture is comprised of several functional units not all simultaneously utilized in all target applications. This application note describes the power savings achieved by utilizing the clock gating and IA-32 core throttling features designed into the EP80579. By default, several internal functional units are brought out of reset with their respective clocks enabled. The clocks for these functional units are disabled on a per unit basis under BIOS control, by programming the IO_DEVICE_CONFIG register. Refer to the Intel® EP80579 Integrated Processor Product Line BIOS Writers Guide for additional details on the IO_DEVICE_CONFIG register. Additionally it is feasible to configure the IA-32 core internal clock to throttle, to lower the aggregate frequency for lower data rate applications. This results in additional power savings for applications that do not require the IA-32 core to operate at the normal internal clock rate. The power savings that is achieved using these features is presented within this document. These power saving techniques are used, in conjunction with the power management capabilities described in the Intel® EP80579 Integrated Processor Product Line Datasheet, to determine the total power consumption for a particular application. Techniques for Lowering Power Consumption in Design Utilizing the Intel® EP80579 Integrated Processor Product Line February 2010 Application Note Order Number: 320180-003US 5 Techniques for Lowering Power Consumption 3.0 Device Disabling There are several internal functional units within the EP80579 that come up out of reset with their internal clocks enabled, but BIOS can be used to disable the units that are not utilized in the platform application. This allows applications that do not require the use of all of the hardware interface units to reduce the total platform power consumption. Devices are enabled/disabled by using the IO_DEVICE_CONFIG Register. BIOS uses this register to put unused devices into a powered down state. Devices that are disabled do not show up in the PCI configuration space, hence the IO_DEVICE_CONFIG Register has to be configured prior to PCI enumeration to avoid potential conflicts. Table 2 provides a list of devices that are disabled with BIOS by using the IO_DEVICE_CONFIG Register. Note: Consult with your BIOS vendor to configure the IO_DEVICE_CONFIG register to disable any unused interface devices in your platform design. Table 2. Configurable Devices That Can be Disabled Device Description PCIE1 PCI Express Port 1 PCIE0 PCI Express Port 0 SATA1 Serial ATA Port 1 SATA0 Serial ATA Port 0 GbE2 Gigabit Ethernet Port 2 GbE1 Gigabit Ethernet Port 1 GbE0 Gigabit Ethernet Port 0 USB1 Universal Serial Bus Port 1 USB0 Universal Serial Bus Port 0 CAN1 Controller Area Network Port 1 CAN0 Controller Area Network Port 0 TDM Time Division Multiplex Ports (HSS) SSP Synchronous Serial Port Techniques for Lowering Power Consumption in Design Utilizing the Intel® EP80579 Integrated Processor Product Line Application Note February 2010 6 Order Number: 320180-003US Techniques for Lowering