Design and Evaluation of Network Processor Systems and Forwarding Applications
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C5ENPA1-DS, C-5E NETWORK PROCESSOR SILICON REVISION A1
Freescale Semiconductor, Inc... SILICON REVISION A1 REVISION SILICON C-5e NETWORK PROCESSOR Sheet Data Rev 03 PRELIMINARY C5ENPA1-DS/D Freescale Semiconductor,Inc. F o r M o r G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc... Freescale Semiconductor,Inc. F o r M o r G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc... Freescale Semiconductor,Inc. Silicon RevisionA1 C-5e NetworkProcessor Data Sheet Rev 03 C5ENPA1-DS/D F o r M o r Preli G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m m d u c t , inary Freescale Semiconductor, Inc... Freescale Semiconductor,Inc. F o r M o r G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc. C5ENPA1-DS/D Rev 03 CONTENTS . -
Design and Implementation of a Stateful Network Packet Processing
610 IEEE/ACM TRANSACTIONS ON NETWORKING, VOL. 25, NO. 1, FEBRUARY 2017 Design and Implementation of a Stateful Network Packet Processing Framework for GPUs Giorgos Vasiliadis, Lazaros Koromilas, Michalis Polychronakis, and Sotiris Ioannidis Abstract— Graphics processing units (GPUs) are a powerful and TCAMs, have greatly reduced both the cost and time platform for building the high-speed network traffic process- to develop network traffic processing systems, and have ing applications using low-cost hardware. The existing systems been successfully used in routers [4], [7] and network tap the massively parallel architecture of GPUs to speed up certain computationally intensive tasks, such as cryptographic intrusion detection systems [27], [34]. These systems offer a operations and pattern matching. However, they still suffer from scalable method of processing network packets in high-speed significant overheads due to critical-path operations that are still environments. However, implementations based on special- being carried out on the CPU, and redundant inter-device data purpose hardware are very difficult to extend and program, transfers. In this paper, we present GASPP, a programmable net- and prohibit them from being widely adopted by the industry. work traffic processing framework tailored to modern graphics processors. GASPP integrates optimized GPU-based implemen- In contrast, the emergence of commodity many-core tations of a broad range of operations commonly used in the architectures, such as multicore CPUs and modern graph- network traffic processing applications, including the first purely ics processors (GPUs) has proven to be a good solution GPU-based implementation of network flow tracking and TCP for accelerating many network applications, and has led stream reassembly. -
Embedded Multi-Core Processing for Networking
12 Embedded Multi-Core Processing for Networking Theofanis Orphanoudakis University of Peloponnese Tripoli, Greece [email protected] Stylianos Perissakis Intracom Telecom Athens, Greece [email protected] CONTENTS 12.1 Introduction ............................ 400 12.2 Overview of Proposed NPU Architectures ............ 403 12.2.1 Multi-Core Embedded Systems for Multi-Service Broadband Access and Multimedia Home Networks . 403 12.2.2 SoC Integration of Network Components and Examples of Commercial Access NPUs .............. 405 12.2.3 NPU Architectures for Core Network Nodes and High-Speed Networking and Switching ......... 407 12.3 Programmable Packet Processing Engines ............ 412 12.3.1 Parallelism ........................ 413 12.3.2 Multi-Threading Support ................ 418 12.3.3 Specialized Instruction Set Architectures ....... 421 12.4 Address Lookup and Packet Classification Engines ....... 422 12.4.1 Classification Techniques ................ 424 12.4.1.1 Trie-based Algorithms ............ 425 12.4.1.2 Hierarchical Intelligent Cuttings (HiCuts) . 425 12.4.2 Case Studies ....................... 426 12.5 Packet Buffering and Queue Management Engines ....... 431 399 400 Multi-Core Embedded Systems 12.5.1 Performance Issues ................... 433 12.5.1.1 External DRAMMemory Bottlenecks ... 433 12.5.1.2 Evaluation of Queue Management Functions: INTEL IXP1200 Case ................. 434 12.5.2 Design of Specialized Core for Implementation of Queue Management in Hardware ................ 435 12.5.2.1 Optimization Techniques .......... 439 12.5.2.2 Performance Evaluation of Hardware Queue Management Engine ............. 440 12.6 Scheduling Engines ......................... 442 12.6.1 Data Structures in Scheduling Architectures ..... 443 12.6.2 Task Scheduling ..................... 444 12.6.2.1 Load Balancing ................ 445 12.6.3 Traffic Scheduling ................... -
Content Marketing Members-Only Conference
Content Marketing Members-Only Conference Wednesday, March 12, 2014 | Charles Schwab & Co. Inc. | San Francisco, CA at We’ll be live tweeting throughout the conference (@ANAMarketers), as well as posting photos and other information at facebook.com/ANA. www.ana.net Table of Contents ANA Content Marketing Members-Only Conference at Charles Schwab & Co. Agenda ............................................................................ pg 2 Speaker Bios .................................................................... pg 4 Attendees ........................................................................ pg 7 ANA Member Benefits .....................................................pg 15 www.ana.net 1 Agenda ANA Content Marketing Members-Only Conference at Charles Schwab & Co. WEDNESDAY, MARCH 12, 2014 to expand the opportunity to engage balance different content strategies for consumers and to build brand affinity different types of brands, or measure Breakfast (8:15 a.m.) in a new way that complements tradi- real results? The next five years will see tional advertising. a strategic inflection for marketing and advertising, and content will be at the Helen Loh General Session (9:00 a.m.) core. This session will talk through the Vice President, Content and Digital Marketing business case, the process, the tactics Charles Schwab & Co. Inc. BENJAMIN MOORE USES CONTENT TO and real-life examples of how real CONNECT WITH DIFFERENT AUDIENCE Tami Dorsey brands are using content to drive real SEGMENTS Editorial Director marketing results. Charles Schwab & Co. Inc. Staying true to their namesake’s 130+ Robert Rose Chief Strategist year-old vision, Benjamin Moore & Co. INTEL DEVELOPS A BRANDED Content Marketing Institute is committed to producing the highest CONTENT FORMULA TO ENSURE quality paints and finishes in the indus- try. But marketing to their disparate REPEATED SUCCESS Lunch (12:50 p.m.) target markets (contractors to home- When Intel & Toshiba launched “The owners, as well as designers and archi- Inside Experience” in 2011 it was General Session Cont. -
Crosstalk and Signal Integrity in Ring Resonator Based Optical Add/Drop Multiplexers for Wavelength-Division-Multiplexing Networks
Crosstalk and Signal Integrity in Ring Resonator Based Optical Add/Drop Multiplexers for Wavelength-Division-Multiplexing Networks by Riyadh Dakhil Mansoor, B.Eng, M.Sc, MIET. School of Engineering and Sustainable Development De Montfort University A thesis submitted in partial fulfilment of the requirements for the degree of Doctor of Philosophy July 2015 To my family. i ABSTRACT With 400 Gbps Ethernet being developed at the time of writing this thesis, all-optical networks are a solution to the increased bandwidth requirements of data communication allowing architectures to become increasingly integrated. High density integration of optical components leads to potential ‘Optical/Photonic’ electromagnetic compatibility (EMC) and signal integrity (SI) issues due to the close proximity of optical components and waveguides. Optical EMC issues are due to backscatter, crosstalk, stray light, and substrate modes. This thesis has focused on the crosstalk in Optical Add/Drop Multiplexers (OADMs) as an EMC problem. The main research question is: “How can signal integrity be improved and crosstalk effects mitigated in small-sized OADMs in order to enhance the optical EMC in all-optical networks and contribute to the increase in integration scalability?” To answer this question, increasing the crosstalk suppression bandwidth rather than maximizing the crosstalk suppression ratio is proposed in ring resonator based OADMs. Ring resonators have a small ‘real estate’ requirement and are, therefore, potentially useful for large scale integrated optical systems. A number of approaches such as over-coupled rings, vertically-coupled rings and rings with random and periodic roughness are adopted to effectively reduce the crosstalk between 10 Gbps modulated channels in OADMs. -
Network Processors: Building Block for Programmable Networks
NetworkNetwork Processors:Processors: BuildingBuilding BlockBlock forfor programmableprogrammable networksnetworks Raj Yavatkar Chief Software Architect Intel® Internet Exchange Architecture [email protected] 1 Page 1 Raj Yavatkar OutlineOutline y IXP 2xxx hardware architecture y IXA software architecture y Usage questions y Research questions Page 2 Raj Yavatkar IXPIXP NetworkNetwork ProcessorsProcessors Control Processor y Microengines – RISC processors optimized for packet processing Media/Fabric StrongARM – Hardware support for Interface – Hardware support for multi-threading y Embedded ME 1 ME 2 ME n StrongARM/Xscale – Runs embedded OS and handles exception tasks SRAM DRAM Page 3 Raj Yavatkar IXP:IXP: AA BuildingBuilding BlockBlock forfor NetworkNetwork SystemsSystems y Example: IXP2800 – 16 micro-engines + XScale core Multi-threaded (x8) – Up to 1.4 Ghz ME speed RDRAM Microengine Array Media – 8 HW threads/ME Controller – 4K control store per ME Switch MEv2 MEv2 MEv2 MEv2 Fabric – Multi-level memory hierarchy 1 2 3 4 I/F – Multiple inter-processor communication channels MEv2 MEv2 MEv2 MEv2 Intel® 8 7 6 5 y NPU vs. GPU tradeoffs PCI XScale™ Core MEv2 MEv2 MEv2 MEv2 – Reduce core complexity 9 10 11 12 – No hardware caching – Simpler instructions Î shallow MEv2 MEv2 MEv2 MEv2 Scratch pipelines QDR SRAM 16 15 14 13 Memory – Multiple cores with HW multi- Controller Hash Per-Engine threading per chip Unit Memory, CAM, Signals Interconnect Page 4 Raj Yavatkar IXPIXP 24002400 BlockBlock DiagramDiagram Page 5 Raj Yavatkar XScaleXScale -
Intel® IXP42X Product Line of Network Processors with ETHERNET Powerlink Controlled Node
Application Brief Intel® IXP42X Product Line of Network Processors With ETHERNET Powerlink Controlled Node The networked factory floor enables the While different real-time Ethernet solutions adoption of systems for remote monitoring, are available or under development, EPL, long-distance support, diagnostic services the real-time protocol solution managed and the integration of in-plant systems by the open vendor and user group EPSG with the enterprise. The need for flexible (ETHERNET Powerlink Standardization Group), connectivity solutions and high network is the only deterministic data communication bandwidth is driving a fundamental shift away protocol that is fully conformant with Ethernet from legacy industrial bus architectures and networking standards. communications protocols to industry EPL takes the standard approach of IEEE standards and commercial off-the shelf (COTS) 802.3 Ethernet with a mixed polling and time- solutions. Standards-based interconnect slicing mechanism to transfer time-critical data technologies and communications protocols, within extremely short and precise isochronous especially Ethernet, enable simpler and more cycles. In addition, EPL provides configurable cost-effective integration of network elements timing to synchronize networked nodes with and applications, from the enterprise to the www.intel.com/go/embedded high precision while asynchronously transmitting factory floor. data that is less time-critical. EPL is the ideal The Intel® IXP42X product line of network solution for meeting the timing demands of processors with ETHERNET Powerlink (EPL) typical high performance industrial applications, software helps manufacturers of industrial such as automation and motion control. control and automation devices bridge Current implementations have reached 200 µs between real-time Ethernet on the factory cycle-time with a timing deviation (jitter) less floor and standard Ethernet IT networks in than 1 µs. -
And GPU-Based DNN Training on Modern Architectures
An In-depth Performance Characterization of CPU- and GPU-based DNN Training on Modern Architectures Presentation at MLHPC ‘17 Ammar Ahmad Awan, Hari Subramoni, and Dhabaleswar K. Panda Network Based Computing Laboratory Dept. of Computer Science and Engineering The Ohio State University [email protected], {subramon,panda}@cse.ohio-state.edu CPU based Deep Learning is not as bad as you think! • Introduction – CPU-based Deep Learning – Deep Learning Frameworks • Research Challenges • Design Discussion • Performance Characterization • Conclusion Network Based Computing Laboratory MLHPC ‘17 High-Performance Deep Learning 2 GPUs are great for Deep Learning • NVIDIA GPUs have been the main driving force for faster training of Deep Neural Networks (DNNs) • The ImageNet Challenge - (ILSVRC) – 90% of the ImageNet teams used GPUs in 2014* https://www.top500.org/ – DL models like AlexNet, GoogLeNet, and VGG – GPUs: A natural fit for DL due to the throughput-oriented nature – GPUs are also growing in the HPC arena! *https://blogs.nvidia.com/blog/2014/09/07/imagenet/ Network Based Computing Laboratory MLHPC ‘17 High-Performance Deep Learning 3 https://www.top500.org/statistics/list/ But what about CPUs? • Intel CPUs are everywhere and many-core CPUs are emerging according to Top500.org • Host CPUs exist even on the GPU nodes – Many-core Xeon Phis are increasing • Xeon Phi 1st generation: a many-core co-processor • Xeon Phi 2nd generation (KNL): a self-hosted many- core processor! • Usually, we hear CPUs are 10x – 100x slower than GPUs? [1-3] – But can we do better? 1- https://dl.acm.org/citation.cfm?id=1993516 System Count for Xeon Phi 2- http://ieeexplore.ieee.org/abstract/document/5762730/ 3- https://dspace.mit.edu/bitstream/handle/1721.1/51839/MIT-CSAIL-TR-2010-013.pdf?sequence=1 Network Based Computing Laboratory MLHPC ‘17 High-Performance Deep Learning 4 Deep Learning Frameworks – CPUs or GPUs? • There are several Deep Learning (DL) or DNN Training frameworks – Caffe, Cognitive Toolkit, TensorFlow, MXNet, and counting... -
Effective Compilation Support for Variable Instruction Set Architecture
Effective Compilation Support for Variable Instruction Set Architecture Jack Liu, Timothy Kong, Fred Chow Cognigine Corporation 6120 Stevenson Blvd. Fremont, CA 94538, USA g fjackl,timk,fredc @cognigine.com Abstract running embedded applications. these application specific instruction set processors (ASIPs) [1, 2] use instruction sets customized towards a specific type of application so they Traditional compilers perform their code generation can deliver efficient run-time performance for typical pro- tasks based on a fixed, pre-determined instruction set. This grams written for that application area. Because the instruc- paper describes the implementation of a compiler that de- tion set is pre-determined, the compiler is built and config- termines the best instruction set to use for a given pro- ured to generate code based on a custom, fixed instruction gram and generates efficient code sequence based on it. We set [16]. first give an overview of the VISC Architecture pioneered at Cognigine that exemplifies a Variable Instruction Set Ar- The Variable Instruction Set Communications Architec- chitecture. We then present three compilation techniques ture (VISC Architecture ÌÅ ) from Cognigine represents a that, when combined, enable us to provide effective com- very different approach in the attempt to provide greater pilation and optimization support for such an architecture. configurability in compiling embedded software. The VISC The first technique involves the use of an abstract opera- Architecture can perform a complex set of instructions con- tion representation that enables the code generator to op- sisting of multiple, fine and coarse grain operations that op- timize towards the core architecture of the processor with- erate on multiple operands at the same time in one fixed out committing to any specific instruction format. -
Intel740™ Graphics Accelerator
Intel740™ Graphics Accelerator Design Guide August 1998 Order Number: 290619-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The Intel740™ graphics accelerator may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Such errata are not covered by Intel’s warranty. Current characterized errata are available upon request. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by: calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. -
NP-5™ Network Processor
NETWORK PROCESSOR PRODUCT BRIEF † NP-5™ Network Processor 240Gbps NPU for Carrier Ethernet Applications HIGHLIGHTS Mellanox’s NP-5 is a highly-flexible network processor with integrated traffic management, targeting Carrier Ethernet Switches and Routers (CESR) and other Carrier Ethernet platforms – 240Gbps wire-speed network processor aimed that require high performance, flexible packet processing and fine-grained traffic management. at Carrier Ethernet applications TARGET APPLICATIONS – Integrated 240Gbps traffic management NP-5’s flexibility and integration allows system vendors to deliver cost effective solutions that providing granular bandwidth control can easily adapt to changing market requirements. – Up to 480Gbps peak processing data path and Typical applications include: Stand-alone pizza box solutions: CoS classification • Line cards in modular chassis: • Ethernet Aggregation Nodes – Suited for line card, services card and pizza box • Edge and Core Routers • Server Load Balancing Switches applications • Transport Switches • Multi-10Gbps Firewalls & VPN – On-chip control CPU for host CPU offload • Data Center Switches • Intrusion Detection Appliances • 3G/4G Wireless Infrastructure Equipment • Network Monitoring and Analysis Services – Power management for minimizing line card and system power dissipation SOFTWARE TOOLS – Operations, Administration and Management Mellanox supplies a comprehensive set of software tools to facilitate system design for NP-5 (OAM) processing offload based products. The toolset manages the data plane and allows designers to edit, build and – Synchronous Ethernet and IEEE1588v2 offload debug microcode applications for the Mellanox’s network processors with a unified GUI. for Circuit Emulation Services Designers can quickly develop and test the microcode using cycle-accurate simulation and debugging tools including breakpoints, single-step program execution and access to internal – IP reassembly for advanced packet processing resources. -
Exjobb Text V1.Pages
DEGREE PROJECT IN COMPUTER SCIENCE AND ENGINEERING, SECOND CYCLE, 30 CREDITS STOCKHOLM, SWEDEN 2017 Using crowdsourcing as a production method in filmmaking – a case study JOHAN LUNDH HEINSTEDT KTH ROYAL INSTITUTE OF TECHNOLOGY SCHOOL OF COMPUTER SCIENCE AND COMMUNICATION Using crowdsourcing as a production method in filmmaking – a case study Att använda crowdsourcing inom filmproduktion – en fallstudie Degree Project in Media Technology, second cycle, 30 credits Master of Science in Engineering in Media Technology School of Computer Science and Communications (CSC), KTH Johan Lundh Heinstedt, [email protected] Supervisor Christopher Rosenqvist Examiner Leif Handberg 2017-06-18 Sammanfattning Samtidigt som att våra beteendemönster i hur vi konsumerar media förändras i takt med att nya medieteknologier uppstår, förändras också sättet media produceras. Filmskapande följer många gånger en särskild process (ofta med en tydlig hierarki av specialister inom produktionsgruppen) och berättelsen har traditionellt sett berättats från en part till den andre – från producenten/regissören till publiken. Men internets intåg har i många avseenden förändrat filmindustrin, vilket har öppnat upp för en ökad dialog mellan dessa två parter, vilket har omformat publikens position till en mer medskapande sådan. Detta har resulterat i en större demokratisering av filmmediet, där den en gång passiva publiken nu involverar sig mer i den kreativa filmskapandeprocessen. Crowdsourcing, som redan är vanligt förekommande inom exempelvis produktdesign och serviceindustrier,