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Network Processors the Morgan Kaufmann Series in Systems on Silicon Series Editor: Wayne Wolf, Georgia Institute of Technology

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Network Processors the Morgan Kaufmann Series in Systems on Silicon Series Editor: Wayne Wolf, Georgia Institute of Technology Network Processors The Morgan Kaufmann Series in Systems on Silicon Series Editor: Wayne Wolf, Georgia Institute of Technology The Designer’s Guide to VHDL, Second Edition Peter J. Ashenden The System Designer’s Guide to VHDL-AMS Peter J. Ashenden, Gregory D. Peterson, and Darrell A. Teegarden Modeling Embedded Systems and SoCs Axel Jantsch ASIC and FPGA Verification: A Guide to Component Modeling Richard Munden Multiprocessor Systems-on-Chips Edited by Ahmed Amine Jerraya and Wayne Wolf Functional Verification Bruce Wile, John Goss, and Wolfgang Roesner Customizable and Configurable Embedded Processors Edited by Paolo Ienne and Rainer Leupers Networks-on-Chips: Technology and Tools Edited by Giovanni De Micheli and Luca Benini VLSI Test Principles & Architectures Edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen Designing SoCs with Configured Processors Steve Leibson ESL Design and Verification Grant Martin, Andrew Piziali, and Brian Bailey Aspect-Oriented Programming with e David Robinson Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation Edited by Scott Hauck and André DeHon System-on-Chip Test Architectures Edited by Laung-Terng Wang, Charles Stroud, and Nur Touba Verification Techniques for System-Level Design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad VHDL-2008: Just the New Stuff Peter J. Ashenden and Jim Lewis On-Chip Communication Architectures: System on Chip Interconnect Sudeep Pasricha and Nikil Dutt Embedded DSP Processor Design: Application Specific Instruction Set Processors Dake Liu Processor Description Languages: Applications and Methodologies Edited by Prabhat Mishra and Nikil Dutt Network Processors Architecture, Programming, and Implementation Ran Giladi Ben-Gurion University of the Negev and EZchip Technologies Ltd. AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO Morgan Kaufmann is an imprint of Elsevier Morgan Kaufmann Publishers is an imprint of Elsevier. 30 Corporate Drive, Suite 400, Burlington, MA 01803 This book is printed on acid-free paper. ϱ Copyright © 2008 by Elsevier Inc. All rights reserved. Designations used by companies to distinguish their products are often claimed as trademarks or registered trademarks. In all instances in which Morgan Kaufmann Publishers is aware of a claim, the product names appear in initial capital or all capital letters. Readers, however, should contact the appropriate companies for more complete information regarding trademarks and registration. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, scanning, or otherwise, without prior written permission of the publisher. Permissions may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone: (+44) 1865 843830, fax: (+44) 1865 853333, e-mail: [email protected]. You may also complete your request on-line via the Elsevier homepage (http://elsevier.com), by selecting “Support & Contact” then “Copyright and Permission” and then “Obtaining Permissions.” Library of Congress Cataloging-in-Publication Data Giladi, Ran. Network processors: architecture, programming, and implementation/Ran Giladi. p. cm.—(The Morgan Kaufmann systems on silicon series) Includes bibliographical references and index. ISBN 978-0-12-370891-5 (alk. paper) 1. Network processors. 2. Routing (Computer network management)—Equipment and supplies. 3. Packet switching (Data transmission)—Equipment and supplies. I. Title. TK5105.543.G55 2008 621.382’1–dc22 2008024883 For information on all Morgan Kaufmann publications, visit our Website at www.mkp.com or www.books.elsevier.com Printed in the United States 08 09 10 11 12 10 9 8 7 6 5 4 3 2 1 Working together to grow libraries in developing countries www.elsevier.com | www.bookaid.org | www.sabre.org In memory of my father Benjamin (Sontag) Z”L To my mother Rita (Aaron) To my beloved wife Kora To Ornit, Niv, and Itamar, our wonderful children, and to my dear brother Eival This page intentionally left blank Contents Preface ............................................................................................ xi CHAPTER 1 Introduction and Motivation ........................................... 1 1.1 Network Processors Ecosystem ............................................ 1 1.2 Communication Systems and Applications ........................... 2 1.3 Network Elements ................................................................ 6 1.4 Network Processors .............................................................. 8 1.5 Structure of This Book .......................................................... 10 1.6 Summary ............................................................................... 12 PART 1 Networks CHAPTER 2 Networking Fundamentals .............................................. 15 2.1 Introduction .......................................................................... 16 2.2 Networks Primer ................................................................... 17 2.3 Data Networking Models ...................................................... 21 2.4 Basic Network Technologies ................................................. 25 2.5 Telecom Networks ................................................................ 26 2.6 Data Networks ...................................................................... 38 2.7 Summary ............................................................................... 69 Appendix A ............................................................................ 70 Appendix B ........................................................................... 72 CHAPTER 3 Converged Networks ........................................................ 77 3.1 Introduction .......................................................................... 77 3.2 From Telecom Networks to Data Networks .......................... 78 3.3 From Datacom to Telecom .................................................... 87 3.4 Summary ............................................................................... 134 Appendix A ............................................................................ 135 CHAPTER 4 Access and Home Networks ........................................... 149 4.1 Access Networks ................................................................... 149 4.2 Home and Building Networks ............................................... 178 4.3 Summary ............................................................................... 180 PART 2 Processing CHAPTER 5 Packet Processing ............................................................ 183 5.1 Introduction and Defi nitions ................................................ 183 5.2 Ingress and Egress ................................................................. 186 5.3 Framing ................................................................................. 188 viii Contents 5.4 Parsing and Classifi cation ...................................................... 195 5.5 Search, Lookup, and Forwarding ........................................... 205 5.6 Modifi cation .......................................................................... 236 5.7 Compression and Encryption ............................................... 237 5.8 Queueing and Traffi c Management ....................................... 238 5.9 Summary ............................................................................... 239 CHAPTER 6 Packet Flow Handling ...................................................... 241 6.1 Defi nitions ............................................................................. 242 6.2 Quality of Service .................................................................. 243 6.3 Class of Service ..................................................................... 244 6.4 QoS Mechanisms ................................................................... 249 6.5 Summary ............................................................................... 286 CHAPTER 7 Architecture........................................................................ 287 7.1 Introduction .......................................................................... 287 7.2 Background and Defi nitions.................................................. 289 7.3 Equipment Design Alternatives: ASICs versus NP .................. 308 7.4 Network Processors Basic Architectures............................... 309 7.5 Instruction Set (Scalability; Processing Speed) ..................... 314 7.6 NP Components .................................................................... 314 7.7 Summary ............................................................................... 335 CHAPTER 8 Software .............................................................................. 337 8.1 Introduction .......................................................................... 338 8.2 Conventional Systems ........................................................... 342 8.3 Programming Models Classifi cation ...................................... 348 8.4 Parallel Programming ............................................................ 349 8.5 Pipelining .............................................................................. 355 8.6 Network Processor Programming ......................................... 359 8.7 Summary ............................................................................... 363 Appendix A ...........................................................................
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