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Object-Oriented Reconfigurable Processing for Wireless Networks Andrew A Object-Oriented Reconfigurable Processing for Wireless Networks Andrew A. Gray, Clement Lee, Payman Arabshahi, Jeffrey Srinivasan Jet Propulsion Laboratory, California Institute of Technology 4800 Oak Grove Drive, MS 238-343, Pasadena, CA 91101 USA Abstract – We present an outline of reconfigurable processor while at the same time being sensitive and potentially error technologies and design methods with emphasis on an object- prone and costly. oriented approach, and both full and partial dynamic To address these issues, we present design methods reconfiguration. A specific broadly applicable architecture for that facilitate flexibility (leading to prolonged processor implementing a software reconfigurable network processor for lives), and dynamic reconfigurability, along with a generic wireless communication applications is presented; a prototype of which is currently operating in the laboratory. This reconfigurable processor architecture. Dynamic partial architecture, its associated object oriented design methods, and reconfiguration of the network processor will greatly partial reconfiguration techniques enable rapid-prototyping increase the value of the processor within the network. For and rapid implementations of communications and navigation instance the processor’s ability to perform a very large signal processing functions; provide long-life communications number of temporally separated (time-multiplexed) infrastructure; and result in dynamic operation within functions will dramatically increase network elasticity and networks with heterogeneous nodes, as well as compatibility compatibility (see Fig. 1). with other networks. This work builds upon numerous The paradigms will also empower the design engineer advances in commercial industry as well as military software with tools required for rapid prototyping and radio developments to space-based radios and network processing. The development of such radios and the network implementation of a wide variety of signal processing processor presented here require defining the correct functions. We focus on a “network processor” as a combination of processing methods (“objects”) and developing hardware/software object of choice and example within a appropriate dynamic reconfiguration techniques as a function wireless communication network. of system goals and operating parameters. Network Processor Function 1 Function 2 Function 3 Function 1 Receiver Transmitter encryption/ Receiver I. INTRODUCTION Chain Chain compression Chain Time 1 2 3 4 Processors in use in the telecom industry, especially within the rapidly growing wireless communication sector, are increasingly called to task on a diversity of applications, Fig. 1. Time multiplexed processor functions. and faced with ever-stringent operational constraints. Many potential applications for these processors often cannot be II. ARCHITECTURE DEFINITION anticipated at design time. Moreover, the value of adapting to For our purposes we assume that all processing performed new requirements and continuing cost-efficient, high- by the reconfigurable network processor (shown in Fig. 2) performance operation within such dynamic networks is is entirely digital, and consider the case of conventional extremely high, driving the need for reconfigurability [1-5]. continuous-time processing; although reconfigurable The reconfigurable processor architecture is typically a analog systems are also possible [6,7]. composite of generic microprocessors, field programmable gate arrays (FPGAs), digital signal processors (DSPs), as well as traditional digital and mixed-signal applications specific integrated circuits (ASICs) and discrete analog- RF Processing Reconfigurable AD/DA circuits. It is currently determined by experienced design (ASICs, Discrete Network Conversion engineers who decide upon and consider numerous tradeoffs components) Processor involving, among others, complexity, cost, development time, mass, size, flexibility, power consumption, and Fig. 2. Generic model of a network processor. reliability in order to achieve target system requirements and performance metrics. Given the variety of processors and Our key considerations are flexibility and computational development platforms available in the commercial market, performance for which the primary measure is and the increasing complexity of problem solutions, these fixed/floating operations per second. judicious decisions are generally extraordinarily complex Figures 3 and 4 represent an abstract depiction of three general classes of processor types under consideration for The work described in this publication was carried out as part of a task our generic architecture definition: ASICs, FPGAs, DSPs, funded by the Technology and Applications Program (TAP) at the Jet and microprocessors [8,9]. Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration. mind for the network processor is in satellite networks or Microprocessor dense ad hoc wireless sensor networks. Again, the primary motivations have continued to be flexibility and DSP computational power; if less processing power or less Flexibility FPGA flexibility were desired a different architecture would be chosen. Figure 5 illustrates a conceptual framework of the design. ASIC Software Processor Reconfigurable Hardware (G3 Power PC) (Xilinx FPGA) Power Consumption Application Layer Fig. 3. Illustration of flexibility versus power consumption. Transport Layer ASIC Operations per FPGA Network Layer Second DSP Data Link Layer Microprocessor Configure Software and Design and Implementation Time Hardware Physical Layer Fig. 4. Illustration of processing power versus design time. Processing (Software-Defined Radio) FPGAs offer reconfigurability on the bit-level at the cost Processing Implemented in Processing Implemented in of larger chip integration areas and slower maximum clock Flexible Software Power Efficient frequency as compared to custom and semi-custom very Reconfigurable Hardware large scale integrated (VLSI) processors. FPGAs may Fig. 5. Network layers implemented in a reconfigurable compete with or complement microprocessors. Indeed processor. Note the degree of overlap of various layers FPGAs are becoming so sophisticated that the majority of within the domain of either the software processor, or the certain microprocessor and DSP cores may be implemented reconfigurable hardware. in them. Finally, the key performance advantages of FPGAs over software processors are their high computational Hybrid software and reconfigurable hardware design, performance and low power consumption. These are as well as reconfiguration of network layers in the primarily the result of the very high degrees of parallelism processor, calls for a unified object-oriented design and pipelining possible in designs implemented in FPGAs paradigm encompassing hardware, software, and the [10]. interface between the two. The processor architecture in At the same time, FPGAs cannot yet implement the most Fig. 5 was developed to allow the algorithms and signal powerful and sophisticated microprocessors. In addition the processing of various layers to be accomplished in a large quantity of developed software and variety of logical way: with some functions logically being development tools available for such processors offers implemented in software and some logically in hardware. advantages in using them rather than FPGAs. The goal is to develop design tools that facilitate this The generic reconfigurable processor architecture logical placement of processing. presented below is motivated by these factors, both positive The prototype of Fig. 5 assumes a 1 million gate Xilinx and negative. The reconfiguration of the architecture in our FPGA and a 700 MHz PowerPC processor. Note that the design has to be performed by a controlling agent which reconfiguration of the software and hardware processors is should reside in the software processor given the current defined by software control. state-of-the art FPGA design tools [10]. This software processor also needs computational power to perform other III. OBJECT ORIENTED DESIGN AND RECONFIGURATION functions (e.g. transmit, receive), and applications that find a The first step in implementing a system design in the logical implementation in software (e.g. data compression). architecture shown in Fig. 5 is to represent it in an Accordingly for the network processor outlined above, implementation-independent form. This is done to provide we have chosen an architecture based on an FPGA and a a context in which to evaluate various implementation reduced instruction set computer (RISC) microprocessor that choices against numerous design constraints. It is crucial acts as the software processor. The primary application in that a well-defined route exist from the implementation- • Keeping objects and classes simple: Excessive independent model to the chosen implementation technology. numbers of attributes in a class should be avoided – an Additionally it is essential that subsets of the design average of one or two attributes for each service in a (“objects”), either hardware, software or a combination – for class is usually all that is required. which partial near real-time reconfiguration is desired – be logically and temporally separable from other parts of the B. Hardware Objects design without interrupting the flow of data processing. There has been little work on broadly applicable design Applying concepts of object-oriented (OO)
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