Intel740™ Graphics Accelerator
Design Guide
August 1998
Order Number: 290619-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The Intel740™ graphics accelerator may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Such errata are not covered by Intel’s warranty. Current characterized errata are available upon request. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by: calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
Intel740™ Graphics Accelerator Design Guide Contents
1 Introduction ...... 1-1 1.1 About This Design Guide ...... 1-1 1.2 References...... 1-2 2 Addin Card Design...... 2-1 2.1 Introduction ...... 2-1 2.1.1 Design Features...... 2-2 2.1.1.1 Intel740™ Graphics Accelerator...... 2-2 2.1.2 BT829B - Video Decoder ...... 2-3 2.1.2.1 BT869 - TV Encoder...... 2-3 2.1.3 Terminology ...... 2-3 2.1.3.1 Power Sources ...... 2-3 2.1.3.2 Fences...... 2-4 2.1.3.3 Stitching...... 2-4 2.2 Layout and Routing Guidelines...... 2-5 2.2.1 Placement ...... 2-5 2.2.2 Board Description ...... 2-6 2.2.3 BGA Component...... 2-8 2.2.3.1 Layout Requirements...... 2-8 2.2.3.2 Ground Connections...... 2-9 2.2.3.3 Power Connections...... 2-9 2.2.3.4 Decoupling...... 2-10 2.2.3.5 General Signal Routing...... 2-11 2.2.4 Voltage Regulator ...... 2-11 2.2.5 Bt829 Video Decoder...... 2-11 2.2.5.1 Ground Planes...... 2-12 2.2.5.2 Power Planes...... 2-12 2.2.5.3 Passive Components and Signal Routing ...... 2-12 2.2.6 Bt869 Video Encoder ...... 2-12 2.2.6.1 Ground Planes...... 2-12 2.2.6.2 Power Planes...... 2-13 2.2.6.3 Passive Components and Signal Routing ...... 2-13 2.2.6.4 AGP Layout and Routing Guidelines ...... 2-13 2.2.6.5 Intel740™ Graphics Accelerator Memory Layout and Routing Guidelines...... 2-14 2.2.6.6 Intel740™ Graphics Accelerator Memory Configurations...... 2-17 2.2.6.7 TV Out Interface ...... 2-20 2.2.6.8 Analog Signals...... 2-20 2.2.7 UL and FCC Considerations ...... 2-20 2.3 Addin Card Schematics ...... 2-21
Intel740™ Graphics Accelerator Design Guide iii 3 3 Device AGP MotherBoard Design ...... 3-1 3.1 Introduction ...... 3-1 3.1.1 Overview...... 3-1 3.1.2 About This Chapter...... 3-2 3.1.3 Block Diagram ...... 3-2 3.1.4 Implementation Issues...... 3-3 3.1.4.1 Disabling A Master Device ...... 3-3 3.1.4.2 Low Power Logic Implementation...... 3-4 3.1.4.3 GPO27# and GPO28# Signal Duration ...... 3-5 3.1.5 State Diagrams ...... 3-5 3.1.5.1 Signal Quality and Timing Issues ...... 3-6 3.1.5.2 Strobe Edge Quality Issues ...... 3-7 3.1.5.3 Clock Issues ...... 3-7 3.1.6 Design Recommendations...... 3-9 3.1.6.1 Voltage Definitions...... 3-9 3.1.6.2 General Design Recommendation ...... 3-9 3.2 3 Device AGP Motherboard Layout and Routing Guidelines...... 3-9 3.2.1 BGA Quadrant Assignment ...... 3-10 3.2.2 Board Description ...... 3-12 3.2.3 3-point AGP Design Guidelines ...... 3-12 3.2.3.1 Layout and Routing ...... 3-12 3.2.3.2 Data and strobe definitions...... 3-13 3.2.3.3 Assumptions for Board Design Guidelines ...... 3-14 3.2.3.4 Add-in Card guideline assumptions:...... 3-14 3.2.3.5 Motherboard Guideline Assumptions ...... 3-14 3.2.3.6 3-Load AGP Topology ...... 3-16 3.2.3.7 Overall Solution Space ...... 3-16 3.2.4 Intel740™ Graphics Accelerator Memory Layout and Routing Guidelines ...... 3-18 3.2.4.1 3 Device AGP Intel740™ Graphics Accelerator Memory Configurations ...... 3-21 3.3 3 Device AGP Motherboard Reference Design Schematics ...... 3-22 4 Thermal Considerations...... 4-1 5 Mechanical Information...... 5-1 5.1 Board Dimensions ...... 5-1 5.2 Fan/Heatsink Hole Pattern...... 5-1 5.3 VMI Header Placement...... 5-2 5.4 50 Pin Video Connector...... 5-3 5.5 Bracket...... 5-4 5.6 NLX Considerations...... 5-5 6 Third Party Vendors...... 6-1 6.1 Voltage Regulator ...... 6-1 6.2 50 Pin Connector ...... 6-1 6.3 Fan/Heatsink...... 6-1 6.4 Flash Components...... 6-1 6.5 Video Encoders/Decoders ...... 6-1 6.6 DVD Daughter Cards...... 6-2 6.7 TV Tuner...... 6-2 A Application Notes B Reference Information
iv Intel740™ Graphics Accelerator Design Guide Figures
2-1 Example of Power Plane Separation ("fencing")...... 2-4 2-2 Example of Power Plane Stitching...... 2-4 2-3 Major Signal Sections ...... 2-5 2-4 Example ATX Layout ...... 2-6 2-5 Four Layer Board Stack-up...... 2-7 2-6 Metal Defined land dimensions...... 2-8 2-7 BGA Trace ...... 2-8 2-8 Dogbone Via Pattern...... 2-9 2-9 Suggested VCC Planes for the Intel740™ Graphics Accelerator ...... 2-10 2-10 Intel740™ Graphics Accelerator Decoupling ...... 2-10 2-11 Intel740™ Graphics Accelerator BGA Routing Example ...... 2-11 2-12 Layout Dimensions (MA[11:0])...... 2-15 2-13 Layout Dimensions (MD[63:0], DQM[7:0]) ...... 2-15 2-14 Layout Dimensions (WEA#, SRASA#, SCASA#, CSA1#, CSB0#)...... 2-15 2-15 Layout Dimensions (WEB#, SRASB#, SCASB#, CSA0#) ...... 2-16 2-16 Memory Layout Dimensions (TCLK0)...... 2-16 2-17 Memory Layout Dimensions (TCLK1)...... 2-16 2-18 Memory Layout Dimensions (RCLK and OCLK to RCLK) ...... 2-17 2-19 2/4 MB Local Memory Connection (64-bit data path) ...... 2-17 2-20 4/8 MB Local Memory Connection (64-bit data path) ...... 2-18 2-21 8 MB Local Memory Connection (64-bit data path) ...... 2-19 2-22 Layout Dimensions, Digital TV Bus...... 2-20 2-23 512Kx32 and 256Kx32 Pinout Compatibility...... 2-24 2-24 1M X 16 Pinout Compatibility...... 2-24 3-1 Pentium® II Processor / Intel® 440BX AGPset/Intel 740 Graphics Accelerator System Block Diagram ...... 3-3 3-2 The Schematic Diagram for GPO27#, PCIRST# (System Reset), RESET#, ROMA16 Signals ...... 3-4 3-3 The Schematic Diagram for the WEB#, SCASB#, SRASB#, CS0B#, CS1B# and TEST ...... 3-5 3-4 Intel740™ Graphics Controller (On Board Device) Remains in Low Power Mode ...... 3-6 3-5 Intel740™ Graphics Controller (On Board Device) State Diagram...... 3-6 3-6 Point-to-Point Topology ...... 3-8 3-7 Major Signal Sections ...... 3-10 3-8 Example ATX Placement for a UP Pentium® II Processor / Intel® 440BX AGPset / Intel 740 Graphics Accelerator Design ...... 3-11 3-9 Four Layer Board Stack-up...... 3-12 3-10 Point-to-Point Topology ...... 3-15 3-11 3 Device Data Load Topology...... 3-16 3-12 3 Device Strobe Load Topology...... 3-16 3-13 3 Device Data Load Topology (Solution 1 is Shown)...... 3-17 3-14 3 Device Strobe Load Topology (Solution 1 is shown) ...... 3-17 3-15 Clock Topology and Matching...... 3-17 3-16 Layout Dimensions (MA[11:0])...... 3-19 3-17 Layout Dimensions (MD[63:0], DQM[7:0]) ...... 3-19 3-18 Layout Dimensions (WEA#, SRASA#, SCASA#, CSA0#) ...... 3-20 3-19 Memory Layout Dimensions (TCLK1)...... 3-20 3-20 Memory Layout Dimensions (RCLK and OCLK to RCLK) ...... 3-21
Intel740™ Graphics Accelerator Design Guide v 3-21 2/4 MB Local Memory Connection (64-bit data path) ...... 3-21 3-22 512Kx32 and 256Kx32 Pinout Compatibility...... 3-26 3-23 1M X 16 Pinout Compatibility...... 3-26 5-1 Mounting Hole Locations (Fan/Heatsink Assembly) ...... 5-1 5-2 VMI Header Placement...... 5-2 5-3 DVD Daughter Card Dimensions (ATX and NLX)—Top Side ...... 5-2 5-4 50 Pin Video Connector Schematic ...... 5-3 5-5 Recommended Bracket Placement ...... 5-4 5-6 Recommended Bracket Cutout...... 5-4
vi Intel740™ Graphics Accelerator Design Guide Tables
2-1 Mix and Match Options For Intel740™ Graphics Accelerator Card ...... 2-2 2-2 Intel740™ Graphics Accelerator Power Supplies ...... 2-3 2-3 Bt829B GND and AGND Pins...... 2-12 2-4 Bt829B VCC and AVCC Pins...... 2-12 2-5 Bt869 Digital and Analog Power Pins ...... 2-13 2-6 AGP Signal Lengths...... 2-13 2-7 Strobes and Corresponding Signal Groups ...... 2-13 2-8 Supported Memory Options (Other Memory Options Are Not Supported)...... 2-14 2-9 Memory Layout Restrictions (See Figure 2-12 and Figure 2-13)...... 2-14 2-10 Memory Layout Restrictions (See Figure 2-14 and Figure 2-15)...... 2-15 2-11 Memory Layout Restrictions (See Figure 2-16 and Figure 2-17)...... 2-16 2-12 TV Out/ROMA Trace Lengths (See Figure 2-22)...... 2-20 2-13 GPIO Functions ...... 2-21 3-1 State of Signals to be Driven After System Reset but at Least One Clock Prior to Asserting TEST ...... 3-4 3-2 Signal Duration of the GPO Signals from PIIX4...... 3-5 3-3 Data and Associated Strobe ...... 3-13 3-4 Data Signal and Strobe Guideline Assumptions ...... 3-14 3-5 Control and Clock Signal Guideline Assumptions...... 3-14 3-6 Data signal and strobe requirements ...... 3-14 3-7 Control Signal Line Length Requirements ...... 3-15 3-8 Strobe and Data Segment Solution Space ...... 3-16 3-9 Clock Segment Solution Space ...... 3-18 3-10 Supported Memory Options (Other Memory Options Are Not Supported)...... 3-18 3-11 Memory Layout Restrictions (See Figure 3-16 and Figure 3-17)...... 3-19 3-12 Memory Layout Restrictions (See Table 3-16 and Table 3-17) ...... 3-19 3-14 Memory Layout Restrictions (See Figure 3-19) ...... 3-20 3-13 Memory Layout Restrictions (See Figure 3-19) ...... 3-20 4-1 Thermal Design Considerations Chart...... 4-1
Intel740™ Graphics Accelerator Design Guide vii Revision History
Date Revision Description
2/98 -001 Initial Release. Part 2: Added Figure 2-2; added “Note” verbiage in 2.14. Part 3: Added verbiage to 3.3.5; Modified Figures 4/98 -002 3-14, 3-15, 3-16, 3-19; Modified Table 3-10. Part 5: Modified Figure 5-6. Restructured document and added a motherboard design: Chapter 2 contains the Addin Card design. This chapter combines 7/98 -003 revision 2 Chapters 1, 2, 3, and Appendix A. Only re-organizaiton; the information is the same. Chapter 2 adds the motherboard design.
viii Intel740™ Graphics Accelerator Design Guide 1 Introduction
Introduction
Introduction 1
This document provides a complete package of design information for the Intel740™ Graphics Accelerator. There are two design discussed: • ATX Addin Card Design (Chapter 2 provides design considerations, layout and routing guidelines, and schematic diagrams) • Motherboard Design (Chapter 3 provides design considerations, layout and routing guidelines, and schematic diagrams)
The purpose of the reference design is to provide a comprehensive design encompassing every Intel740™ graphics accelerator interface. The designer of another board may then modify this design as needed since the basic hook-up will remain the same.
For the latest Intel740™ graphics accelerator information, please visit Intel’s website at:
http://developer.intel.com/design/graphics/740.htm
1.1 About This Design Guide
This design guide is intended for hardware designers who are experienced with PC architectures and board design. The design guide assumes that the designer has a working knowledge of the vocabulary and practices of PC hardware design. • This chapter introduces the designer to the organization and purpose of this design guide and provides a list of references and related documents. • Chapter 2, "Addin Card Design"—This chapter provides a detailed set of Intel740™ graphics accelerator design information for ATX and NLX graphics cards. The basis of the design information is a reference ATX card design. Schematics for the reference design are provided at the end of the chapter. • Chapter 3, "3 Device AGP Motherboard Design"—This chapter provides design guidelines for developing a motherboard based on the Pentium II® processor, Intel® 440BX AGPset, and the Intel740™ graphics accelerator. The main focus of this chapter is the guidelines for developing a 3-point AGP solution with the Intel740 graphics accelerator and provides a detailed set of design information for a 3-point AGP reference design (DS1P/440BX/I740). Schematics for the reference design are provided at the end of the chapter. • Chapter 4, "Thermal Considerations"—This chapter introduces the topic of thermal considerations. See Application Note 653 in Appendix A for a comprehensive description of thermal considerations. • Chapter 5, "Mechanical Information"— This chapter provides mechanical information on Fan/ Heatsink, VMI Header Placement, Video Connector, brackets, and NLX considerations. • Chapter 6, "Third Party Vendor Information"— This section includes information regarding various third-party vendors who provide products to support the Intel 440BX AGPset and the Intel740 graphics accelerator. • Appendix A, "Application Notes"—This appendix contains Application Note 653, Thermal Design Considerations. The application note provides a comprehensive guide to thermal design • Appendix B, "Reference Information"—This appendix provides reference information for designing with the Intel740 graphics accelerator. The appendix contains information on
Intel740™ Graphics Accelerator Design Guide 1-1 Introduction
SDRAM/SGRAM Graphics SO-DIMM Modules. The appendix also contains information on PC SGRAM specifications.
1.2 References
• Intel740™ Graphics Accelerator Datasheet: Contact your field sales representative (Literature order #290618) or visit the Intel740™ Graphics Accelerator WEB page at: http://developer.intel.com/design/graphics/740.htm • Accelerated Graphics Port Interface Specification Rev 1.0: Contact www.agpforum.com • Bt829A/Bt827A/Bt825A VideoStreamII Decoders Oct. 1996: Contact Rockwell* Semiconductor • Bt868/869 Flicker-Free Video Encoder with UltrascaleTM Technology: Contact Rockwell* Semiconductor • VMI 1.4 Interface Specification: Contact SGS Thompson Microelectronics • PC ’98: Contact www.microsoft.com/hwdev • PC SGRAM Specification: See Appendix B • SO-DIMM Module Specification: See Appendix B • Intel740™ Graphics Accelerator Application Note 653 - Thermal Design Considerations: See Appendix A • Intel 440BX AGPset Design Guide. Contact your field sales representative (Literature order #290634). or visit the 440BX AGPSet WEB page at: http://developer.intel.com/design/pcisets/designex/290634.htm
1-2 Intel740™ Graphics Accelerator Design Guide 2 Intel740™ Graphics Accelerator Addin Card Design
Addin Card Design
Addin Card Design 2
This chapter provides a complete package of design information for the Intel740™ graphics accelerator. Usage of the Intel740™ graphics accelerator on an ATX and NLX graphics card is discussed. The basis of this document is a reference ATX card.
2.1 Introduction
The reference design card described in this document contains the following features. • ATX Form Factor • Memory — 100 MHz SDRAM or SGRAM — SO-DIMM Memory Upgrade Socket — 2,4 MB Solder-Down Option • BIOS — Support for Flash or ROM — Capable of Supporting up to 256KB • Monitor — Hardware Support for DDC 2B • Video —Capture — Bi-Directional VMI Video Port for DVD Hardware — CCIR 601 8/16-bit Video Capture Port — NTSC, PAL, and SECAM Inputs Accepted — Intercast Capable — Video-Conferencing Capable — Output — NTSC or PAL TV Output — Flicker Free TV Output — Overscan Compensation — 50-Pin Video Connector — S-Video In/Out — Composite In/Out —TV Tuner • I2C Programmability
Intel740™ Graphics Accelerator Design Guide 2-1 Addin Card Design
Table 2-1 lists the various functions capable of being supported by the reference card design. This table describes which component is necessary for a specific feature. For hookup information, the corresponding schematic page should be referenced. Intel740™ Graphics Accelerator Table 2-1. Mix and Match Options For Intel740™ Graphics Accelerator Card
Intel740™ DVD Chip/ SO-DIMM Memory Component/ Graphics BT829 BT869 Daughter Module Components Functionality Accelerator Page 5 Page 6 Card Page 11 Page 12 Page 3 Page 7
2D/3D X Video Capture X X TV Out X X DVD (HW) X X 2 MB X (1) 256K x 64 (2) 256K x 32 (1) 512K x 64 (2) 512K x 64 4 MB X or or (2) 256K x 64 (4) 256K x 32 8 MB X (1) 1M x 64 (4) 1M x 16
2.1.1 Design Features
2.1.1.1 Intel740™ Graphics Accelerator
The Intel740™ graphics accelerator is the main component of the graphics reference design. This component delivers high performance 3D/2D graphics and video capabilities. Each of the interfaces are described below. • Accelerated Graphics Port (AGP) Interface. The AGP interface is a new interface designed for 3D graphics. This interface provides increased bandwidth over PCI, side band addressing, and AGP memory 3D texture storage. For a more complete description of the AGP interface refer to the Intel740™ Graphics Accelerator Datasheet and AGP Specification. • Local Memory Interface. The memory interface on the Intel740™ graphics accelerator can operate at speeds up to 100 MHz. An SDRAM interface supports SGRAM and SDRAM to be used for different memory densities. • VMI Interface. A bi-directional VMI like port is incorporated into the Intel740™ graphics accelerator providing a mechanism for affordable DVD. Video capture is also supported using the video port pins. • TV Out Interface. Intel has worked with Rockwell* (Brooktree*) to design an interface capable of supporting a high quality TV out chip. This interface allows the Intel740™ graphics accelerator to output on a monitor, TV, or both. • BIOS Interface. The Intel740™ graphics accelerator supports a FLASH or ROM BIOS. Up to 256Kx8 can be supported. • GPIO Interface. Nine GPIO signals exist on the Intel740™ graphics accelerator. GPIO[8:0] allow for power management, DDC, I2C, thermal fault sensing, and other general features. • DAC Interface. An integrated DAC provides display resolutions up to 1600x1200.
2-2 Intel740™ Graphics Accelerator Design Guide Addin Card Design
2.1.2 BT829B - Video Decoder
The Bt829B is a video capture processor used to convert analog video data into CCIR 601 digital video data. This chip contains the following capabilities. • Analog Inputs. The Bt829B contains four composite video inputs along with one chroma and one luma input for s-video. • I2C Interface. Control of the Bt829B is accomplished though the use of an I2C interface. All of the chip’s registers are programmed using this interface as is the selection of the analog input source to use in generating digital video data. • Video Port. The Bt829B contains a video port capable of outputting 8 or 16 bit data. The data format is YUV 4:2:2 with HSYNC, VSYNC, and PIXEL CLOCK as control signals.
2.1.2.1 BT869 - TV Encoder
The Bt869 provides high quality TV out. This component contains the following interfaces: • Input Port. The Bt869 is capable of receiving data in two formats. The format used by this reference design for receiving data is through the 24 bit digital port accepting data on both edges of the reference clock. This mode of operation is documented in the Intel740™ Graphics Accelerator Datasheet. The second method for capturing data is through the use of the VMI protocol. This interface is documented in the VMI 1.4 Interface Specification. • Flicker Filter Output. The output of the Bt869 is a very high quality flicker filtered output. This is due to a 5 tap internal filter. Output can be displayed in interlaced, non-interlaced, PAL, or NTSC formats. Macrovision7 output is also supported in the Bt869 component. The Bt869 is capable of displaying composite or S-Video data. • I2C Interface. Control of the Bt869 is achieved through the I2C port.
2.1.3 Terminology
2.1.3.1 Power Sources
The card is supplied with four voltages through the edge connector. Other voltages are derived on- board. Thus, the Power Layer of the board must be divided into several distinct planes. Table 2-2 lists the various power elements on the Intel740™ graphics accelerator reference design. Each of the voltage sources are supplied by a plane except for 12 volts, which is supplied by a 25 mil trace.
Table 2-2. Intel740™ Graphics Accelerator Power Supplies
Schematic Max Description Voltage Source Symbol Current
VDDQ3 3.3V AGP Supply +3.3V 8.0A Edge connector VCC3 3.3V Logic Supply +3.3V 6.0A Edge connector VCC 5V Logic Supply +5.0V 2.0A Edge connector +12V 12V Supply +12V 1.0A Edge connector VCC2 2.7V Core Supply +2.7V 3.0A VCC3, via Voltage Regulator 3VAA_BT869 3.3V Analog Supply +3.3V < 1.0A VCC3, via Ferrite Bead AVCC 5V Analog Supply +5.0V < 1.0A VCC, via “fence”
Intel740™ Graphics Accelerator Design Guide 2-3 Addin Card Design
2.1.3.2 Fences
A “fence” is a line routed out of the plane such that a given area is isolated from the rest of the plane except at a single point of contact, conceptually the “gate” in the fence. A fence will minimize noise originating from digital signaling onto the analog signals. This provides higher quality video for both the Bt829B and Bt869. An example of a fenced power plane is shown in Figure 2-1. The heavy black line is the routed area. The width of the gate or opening can be up to 75% of the length of the IC in question. The width of the routed fence should conform to the separation routing between power planes (i.e., 25 mils minimum). Figure 2-1. Example of Power Plane Separation ("fencing")
Fenced area Routed “fence” (e.g. AVCC) “gate” Overlying Chip
Plane (e.g. VCC)
2.1.3.3 Stitching
Power plane “stitching” is required between the VCC3 and VDDQ3 planes. Stitching two isolated planes together with capacitors allows a current return path for high frequency signals which pass over split power planes. This helps to eliminate EMI. The six 0.1 µF capacitors coupling VCC3 to VDDQ3 should be spaced evenly if possible. Note the VDDQ3 plane is only near the AGP connector. An example of stitching is shown in Figure 2-2. This figure illustrates the power planes and, therefore, does not show signal traces between capacitors. The general rule for power plane stitching is to have a capacitor placed between every four signals crossing the two planes. As an example, there should be a capacitor, four signals, a capacitor, another four signals, and so forth ending with a capacitor. Figure 2-2. Example of Power Plane Stitching
VCC3
cap IC
cap cap VDDQ3 cap
2-4 Intel740™ Graphics Accelerator Design Guide Addin Card Design
2.2 Layout and Routing Guidelines
This chapter describes layout and routing recommendations to insure a robust design. These guidelines should be followed as closely as possible. Any deviations from the guidelines listed here should be simulated to insure adequate margin is still maintained in the design.
2.2.1 Placement
The ball connections on the Intel740™ graphics accelerator have been assigned to simplify routing and keep board fabrication costs down by enabling a 4-layer design. Figure 2-3 shows the four signal quadrants of the Intel740 graphics accelerator. Component placement should be done with this general flow in mind. This will simplify routing and minimize the number of signals which must cross. The individual signals within the respective groups have also been optimized to be routed using only 2 PCB layers.
A complete list of signals and ball assignments can be found in the Intel740™ Graphics Accelerator Datasheet. Figure 2-3. Major Signal Sections
BIOS/Flicker VMI Port Quadrant Quadrant Pin #1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Intel740 A B Top View C D E F G H J K L M A.G.P. N Quadrant P R T U V W Y AA AB AC AD AE AF Local Memory Quadrant
Intel740™ Graphics Accelerator Design Guide 2-5 Addin Card Design
An example of the proposed component placement for an ATX form factor design is shown in Figure 2-4. This is the placement used on the reference card. For NLX placement issues, refer to Section 5.6, “NLX Considerations” on page 5-5.
ATX Form Factor: • The example placement (Figure 2-4) shows the Bt829B, Bt869, SO-DIMM Module, Intel740 graphics accelerator, VMI Port connections along with a 50 pin video connector. • The trace length limitation between critical connections will be addressed later in this document. • Figure 2-4 is for reference only. The choice of size of memory, whether to have an SO-DIMM connector, what video components to place on the board, and which video connectors to have on the bracket will have to be evaluated by the board designer. Figure 2-4. Example ATX Layout
Bt829B SO-DIMM Connector
VGA Connector
Memory
Bt869
28F010 Intel740™ Intel740 50 Pin Flash Chip Memory Connector BIOS VMI Port
Connectors
2.2.2 Board Description
Even with the following recommendations, it is important to simulate your design.
A 4-layer stack-up arrangement is recommended. The stack-up of the board is shown in Figure 2-5. The impedance of all the signal layers are to be between 50 and 80 ohms. Lower trace impedance will slow signal edge rates, over & undershoot, and have less cross-talk than higher trace impedance. Higher trace impedance will create faster edge rates and decrease signal flight times. Prepreg is FR-4 material.
2-6 Intel740™ Graphics Accelerator Design Guide Addin Card Design
Figure 2-5. Four Layer Board Stack-up
Z = 65 ohms Primary Signal Layer (1/2 oz. cu.) 6 mils PREPREG Ground Plane (1 oz. cu.) 50 mils CORE Power Plane (1 oz. cu) 6 mils PREPREG Z = 65 ohms Secondary Signal Layer (1/2 oz. cu)
Total board width = 62 + .6 mils
Note: Top and bottom routing layers specify 1/2 oz. cu. However, by the time the board is plated, the traces will end up with about 1 oz. cu. Please check with your fabrication vendor on the exact value and insure that any signal simulation accounts for this.
Note: Thicker core helps reduce board warpage issues, while thinner prepreg reduces trace impedance.
Additional guidelines on board buildup, placement and layout include: • All layers should be cut back from the substrate outer edge by 0.050”. A 0.025”-wide strip should be added to all signal and power layers around the outer edge and tied to the ground plane. • All power and ground traces between vias and pads for all components should be at least as wide as the component power or ground pad itself. • Through-hole vias, unless otherwise noted, are 10 mil drill, 25 mil diameter pad. Via capping is required. All vias on the secondary side should be covered with solder mask. All vias on the primary side are to be encroached with solder mask and anti-pad unless board dryness has been guaranteed. • To minimize solder wicking with the BGA, the component side solder mask should be applied prior to tinning the copper. There should be no surface mount over bare copper (S.M.O.B.C.). • The solder mask must cover the trace between the via and pad. • The board impedance (Z) should be between 50 and 80 ohms (65 ohms ±20%). • FR-4 material should be used for the board fabrication. • The ground plane should not be split on the ground plane layer. If a signal must be routed for a short distance on a power plane, then it should be routed on a VCC plane, not the ground plane. • Keep vias for decoupling capacitors as close to the capacitor pads as possible. • Keep isolated power planes as close as possible to each other. This will minimize impedance mismatch at the split. • All decoupling capacitors should be tied to the ground plane by a trace at least as wide as the via ring to the plane.
Intel740™ Graphics Accelerator Design Guide 2-7 Addin Card Design
2.2.3 BGA Component
2.2.3.1 Layout Requirements
The following layout requirements should be followed when routing the 468 MBGA package. • All non-ground BGA lands should be Metal Defined (MD) lands with the following nominal dimensions (see Figure 2-6). — Metal pad: 20 (6/6 routing) / 24 mils (5/5 routing) — Solder mask opening: 24 mil (20 mil pad) / 27 mils (24 mil pad) • Any trace connected to a MBGA land or PTH via in the MBGA land grid array should be teardropped. The teardrop should leave the trace at a 45° angle and intersect the via tangentially (see Figure 2-7). • The minimum distance between the gold finger edge of the card and the center of the first row of MBGA lands should be 525 mils, and 480 mils from the end of the start of the bevel. • All BGA ground vias should use 16 mil drill with no thermal reliefs. Figure 2-6. Metal Defined land dimensions
Solder Mask Opening
(.024”) (.020”) .027” .024”
Metal Pad
Figure 2-7. BGA Trace
Cover Trace with Solder Mask BGA Land PTH Via
45° 45° .010” min Recommended to be as wide as via
2-8 Intel740™ Graphics Accelerator Design Guide Addin Card Design
2.2.3.2 Ground Connections
All lands in the four corners and center are Vss (GND). Thermal analysis requires that each Vss ball connect to an adjacent via which passes through to the solder side of the board, one via per ball, with a trace as wide as the via. Heat will dissipate through these vias to the GND plane as well as to the air on the solder side. Figure 2-8. Dogbone Via Pattern
2.2.3.3 Power Connections
The VCC2 plane should be as wide as practical for high current-carrying capacity. Because of the interspersing of VCC2 and VCC3 pins on the Intel740™ graphics accelerator, a polygon will be needed on one of the signal layers to extend the VCC3 plane to the isolated VCC3 pins (Figure 2-9). The VCC2 polygon is a separate plane on the VCC Layer; the darker VCC3 polygon is a power flood on the solder side and connects to the VCC3 plane on the VCC Layer through vias.
Intel740™ Graphics Accelerator Design Guide 2-9 Addin Card Design
Gr Figure 2-9. Suggested VCC Planes for the Intel740™ Graphics Accelerator
VCC2 VCC3
VCC2 on VCC Layer
VCC3 on Secondary Side Signal Layer
vcc_pl.vsd
2.2.3.4 Decoupling
Decoupling capacitors should ideally be placed as close as possible to the Intel740 graphics accelerator. This means that the best decoupling will occur if the capacitors are placed directly underneath the component. If a single sided board is required and capacitors cannot be placed underneath the component then decoupling is recommended at the corners of the Intel740 graphics accelerator package. At least a 0.1 µF and 0.01 µF are recommended for each corner. By placing the capacitors in this location all of the traces can “break-out” from the BGA package on all four sides. Figure 2-10. Intel740™ Graphics Accelerator Decoupling
0.1uF 0.1uF 0.01uF 0.01uF Intel740 Graphics Accelerator (468 BGA)
0.1uF 0.1uF 0.01uF 0.01uF
2-10 Intel740™ Graphics Accelerator Design Guide Addin Card Design
2.2.3.5 General Signal Routing
Figure 2-11 depicts general escape of traces from the five rows of BGA ball pads. The first three ball rows can be routed on the primary layer. The last two must be routed through vias to the secondary layer. Underneath the BGA, trace routing should be 5 on 5 or 6 on 6. Once the traces have left the BGA, however, routing should expand to 5 on 10 or 6 on 12. The ratio should be kept as 1:2.
The signals AD_STB_A, AD_STB_B and SB_STB should have a spacing of 1:4 to other signals. Using this extra spacing between these specific signals will help to keep crosstalk to a minimum. Figure 2-11. Intel740™ Graphics Accelerator BGA Routing Example
COMPONENT SIDE ROUTING FOR 5 ROWS OF BALL PADS
R1
R2
R3
R4
R5
2.2.4 Voltage Regulator
The physical tab (used as a built in heatsink) on the MOSFET package is the drain pin, and will need a tab-shaped pad to solder to.
Note: The resistor/capacitor network between the COMP pin (pin 5) and the GND pin (pin 3) of the LT1575 should be connected directly to the GND pin of the device rather than tied to the ground plane.
2.2.5 Bt829 Video Decoder
Note: Rockwell* Semiconductor should be contacted for up to date layout recommendations.
Intel740™ Graphics Accelerator Design Guide 2-11 Addin Card Design
2.2.5.1 Ground Planes
The Bt829B and associated circuitry have two ground planes, GND and ANALOG_GND (AGND). These are electrically the same plane but should be separated by a fence, as described in Section 2.1.3.2, “Fences” on page 2-4. The schematic illustrates which pins attach to which plane as does Table 2-3. The opening in the fence should be under the Bt829B and be up to 75% of the IC’s width. The AGND plane is the isolated or subset plane, hence GND is the return path for current. The AGND plane should be as small as possible.
Table 2-3. Bt829B GND and AGND Pins
Bt829 Ground Pins
GND 11, 21, 31, 33, 39, 77, 81, 90, 93, 95, 100 AGND 42, 47, 54, 56, 58, 61, 66, 71, 75
2.2.5.2 Power Planes
The Bt829 and associated circuitry have three power planes, VCC3, VCC and AVCC. The latter two are digital and analog +5V, respectively. As above, these are electrically the same plane but separated by a fence. This fence and the AVCC plane should parallel the AGND fence and plane closely, with the opening in about the same location.
Table 2-4. Bt829B VCC and AVCC Pins
Bt829B 5V Pins
VCC 10, 38, 76, 88, 96 AVCC 40, 44, 48, 60, 65, 72
2.2.5.3 Passive Components and Signal Routing
All passive components should be placed as near to the Bt829B as possible. These parts include: the 0.1µF and 0.01µF bypass capacitors, the 10µF capacitors, the 75 ohm terminating resistors, and the crystal oscillator circuitry.
Note: There must be NO digital signals routed under or above the analog power and ground planes (AVCC and AGND).
The filter circuits on the four video input signals (TUNER, SV_LUM, SV_CHR, CV_IN) need to be located near the 50-pin connector. Note that other designs not using a 50 pin video connector should have the filter circuits placed as close as possible to the input connectors. The analog traces should not be routed such that they parallel other analog signals at a close spacing for a long length. Wherever analog signals run in parallel, separated by less than 15 mils for longer than 250 mils, run a ground line between them of approximately 12 mils width.
2.2.6 Bt869 Video Encoder
Note: Rockwell Semiconductor should be contacted for up to date layout recommendations.
2.2.6.1 Ground Planes
Only one ground plane is recommended for the Bt869. This ground plane should be formed as a fence underneath the Bt869.
2-12 Intel740™ Graphics Accelerator Design Guide Addin Card Design
2.2.6.2 Power Planes
The Bt869 and associated circuitry have two power planes, VCC3 and 3VAA_BT869. The 3VAA_BT869 plane is a separate cutout, joined to VCC3 by a ferrite bead. The device should reside entirely above the 3VAA_BT869 plane, as there are no VCC3 connections to the device. So long as the 3VAA_BT869 plane underlies all the analog components, it should be as small as possible.
Table 2-5. Bt869 Digital and Analog Power Pins
Bt869 3V Pins
3VAA_BT869 (Analog) 69, 71, 73, 80 3VAA_BT869 (Digital) 19, 20, 30, 40, 46, 47, 57, 60, 61
2.2.6.3 Passive Components and Signal Routing
All passive components should be placed as close to the Bt869 device as possible. These devices consist of: the 0.1µF and 0.01µF bypass capacitors, the 10µF capacitors, the crystal oscillator circuitry, and the 0.1µF capacitors and 75 ohm resistors at the VREF, VBIAS and FSADJUST pins as well as the protection diodes.
Note: There must be NO digital signals routed under or above the analog power and ground planes (3VAA_BT869 and AGND).
The filter circuits on the three video output signals (TVOUT_Y, TVOUT_C, TVOUT_CVBS) must be very near the 50-pin connector or other output connectors. Long lengths of closely spaced parallel analog signals should be avoided. Wherever analog signals run in parallel, separated by less than 15 mils for longer than 250 mils, run a ground line between the video input traces of approximately 12 mils width.
2.2.6.4 AGP Layout and Routing Guidelines
This section describes the group of signals that runs between the Intel740 graphics accelerator AGP Interface and the AGP edge connector. For the definition of AGP functionality (protocols, rules and signaling mechanisms, as well as the platform level aspects of AGP functionality), refer to the latest AGP Interface Specification. This document focuses only on specific Intel740 graphics accelerator recommendations for the AGP interface. The general length requirements are shown in Table 2-6.
Table 2-6. AGP Signal Lengths
Group Recommendation All ≤ 3.0” CLK 2.6” ± 0.4”
Mismatch between strobe and data traces must be less than 0.5”. Thus the trace length for signals within a group must be within ±0.5” of the corresponding strobe’s trace length, as indicated in Table 2-7.
Table 2-7. Strobes and Corresponding Signal Groups
Group Strobe Recommendation
AD[31:16], C/BE[3:2]# AD_STB_B LAD_STB_B ± 0.5”
AD[15:0], C/BE[1:0]# AD_STB_A LAD_STB_A ± 0.5”
SBA[7:0] SB_STB LSB_STB ± 0.5”
Intel740™ Graphics Accelerator Design Guide 2-13 Addin Card Design
For example, AD29 and AD_STB_B must not be mismatched by more than 0.5”. No such comparison, however, should be enforced between AD29 and AD30, or AD29 and C/BE2#, etc. Note: AGP strobes must be separated by 2X normal signal spacing (i.e., if normal spacing is 5/10 or 6/12, the strobe signals must be separated from other traces by 20 or 24 mils, respectively).
2.2.6.5 Intel740™ Graphics Accelerator Memory Layout and Routing Guidelines
The Intel740 graphics accelerator integrates a memory controller which supports a 64-bit memory data interface. SGRAM can be used in addition to SDRAM if it is configured to perform as an SDRAM. The Intel740 graphics accelerator generates the Row Address Strobe (SRAS[A:B]#), Chip Selects (CS0[A:B]#, CS1[A:B]#), Column Address Strobe (SCAS[A:B]#), Byte Enables (DQM[0:7]#), Write Enables (WE[A:B]#), and Memory Addresses (MA). The memory controller interface is fully configurable through a set of control registers.
Eleven memory address signals (MAx[10:0]) allow the Intel740™ graphics accelerator to support a variety of commercially available SO-DIMMs and components. Two SRAS# lines permit two 64-bit wide rows of SDRAM. All write operations must be one Quadword (QWord). The Intel740 graphics accelerator supports memory up to 100 MHz.
Rules for populating a Intel740 graphics accelerator Memory: • Memory can be populated using either an SO-DIMM or components. • SDRAM and SGRAM components and/or SO-DIMMs can be mixed. • The DRAM Timing register, which provides the DRAM speed grade control for the entire memory array, must be programmed to use the timings of the slowest memories installed.
Possible DRAM and system options supported by the Intel740 graphics accelerator are shown in Table 2-8.
Table 2-8. Supported Memory Options (Other Memory Options Are Not Supported)
SDRAM/ SDRAM/ SDRAM/ Local Memory SGRAM SGRAM SGRAM Addressing Address Size Size Technology Density Width
Row Column Min Max
8 Mbit 256K 32 Asymmetric 10 8 2MB 4MB 16Mbit 512K 32 Asymmetric 11 8 4MB 8MB 16Mbit 1M 16 Asymmetric 12 8 8MB 8MB
There are several groups of signals within the memory bus with layout restrictions.
Table 2-9. Memory Layout Restrictions (See Figure 2-12 and Figure 2-13)
Signal Intel740™ to SO-DIMM SO-DIMM SGRAM Stub SGRAM Stub
Min Max Min Max Min Max
MA[11:0] n/a 4.0” 0.25” 0.9” 0.25" 0.6” MD[63:0], DQM[7:0] n/a 3.0” 0.25” 0.9” 0.25" 0.4”
2-14 Intel740™ Graphics Accelerator Design Guide Addin Card Design
Figure 2-12. Layout Dimensions (MA[11:0])
SGRAM 4.0” 0.25” - 0.9” Intel740™ 0.25” - 0.6” Intel740Chip 0.25” - 0.6”
SO-DIMM SGRAM
Figure 2-13. Layout Dimensions (MD[63:0], DQM[7:0])
3.0” 0.9” 0.4” Intel740™ Intel740Chip SGRAM
0.4”
SO-DIMM SGRAM
Table 2-10. Memory Layout Restrictions (See Figure 2-14 and Figure 2-15)
Intel740™ to SO-DIMM to SGRAM Signal SGRAM Stub SO-DIMM Stub
Min Max Min Max Min Max
WEA#, SRASA#, SCASA#, n/a 4.0” n/a n/a CSA1#, CSB0# WEB#, SRASB#, SCASB#, n/a 4.0” 0.25” 0.9” 0.25” 0.6” CSA0#
Figure 2-14. Layout Dimensions (WEA#, SRASA#, SCASA#, CSA1#, CSB0#)
2.0” - 4.00” Intel740™ Intel740 Chip SO-DIMM
Intel740™ Graphics Accelerator Design Guide 2-15 Addin Card Design
Figure 2-15. Layout Dimensions (WEB#, SRASB#, SCASB#, CSA0#)
SGRAM 2.0” - 4.0” Intel740™ 0.25” - 0.6” Intel740 0.25” - 0.9” Chip 0.25” - 0.6”
SGRAM
Table 2-11. Memory Layout Restrictions (See Figure 2-16 and Figure 2-17)
Intel740™ to Resistor to SO-DIMM to Signal SGRAM Stub Resistor SO-DIMM SGRAM Stub
Min Max
TCLK0 0.6” 2.4” ±0.25” n/a n/a n/a TCLK1 0.6” 2.4” ±0.25” 1.0” 0.4” 0.6”
Figure 2-16. Memory Layout Dimensions (TCLK0)
0.6” 2.4” +/- 0.25”
Intel740™Intel740 SO-DIMM Chip Connector 0Ω
Figure 2-17. Memory Layout Dimensions (TCLK1)
0.6” 2.4” +/- 0.25”
Intel740™Intel740 SO-DIMM Chip Connector 0Ω
2-16 Intel740™ Graphics Accelerator Design Guide Addin Card Design
Signal Intel740™ to Resistor
OCLK to Resistor 2.75” ±0.25
RCLK0, RCLK1 3.0” ±0.25”
Note: It is important to match clock lengths. For example, if the length from OCLK to Resistor is 1.03, then the length from Resistor to RCLK should be 3.03. Figure 2-18. Memory Layout Dimensions (RCLK and OCLK to RCLK)
2.75” +/- 0.25 Intel740™Intel740 Chip OCLK 33Ω 3.0” +/- 0.25” 33Ω
RCLK0
3.0” +/- 0.25”
RCLK1
2.2.6.6 Intel740™ Graphics Accelerator Memory Configurations
In the following discussion the term row refers to a set of memory devices that are simultaneously selected by an SRAS and the CS# signal.
Configuration #1: In this configuration, the minimum amount of memory (2MB) is supported. Note that, the same copy of all control signals goes to each component. Figure 2-19. 2/4 MB Local Memory Connection (64-bit data path)
Intel740™Intel740 Chip MD[63:0] MA[11:0]
CSx[A:B]# DQM[3:0] DQM[7:4] RCLKx OCLK
WEA# CS0A# SRASA# 256K/512K X 32 SCASA# MD[31:0] TCLKA
WEA# CS0A# SRASA# 256K/512K X 32 SCASA# MD[63:32] TCLKA
Intel740™ Graphics Accelerator Design Guide 2-17 Addin Card Design
Configuration #2: Two rows of memory are supported in this configuration. If 256Kx32 components are used 4MB of memory is obtainable, if 512Kx32 is used, then 8MB is supported. Note that both rows of memory receive different copies of each control signal, for loading reasons. Figure 2-20. 4/8 MB Local Memory Connection (64-bit data path)
Intel740™Intel740 Chip MD[63:0] MA[11:0]
CSx[A:B]# DQM[3:0] DQM[7:4] RCLKx OCLK
WEA# CS0A# SRASA# 256K/512K X 32 SCASA# MD[31:0] TCLKA
WEA# CS0A# SRASA# 256K/512K X 32 SCASA# MD[63:32] TCLKA
WEB# CS1A# SRASB# 256K/512K X 32 SCASB# MD[31:0] TCLKB
WEB# CS1A# SRASB# 256K/512K X 32 SCASB# MD[63:32] TCLKB
2-18 Intel740™ Graphics Accelerator Design Guide Addin Card Design
Configuration #3: One row of memory is supported in this configuration using 1Mx16 SDRAMs. Only the maximum allowable amount of memory (8MB) is supported in this configuration. Note that each copied signal is sent to only two components. Figure 2-21. 8 MB Local Memory Connection (64-bit data path)
Intel740™Intel740 Chip MD[63:0] MA[11:0]
CSx[A:B]#DQM[1:0] DQM[3:2] DQM[5:4] DQM[7:6] RCLKx OCLK
WEA# CS0A# SRASA# 1M X 16 SCASA# MD[15:0] TCLKA
WEB# CS0B# SRASB# 1M X 16 SCASB# MD[31:16] TCLKB
WEA# CS0A# SRASA# 1M X 16 SCASA# MD[47:32] TCLKA
CS0B# WEB# SRASB# 1M X 16 SCASB# MD[63:48] TCLKB
Intel740™ Graphics Accelerator Design Guide 2-19 Addin Card Design
2.2.6.7 TV Out Interface
The TV out bus is the group of signals that carry digitized display data from the Intel740 graphics accelerator to the Bt869 flicker filter TV-out component. This interface is shared with the BIOS interface. Table 2-12 gives the maximum trace lengths between components.
Table 2-12. TV Out/ROMA Trace Lengths (See Figure 2-22)
Intel740™ to BIOS Signal BIOS Stub BIOS to Bt869 Stub
Min Max Min Max Min Max
ROMA[17:0] 0.0” 3.5” 0.0” 1.5” 0.0” 4.0”
Figure 2-22. Layout Dimensions, Digital TV Bus
0.0” - 3.5” 0.0” - 4.0” Intel740™ Intel740Chip Bt869 0.0” - 1.5”
BIOS ROM
2.2.6.8 Analog Signals
It is recommended that all analog signal traces be 75Ω ±5%. It is important that these traces not violate the 5x10 mil spacing for the 65Ω traces. Analog traces include the DAC R, G, B traces, all of the inputs to the Bt829B component and outputs from the Bt869 component.
2.2.7 UL and FCC Considerations
Certain precautions should be taken in the design of the of a graphics card to ensure passing safety and EMI tests. These precautions are listed below. • When a signal can be hot plugged, clamping diodes should be used to limit voltage spikes. • When a voltage leaves the card, a fuse should be placed in the path to protect from a short circuit. • Sockets, Fans and Brackets should be grounded. • Separate Power Planes of the same voltage should be stitched together.
2-20 Intel740™ Graphics Accelerator Design Guide Addin Card Design
2.3 Addin Card Schematics
This section describes the Intel740™ Graphics Accelerator Reference Design Schematics. Please read this section carefully to observe all design recommendations and requirements.
The description of each schematic page is named by the logic block shown on that page.
Cover Sheet (Schematic Page 1)
The Cover Sheet shows the schematic page titles, page numbers, disclaimers and power pins.
Block Diagram (Schematic Page 2)
This page shows a block diagram overview of the Intel740 AGP card design. Schematic page numbers for each of the major schematic components are shown.
Intel740™ Graphics Accelerator (Schematic Pages 3,4)
This page shows all of the connections to the Intel740 graphics accelerator. Each Intel740 graphics accelerator interface is hooked up in this reference design. Beginning in the upper left hand corner of the page, the video capture port is shown. Internally, the input pins are pulled down. These pins contain a strapping option for subsystem ID. In this case the reference design has an ID of 0100h. Bits that should be a “1” may be pulled up using a 2K pull-up resistor. If the graphics design will not have video, the only concern is pulling the bus up to the correct value for the subsystem ID. The video control signals may be left unconnected. The BIOS interface multiplexes the BIOS, vendor ID, and flicker filter TV encoder. The ROMA lines are internally pulled down and may be pulled up using a 2K pull-up resistor. The video host port connects directly to the VMI header. The section labeled AGP interface connects directly to the AGP connector. The memory interfaces connect to an SO-DIMM connector and memory components. Each of the 9 GPIOs serve a different function in the reference design. Table 2-13 lists the function assigned to the GPIOs.
Table 2-13. GPIO Functions
GPIO FUNCTION
GPIO0 I2C Data GPIO1 I2C Clock GPIO2 DDC Data GPIO3 DDC Clock GPIO4 Fan Fail GPIO5 Extra For DVD Control GPIO6 VP[15:0] Bus Isolation Control GPIO7 Extra For DVD Control GPIO8 Power Down
Decoupling for the Intel740 graphics accelerator is shown along the bottom of the schematic page.
Intel740™ Graphics Accelerator Design Guide 2-21 Addin Card Design
Voltage Regulator (Schematic Page 5)
This page shows the circuitry to convert from 3.3 Volts to 2.7 Volts. The regulator used in the reference design does not need any heat sink for the FET. As shown, the FET will be dissipating slightly over 1 watt. If a different voltage regulator solution will be used, calculations will be needed to determine the need for a heatsink. Resistors R50, R44, R42, and R43 are only for the reference card design. These resistors allow different voltage combinations for core and internal Intel740 graphics accelerator PLLs. The table at the top of the page describes the voltage configurations. Core decoupling is shown at the bottom of the page and should be placed close to the Intel740 graphics accelerator.
Bt829B (Schematic Page 6)
The Bt829B component contains analog inputs which require special routing requirements detailed in Section 2.2.5, “Bt829 Video Decoder” on page 2-11. If these analog inputs are not used, then they should be tied to ground as is MUX3 in the reference design. The I2CCS pin is pulled low in the reference design to select an I2C address of 88h and 89h. This selection becomes important if connecting other I2C devices like the Bt869.
Note: Care must be taken to ensure that no two devices use the same address.
The QCLK output of the Bt829B obviates the need for connection to the VRDY input on the Intel740 graphics accelerator as this clock “ANDs” the ACTIVE and CLK outputs of the Bt829B together. The reference design is designed to support NTSC, PAL and SECAM. If only NTSC is desired, the circuitry including Y1 can be removed and XT1I should be tied high or low with XT1O left floating. If only PAL mode of operation is desired, XT1I should be tied high or low with XT1O floating and Y2 should be replaced with Y1. Decoupling for the component is shown at the bottom of the page.
Bt869 (Schematic Page 7)
The Bt869 power supply is generated from the VCC3 supply. Decoupling for this supply is shown at the top of the page. The component contains a 24-bit data port. The Intel740 graphics accelerator connects only to 12 of these bits. The functionality of this interface is described in the Intel740 Graphics Accelerator Datasheet. The slave input is tied to ground to place this chip in master mode. If the digital port were to be used as a VMI port, the component should be placed in slave mode. This page contains the only jumper in the design. This jumper selects which mode (PAL or NTSC) the Bt869 will operate in. The PC ’98 specification recommends this jumper for designs where a TV may be the only output display. The ALTADDR pin is pulled high so that the device responds to an address of 8Ah. This address keeps this device from conflicting with the Bt829B’s I2C address. Note that ROMA17 is wired to the CLKI pin while ROMA14 is connected to the CLKO pin. ROMA17 is also called CLKOUT and ROMA14 is called CLKIN. The Intel740’s graphics accelerator CLKOUT pin corresponds to the Bt869’s CLKI pin while the CLKIN pin corresponds to the CLKO pin on the Bt869. The DAC lines have special routing requirements detailed in section. These DAC lines allow the component to output S-Video and composite video.
VMI Video Connectors (Schematic Page 8)
The VMI video connectors are used for the attachment of a DVD daughter card or video capture card. The capture port is connected to the 26 pin header while the bi-directional host port is connected to the 40 pin header. The reference design uses a 2A fuse for the 3.3 volt supply to the 40 pin header. The 2A fuse is allowed for the 5 volt supply and 1A is allowed for the 12 volt supply. GPIO5 and GPIO7 come to the header for added DVD daughter card functionality control. GPIO8 is used for power down operation on the card. The I2C connections on the 26 pin header are 3.3 volt signals. Mechanical dimensions for the placement of the connectors is shown in Section 5.3, “VMI Header Placement” on page 5-2.
2-22 Intel740™ Graphics Accelerator Design Guide Addin Card Design
AGP Card Edge (Schematic Page 9)
This page details the connections of AGP. All power is derived from this connector. Using the rule of 1A per pin, the 12 volt supply is capable of supplying 1A, the 5 Volt supply is capable of supplying 2A and the 3.3 Volt supply is capable of supplying 8A.
VGA Connector (Schematic Page 10)
The VGA connector provides the RGB output to a monitor. BIOS and hardware provide support for plug-and-play capability.
DDC/I2C (Schematic Page 11)
This page details the 3.3 volt/5 volt signal conversion as well as the DDC/I2C connections. To perform the voltage translation, quick switches are used. The quick switches at the top of the page serve a second function of isolating the VMI port from the Intel740 graphics accelerator. GPIO6 can tri-state this bus to preclude the possibility of contention between something connected to the VMI header and the Bt829B.
SO-DIMM Connector (Schematic Page 12)
The SO-DIMM connector shows a fairly straight forward connection to the Intel740 graphics accelerator memory signals. Note that the primary CS0 connection is tied to the Intel740 graphics accelerator CSA1# signal. The CSB0# signal is connected to CS1 on the connector. The reference design has the first row of memory down on the graphics card. The second row of memory is assumed to be placed in the SO-DIMM connector.
Note: It is important not to have the memory on the graphics card and memory on the SO-DIMM connector connected to the same row.
SGRAMS (Schematic Page 13)
The SGRAMs shown on this page are labeled as 512Kx32. The schematic pinout is actually capable of supporting either the 512Kx32 or 256Kx32 SGRAMs. This dual-support connection is achieved through the following method. The 512Kx32 Jedec standard defines AP on pin 51 which is address 9. BS is on pin 29 and is also labeled as address 10. Address 8 is on pin 30. The Intel740 contains the AP on its address 8 pin and BS on address 9 pin. Since the 256Kx32 has AP with graphics accelerator address 8 and on pin 51 along with BS with address 9 on pin 29 and a no connect on pin 30, either the 512K or the 256K SGRAMs are capable of being supported in the same design (see Figure 2-23).
Note: It is important to disable the special features of SGRAM. This will make the SGRAM operate as an SDRAM, thus making it compatible with the Intel740 graphics accelerator.
Intel740™ Graphics Accelerator Design Guide 2-23 Addin Card Design
Figure 2-23. 512Kx32 and 256Kx32 Pinout Compatibility
A8/AP Pin 51 A9/AP Intel740™ A9/BS Pin 29 A10/BS Intel740 Chip A10 Pin 30 A8 A7 A7 512Kx32 . . SGRAM . . Jedec A0 A0 Standard
Intel740™ A8/AP Pin 51 A8/AP A9/BS Pin 29 A9/BS Intel740 Chip A10 Pin 30 NC A7 A7 256Kx32 . . SGRAM . . Jedec A0 A0 Standard
Figure 2-24. 1M X 16 Pinout Compatibility
A11/BS A11 A10/AP A10 A9 A9 A8 A8 Intel740™ 1M X 16 Chip . . SDRAM . . . . A1 A1 A0 A0
2-24 Intel740™ Graphics Accelerator Design Guide Addin Card Design
Video Connector (Schematic Page 14)
This page shows a specially designed solution to the problem of too many connectors and not enough board space. This 50 pin connector allows external hookup for a tuner, S-Video in, S-Video Out, composite video in, and composite video out. The input connections feed to the Bt829B component while the out connections come from the Bt869. Individual designs may or may not have all possible connectors and, therefore, may not need this type of solution.
BIOS/FAN (Schematic Page 15)
This page shows the connections to the flash BIOS and fan power. The BIOS used in this design is a PLCC socket for early debug capabilities. To use less board space a TSOP package may be the preferred component. Since the selected part is a 5 volt part, the data lines are isolated from the Intel740 graphics accelerator by a level shifter.
Note: The Intel740 graphics accelerator does not require a fan for AGP compliant systems. These design features have been added for ease of use if the customer determines a fan is required. Refer to the Thermal Application Note and software to determine the correct thermal solution.
The fan powerdown control is done through the use of a FET. Normal operation of the fan is allowed by the 4.7 KΩ pull-up resistor (R26). If powerdown is desired, the GPIO8 pin will turn the FET off. Pin 3 of the fan header allows the fan to signal the Intel740 graphics accelerator that it has failed.
Intel740™ Graphics Accelerator Design Guide 2-25 Addin Card Design
2-26 Intel740™ Graphics Accelerator Design Guide A B C D E
INTEL740(TM) GRAPHICS ACCELERATOR FULL FEATURED REFERENCE CARD
4 4
TITLE PAGE COVER SHEET P.1 BLOCK DIAGRAM P.2 INTEL740(TM) GRAPHICS ACCELERATOR (A) P.3 INTEL740(TM) GRAPHICS ACCELERATOR (B) P.4 +12V VOLTAGE REGULATOR P.5 +12V = 12V ANALOG UNLESS OTHERWISE SPECIFIED BT829B VIDEO DECODER P.6 VCC BT869 VIDEO ENCODER P.7 VCC = 5V DIGITAL UNLESS OTHERWISE SPECIFIED VMI VIDEO CONNECTOR P.8
AGP CONNECTOR P.9 VCC3 VGA CONNECTOR P.10 VCC3 = 3.3V DIGITAL UNLESS OTHERWISE SPECIFIED VMI/DDC/I2C/FANFAIL LEVEL SHIFTER P.11 SO-DIMM P.12 VDD VDDQ = 3.3V AGP POWER SUPPLY SGRAM P.13 VIDEO CONNECTORS P.14 VCC_CORE = VOLTAGE SUPPLIED TO THE INTEL740 CHIP CORE 3 BIOS/FAN CONNECTOR P.15 3
REVISION HISTORY P.16 GND = DIGITAL GND P.17
THIS SPECIFICATION IS PROVEDED AS IS WITH NO WARRANTIES WHATSOVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PRPERTY RIGHTS IS GRANED HEREIN.
INTEL DISCLAIMS ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OF INFORMATION IN THIS SPECIFICATION. INTEL DOES NOT WARRANT OR REPRESENT THAT SUCH USE WILL NOT INFRINGE SUCH RIGHTS.
I2C IS A TWO-WIRE COMMUNICATIONS BUS/PROTOCOL DEVELOPED BY PHILIPS. SMBUS IS A SUBSET OF THE I2C BUS/PROTOCOL AND WAS DEVELOPED BY INTEL. IMPLEMENTATIONS OF THE I2C BUS/PROTOCAL OR THE SMBUS BUS/PROTOCOL MAY REQUIRE LICENSES FROM VARIOUS
2 ENTITIES, INCLUDING PHILIPS ELECTRONICS N.V. AND NORTH 2 AMERICAN PHILIPS CORPORATION.
*THIRD-PARTY BRANDS AND NAMES ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS.
COPYRIGHT * INTEL CORPORATION 1997
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Title Cover Sheet Size Document Number Rev C Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 1 of 16 A B C D E A B C D E
VMI CONNECTOR p. 8 4 4
VIDEO VOLTAGE REGULATOR DECODER VIDEO CONNECTORS p. 5 p. 6 p. 14
CNTL
3 3
TV TUNER INTEL740(TM) ADDR GRAPHICS MEMORY CONNECTOR Graphics Accelerator DATA p. 13 p. 14 p. 3, 4
VGA/DDC CONNECTOR p. 10
2 2 p. 12 SO-DIMM ADDR/DATA CNTL AGP SIDEBAND FLASH ADDR/DATAA BIOS p. 15
A.G.P. CONNECTOR
1 1 VIDEO p. 9 ENCODER p. 7 Title Block Diagram Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 2 of 16 A B C D E A B C D E
4 4
SUBSYSTEM ID IS 0X100 VCC_CORE VCC3 VDDQ VCC3 VCC3
U9A R22 2K 6,11 3VVP[15:0] E07 E09 E11 E13 E14 E16 E18 E20 H22 AB07 AB09 AB11 AB13 AB14 AB16 AB18 AB20 F25 G23 G25 G26 GO5 J05 L05 N05 P05 T05 V05 Y05 AC06 AB08 AB10 AB12 AC13 AC14 AB15 AB17 AB19 AC21 Y22 V22 T22 P22 N22 L22 J22 G22 D06 E08 E10 E12 D13 D14 E15 E17 E19 AD[31:0] 9 3VVP0 C17 Y04 AD0 VENDOR ID IS 0X8086 VP0 AD0 NOTE: 3VVP1 A18 Y02 AD1 D17 VP1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC AD1 Y03 3VVP2 VCCA VCCP VCCA VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP AD2 ----- VP2 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ AD2 3VVP3 B18 Y01 AD3 VP3 AD3 THIS I.D. NEEDS TO C18 W05 3VVP4 VP4 AD4 AD4 3VVP5 A19 W03 AD5 REFLECT BOARD VENDOR VP5 AD5 D18 W04 3VVP6 VP6 AD6 AD6 VCC3 3VVP7 B19 VDDQ W02 AD7 VP7 AD7 3VVP8 C19 VCC3 V02 AD8 VP8 AD8 3VVP9 A20 V03 AD9 VP9 AD9 3VVP10 D19 V01 AD10 VP10 AD10 3VVP11 B20 U05 AD11 VP11 AD11 3VVP12 C20 C124 C117 C123 C132 C130 C131 U03 AD12 VP12 AD12 R47 R52 R51 R55 3VVP13 A21 .1UF .1UF .1UF .1UF .1UF .1UF U04 AD13 D20 VP13 AD13 U02 2K 2K 2K 2K 3VVP14 VP14 AD14 AD14 3VVP15 B21 T04 AD15 VP15 AD15 VIDEO CAPTURE P03 AD16 AD16 J24 P02 AD17 11 3VVRDY VRDY# AD17 K22 P04 AD18 6,11 3VHREF HREF# AD18 L23 VCC3 P01 6,11 3VVREF VREF# AD19 AD19 L24 N03 AD20 6,11 3VVCLK VCLK AD20 N01 7,15 ROMA[17:0] AD21 AD21 3 N04 AD22 3 AD22 ROMA0 A07 N02 AD23 ROMA0 AD23 ROMA1 B08 C17 C121 C112 C110 C76 C70 C109 C74 M04 AD24 ROMA1 AD24 ROMA2 A08 M02 AD25 ROMA2 22UF 10UF .1UF .1UF .01UF .01UF .01UF .1UF AD25 ROMA3 B09 M05 AD26 ROMA3 AD26 ROMA4 A09 L01 AD27 ROMA5 B10 ROMA4 AD27 L03 AD28 ROMA5 AD28 A10 L02 ROMA6 ROMA6 AD29 AD29 ROMA7 B11 L04 AD30 ROMA7 AD30 D11 K01 ROMA8 ROMA8 AD31 AD31 ROMA9 C10 ROMA9 ROMA10 D09 VDDQ ROMA10 ROMA11 D10 V04 ROMA11 C/BE0# CBE0# 9 ROMA12 A11 U01 ROMA12 C/BE1# CBE1# 9 C11 R01 ROMA13 ROMA13 C/BE2# CBE2# 9 ROMA14 D12 M03 ROMA14 C/BE3# CBE3# 9 ROMA15 B12 C113 C115 C128 C116 C125 C114 C126 C133 ROMA15 ROMA16 A12 F02 ROMA16 .1UF .01UF .1UF .01UF .1UF .01UF .1UF .01UF CLK CLK 9 ROMA17 C12 B07 ROMA17 H01 3VROMD0 BIOS INTERFACE SBA0 ROMD0 AGP INTERFACE SBA0 3VROMD1 A06 J04 SBA1 3VROMD2 B06 ROMD1 SBA1 J02 SBA2 ROMD2 SBA2 C06 J03 3VROMD3 ROMD3 SBA3 SBA3 3VROMD4 D07 K03 SBA4 ROMD4 SBA4 3VROMD5 C07 K05 ROMD5 SBA5 SBA5 3VROMD6 D08 K02 SBA6 ROMD6 SBA6 3VROMD7 C08 K04 SBA7 ROMD7 VCC3 SBA7 C09 G03 15 3VROMD[7:0] 15 ROMOE# ROMOE# RESET# RESET# 6,7,8,9 SBA[7:0] 9 15 ROMWE# C13 G04 INTA# 9 ROMWE# INT R05 STOP# STOP# 9 IREFSET# D21 T03 PAR 9 IREFSET# PAR R04 TRDY# TRDY# 9 L25 C39 C54 C111 C44 C98 T01 IRDY# 9 R24 VSS IRDY# AA02 10UF .1UF .1UF .01UF .01UF R03 FRAME# 9 VSSA FRAME# T02 562 DEVSEL# 9 DEVSEL VDDQ 1% TP_03J26 J23 G02 REQ# 9 LEFT REQ# H05 2 GNT GNT# 9 2 TP_03L24 H26 NC TP_03L23 H25 H02 DBF# 9 ST[2:0] 9 L12 NC DBF# VSS G01 ST0 R59 B17 ST0 H04 11 3VVMIINT# VMIINT# ST1 ST1 267 11 3VVMIRDY A17 USE TANTALUM CAPACITORS FOR 10 AND 22UF H03 ST2 1% D16 VMIRDY ST2 8 VMIRD# VMIRD# 8 VMIWR# C16 J01 SB_STB 9 B16 VMIWR# SBSTB 8 VMICS# VMICS# VMIHA0 A16 M01 VMIHA0 ADSTB_1 AD_STB_B 9 VMIHA1 D15 W01 R60 VMIHA1 ADSTB_0 AD_STB_A 9 C15 R02 AGPREF C127 VMIHA2 VMIHA2 AGPREF 182 VMIHA3 B15 A01 VMIHA3 VSS .01UF 1% VMIHA4 A15 A02 VMIHA4 VSS A03
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSA VSS VSS VSSA VSS VSS VSS VSS VSS VSS VSSA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSVSS VSS 8 VMIHA[4:0] L11 F23 F22 F21 F20 F07 F06 F05 F03 H24 E26 E25 E24 E23 E22 E21 E06 E05 E04 E03 E02 E01 D26 D25 D24 D23 D22 D05 D04 D03 D02 D01 C26 C25 C24 C23 C22 C05 C04 C03 C02 C01 B26 B25 B24 B23 B22 B05 B04 B03 B02 B01 A26 A25 A24 A23 A22 A05 A04 INTEL740 G21 G06 INTEL740 (A) AF22 AF05 AF04 AF03 AF02 AF01 AE26 AE25 AE24 AE23
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Title Intel740(TM) Graphics Accelerator(A) Size Document Number Rev C Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 3 of 16 A B C D E A B C D E
VCC3 VCC3 Y3 66.6667MHZ 3 1 OUT OE 4 2 VCC3GND U9 OSC MA[11:0] 12,13 GFX_OSC AA23 AD17 MA0 12,13 CKE CKE MA0 AF16 MA1 4 MA1 4 H23 AC17 MA2 XTAL1 MA2 AE16 MA3 12,13 MD[63:0] MA3 AD18 MA4 MA4 MD0 AD06 AF17 MA5 MD0 MA5 MD1 AE06 AC18 MA6 MD1 MA6 MD2 AC07 AE17 MA7 MD2 MA7 MD3 AF06 AD19 MA8 MD3 MA8 MD4 AD07 AF18 MA9 MD4 MA9 MD5 AF07 AC19 MA10 MD5 MA10 MD6 AC08 AE18 MA11 MD6 MA11 MD7 AE07 AE19 MD7 WEA# WEA# 12 MD8 AD08 AF19 MD8 WEB# WEB# 13 MD9 AF08 AF20 MD9 SRASA# SRASA# 12 MD10 AC09 AE20 MD10 SRASB# SRASB# 13 MD11 AE09 AD20 MD11 SCASA# SCASA# 12 MD12 AD09 AC20 MD12 SCASB# SCASB# 13 MD13 AF09 AA25 MD13 CSA0# CSA0# 13 MD14 AC10 AA26 MD14 CSA1# CSA1# 12 MD15 AE10 Y23 MD15 CSB0# CSB0# 12 DQM[7:0] 12,13 MD16 AC12 Y24 TP_03Y26 MD16 CSB1# MD17 AF11 AD10 DQM0 MD17 DQM0 MD18 AD12 AF10 DQM1 MD18 DQM1
MD19 AE12 DRAM INTERFACE AD11 DQM2 MD19 DQM2 MD20 AD13 AE11 DQM3 3 MD20 DQM3 3 MD21 AF12 R22 DQM4 MD21 DQM4 MD22 AD14 T25 DQM5 MD22 DQM5 MD23 AE13 R23 DQM6 MD23 DQM6 MD24 AD15 T26 DQM7 MD24 DQM7 33 MD25 AF13 AF21 RT0 R46 MD25 TCLKA 33 TCLK0 12 MD26 AC15 AE21 RT1 R45 MD26 TCLKB TCLK1 13 MD27 AF14 AD21 TDLY MD27 OCLK MD28 AD16 AC11 RCLK0 MD28 RCLK0 MD29 AF15 T24 RCLK1 MD29 RCLK1 33 MD30 AC16 R38 MD30 MD31 AE15 AA24 TP_03AA24 VCC3 MD31 RSVD 33 MD32 W22 AE08 TP_03AE08 R37 MD32 RSVD MD33 Y25 AE14 TP_03AE14 MD33 RSVD MD34 W23 V24 TP_03V24 MD34 RSVD MD35 Y26 N25 TP_03N25 MD35 MEMORY DATA BUS RSVD MD36 W24 R61 MD36 MD37 W25 R49 MD37 4.7K MD38 V23 MD38 4.7K MD39 W26 F24 MD39 RED RED 10 MD40 U22 F26 MD40 GREEN GREEN 10 MD41 V25 G24 MD41 BLUE BLUE 10 MD42 U23 MD42 MD43 V26 J25 MD43 VSYNC VSYNC 10 2 MD44 U24 J26 2 MD44 HSYNC HSYNC 10 MD45 U25 K26 MD45 DDCCLK 3VDDCCL 11 MD46 T23 K25 MD46 DDCDATA 3VDDCDA 11 MD47 U26 MD47 DISPLAY INT MD48 R24 K23 MD48 GPIO0 3VSDA 6,7,8,11,12 MD49 R25 K24 MD49 GPIO1 3VSCL 6,7,8,11,12 MD50 P23 C14 MD50 GPIO4 GPIO4 15 MD51 R26 B14 MD51 GPIO5 GPIO5 8 MD52 P24 A14 MD52 GPIO6 GPIO6 11 MD53 P25 B13 MD53 GPIO7 GPIO7 8 MD54 N24 A13 MD54 GPIO8 GPIO8 6,7,8,15 MD55 P26 MD55 MD56 N23 C21 MD56 IWASTE MD57 N26 VCC_PLL R5 R7 MD57 MD58 M24 MD58 20K 20K MD59 M26 F01 MD59 VCCDP MD60 M23 F04 MD60 VCCAP MD61 M25 AA01 MD61 VCCDP MD62 M22 AA04 MD62 VCCAP MD63 L26 AF23 MD63 VSS AF24 AF26 VSS AF25 VSVSS VSS S VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 1 1 L16 L15 L14 L13 Y21 Y06 T16 T15 T14 T13 T12 T11 P16 P15 P14 P13 P12 P11 N16 N15 N14 N13 N12 N11 R16 R15 R14 R13 R12 R11 M16 M15 M14 M13 M12 M11 AE22 AE05 AE04 AE03 AE02 AE01 AB26 AB25 AB24 AB23 AB22 AB21 AB06 AB05 AB04 AB03 AB02 AB01 AA22 AA21 AA20 AA07 AA06 AA05 AA03 AD26 AD25 AD24 AD23 AD22 AD05 AD04 AD03 AD02 AD01 AC26 AC25 AC24 AC23 AC22 AC05 AC04 AC03 AC02 AC01
INTEL740 Title Intel740(TM) Graphics Accelerator(B) Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 4 of 16 A B C D E A B C D E
POWER CONFIGURATION* ______R50 R44 R42 R43 CORE PLL STUFF EMPTY STUFF EMPTY 3.3V 2.7V EMPTY STUFF STUFF EMPTY 2.7V 2.7V STUFF EMPTY EMPTY STUFF 3.3V 3.3V EMPTY STUFF EMPTY STUFF 2.7V 3.3V *DEFAULT +12V 4 4 VCC3 VCC_CORE
R50 0 C52 1UF U7 LT1575 R44 1 8 C53 C40 SHDN IPOS 0 2 7 VIN INEG 1UF 100UF 3 6 L_GATE R36 GND GATE 4 5 COMP1 * THE DEFAULT POWER CONFIGURATION FB COMP 4.7 IS NOT REPRESENTED HERE
NOTE: VCC_PLL 3 3 ---- FB1575 THE NET CONNECTING C60 TO C61 R40 VCC_REGULATED R42 SHOULD BE CONNECTED DIRECTLY TO PIN 3 OF THE LT1575 DUE TO 150 0 THE GROUND BOUNCE SENSIVITITY OF THE LT1575 COMPENSATION PIN R35 R43 7.5K R_ R41 C60 GATE 0 120 10PF TO VARY THE OUTPUT VOLTAGE, REPLACE Q2 2 R40 WITH THE FOLLOWING VALUES TO DRN 1 ACHIEVE THE VARIOUS OUTPUT GATE 3 RECOMMENDED HEXFET: VOLTAGES: SRC ------MOTOROLA PART# MTD3055VLT4
R40 VOUT M_CO HEXFET SAMSUNG CORNING CO. LTD ------2 PART# SSR3055-TM 2 150 2.7V MP1 160 2.8V C61 170 2.9V 1000PF 180 3.0V
VCC_CORE
C86 C75 C64 C80 C81 C65 C63 C62 C87 C89 C88 C82 22UF 10UF .1UF .1UF .01UF .01UF .1UF .1UF .01UF .01UF .1UF .01UF
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Title Voltage Regulator Size Document Number Rev A Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 5 of 16 A B C D E A B C D E
NOTE: ANALOG PLANE NEEDS TO BE FENCED FROM THE DIGITAL PLANE
VCC3 VCC
4 BT829B 4 U4 92 30 20 1 96 88 76 38 10 3 3 3 50
C1 MUX3 VCC VCC VCC VCC VCC
MUX2 45 VCC VCC VCC3 VCC 53 MUXOUT_YIN 14 SV_LUM MUX2 MUXOUT C27 MUX1 57 14 CV_IN MUX1 C28 MUX0 55 14 TUNER 1UF MUX0 1UF 41 AGCCAP 52 AGCCAP 1UF YIN C38 CIN 67 43 14 SV_CHR CIN REFOUT TP_0559 59 82 TP_0582 SYNCDET HRESET* 79 1UF 3VVREF 3,11 R10 R17 VRESET* 49 83 3VHREF 3,11 62 YREF+ ACTIVE 94 75 75 YREF- QCLK 3VVCLK 3,11 REFOUT 64 78 TP_0578 CREF+ FIELD 73 89 TP_0589 CREF- CBFLAG 3VVP[15:0] 3,11 R9 R19 CLEVEL 74 CLEVEL 68 2 3VVP15 75 75 NC VD15 101 3 3VVP14 NC VD14 C5 C2 C6 51 4 3VVP13 NC VD13 46 5 3VVP12 .1UF .1UF .1UF NC VD12 63 6 3VVP11 NC VD11 70 7 3VVP10 3 NC VD10 3 69 8 3VVP9 VCC3 NC VD9 9 3VVP8 VD8 19 22 3VVP7 4,7,8,11,12 3VSCL SCL VD7 18 23 3VVP6 4,7,8,11,12 3VSDA SDA VD6 14 24 3VVP5 I2CCS VD5 15 25 3VVP4 3,7,8,9 RESET# RST* VD4 26 3VVP3 R26 VD3 27 3VVP2 VCC3 VD2 10K VCC3 28 3VVP1 VD1 29 3VVP0 VD0 98 84 TP_0584 OE* DVALID 91 87 CCVALID 4,7,8,15 GPIO8 PWRDN CCVALID 86 TP_0586 80 VACTIVE* 85 NUMXTAL OEPOLE 12 XT0I XT0I 34 13 XT0O TCK XT0O 36 16 XT1I TMS XT1I 37 17 XT1O TDI XT1O VCC TP_0532 32 97 TP_0597 TDO CLKX1 35 99 TP_0599 R11 R18 TRST* CLKX2 42 40 GND AVCC 1M 1M 2 47 44 VCC 2 54 GND AVCC 48 TIE PINS TO Y1 Y2 GND AVCC 56 60 ANALOG FENCE 58 GND AVCC 65 C12 C48 C7 C51 C49 61 GND AVCC 72 GND AVCC 35.46895MHZ 28.63636MHZ 10UF .01UF .1UF .01UF .1UF 66 71 GND L3 L6 GND 75 C21 C22 2.7UH C33 C34 2.7UH
GNDGND GND GND GND GND GND GND GND GND GND GND 22PF 22pF 22pF 22pF
VCC3 95 93 90 81 77 39 33 31 21 11 100
XT1CAP XT0CAP
C23 C35 68PF 100PF C16 C43 C45 C100 C101 10UF .1UF .01UF .1UF .01UF
DECOUPLING FOR ANALOG FENCE
VCC 1 1
C13 C14 C32 C29 C4 C3 10UF 10UF .01UF .1UF .01UF .1UF Title Bt829B Video Decoder Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 6 of 16 A B C D E A B C D E
VCC3 3VAA_BT869 FB3 NOTE: MAKE 3VAA_BT869 A CUTOUT IN POWER PLANE NOTE: ANALOG PLANE NEEDS TO BE FENCED FROM THE DIGITAL PLANE 1 2 PRIMARY SIGNALS SHOULD NOT CROSS CUTOUT
FB C50 C79 C55 C59 C58 C57 C69 C56 C71 C68 C96 C93 C94 10UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .01UF 10UF .1UF .01UF 4 4
3VAA_BT869 U8 BT868/869 1P
34 59 33 P<23> VAA_PLL 80 32 P<22> VAA 69 29 P<21> VAA_DACA 73 28 P<20> VAA_DACC 71 27 P<19> VAA_DACB 26 P<18> 19 25 P<17> VDD_I 20 24 P<16> VDD1 30 C95 P<15> VDD_O 23 40 .1UF 18 P<14> VDD2 46 3,15 ROMA[17:0] 17 P<13> VDD_SO 47 P<12> VDD_SI ROMA11 16 57 P<11> VDD_CO ROMA10 15 60 P<10> VDD3 ROMA9 14 61 3 P<9> VDD_X 3 ROMA8 13 P<8> ROMA7 12 75 COMP2 P<7> COMP ROMA6 11 P<6> ROMA5 10 68 P<5> DACA TVOUT_Y 14 ROMA4 9 P<4> ROMA3 8 70 P<3> DACB ROMA2 7 P<2> 3 ROMA1 6 72 P<1> DACC ROMA0 5 CR8 R53 P<0> 78 FSADJUST869 FSADJUST CR 75 1% 3,15 ROMA16 77 VBIAS869 3,15 ROMA15 VBIAS 76 VREF869 3,15 ROMA12 VREF 2 1 37 FIELD 56 R58 CLKO 3VAA_BT869 3VAA_BT869 66 C107 C108 RESERVED1 100 TVOUT_C 14 35 67 .1UF .1UF R39 36 HSYNC* RESERVED2 2 38 VSYNC* NC1 3 10K BLANK* NC2 3
2 51 1 CR7 2 SLAVE AGND1 R54 4,6,8,15 GPIO8 52 79 CR 50 SLEEP AGND2 65 PAL AGND_DAC1 75 1% ALTADDR 48 74 ALTADDR AGND_DAC2 49 4 2 1 VDDMAX VSS 21 44 VSS 39 4,6,8,11,12 3VSDA 45 SID VSS 22 4,6,8,11,12 3VSCL SIC VSS_I 31 TVOUT_CVBS 14 54 VSS_O 41 3 ROMA17 CLKI VSS 42 VCC3 63 VSS_SI 43 62 XTALIN VSS_SO 55 3 XTALOUT VSS_CO 64 CR6 R56 53 VSS_X 58 3,6,8,9 RESET# RESET* AGND_PLL CR 75 1% MODE869 R3 69
10K 2 1 T869 J1 1X3HDR C106 XTALIN8
NTSC_MODE XTALOU 1 2 ROMA13 3,15 1 PAL_MODE 1 3 ROMA14 3,15 22PF R57 PINS 1-2 = NTSC Y4 1M R6 PINS 2-3 = PAL 13.500MHZ 10K Title C105 Bt869 Video Encoder Size Document Number Rev Note: Y4 should be parrallel resonant 20 pF load. B 2.1 22PF Intel740(TM) Graphics Accelerator Reference Card Date: Thursday, April 09, 1998 Sheet 7 of 16 A B C D E A B C D E
+12V VCC VCC3
4 4
3 VMIHA[3:0] 2X20RCPT J7 RT3 VMIHA0 Y7 Z1 HA0 12V THERMISTOR VMIHA1 Z8 HA1 VMIHA2 Y8 Y9 t HA2 5V 11 5VVP[7:0] VMIHA3 Z9 Z5 HA3 5V Z16 5V 5VVP0 Y1 HD0 5VVP1 Z2 Y16 VMI3V PHYSICAL PINOUT VIEW OF THE 40 PIN HEADER (COMPONENT SIDE) HD1 3.3V 5VVP2 Y3 Z13 HD2 3.3V 5VVP3 Z4 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 HD3 5VVP4 Y4 Y18 TP_07Y18 Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 Z9 Z10 Z11 Z12 Z13 Z14 Z15 Z16 Z17 Z18 Z19 Z20 HD4 KEY 5VVP5 Y5 HD5 5VVP6 Z6 Y2 HD6 GND 5VVP7 Y6 Y11 HD7 GND Z3 NOTE: GND TP_07Z19 Z19 Z10 40-PIN FEMALE HEADER RECOMMENDED PARTS Y10 INSERT# GND 3,6,7,9 RESET# ------Y12 RESET# Z7 3 VMIWR# TP_07Z7 AMP PART# 2-535598-3 Y13 WR# OSC Z14 11 5VVMIRDY TP_07Z14 Y14 READY SCLK Z15 BERG PART# 68683-320 3 11 5VVMIINT# TP_07Z15 3 Z11 INTREQ# LRCK Z20 3 VMICS# CS# AUDGND Z12 Y19 TP_07Y19 3 VMIRD# RD# AUDIOL Y20 TP_07Y20 AUDIOR Y15 TP_07Y15 PCMDATA Y17 VMIHA4 3 USRDEF Z17 GPIO5 4 USRDEF Z18 USRDEF GPIO8 4,6,7,15
2X20RCPT
2 2
J6 2X13 MALE HDR 5VVP[15:8] 11 Z1 Y1 5VVP8 GND VID0 Z2 Y2 5VVP9 GND VID1 Z3 Y3 5VVP10 PHYSICAL PINOUT VIEW OF THE 26 PIN HEADER (COMPONENT SIDE) GND VID2 Z4 Y4 5VVP11 11 5VVRDY VACTIVE VID3 Z5 Y5 5VVP12 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 4 GPIO7 USRDEF VID4 Z6 Y6 5VVP13 Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 Z9 Z10 Z11 Z12 Z13 11 5VVREF VREF VID5 Z7 Y7 5VVP14 4,6,7,11,12 3VSCL I2CCLK VID6 Z8 Y8 5VVP15 R63 GND VID7 0 Z9 Y9 L5VVCLK R62 GND PIXCLK 5VVCLK 11 Z10 Y10 L5VHREF NOTE: GND HREF 5VHREF 11 Z11 Y11 TP_0724 GND NC 0 26-PIN MALE HEADER RECOMMENDED PARTS TP_0723 Z12 Y12 TP_0726 ------Z13 USRDEF NC Y13 4,6,7,11,12 3VSDA I2CDAT GND AMP PART# 1-103186-3 BERG PART# 67997-426
2X13 MALE HDR
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Title VMI Video Connectors Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 8 of 16 A B C D E A B C D E
+12V VCC3 VDDQ
NOTE: ---- USE TANTALUM CAPS C120 C122 C129 22UF 22UF 22UF +12V VCC3 VDDQ VCC
4 4 J8 AGP CARD EDGE 3 AD[31:0] GOLD AD31 B26 A1 AD31 12V AD30 A26 B2 AD30 VCC5 AD29 B27 B3 AD29 VCC5 AD28 A27 AD28 AD27 B29 A9 AD27 VCC AD26 A29 B9 AD26 VCC AD25 B30 A16 AD25 VCC AD24 A30 B16 AD24 VCC AD23 B33 A28 AD23 VCC AD22 A35 B28 AD22 VCC AD21 B35 A45 AD21 VCC AD20 A36 B45 AD20 VCC AD19 B36 AD19 AD18 A38 A34 AD18 VDDQ AD17 B38 B34 AD17 VDDQ AD16 A39 A40 AD16 VDDQ AD15 A51 B40 AD15 VDDQ AD14 B53 B47 AD14 VDDQ AD13 A53 A52 AD13 VDDQ AD12 B54 B52 AD12 VDDQ AD11 A54 A58 3 AD11 VDDQ 3 AD10 B56 B58 AD10 VDDQ AD9 A56 A64 AD9 VDDQ AD8 B57 B64 AD8 VDDQ SBA[7:0] 3 AD7 B60 AD7 AD6 A60 A21 SBA7 AD6 SBA7 R64 AD5 B62 B21 SBA6 AD5 SBA6 RAD_STB_A AD4 A62 A20 SBA5 3 AD_STB_A AD4 SBA5 AD3 B63 B20 SBA4 AD3 SBA4 43 AD2 A63 A17 SBA3 AD2 SBA3 AD1 B65 B17 SBA2 AD1 SBA2 AD0 A65 A15 SBA1 AD0 SBA1 R65 B15 SBA0 RAD_STB_B B59 SBA0 R66 3 AD_STB_B B32 AD_STB0 B18 SB_STB 3 43 AD_STB1 SB_STB A33 A5 0 3 CBE3# B39 C_BE*3 GND B5 3 CBE2# B51 C_BE*2 GND A13 3 CBE1# A57 C_BE*1 GND B13 3 CBE0# C_BE*0 GND 3 ST[2:0] A19 GND B19 GND ST2 B11 A31 ST2 GND ST1 A10 B31 ST1 GND 2 ST0 B10 A37 2 ST0 GND B37 GND TP_08B4 B4 A43 USB+ GND TP_08A4 A4 B43 USB- GND A49 GND TP_08A66 A66 B49 RSVD GND TP_08B66 B66 A55 RSVD GND B55 A6 GND A61 3 INTA# INTA GND TP_08B6 B6 B61 B7 INTB GND 3 CLK PCICLK A7 B1 TP_08B1 3,6,7,8 RESET# PCIRST* OVRCNT* B12 A48 TP_08A48 3 DBF# RBF* PME* TP_08A12 A12 A2 TP_08A2 PIPE* RSVD B14 TP_08B14 B8 RSVD A14 3 REQ# TP_08A14 A8 GREQ* RSVD 3 GNT# GGNT* A42 TP_08A42 RSVD B46 B42 TP_08B42 3 DEVSEL# DEVSEL* RSVD A46 A44 TP_08A44 3 TRDY# TRDY* RSVD B41 B44 TP_08B44 3 IRDY# IRDY* RSVD A41 A11 TP_08A11 3 FRAME# FRAME* RSVD A47 A18 TP_08A18 3 STOP# STOP* RSVD TP_08B48 B48 A32 TP_08A32 PERR* RSVD 1 TP_08B50 B50 A3 TP_08A3 1 SERR* RSVD A50 A59 TP_08A59 3 PAR PAR RSVD
Title AGP Card Edge Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 9 of 16 A B C D E A B C D E
VCC3
4 4 CR4 1
3
2 VCC3
VCC VCC VCC BAV99 CR2 CR3 1 1
3 3 RT1 2 R2 THERMISTOR 2 1K t CR5 BAV99 BAV99 1 SOT23S DIO HIDDEN PINS: 3 GND: 16,17 CR1 USED FOR BRD MOUNT 2 1 3 3 3 BAV99 R1 FB4 1K 2 1 2 J2 4 RED FB 6 FUSE_5 BAV99 11 R34 L_RED 1 75 C67 C66 7 22PF 22PF 12 L_GREEN 2 MON0PU 8 13 L_BLUE 3 9 5VDDCDA 11 FB2 14 1 2 4 4 GREEN MON2PU 10 FB 15 R28 5 R20 VGA_HSYNC HSYNC 4 C47 C46 75 0 R21 22PF 22PF VGA CONN VGA_VSYNC VSYNC 4 0 2 2
FB1 5VDDCCL 5VDDCCL 11 1 2 4 BLUE FB R25 75 C42 C41 22PF 22PF
1 1
Title VGA Connector Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 10 of 16 A B C D E A B C D E
QSV
QS3861 8 5VVP[15:0] U2 3VVP[15:0] 3,6 5VVP0 2 22 3VVP0 4 A0 B0 4 5VVP1 3 21 3VVP1 A1 B1 5VVP2 4 20 3VVP2 C8 C9 A2 B2 5VVP3 5 19 3VVP3 VCC A3 B3 .1UF .01UF 5VVP4 6 18 3VVP4 A4 B4 5VVP5 7 17 3VVP5 A5 B5 5VVP6 8 16 3VVP6 A6 B6 5VVP7 9 15 3VVP7 10 A7 B7 14 R4 8 5VVRDY 3VVRDY 3 11 A8 B8 13 8 5VVREF A9 B9 3VVREF 3,6 1.62K 23 24 QSV 1 BE* QSV 12 NC GND 15 QSV
QS3861 R8 10K
QSV 8 5VVP[15:0] U5 QS3861 3VVP[15:0] 3,6 5VVP15 2 22 3VVP15 A0 B0 5VVP14 3 21 3VVP14 A1 B1 5VVP13 4 20 3VVP13 3 A2 B2 3 5VVP12 5 19 3VVP12 A3 B3 5VVP11 6 18 3VVP11 C24 C25 A4 B4 5VVP10 7 17 3VVP10 A5 B5 .1UF .01UF 5VVP9 8 16 3VVP9 A6 B6 5VVP8 9 15 3VVP8 10 A7 B7 14 8 5VHREF 3VHREF 3,6 11 A8 B8 13 8 5VVCLK A9 B9 3VVCLK 3,6 23 24 4 GPIO6 QSV 1 BE* QSV 12 NC GND
QS3861
VCC VCC3
R29 R15 2 10K 10K 2 R30 R14 10K 10K
R31 R13 2.2K 2.2K QSV R32 R12 2.2K 2.2K U3 QS3861 2 22 C10 C11 8 5VVMIINT# 3VVMIINT# 3 3 A0 B0 21 8 5VVMIRDY 3VVMIRDY 3 .1UF .01UF 4 A1 B1 20 14 5VSCL A2 B2 3VSCL 4,6,7,8,12 14 5VSDA 5 19 3VSDA 4,6,7,8,12 6 A3 B3 18 10 5VDDCDA 3VDDCDA 4 7 A4 B4 17 10 5VDDCCL A5 B5 3VDDCCL 4 TP_1008 8 16 TP_1016 A6 B6 TP_1009 9 15 TP_1015 A7 B7 TP_1010 10 14 TP_1014 A8 B8 TP_1011 11 13 TP_1012 A9 B9 1 23 24 QSV 1 1 BE* QSV 12 NC GND
QS3861 Title DDC/I2C Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 11 of 16 A B C D E A B C D E
VCC3
SO-DIMM CONN.
J476 75 64 63 48 47 28 27 12 11 4 4 3 3 3 3 3 3
4,13 MA[11:0] VCC3 VCC VCC3 VCC VCC VCC3 VCC VCC3 VCC VCC MD[63:0] 4,13 MA11 79 3 MD63 RSVD(A11) DQ63 MA10 80 4 MD62 RSVD(A10) DQ62 MA9 81 5 MD61 A9 DQ61 MA8 82 6 MD60 A8 DQ60 MA7 83 7 MD59 A7 DQ59 MA6 84 8 MD58 A6 DQ58 MA5 87 9 MD57 A5 DQ57 MA4 88 10 MD56 A4 DQ56 MA3 89 13 MD55 A3 DQ55 MA2 90 14 MD54 A2 DQ54 MA1 91 15 MD53 A1 DQ53 MA0 92 16 MD52 A0 DQ52 17 MD51 DQ51 67 18 MD50 4 SRASA# RAS* DQ50 68 19 MD49 4 SCASA# CAS* DQ49 69 20 MD48 4 WEA# WE* DQ48 29 MD47 DQ47 65 30 MD46 4 CSB0# CS1 DQ46 66 31 MD45 4 CSA1# CS0 DQ45 32 MD44 3 DQ44 3 73 33 MD43 4 TCLK1 CLK1 DQ43 74 34 MD42 4 TCLK0 CLK0 DQ42 35 MD41 DQ41 70 36 MD40 4,13 CKE CKE DQ40 57 39 MD39 DSF DQ39 40 MD38 DQ38 141 41 MD37 4,6,7,8,11 3VSDA SDA DQ37 142 42 MD36 4,6,7,8,11 3VSCL SCL DQ36 43 MD35 4,13 DQM[7:0] DQ35 44 MD34 DQ34 DQM7 23 45 MD33 DQMB7 DQ33 DQM6 24 46 MD32 DQMB6 DQ32 DQM5 25 95 MD31 DQMB5 DQ31 DQM4 26 96 MD30 DQMB4 DQ30 DQM3 115 97 MD29 DQMB3 DQ29 DQM2 116 98 MD28 DQMB2 DQ28 DQM1 117 99 MD27 DQMB1 DQ27 DQM0 118 100 MD26 DQMB0 DQ26 93 101 MD25 VCC3 DQ25 94 102 MD24 VCC3 DQ24 113 105 MD23 VCC3 DQ23 114 106 MD22 VCC3 DQ22 VCC3 129 107 MD21 VCC3 DQ21 2 130 108 MD20 2 VCC3 DQ20 143 109 MD19 VCC3 DQ19 144 110 MD18 VCC3 DQ18 145 111 MD17 NC DQ17 146 112 MD16 NC DQ16 147 121 MD15 NC DQ15 148 122 MD14 NC DQ14 TP_1158 58 123 MD13 RFU DQ13 TP_1159 59 124 MD12 RFU DQ12 TP_1160 60 125 MD11 RFU DQ11 TP_1161 61 126 MD10 RFU DQ10 62 127 MD9 SBA DQ9 128 MD8 DQ8 TP_1149 49 131 MD7 RSVD DQ7 TP_1150 50 132 MD6 RSVD DQ6 TP_1151 51 133 MD5 RSVD DQ5 TP_1152 52 134 MD4 RSVD DQ4 TP_1153 53 135 MD3 RSVD DQ3 TP_1154 54 136 MD2 RSVD DQ2 TP_1177 77 137 MD1 RSVD DQ1 TP_1178 78 138 MD0 RSVD DQ0 140 1 139 GND GND 2 1 120 GND GND 21 1 119 GND GND 22 GND GND
GND GND GND GND GND GND GND GND GND GND Title SO-DIMM Connector 86 85 72 71 56 55 38 37 SODIMM CONNECTOR 104 103 Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 12 of 16 A B C D E A B C D E
VCC3 VCC3
4 4
C36 C77 C78 C118 .1UF .01UF .1UF .01UF
VCC3 VCC3 VCC3
VCC3 VCC3 VCC3
SGRAM 512Kx32 SGRAM 512Kx32
U1215 35 65 73 67 22 14 8 U615 35 65 73 67 22 14 8 3 3
92 3 3 3 3 3 89 92 3 3 3 3 3 89 93 NC NC 90 93 NC NC 90 NC NC NC NC
94 VCC VCC3 VCC VCC3 VCC VCC VCC3 VCC 91 94 VCC3 VCC VCC VCC3 VCC VCC3 VCC VCC 91 MD[31:0] 4,12 MD[63:32] 4,12 79 NC NC 2 79 NC NC 2 VCC3 VCC3 VCC3 VCC3 55 84 MD31 55 84 MD63 4 TCLK1 CLK DQ31 CLK DQ31 83 MD30 83 MD62 DQ30 DQ30 59 81 MD29 59 81 MD61 VDDQ DQ29 VDDQ DQ29 58 80 MD28 58 80 MD60 VREF/MCH DQ28 VREF/MCH DQ28 TP_17195 95 78 MD27 TP_17295 95 78 MD59 NC/DRDY DQ27 NC/DRDY DQ27 54 77 MD26 54 77 MD58 4,12 CKE CKE DQ26 4,12 CKE CKE DQ26 96 75 MD25 96 75 MD57 VCC3 DQ25 VCC3 DQ25 28 74 MD24 28 74 MD56 4 CSA0# CS* DQ24 4 CSA0# CS* DQ24 21 MD23 21 MD55 DQ23 DQ23 27 20 MD22 27 20 MD54 4 SRASB# RAS* DQ22 4 SRASB# RAS* DQ22 18 MD21 18 MD53 DQ21 DQ21 26 17 MD20 26 17 MD52 4 SCASB# CAS* DQ20 4 SCASB# CAS* DQ20 13 MD19 13 MD51 DQ19 DQ19 25 12 MD18 25 12 MD50 4 WEB# WE* DQ18 4 WEB# WE* DQ18 10 MD17 10 MD49 DQ17 DQ17 53 9 MD16 53 9 MD48 4,12 DQM[3:0] DSF DQ16 4,12 DQM[7:4] DSF DQ16 72 MD15 72 MD47 DQ15 DQ15 DQM3 57 71 MD14 DQM7 57 71 MD46 DQM3 DQ14 DQM3 DQ14 DQM2 24 69 MD13 DQM6 24 69 MD45 DQM2 DQ13 DQM2 DQ13 2 DQM1 56 68 MD12 DQM5 56 68 MD44 2 DQM1 DQ12 DQM1 DQ12 DQM0 23 64 MD11 DQM4 23 64 MD43 DQM0 DQ11 DQM0 DQ11 101 63 MD10 101 63 MD42 NC DQ10 NC DQ10 MA9 29 61 MD9 MA9 29 61 MD41 A10(BA) DQ9 A10(BA) DQ9 MA8 51 60 MD8 MA8 51 60 MD40 A9(AP) DQ8 A9(AP) DQ8 MA10 30 7 MD7 MA10 30 7 MD39 A8 DQ7 A8 DQ7 MA7 50 6 MD6 MA7 50 6 MD38 A7 DQ6 A7 DQ6 MA6 49 4 MD5 MA6 49 4 MD37 A6 DQ5 A6 DQ5 MA5 48 3 MD4 MA5 48 3 MD36 A5 DQ4 A5 DQ4 MA4 47 1 MD3 MA4 47 1 MD35 A4 DQ3 A4 DQ3 MA3 34 100 MD2 MA3 34 100 MD34 A3 DQ2 A3 DQ2 MA2 33 98 MD1 MA2 33 98 MD33 A2 DQ1 A2 DQ1 MA1 32 97 MD0 MA1 32 97 MD32 A1 DQ0 A1 DQ0 MA0 31 40 MA0 31 40 5 A0 NC 41 5 A0 NC 41 11 GND NC 42 11 GND NC 42 4,12 MA[10:0] 4,12 MA[10:0] 19 GND NC 43 19 GND NC 43 62 GND NC 44 62 GND NC 44 70 GND NC 45 70 GND NC 45 76 GND NC 52 76 GND NC 52 82 GND NC 87 82 GND NC 87 99 GND NC 88 99 GND NC 88 NC NC NC NC NC NC NC NC
GNDGND GND GND GND NC GNDGND GND GND GND NC
SGRAM 512Kx32 SGRAM 512Kx32
1 16 46 66 85 36 37 38 39 16 46 66 85 36 37 38 39 1
Title SGRAMS Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 13 of 16 A B C D E A B C D E
+12V
C103 4 RT2 4 THERMISTOR t 22PF L9 CONX_20 TVOUT_Y 7 1.8UH C102 C104 330PF 220PF
11 5VSCL
11 5VSDA
L5 C84 6 TUNER TVTUNERIN 3.3UH SVINC
22PF C26 C31 3 L7 3 330PF 330PF 2 4 401 403 405 CONX_24 TVOUT_C 7 1.8UH TP_1 TP_140 TP_1 TP_140 TP_1
C83 C85 330PF 220PF I 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L1 J5 51 52 6 SV_LUM 3.3UH 50 PIN SCS
C15 C20 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 330PF 330PF
C91 7 9 426 428
TP_1 TP_142 TP_1 TP_142 22PF L4 L8 2 2 6 SV_CHR CONX_47 TVOUT_CVBS 7 3.3UH 1.8UH
C37 C30 C90 C92 330PF 330PF TVTUNER12V 330PF 220PF SVINY
RCA_IN
L2 6 CV_IN 3.3UH
C19 C18 PHYSICAL PINOUT OF THE 50 PIN CONNECTOR (FACE VIEW) 330PF 330PF 51 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 52 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
1 1
NOTE: 50-PIN FEMALEL SCSI CONNECTOR RECOMMENDED PART ------Title AMP PART# 787170-5 Video Connector Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 14 of 16 A B C D E A B C D E
+12V VCC 11 QSV VCC3
VCC 4 R48 C72 C119 C73 C97 C99 4 2K .1UF 22UF .01UF .1UF .01UF PLCC SOCKET FOR BIOS U11 24 32 3 ROMOE# 31 OE# VCC 16 3 ROMWE# 22 WE# GND 4,6,7,8 GPIO8 CE# 3,7 ROMA[17:0] ROMA16 2 21 5VROMD7 A16 DQ7 ROMA15 3 20 5VROMD6 A15 DQ6 ROMA14 29 19 5VROMD5 A14 DQ5 ROMA13 28 18 5VROMD4 A13 DQ4 ROMA12 4 17 5VROMD3 A12 DQ3 ROMA11 25 15 5VROMD2 A11 DQ2 ROMA10 23 14 5VROMD1 A10 DQ1 ROMA9 26 13 5VROMD0 A9 DQ0 ROMA8 27 A8 ROMA7 5 A7 QS3861 ROMA6 6 1 U13 A6 VPP ROMA5 7 30 5VROMD7 2 22 3VROMD7 A5 RP* A0 B0 ROMA4 8 VCC 5VROMD6 3 21 3VROMD6 A4 A1 B1 ROMA3 9 5VROMD5 4 20 3VROMD5 3 A3 A2 B2 3 ROMA2 10 5VROMD4 5 19 3VROMD4 A2 A3 B3 ROMA1 11 5VROMD3 6 18 3VROMD3 A1 A4 B4 ROMA0 12 5VROMD2 7 17 3VROMD2 A0 A5 B5 5VROMD1 8 16 3VROMD1 U10 A6 B6 Mounting Holes for Fan 5VROMD0 9 15 3VROMD0 10 A7 B7 14 PLCC SOCKET TP_U51410 TP_U51414 1 4 11 A8 B8 13 TP_U51411 TP_U51413 3VROMD[7:0] 3 NOTE: A9 B9 2 3 32-PIN PLCC SOCKET RECOMMENDED PART 23 24 QSV 1 BE* QSV 12 ------NC GND AMP PART# 3-822273-1 QS3861 MH1 MH2 MH3 MH4
VCC NOTE: FET MUST BE CAPABLE OF SOURCING 160MA VCC
2 R27 2 4.7K
U1-2 74LVT125 Q1 5 6 5VFF MOSFET P
R33 Stuffing Option
4 0 When Used, Fan Is Always On VCC3
4,6,7,8 GPIO8
FANPOWER R16 FAN HEADER 4.7K 1X3HDR J3
1 1 R23 1 2 FANOUT 3 GPIO4 4
0 Title BIOS/FAN Size Document Number Rev B Intel740(TM) Graphics Accelerator Reference Card 2.1 Date: Thursday, April 09, 1998 Sheet 15 of 16 A B C D E A B C D E
1.1 REVISIONS 1.5 REVISIONS PULL-DOWN REISITOR ON GPIO4 REMOVED C39, C41, C42, & C44 CHANGED TO 15PF ON P.5, NO PACKAGE SIZE CHANGE NEEDED SIGNAL GPI08 ADDED TO VMI 2X20 HEADER ON PIN Z18 FAN FAIL SIGNAL REMOVED FROM QSWITCH SIGNALS XT1CAP AND XT0CAP RELOCATED SINCE XTAL FILTERS CHANGED ON P.5 OE# ON INTEL740(TM) GRAPHICS ACCELERATOR OSCILLATOR PULLED HI TO 3.3V L3 AND L4 ON P.5 CHANGED TO 4.7UH NAD LOCATION IN XTAL FILTER CIRCUIT CHANGED MEMORY ADDRESSES 8,9 AND 10 FROM INTEL740 CONNTECTED TO 9,10 AND 8 OF SODIMM CONNECTOR, RESPECTIVELY GPIO4 PULLED UP TO 3.3V THRU 4.7K RESISTOR PIN 36, 37, 80, & 85 CONNECTED TO VCC3 INSTEAD OF VCC ON THE BT829ALV ON P.5 R20 ON P.5 NOW CONNECTS TO VCC3 INSTEAD OF VCC 1.2 REVISIONS C20, C22, C23 AND C26 ON P.5 CHANGED FROM 0.1UF TO 1UF. THESE ARE THE AC CAPS TO MUX INPUTS. THIS REQUIRED A PACKAGE SIZE CHANGED FROM 0805 TO 1206. 4 MEMORY ADDRESSES 8,9 AND 10 FROM INTEL740(TM) GRAPHICS ACCELERATOR CONNECTED TO 8,9 AND 10 OF 4 SODIMM CONNECTOR, RESPECTIVELY VCC CONNECTION TO PIN 59 OF BT829B (P.5) DELETED. WIRE LEFT OPEN AND RENAMED TP_0559. POWER SUPPLY VDDQ3 CHANGED TO VDD REMOVED NOTE NEAR PIN 59 OF BT829B (P.5) WHICH STATED TIE TO ANALOG FENCE 1.3 REVISIONS DELETED R13, R18 & R19 FROM P.5 OF SCHEMATICS. REMOVED 1UF CAP BETWEEN PIN 1 AND GND OF LT1575 ON P.4 REPLACED C38 ON P.5 WITH A SHORT. THE SIGNALS MUXOUT AND YIN WERE THUS REMOVED AND RENAMED ADDED 1UF CAP TO VCC3 NEAR PIN 1 OF HEXFET ON P.4 AS ONE SIGNAL MUXOUT_YIN REPLACED 220UF CAP WITH 100UF CAP ON P.4 LAYOUT NOTE ADDED TO P.4 SIGNAL NAME BROMWE# REMOVED FROM P.14 GPIO7 SIGNAL NAME AND NET REMOVED FROM P.14 AND CONNECTED TO PIN Z5 OF THE 2X13 HDR ON P.7 1.4 REVISIONS ROMWE# SIGNAL NO LONGER USES 74LVT125 ON P.14 BUT CONNECTS DIRECTLY TO BIOS PIN 31 PULL-UP RESISTOR TO VCC3, R13, ADDED ON P.14 AND CONNECTED TO THE ROMWE# SIGNAL SIGNAL NAMES L RED, L GREEN, L BLUE CHANGED TO L_RED, L_GREEN AND L_BLUE, RESPECTIVELY, ON P.9 SIGNAL NAMES VGA SHYNC AND VGA VSYNC CHANGED TO VGA_HSYNC AND VGA_VSYNCE ON P.9 SIGNAL NAME TP_0709 REMOVED FROM 2X13 HDR ON P.7 AND CHANGED TO GPOI7 NET NAMES CONX_20, CONX_24 AND CONX_47 ADDED TO P.13 MOUNTING HOLES FOR FAN ADDED TO P.14 R63 ON P.6 CHANGED FROM 75 TO 100 OHMS FOR HIDDEN PINS OF FAN MOUNTING HJOLES ADDED TO P.1 R62 REMOVED AND REPLACED BY A SHORT ON P.6 AGND CHANGED TO GND GLOBALLY AVCC CHANGED TO VCC GLOBALLY SIGNAL NAME M_COMP2 REMOVED FROM P.6 ON HIDDEN PINS OF BT829ALV REMOVED FROM P.5 C112 REMOVED FROM P.6 PROPERTY OF BT829ALV ADDED, HIDDEN PINS DESIGNATED AS ANALOG_GND CONNECT TO GND POWER NOTES CHANGED ON P.1 TO REFLECT AGND AND AVCC REMOVAL BT829ALV NAME CHANGED TO BT829B ON P.1 AT 2 PLACES AND P.5 AT 2 PLACES BT868, 869 TV OUT NOTE ON P.2 CHANGED TO VIDEO ENCODER 1.41 AGP CONNECTOR NOTE ON P.2 CHANGED TO A.G.P. CONNECTOR THE 4 GND RINGS OF FAN MOUNTING HOLES BROUGHT OUT EXTERNALLY P.14 THE 4 NC MOUNTING HOLES ARE STILL LEFT AS HIDDEN 1.6 REVISIONS 1.42 ALL REFERENCE DESIGNATORS CHANGED 0 OHM RESISTOR ADDED TO GPIO4 LINE ON P.14 HIDDEN POWER PINS NOTATION ON P.1 CHANGED UNSTUFFED 0 OHM RESISTOR ADDED BETWEEN DRAIN AND SOURCE OF PMOSFET ON P.14 PINOUT CHANGED ON INTEL740(TM) GRAPHICS ACCELERATOR ON PINS SPARE2, SPARE1, LEFT, VSYNC, 1.61 REVISIONS 3 HSYNC, VREF, AND VCLK. 3 50 PIN VIDEO PINOUT CHANGED ON P.13, PIN 1 NEEDED TO CHANGE DUE TO PAD PATTERN DEFINITION NEW PIN'S ARE H25, H26, J23, J25, J26, L23, & L24 RESPECTIVELY ON P.3. DIAGRAM SHOWING THE PHYSICAL PINOUT OF THE 50 PIN VIDEO CHANGED ACCORDINGLY ON P.13 NO OTHER PINS AFFECTED. NOTE ON P.4 WHICH STATED ...R10 WITH THE ... CHANGED TO ...R35 WITH THE... 1.43 NOTE ON P.4 WHICH STATED ...R10 VOUT... CHANGED TO ...R35 VOUT... ADDED DISCLAIMERS TO P.1 NOTE ON P.4 WHICH STATED ...C12 TO C11... CHANGED TO ...C60 TO C61... ADDED NOTE REGARDING HIDDEN PINS OF VGA CONNECTOR ON P.1 C21, C22, C33, & C34 ON P.5 CHANGD TO 22PF CAPS, SAME PACKAGE SIZE AGP NOTE CHANGED TO A.G.P. ON P.8 L3 AND L6 ON P.5 CHANGED TO 2.7UH, SAME PACKAGE SIZE COMPATIBILITY NOTE REMOVED FROM TITLE ON P.10 C23 ON P.5 CHANGED TO 68PF, SAME PACKAGE SIZE 512X32 SGRAMS NOTE CHANGED TO JUST SGRAMS C35 ON P.5 CHANGED TO 100PF, SAME PACKAGE SIZE BUTEO TV ENCODER NOTE CHANED TO BT869 VIDEO ENCODER REF DESIGNATOR FOR C16 ON P.4 CHANGED TO C40 POWER PINS NOTE CHANGED TO HIDDEN POWER PINS ON P.1 REF DESIGNATOR FOR C40 ON P.5 CHANGED TO C16 BT829B NOTE CHANGED TO BT829ALV VIDEO DECODER ON P.1 & 5 ADDED NOTE ON P.4 REGARDING VARYING THE OUTPUT VOLTAGE OF REGULATOR SIGNAL NAME XTL1 CHANGED TO XT1I ONP.5, PIN16 OF BT829ALV 1.720K REVISIONSPULL-DOWN RESISTOR TO GND ADDED TO GPIO8 SIGNAL ON P.3 SIGNAL NAME XT10 CHANGED TO XT1O ON P.5, PIN17 OF BT829ALV PINS F01, AA01, F04 & AA04 REMOVED FROM HIDDEN PINS OF INTEL740(TM) GRAPHICS ACCELERATOR CONNECTED TO VCC3 ON P.1 1.44 PINS F01, AA01, F04 & AA04 ADDED TO INTEL740(TM) GRAPHICS ACCELERATOR SYMBOL AND CONNECTED TO SIGNAL VCC_PLL ON P.3 NOTE ON HIDDEN VCC PINS FOR BT829ALV CHANGED, PIN 28 TO 38 ON P.1 VCC2 NOTES ON P.1 CHANGED TO VCC_CORE TO REFLECT THE CORE POWER SUPPLY CHANGED ON P.4 POWER PLANE VDD CHANGED TO 3VAA_BT829 FOR 3 PROTECTION DIODES ON P.6 HIDDEN INTEL740(TM) GRAPHICS ACCELERATOR PINS WHICH WERE CONNECTED TO VCC2 CHANGED TO CONNECT TO VCC_CORE SIGNAL NAMES L_GATE, R_GATE, COMP1 M_COMP1 ADN FB1575 ADDED TO P.4 THE FOLLOWING ARE HIDDEN PINS WHICH WERE CONNECTED TO VCC2 CHANGED TO CONNECT TO VCC_CORE SIGNAL NAMES XT1CAP AND XT0CAP ADDED TO NETS ON P.5 E07, E09, E11, E13, E14, E16, E18, H22, AB07, AB09, AB11, AB13, AB14, AB16, AB18, AB20 SIGNAL NAMES XTALIN869, XTALOUT869, M_COMP2, COMP2, FSADJUST869, VBIAS869 AND VREF869 ADDED TO NETS ONP.6 OUTPUT OF REGULATOR SIGNAL NAME CHANGED TO VCC_REGULATED FROM VCC2 ON P.4 SIGNAL NAME VMI3V ADDED TO NET ON P.7 TWO 0 OHM RESISTORS ADDED, BOTH CONNECTED TO VCC_CORE, ONE CONNECTED TO VCC_REGULATED, 2 SIGNAL NAME FANPOWER ADDED TO NET ON P.14 2 THE OTHER VCC3 ON P.4 ANOTHER TWO 0 OHM RESISTORS ADDED, SMALLER PACKAGE, BOTH CONNECTED TO VCC_PLL 1.45 ONE CONNECTED TO VCC_REGULATED, THE OTEHR VCC3 ON P.4 SIGNAL NAME CCVALID ADDED TO P.5 ADDED ON P.4 TO DESCRIBE THE RESISTOR STUFFING OPTIONS FOR CORE AND PLL POWER CHANGED PMOSFET ON P.14 FROM A 3 PIN DEVICE TO A 4 PIN DEVICE, THE MIDDLE PIN (2) AND THE 1.46 TAB (4) ON TEH PHYSICAL DEVICE ARE ELECTRICALLY THE SAME, BOTH ARE DRAINS SIGNAL NAME GFX_OSC ADDED TO P.3 VCC2 POWER SYMBOL CONNECTED TO DECOUPLING CAPACITORS ON P.4 CHANGED TO VCC_CORE' SIGNAL NAME MODE869 ADDED TO P.6, PIN 50 OF BT869 VCC2 NO LONGER EXISTS SIGNAL NAME PAL_MODE ADDED TO 1X3HDR ON P.6 SIGNAL NAME NTSC_MODE ADDED TO 1X3HDR ON P.6 1.8 REVISIONS REFERENCE DESIGNATORS CHNAGED ACCORDING TO PHYSCIAL LOCATION ON BOARD BY LAYOUT COMPANY 1.46 1.9 REVISIONS NOTE STATING NEED A 10% VERSION CREATED REMOVED FROM P.8 NOTES ON REFERENCE DESIGNATORS ON PAGE 1 UPDATED POWER SUPLY VCC3 CHNAGED TO VCC ON C123 ON P.14 NOTE REGARDING 0 OHM STUFFING OPTIONS ON P.4 CHANGED POWER SUPPLY VCC3 CHANGED TO VCC ON BIOS SKT ON P.14 NOTE REGARDING DEFAULT POWER CONFIGURATION ADDED TO P.4 SIGNAL NAME 5VSDA CHANEGD TO 3VSDA ON U9.Z13 ON P.7 HIDDEN RULE ON AD<31:0> CHANGED TO HIDDEN AGP CONNECTOR NOTES ON PINS CHANGED ON P.8, NO SIGNAL NAMES WERE CHANGED ON THE CONNECTOR NAMES GAD[31:0] CHANGED TO AD[31:0], SMB1 AND SMB0 CHANGED TO RSVD 2.0 REVISIONS GAD_STB0 AND GAD_STB1 CHANGED TO AD_STB0 AND AD_STB1, RESPECTIVELY OSC Y3 VALUE CHANGED TO 66.6667MHz (p.4) GC-BE*3,2,1,0 CHANGED TO CBE*3,2,1,0 RESPECTIVELY GSTOP*, GPERR*, AND GPAR CHANGED TO STOP*, PERR*, SERR* AND PAR, RESPECTIVELY 2.1 REVISIONS Made Power Pins Visible and changed names to match the Datasheet,
1 Swapped pin numbers for WEA# and WEB# (p.3,4) 1
Made power pins visible (p.6) Changed VCC3 voltages on part to 3VAA_BT869, Changed R58 to 100 ohms (p.7) Pin A3 on AGP connector disconnected from Ground, changed VDD to VDDQ (p.9) Made power pins visible (p.11) Made power pins visible, Changed Clock Routing (p.12) Title Made power pins visible (p.13) Revision History Size Document Number Rev Added descriptive text to Fan control, made C Intel740(TM) Graphics Accelerator Reference Card 2.1 power pins visible (p.15) Date: Thursday, April 09, 1998 Sheet 16 of 16 A B C D E 3 Intel740™ Graphics Accelerator 3 Device AGP Motherboard Design
3 Device AGP MotherBoard Design
3 Device AGP MotherBoard Design 3
3.1 Introduction
This chapter provides design guidelines for developing a 3 device AGP motherboard based on the Pentium II® processor, Intel® 440BX AGPset, and the Intel740™ graphics accelerator. The main focus of this chapter is the guidelines for developing a 3-point AGP solution with the Intel740 graphics accelerator. The configuration for the 3-point AGP is to have an 82443BX (Target) with two AGP masters. • One AGP master is located on the motherboard (Intel740 Graphics Accelerator) along with the target, and • Another AGP master is located on an add-in card that connects to the motherboard through a standard AGP connector.
Only one AGP master is enabled at any one time. When the add-in card is installed in the system, the AGP master on the add-in card is the only one that may be enabled. The Intel740 graphics accelerator on the motherboard may be enabled only when the add-in card is removed from the system. The desire for a 3-point AGP solution is to allow an upgrade path from the master device on the motherboard to a master device on an add-in card.
This section contains references to sections already discussed in the reference card section of this design guide. Since the focus of this section is only the 3-point AGP implementation with the Intel740 graphics accelerator, many of the layout and routing guidelines for the motherbaord are referenced to the Intel® 440BX AGPset Design Guide. 3.1.1 Overview
The reference 3 device AGP motherboard design described in this document contains the following features. • Full support for a Pentium® II processor (DS1P), with system bus frequencies of 100/66 MHz • Intel 440BX AGPset — 82443BX Host Bridge Controller — 8237EB PCI ISA IDE Accelerator (PIIX4E) • 100/66 Mhz Memory Interface: A wide range of DRAM support including — 64-bit memory data interface plus 8 ECC bits and hardware scrubbing — SDRAM (Synchronous) DRAM Support only for desktop and server applications — 16Mbit, 64Mbit DRAM Technologies • 2 PCI Add-in Slots — PCI Specification Rev. 2.1 Compliant • 1 Shared PCI/ISA Add-in Slot • 1 AGP Slot — AGP Interface Specification Rev 1.0 Compliant — AGP 66/133 MHz, 3.3V device support
Intel740™ Graphics Accelerator Design Guide 3-1 3 Device AGP MotherBoard Design
• Intergrated IDE Controller with Ultra DMA/33 support — PIO mode 4 transfers — PCI IDE Bus Master Support • Intergrated Universal Serial Bus (USB) Controller with 2 USB ports • Intergrated System Power Management Support • On-board Floppy, Serial, Parallel Ports, • Intel 740 Graphics Accelerator — Accelerated Graphics Port (AGP) Interface — Memory 100 MHz SDRAM or SGRAM Support 2,4 MB Solder-Down Option
3.1.2 About This Chapter
This chapter is intended for hardware design engineers who are experienced in the design of PC motherboards or memory subsystem. This document is organized as follows: • Section 1, "Introduction"—This section provides an overview of the features of a 3-point AGP reference design (DS1P/440BX/I740). Chapter 1 also provides a general component overview of the Pentium II processor, Intel 440BX AGPset, and the Intel 740 graphics accelerator. This section also provides implementation issues associated with a 3-point AGP design and design recommendations which Intel feels will provide flexibility to cover a broader range of products within a market segment. • Section 3.2, "3 Device AGP Motherboard Layout and Routing Guidelines"—This section provides detailed layout, routing, and placement guidelines for the AGP bus and local memory subsystem. Design guidelines for other buses (Host GTL+, PCI, and DRAM) are covered in the Intel 440BX AGPset design guidelines. • Section 3.3, "3 Device AGP Motherboard Reference Design Schematics"—This chapter provides the schematics used in the reference design.
3.1.3 Block Diagram
Figure 3-1 shows a block diagram of a typical platform based on the Intel 440BX AGPset with the Intel740 graphics accelerator. The 82443BX system bus interface supports up to two Pentium II processors at the maximum bus frequency of 100 MHz. The physical interface design is based on the GTL+ specification and is compatible with the Intel 440BX AGPset solution. The 82443BX provides an optimized 72-bit DRAM interface (64-bit Data plus ECC). This interface supports 3.3V DRAM technologies.
3-2 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
Figure 3-1. Pentium® II Processor / Intel® 440BX AGPset/Intel 740 Graphics Accelerator System Block Diagram
Pentium® II Processor
Host Bus
AGP SLOT 72 Bit 82443BX w/ECO AGP Bus Host Bridge Main 66/100 Memory MHz Intel 740 SDRAM Support Grahics Accelerator
PCI Slots
Display Primary PCI Bus Graphics Local Memory (PCI Bus #0)
System Mgnt (SM) Bus
2 IDE Ports 82371EB (Ultra DMA/33) (PIIX4E) IO (PCI-to-ISA APIC Bridge) 2 USB USB Ports ISA Slots USB
ISA Bus
System BIOS sys_blk.vsd
3.1.4 Implementation Issues
The following are design issues involved in implementing a 3-load AGP bus. These issues must be studied and implemented carefully in order to produce a functional design.
3.1.4.1 Disabling A Master Device
There are two master devices that must each have the ability to be disabled in a logical point-to- point bus. These devices are the master graphics controller on the motherboard and the master graphics controller on the AGP add-in card. Several issues effect the ability to, and the way in which, a master graphics controller is disabled.
One issue concerns the add-in card and the other concerns the graphics controller components themselves. Since the current AGP specification has made no provision for a general method of disabling a master device, this function must be defined for on an individual basis depending on the operating characteristics of each master device. The graphics controller that is used as the down device on the motherboard must have a mechanism that disables the device in a manner acceptable to the implementation of a logical point-to-point bus. The Intel 740 has such a mechanism that
Intel740™ Graphics Accelerator Design Guide 3-3 3 Device AGP MotherBoard Design
allows it to be put in a low power state. In this low power state, the Intel740 chip is disabled and will not initiate or respond to cycles on the AGP bus. In addition, the power consumption of this device in this state is less than 1 Watt. To put the Intel740 chip into the low power mode, the following sequence of events must occur in the order stated. 1. ROMA16 must be asserted (high) at the trailing edge of the Intel740 chip RESET# 2. At least one AGP/Core clock before TEST is asserted the following signals must driven to the state listed in Table 3-1
Table 3-1. State of Signals to be Driven After System Reset but at Least One Clock Prior to Asserting TEST
Signal State
WEB# 0 SCASB# 1 SRASB# 0 CS0B# 0 CS1B# 0
3. TEST is asserted (asserted =high = 1)
3.1.4.2 Low Power Logic Implementation
Two signals, GPO27# and GPO 28#, from the PIIX4E are used in this design. GPO28 in conjunction with ROMA16 and PCIRST# are used to put the Intel740 chip in low power mode (see Figure 3-2). The additional logic for driving WEB#, SCASB#, SRASB#, CS0B#, CS1B# and TEST is illustrated in Figure 3-2.
A hardware reset to the Intel740 chip takes the device out of the low power state. Since the PCIRST# signal is used to disable the device, it can not be used for this purpose. GPO27 serves as the hardware reset to reset the Intel740 chip. At the trailing edge of GPO27, the Intel740 chip will be functional. Figure 3-2. The Schematic Diagram for GPO27#, PCIRST# (System Reset), RESET#, ROMA16 Signals
Vcc3
4.7 KΩ PIIX4E GPO27# RESET Intel740™ PCIRST# Vcc3 Chip 4.7 KΩ ROMA16 D Q OE#
PCICLK3 Q# IN1 OUT1
3-4 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
Figure 3-3. The Schematic Diagram for the WEB#, SCASB#, SRASB#, CS0B#, CS1B# and TEST
Vcc3 Vcc3 2.2 KΩ TEST OE# OUT1 WEB# D Q IN1 OUT2 IN2 OUT3 SCASB# Intel740™ SRASB# Chip SYSCLK CLR# IN3 OUT4 IN4 OUT5 CS0B# IN5 OUT6 CS1B# IN6 PIIX4E GPO28#
3.1.4.3 GPO27# and GPO28# Signal Duration
Table 3-2. Signal Duration of the GPO Signals from PIIX4
Minimum Signal Active Actual Duration1 Duration
GPO27 from PIIX4 Low (0) 1ms 1ms
GPO28 from PIIX4 Low (0) see note 2 1ms
NOTE: 1. 1ms is the smallest system BIOS increment of time 2. This is the propagation delay from when GPO28# is asserted to valid output at TEST.
Controls Signals From the PIIX4
GPO27 takes the device out of low power mode and puts it into functional mode. The duration of the GPO27 signal should be the minimum of 1ms (see Table 3-2). This requirement is set by the minimum reset time defined in the Accelerated Graphics Port Interface Specification, Revision 1.0.
GPO28 puts the device into low power mode and should be a minimum duration of the sum of the propagation delay for logic depicted in Figure 3-2.
Intel740™ Graphics Accelerator Design Guide 3-5 3 Device AGP MotherBoard Design
3.1.5 State Diagrams
Figure 3-4. Intel740™ Graphics Controller (On Board Device) Remains in Low Power Mode
System Reset
Low Power Mode
At system RESET, the Intel740™ graphics controller on the motherboard is always put into the low power state. The following are examples in which the on board device shall remain in low power state: • AGP add-in card is present • PCI or ISA graphics device is the primary and only graphics device desired • Multimonitor configurations not utilizing the on board graphics device.
Note: When not in use, both GPO27 and GPO28 should be driven high (1). Figure 3-5. Intel740™ Graphics Controller (On Board Device) State Diagram
System Reset
Low Power Mode
Functional Mode
The Intel740 graphics controller down on the motherboard enters the low power mode at system reset. If an enabling event occurs, the device enters the functional mode from the low power mode (See Figure 3-5).
The following are examples in which functional mode would be invoked: • Intel740™ graphics accelerator as the primary and only graphics device • Multimonitor configurations utilizing the Intel740™ graphics controller
3-6 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
3.1.5.1 Signal Quality and Timing Issues
There are two modes of operation for the AGP bus, each with it's own signal quality and timing issues. These two operating modes are 1X mode and 2X mode. Because 1X mode is a common clock mode, flight time of the signal is of the most importance. Both minimum and maximum flight time must be verified. The quality of the signal will also effect the flight time and therefore must also be taken into consideration.
In AGP 2X mode operation the two major areas of concern for signaling are timing skew between the data group signals and their associated strobe signals, and the signal quality of these signals. The skew in a AGP 2X mode bus is comprised of elements that include crosstalk, settling time, component loading differences, and line length differences. Bus topology effects all the above mentioned factors of signal skew except component loading differences.
Signal quality issues may also arise from the nature of the 3-load bus topology. These signal quality issues are caused by the loading and reflections inherent in this topology. Signal quality problems can effect timing and skew by violating edge quality, ringback, and overshoot criteria.
The topology of the logical point-to-point bus only makes these signal quality and timing issues worse since this type of bus contains signal loading from the third device located somewhere in the middle of the bus and the addition of trace stubs in the bus. The loading and trace stubs create a complex allowable routing topology with regard to trace length and component placement. Careful simulation of the bus topology is mandatory to verify proper operation of the AGP system. Both the case where an add-in card is present in the system and the case where the add-in card is not in the system must be evaluated for a complete solution. Depending on how the system is designed the bus will become balanced or unbalanced depending on the add-in card being in or out of the system. Specific design issues faced in implementing a logical point-to-point bus will be discussed in detail in the following sections of this document.
3.1.5.2 Strobe Edge Quality Issues
Due to the high speed nature of 2X mode AGP transfers, an AGP bus design must take into account all aspects of edge and signal quality. Areas of signal quality concern are edge quality, ringback, overshoot, and settling time.
Since the strobe signals act like clocks in 2X mode, their edge signal quality is paramount. Any nonmonotonic signal edges or ledges (steps) occurring in the switching region may cause double clocking or erratic behavior in the input buffer. Nonmonotonic edges and steps in the signal edge while not in the switching region will add to the flight time on the strobe signal and may increase the strobe to data group skew. This added skew may cause the system to fail. The switching region for 2X mode ranges from Vil (0.3Vddq) to Vih (0.5Vddq) centered around a switch point of 0.4Vddq.
Rising and falling edge ringback may also cause double clocking on strobe signals if these ringback levels are large enough. Ringback is analogous to Noise margins. When a noise margin is negative the signal requirements are not met and double clocking could occur. The violation criteria for strobe signal ringback is the same as the above edge quality region. Rising edge ringback may not go below Vih (0.5Vddq), and falling edge ringback may not exceed Vil (0.3Vddq).
See the section on Sensitivity Analysis later in this document for a full explanation of signals quality measurements.
Intel740™ Graphics Accelerator Design Guide 3-7 3 Device AGP MotherBoard Design
3.1.5.3 Clock Issues
Supplying a clock to both AGP master devices raises issues that must be considered when implementing a logical point-to-point bus. Among these issues are clock signal quality, routing, and clock skew. Signal quality and routing are of a major concern since the clock now must be routed to both master components.
A separate clock driver was used to drive the AGP clocks on this design. The topology for each clock is point-to-point and no segment tuning between master devices is required. However, each clock length must still be tuned to the target clock for clock skew reasons. Since separate clock drivers are used, the skew between clock driver outputs must be taken into account in the overall clock skew budget. The output to output skew for the clock chip was 0.25 ns.
Skew between each AGP master clock input and the AGP target (chipset) must be within the 1ns limit called out in the AGP specification, Since we had a driver skew of 0.25ns due to the clock drivers, this meant that our propagation delays and settling times skews could not exceed 0.75 ns. This means that for a single clock driver solution not only must each of the two clock trace segments be balanced in such a way that signal quality is acceptable, but the trace segments must be tuned in such a way as to meet the AGP specified skew requirements.
The clock topologies used are shown in Figure 3-6. This figure shows the clock topology if three clock outputs are available. Each clock is a direct connection to it's respective load. Here the trace segments A and B must be balanced with respect to the target device clock trace in such a way as to meet system clock skew requirements. As mentioned previously, the clock generator output to output skew must also be factored into the overall system clock skew budget. In this topology the AGP target device is assumed to have a separate clock driver and is not shown here. Figure 3-6. Point-to-Point Topology
3-8 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
3.1.6 Design Recommendations
3.1.6.1 Voltage Definitions
For the purposes of this document the following nominal voltage definitions are used:
Vcc 5.0V Vcc3.3 3.3V VccCORE Voltage is dependent on the five bit VID setting Vcc2.5 2.5V VTT 1.5V VREF 1.0V AGPVREF 3.3V +2_7 2.7V VDDQ3 3.3V
3.1.6.2 General Design Recommendation
For general design recommendations, refer to the Intel 440BX AGPset Design Guide sections 1.4.2 and 1.4.3.
3.2 3 Device AGP Motherboard Layout and Routing Guidelines
This section describes layout and routing recommendations to insure a robust design. Follow these guidelines as closely as possible. Any deviations from the guidelines listed should be simulated to insure adequate margin is still maintained in the design. Since the concentration of this section is mainly 3 Device AGP implementation, refer to the Intel 440BX AGPset Design Guide for the remaining design guidelines. It would be beneficial to have that design guide before tying to read this section. Sections that are referred to the Intel 440BX AGPset Design Guide are: • Routing Guidelines — GTL+ Description — GTL+ Layout Recommendations — Single Processor Design — Additional Guidelines — Design Methodology — Performance Requirements — Topology Definition — Pre-Layout Simulation (Sensitivity Analysis) — Placement & Layout • Placement & Layout • Post-Layout Simulation • Validation — Flight Time Measurement — Signal Quality Measurement
Intel740™ Graphics Accelerator Design Guide 3-9 3 Device AGP MotherBoard Design
• Timing Analysis • 82443BX Memory Subsystem Layout and Routing Guidelines — 100/66 MHz 82443BX Memory Array Considerations — 3 DIMM Memory Layout & Routing Considerations — PCI BUS Routing Guidelines — Decoupling Guidelines for an Intel 440BX AGPset Platform — Intel 440BX AGPset Clock Layout Recommendations • Design Checklist • Debug Recommendations
3.2.1 BGA Quadrant Assignment
The ball connections on the Intel740™ graphics accelerator have been assigned to simplify routing and keep board fabrication costs down by enabling a 4-layer design. Figure 3-7 shows the four signal quadrants of the Intel740 graphics accelerator. Component placement should be done with this general flow in mind. This will simplify routing and minimize the number of signals which must cross. The individual signals within the respective groups have also been optimized to be routed using only 2 PCB layers.
A complete list of signals and ball assignments can be found in the Intel740™ Graphics Accelerator Datasheet. Figure 3-7. Major Signal Sections
BIOS/Flicker VMI Port Quadrant Quadrant Pin #1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Intel740 A B Top View C D E F G H J K L M A.G.P. N Quadrant P R T U V W Y AA AB AC AD AE AF Local Memory Quadrant
3-10 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
Figure 3-8 shows the proposed component placement for a single Pentium II processor for the ATX form factor design.
ATX Form Factor 1. The ATX placement and layout below is recommended for single (UP) Pentium II Processor / Intel 440BX AGPset/ Intel740 Graphics Accelerator system design. 2. The example placement below shows 1 Slot 1 connector, 2 PCI slots, 1 Shared slot, 3 DIMM sockets, and one AGP connector. 3. For an ATX form factor design, the AGP compliant graphics device can be either on the motherboard (device down option), or on an AGP connector (up option). 4. The trace length limitation between critical connections will be addressed later in this document. 5. Figure 3-8 is for reference only and the trade-off between the number of PCI and ISA slots, number of DIMM sockets, and other motherboard peripherals need to be evaluated for each design Figure 3-8. Example ATX Placement for a UP Pentium® II Processor / Intel® 440BX AGPset / Intel 740 Graphics Accelerator Design
I/O Ports
PCI0 AGP/PCI1 Pentium® II Slot 1
Intel740 chip
Host Interface PCI Interface 82443BX AGP Interface CKBF
SDRAM Interface CK100
SDRAM DIMMs PIIX4E
IDE 0/1
v002
Intel740™ Graphics Accelerator Design Guide 3-11 3 Device AGP MotherBoard Design
3.2.2 Board Description
For a single Pentium II / Intel 440BX AGPset /Intel 740 Graphics Accelerator motherboard design, a 4 layer stack-up arrangement is recommended. The stack up of the board is shown in Figure 3-9. The impedance of all the signal layers are to be 65 Ω ±15%. Lower trace impedance reduces signal edge rates, overshoot & undershoot, and have less cross-talk than a higher trace impedance. A higher trace impedance increases edge rates and may slightly decrease signal flight times. Figure 3-9. Four Layer Board Stack-up
Z = 60 ohms Primary Signal Layer (1/2 oz. cu.) 5 mils PREPREG Ground Plane (1 oz. cu.) 47 mils CORE Power Plane (1 oz. cu) 5 mils PREPREG Z = 60 ohms Secondary Signal Layer (1/2 oz. cu)
Total board thickness = 62.6
Note that the top and bottom routing layers specify 1/2 oz. cu. However, by the time the board is plated, the traces will end up about 1 oz. cu. Check with your fabrication vendor on the exact trace impedance and PCB signal velocity value and insure that any signal simulation accounts for this.
Note: A thicker core may help reduce board warpage issues.
Additional guidelines on board buildup, placement and layout include: • For a 4-layer single processor design, double ended termination is recommended for GTL+ signals. One termination resistor is present on the Pentium II processor, and the other termination resistor is needed on the motherboard. It may be possible to use single-ended termination, if the trace lengths can be tightly controlled to a 1.5” minimum and 4.0” maximum. • The termination resistors on the GTL+ bus should be 56 ohms ±5%. • The board impedance (Z) should be 65 ohms ± 15%. • FR-4 material should be used for the board fabrication. • The ground plane should not be split on the ground plane layer. If a signal must be routed for a short distance on a power plane, then it should be routed on a VCC plane, not the ground plane. • Keep vias for decoupling capacitors as close to the capacitor pads as possible.
3.2.3 3-point AGP Design Guidelines
3.2.3.1 Layout and Routing
With signal quality, timing, and clock issues in mind, a suitable bus layout and routing must be found. Careful simulation as described in the Sensitivity Analysis section of this document is essential. The nature of the logical point-to-point bus makes it a much harder topology to implement than a physical point-to-point bus. The following discussion will focus on some layout and routing issues associated with a logical point-to-point bus. The layout and routing for a logical point-to-point bus is determined either from simulation results or are verified from simulation
3-12 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
results. The benefit to the former method is that a solution space can be determined before any placement and routing is attempted. This saves time and effort over the method of route, simulate, adjust.
It is, therefore, recommended that the simulation results for the 3-load bus drive the layout and routing. The simulation results will produce a solution space for a particular set of buffer and board conditions. This solution space will give the lengths and conditions for all segments of the 3-load bus. It may be found that the given lengths and/or conditions governing the segments may not be able to be routed for the placement needed on a given board. If this is the case, several options may be pursued. The first is possible modifications to board placement of components. Placement may be adjusted so that the solution space is now able to be routed.
If placement changes are not achievable, tradeoffs in the solution space may be tried. As will be seen later in the Sensitivity Analysis section, changes in length requirements to a particular segment of the topology will result in changes to other segments allowable length and constraints. For example, the maximum allowed length of one segment may be to short to route but the maximum allowed length of another segment may not be needed. By shortening one segment’s maximum allowable length, additional length may be gained in another segment to enable routing of the bus. In another case the solution space found may allow a particular routing mismatch between data and strobe lines on the motherboard. By routing with no mismatch between data and strobe lines on the motherboard, length may be gained in one or more segments.
Another option to change the solution space can be to change the board parameters. These parameters include trace width and space, impedance and variation, and/or dielectric thickness. All of these parameters may have an effect on the solution space which could allow the bus to be routed. Note that is has been shown that moving to a wider trace and space ratio has increased the segment length for the 3-load bus. The length gained to enable routing the bus comes at the cost of increased routing area required by the increased trace and space ratios.
Flight time and skew constraints as well as electrical characteristics set forth in the AGP specification must be followed when designing a logical point-to-point bus. The trace lengths, and allowable trace routing skew lengths may be different than in the case of a physical point-to-point bus, but the actual time allotted for flight time and signal skew must be the same in both cases.
It should be noted that not all implementations of a logical point-to-point bus will yield the same routing solution space. Issues that effect the trace length and routing mismatch allowed in a particular implementation include board impedance range, impedance variations due to crosstalk, and buffer characteristics for both the target (chipset) and master graphics controller down on the motherboard. Variations in all of these areas will yield different simulation results and thus different routing solution spaces. Because of this potential difference in each individual solution, each implementation of a point-to-point bus should be carefully simulated.
3.2.3.2 Data and strobe definitions
Throughout this document, the term “data” refers to AD[31:0], C/BE[3:0]# and SAB[7:0]. The term “strobe” refers to AD_STB[1:0] and SB_STB. When the term data is used it is referring to one of three groups of data as seen in Table 3-3. When the term strobe is used it is referring to one of the three strobes as it relates to the data in its associated group.
Table 3-3. Data and Associated Strobe
Data Associated Strobe
AD[15:0] and C/BE[1:0]# AD_STB0 AD[31:16] and C/BE[3:2]# AD_STB1 SBA[7:0] SB_STB
Intel740™ Graphics Accelerator Design Guide 3-13 3 Device AGP MotherBoard Design
3.2.3.3 Assumptions for Board Design Guidelines
These guidelines are primarily for Accelerated Graphics Port (AGP) designs that use an Intel740 graphics controllers on a 82443BX motherboard and an AGP-compliant add-in card. They assume certain requirements in order to produce an AGP compliant placement and routing solution. These assumptions were used for the initial pre-route analysis of the design.
3.2.3.4 Add-in Card guideline assumptions:
Table 3-4. Data Signal and Strobe Guideline Assumptions
Width:Space Zo Trace Line Length Line Length Matching
1:2 50Ω to 85Ω Data / Strobe 0.0in < line length < 3.0 in Strobe ±0.5 in of group
All of the data line lengths within a group of signals needed to be within ±0.5 inches of their associated strobe. The board impedance needed to be in the range of 50Ω to 85Ω. This range is used to cover design targets and manufacturing tolerances.
Because crosstalk is a large component of skew, it was necessary to specify board routing. All traces needed to be routed with a separation of two times the trace width (6:12). Additionally, all lines within a group needed to be of the same type (microstrip or stripline). This is because microstrip (surface traces) and striplines (buried traces) have different propagation velocities, and mixing these can increase the flight time skew beyond acceptable limits. All the traces on the plugin card provided to us were routed as microstrip.
Table 3-5. Control and Clock Signal Guideline Assumptions
Trace Width:Space Line length
Control signals 1:2 0 < line length < 3.0 Clock 1:4 0.6ns ± 0.1ns *
* The clock trace on the add-in card shall be routed to achieve an interconnect delay of 0.6ns ± 0.1ns as determined from trace length and trace velocity.
3.2.3.5 Motherboard Guideline Assumptions
Data Signal and Strobe Requirements
Table 3-6. Data signal and strobe requirements
Width:Space Zo Trace Line Length Line Length Matching
1:2 50Ω to 80Ω Data / Strobe follow topologies strobe longest signal of group
The motherboard needed to have an impedance range of 50Ω to 80Ω (as recommended by the 82443BX design guide). This range was used to cover design targets and manufacturing tolerances. The maximum line lengths are dependent on the type of trace and the amount of coupling.
The maximum line length was dependent on the routing rules used on the motherboard. These routing rules were created to give freedom for designs by making tradeoffs between signal coupling (trace spacing) and line lengths. These routing rules assumed trace spacings of 1:2 (5:10 mils). Trace spacing refers to the distance between the traces as being the twice the width of the trace.
3-14 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
Longer lines have more crosstalk, therefore longer line lengths require a greater amount of spacing between traces to maintain skew timings
We assumed a 4 layer boardstackup as described earlier.
Control Signal and Clock Requirements
Table 3-7. Control Signal Line Length Requirements
Trace Board Width:Space Line length
Follow lengths and topology for the data and Control signals Motherboard 1:2 strobe signals. Clock Motherboard 1:4 Length determined by clock skew matching.
Some of the control signals require pull-up resistors to be installed on the motherboard. The stub to these pull-up resistors needs to be controlled. Stubs to pull-up resistors need to be kept as short as possible to avoid signal quality issues.
The clock lines on both the motherboard and the add-in card can couple with other traces. It is recommended that the clock spacing (air gap) be at least two times the trace width to any other traces. It is also strongly recommended that the clock spacing be at least four times the trace width to any strobes. The motherboard needs to be designed to the type of clock driver that is being used and motherboard trace topology.
Clock Line Matching
Skew between each AGP master clock input and the AGP target (chipset) must be within the 1ns limit called out in the AGP specification. The driver use on this design can have up to 0.25ns of skew from output to output. This means that propagation delays and settling time skews cannot exceed 0.75 ns. Thus, for a single clock driver solution not only must each of the two clock trace segments be balanced in such a way that signal quality is acceptable, but the trace segments must be tuned in such a way as to meet the AGP specified skew requirements.
The clock topology used are shown in Figure 3-10.
Figure 3-10 shows the clock topology if three clock outputs are available. Each clock is a direct connection to it's respective load. Here the trace segments A and B must be balanced with respect to the target device clock trace in such a way as to meet system clock skew requirements. Figure 3-10. Point-to-Point Topology
Intel740™ Graphics Accelerator Design Guide 3-15 3 Device AGP MotherBoard Design
3.2.3.6 3-Load AGP Topology
Figure 3-11 and Figure 3-12 show the topologies for a 3-load AGP bus. The motherboard is divided into 2 trace segments as shown. These are referred to as segment A and B. The motherboard contains one AGP connector and one AGP master device. In the case of the strobe signals, a 3rd segment was added to represent the stub lengths of the pull up resistors. This segment is referred to as segment D. The net scheduling for this topology is segment A to connector, connector to segment B. Figure 3-11. 3 Device Data Load Topology
Motherboard Add - In Card
AGP 82443BX Segment A Connector Segment C Master
Intel740™ Segment B Chip
Figure 3-12. 3 Device Strobe Load Topology
Motherboard Add - In Card Segment D
AGP 82443BX Segment A Connector Segment C Master
Intel740™ Segment B Chip
3.2.3.7 Overall Solution Space
Two solution spaces were found. Selecting the appropriate solutions is dependent on the 82443BX placement relative to the AGP connector. Solution 1 was implemented on this design.
Table 3-8. Strobe and Data Segment Solution Space
Solution segment A Segment B Segment D
solution 1 3.5” - 5.5” * 2.0” - 3.0” 0.4” - 0.9”
Solution 1. Note that A + B within a group must be matched by 0.5”. Example:
3-16 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
Assume: GAD1 segment A=4.1" segment B=2.7" (A+B=6.8") and GAD2 segment A=3.5" and segment B=3.0" (A+B=6.5"). Notice that GAD1 A and GAD2 have more than 0.5" difference, but A+B is only 0.3" difference. Also, the strobes should be the longest signal in the group. Figure 3-13. 3 Device Data Load Topology (Solution 1 is Shown)
Motherboard0.4" - 0.9" Add - In Card Segment D Segment
AGP 82443BX Segment A Connector Segment C Master 3.5" - 5.5" 0" - 3.0"
Intel740™ Segment B Chip 2.0" - 3.0"
Figure 3-14. 3 Device Strobe Load Topology (Solution 1 is shown)
Motherboard0.4" - 0.9" Add - In Card Segment D Segment
AGP 82443BX Segment A Connector Segment C Master 3.5" - 5.5" 0" - 3.0"
Intel740™ Segment B Chip 2.0" - 3.0"
Clock Solutions Figure 3-15. Clock Topology and Matching
Load 2
Rs 0.3" - 0.4" Gclks Connector 4.4" - 4.6" Rs Clock Gen 0.4" - 0.5" Gclk740 6.4" - 6.6" Rs 0.4" - 0.5" Gclkin Load 1 Load 3 6.2" - 6.4"
Intel740™ Graphics Accelerator Design Guide 3-17 3 Device AGP MotherBoard Design
Table 3-9. Clock Segment Solution Space
Clock Net Driver to resistor lengths Resistor to Load lengths
Gclkin 0.4-0.5 Inches 6.2-6.4 Inches Gclks 0.3-0.4 Inches 4.4-4.6 Inches Gclk740 0.4-0.5 Inches 6.4-6.6 Inches
The clock lines were tuned as detailed in table Table 3-9 to ensure that no clock skew exceeding 0.75 ns occurred. Note that in the case of gclks, the load is the AGP connector.
3.2.4 Intel740™ Graphics Accelerator Memory Layout and Routing Guidelines
The Intel740 graphics accelerator integrates a memory controller that supports a 64-bit memory data interface. SGRAM can be used in addition to SDRAM, if it is configured to perform as an SDRAM. The Intel740 graphics accelerator generates the Row Address Strobe (SRAS[A:B]#), Chip Selects (CS0[A:B]#, CS1[A:B]#), Column Address Strobe (SCAS[A:B]#), Byte Enables (DQM[0:7]#), Write Enables (WE[A:B]#), and Memory Addresses (MA). The memory controller interface is fully configurable through a set of control registers.
Eleven memory address signals (MAx[10:0]) allow the Intel740™ graphics accelerator to support a variety of commercially available components. Two SRAS# lines permit two 64-bit wide rows of SDRAM. All write operations must be one Quadword (QWord). The Intel740 graphics accelerator supports memory up to 100 MHz.
Rules for populating a Intel740 graphics accelerator Memory: • SDRAM and SGRAM components can be mixed. • The DRAM Timing register, which provides the DRAM speed grade control for the entire memory array, must be programmed to use the timings of the slowest memories installed.
Possible DRAM and system options supported by the Intel740 graphics accelerator are shown in Table 3-10.
Table 3-10. Supported Memory Options (Other Memory Options Are Not Supported)
SDRAM/ SDRAM/ SDRAM/ Local Memory SGRAM SGRAM SGRAM Addressing Address Size Size Technology Density Width
Row Column Min Max
8 Mbit 256K 32 Asymmetric 10 8 2MB 4MB 16Mbit 512K 32 Asymmetric 11 8 4MB 8MB 16Mbit 1M 16 Asymmetric 12 8 8MB 8MB
There are several groups of signals within the memory bus with layout restrictions.
3-18 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
Table 3-11. Memory Layout Restrictions (See Figure 3-16 and Figure 3-17)
Signal Intel740™ to SGRAM Stub SGRAM Stub
Min Max Min Max
MA[11:0] .25’’ 4.9” 0.25" 0.6” MD[63:0], DQM[7:0] .25’’ 3.9” 0.25" 0.4”
Figure 3-16. Layout Dimensions (MA[11:0])
SGRAM
0.25" - 0.6" Intel740™ Chip 0.25" - 4.9" 0.25" - 0.6"
SGRAM
Figure 3-17. Layout Dimensions (MD[63:0], DQM[7:0])
Intel740™ 0.25" - 0.4" Chip 0.25" - 3.9" SGRAM
0.25" - 0.6" SGRAM
Table 3-12. Memory Layout Restrictions (See Table 3-16 and Table 3-17)
Signal Intel740™ to SGRAM Stub SGRAM Stub
Min Max Min Max
WEA#, SRASA#, SCASA#, CSA0# 2.25’’ 4.9” 0.25’’ 0.6’’
Intel740™ Graphics Accelerator Design Guide 3-19 3 Device AGP MotherBoard Design
Figure 3-18. Layout Dimensions (WEA#, SRASA#, SCASA#, CSA0#)
SGRAM
0.25" - 0.6" Intel740™ Chip 2.25" - 4.9" 0.25" - 0.6"
SGRAM
Table 3-13. Memory Layout Restrictions (See Figure 3-19)
Signal Intel740™ to Resistor Resistor to SGRAM Stub SGRAM Stub
Min Max
TCLK1 0.6” 3.4” ±0.25” 0.4” 0.6”
Figure 3-19. Memory Layout Dimensions (TCLK1)
SGRAM
0.4" - 0.6" Intel740™ 0.6" 0 3.4" ± 0.025" Chip 0.4" - 0.6"
SGRAM
Table 3-14. Memory Layout Restrictions (See Figure 3-19)
Signal Intel740™ to Resistor
OCLK to Resistor 1.0” ±0.25 RCLK0, RCLK1 3.0” ±0.25”
Note: It is important to match clock lengths. For example, if the length from OCLK to Resistor is 1.03, then the length from Resistor to RCLK should be 3.03 (OCLOCK to Resistor + 2’’).
3-20 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
Figure 3-20. Memory Layout Dimensions (RCLK and OCLK to RCLK)
Intel740™ Chip 1.0 ±0.25" OCLK 33 33 3.0 ±0.25" RCLK0
3.0 ±0.25" RCLK1
3.2.4.1 3 Device AGP Intel740™ Graphics Accelerator Memory Configurations
In the following discussion the term row refers to a set of memory devices that are simultaneously selected by an SRAS and the CS# signal.
Configuration #1: In this configuration, the minimum amount of memory (2MB) is supported. Note that, the same copy of all control signals goes to each component. Figure 3-21. 2/4 MB Local Memory Connection (64-bit data path)
Intel740™Intel740 Chip MD[63:0] MA[11:0]
CSx[A:B]# DQM[3:0] DQM[7:4] RCLKx OCLK
WEA# CS0A# SRASA# 256K/512K X 32 SCASA# MD[31:0] TCLKA
WEA# CS0A# SRASA# 256K/512K X 32 SCASA# MD[63:32] TCLKA
Intel740™ Graphics Accelerator Design Guide 3-21 3 Device AGP MotherBoard Design
3.3 3 Device AGP Motherboard Reference Design Schematics
This section provides schematics for the 3-point AGP reference design. The description of each schematic page is named by the logic block shown on that page.
Cover Sheet P-1
The Cover Sheet shows the Schematic page titles, page numbers and disclaimers.
Block Diagram P-2
This page shows a block diagram overview of the Pentium® II / Intel® 440BX AGPset/ Intel® 740 system design. Also included are page numbers for every major component in the design.
Pentium® II Slot 1 processor connector (part 1) P-3
This page shows the first part of the DS1P connector (up to the key). SLP# connection comes directly from the PIIX4E. Intel recommends placing 0 ohm resistors on the EMI signals. A thermal sensor (the MAX 1617 ME) which connects to an internal processor diode has been included to monitor processor temperature.
Pentium® II Slot 1 processor connector (part 2) P-4
This page shows the remaining part DS1P connector. Also shown are the optional connections for overriding the VID pins from the processor.
Clock Synthesizer and ITP connector P-5
This page shows the new clock synthesizer component the CK100 plus recommended decoupling. The clock synthesizer components must meet all of the system bus, PCI and other system clock requirements. Several vendors offer components that can be used in this design.
This page also shows the In Target Probe (ITP) Connector. The ITP connector is recommended in order to use the In Target Probe tool available from Intel and other tool vendors for Pentium II processor based platform debug.
Note: Some logic analyzer vendors also support the use of the ITP connector. This connector is optional. It is recommended to design these headers into the system for initial system debug and development, and leave the connector footprints unpopulated for production.
82443BX Component (System bus and DRAM Interfaces)P-6
This page shows the 82443BX component, System bus and DRAM Interfaces. The 82443BX connects to the lower 32 bits of the CPU address bus and the CPU control signals, and generates DRAM control signals for the memory interface. In this design, the 82443BX is configured to interface to a memory array of 3 DIMMs.
The CKBF is also shown on this page. The 82443BX delivers a single SDRAM clock to the CKBF which is a 18 output buffer, with an I2C interface which may be used to disable unused clock outputs for EMI reduction. It outputs 4 clocks to each DIMM socket, and 1 back to the 82443BX for data timings.
3-22 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
82443BX Component (PCI and AGP Interfaces) P-7
This page shows the 82443BX component, PCI and AGP Interfaces. The definition of pin AF3 has been changed from SUSCLK to BX-PWROK. Like PIIX4E PWROK, it is connected to the PWROK logic from the Power Connector page (P-26). Note the GCLKIN and GCLKOUT trace length requirements on the AGP interface.
82443BX Component (Memory and System Data Bus Interfaces) P-8
This page shows the 82443BX component, Memory and System Data Bus Interfaces. GTL_REF signal are also shown on this page. Ideally, the GTL_REF signals should be decoupled separately, and as close as possible to the 82443BX component, but this is not a requirement.
DIMM Connectors 0, 1, 2 P- 9-11
These three pages show the DRAM interface connections from the 82443BX to the DRAM array.
The serial presence detect pins are addressed as 1010-000,001,010 respectively. The 82443BX strap pull-up/pull-downs will be located on selected MAB# lines. REGE (pin 147) on each DIMM socket should be pulled high to enable registered DIMMs,
PIIX4E Component P-12
This page shows the PIIX4E component. The PIIX4E component connects to the PCI bus, dual IDE connectors, and the ISA bus. This reference design supports a subset of the power management features of the PIIX4E.
PIIX4E Component P-13
This page shows the PIIX4E component Interrupts, USB, DMA, power management, X-Bus, and GPIO interfaces. Also shown is the CLOCKRUN# pull-down and the external logic needed to handle a power loss condition.
Ultra I/O Component P-14
This page shows the Ultra I/O component. The RTC may optionally be used. An Infra Red Header Port is also optional.
AGP Connector P-15
This page shows the AGP connector. In this design, AGP INTA and INTB are connected to the PCI INTA and INTB through a buffer/driver. The interrupt signals are open-collector, and pulled up to VCC3.3. PCI Connectors P-16/17
These pages show the PCI connectors. In this design, three PCI connectors are used. AD[26, 27, 29, 31] are the preferred lines for the PCI slot IDSELs.
ISA Connectors P-18
This page shows the ISA connectors.
PCI IDE Connectors P-19
This page shows the IDE Connectors. No special logic is required to support Ultra DMA/33 hard drives.
Intel740™ Graphics Accelerator Design Guide 3-23 3 Device AGP MotherBoard Design
USB Headers P-20
This page shows the USB Headers. Note, the voltage divider on the open circuit signals provides logic level transitions for the PIIX4E. Note the placement requirements for the capacitors and series resistors at the bottom left.
Flash BIOS Component P-21
This page shows the 28F002BC-T Flash BIOS component which provides 128K bytes of BIOS memory. A jumper is used to provide the option for allowing the BIOS to be programmed in the system for BIOS upgrades and/or for programming plug and play information into the Flash device.
Note that a 2Meg Flash device may be required for certain applications (motherboard devices such as graphics, SCSI or LAN). An optional 34 pin header has been added to allow for BIOS emulation.
Parallel Port/ Serial and Floppy/ Keyboard & Mouse P-23-25
Nothing new here.
VRM P-25
The top of this page shows the voltage regulator modules (VRM 8.2) connector(s). The VRM 8.2 module provides 5V to VCCcore voltage conversion for the Pentium II processor. The bottom of this page shows two voltage regulators, one for generating the 1.5V GTL+ terminating voltage (VTT), the other is a 2.5V regulator. The VTT generation circuit must be able to provide about 5.0 amps of current under worst case conditions.
Note that the 5.0 amps of current will normally be supplied from two linear regulator devices (about 2.5 amps each), one located at each end of the GTL+ bus traces. However, one linear regulator device (such as the LT1585A-1.5 supplying the entire 5.0 amps) can be used if both ends of the GTL+ bus traces are near each other. For dual processors, two LT1587-1.5s (@ 3A) are recommended.
Power Connectors Front Panel Jumpers P-26
This page shows the system ATX power connector, hardware reset logic, and standard chassis connectors for the hard disk, power LEDs, and speaker output. New to this page are the dual-color LED circuit required to indicate the system state (either ON, OFF, or any of the suspend states), the 6-pin optional ATX connector, and the Wake-On-LAN header.
Note: A CPU Fan Header is required for the Intel Boxed Pentium II processor. The dual-color LED circuit is also used to reduce the voltage going to the power supply fan, thus decreasing its speed and quieting the system.
GTL+ Bus Termination Resistors P-27
This page shows the GTL+ bus termination resistors. The components shown are flat chip resistor array devices. These components are available in both four and eight resistors per package options. These packages have been chosen for their small size to reduce board space required. Discrete, SIP or SOJ resistor packages can also be used but will require more board area. Resistor packs with a corner power pin are not recommended. A decoupling cap per resistor pack is also recommended. Each GTL+ signal that connects between the 82443BX and the Slot 1 must be dual terminated to insure proper GTL+ signaling. Each GTL+ signal should be routed using a daisy chain methodology as described in the GTL+ layout guidelines section of this document. The termination resistors for each net must be located at the ends of the nets. Connect the VTT side of the resistor
3-24 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
packs to as short of a trace as possible before routing to the VTT plane. If the VTT plane is on an inner layer, keep the trace distance to the via as short as possible by placing the via between pins 6 and 7 for each resistor package. Where this is not possible, use multiple vias to the VTT plane for each group of 4 signals. Refer to the GTL+ Specification for more complete details on GTL+ signaling.
Pull-up and Pull-down Resistors P-28/29
These pages show pull-up and pull-down resistors for PCI signals, PIIX4E, Slot 1(CMOS), ISA, and AGP signals. Also shown are spare gates.
Decoupling Capacitors P-30/31
Decoupling Caps P-32
These pages show de-coupling capacitance used in the schematics as well as the voltage dividers used to provide the GTL reference voltage.
Hardware system manager P-33
The LM79 is a hardware system monitor. It monitors voltage regulation, fan RPM and stores POST codes. The device can be accessed via the X-Bus bus or through the PIIX4E SMBus interface. Note the voltage level translation circuitry between the 5-Volt LM79 and the rest of the 3.3-Volt SMBus.
Intel740™ Graphics Accelerator P-34/35
This page shows all of the connections to the Intel740 graphics accelerator. Each Intel740 graphics accelerator interface is hooked up in this reference design. Beginning in the upper left hand corner of the page, the video capture port is shown. Internally, the input pins are pulled down. These pins contain a strapping option for subsystem ID. In this case, the reference design has an ID of 0100h. Bits that should be a “1” may be pulled up using a 2K pull-up resistor. Since this graphics design will not have video, the only concern is pulling the bus up to the correct value for the subsystem ID. The video control signals may be left unconnected. The BIOS interface contains the vendor ID. The section labeled AGP interface connects directly to the AGP connector. The memory interfaces connect to memory components. Decoupling for the Intel740 graphics accelerator is shown in the middle of the schematic page.
VGA Connector P-36
The VGA connector provides the RGB output to a monitor. BIOS and hardware provide support for plug-and-play capability.
SGRAMS P-37 The SGRAMs shown on this page are labeled as 512Kx32. The schematic pinout is actually capable of supporting either the 512Kx32 or 256Kx32 SGRAMs. This dual-support connection is achieved through the following method. The 512Kx32 Jedec standard defines AP on pin 51 which is address 9. BS is on pin 29 and is also labeled as address 10. Address 8 is on pin 30. The Intel740 contains the AP on its address 8 pin and BS on address 9 pin. Since the 256Kx32 has AP with graphics accelerator address 8 and on pin 51 along with BS with address 9 on pin 29 and a no connect on pin 30, either the 512K or the 256K SGRAMs are capable of being supported in the same design (see Figure 3-22). Note: It is important to disable the special features of SGRAM. This will make the SGRAM operate as an SDRAM; thus, making it compatible with the Intel740 graphics accelerator.
Intel740™ Graphics Accelerator Design Guide 3-25 3 Device AGP MotherBoard Design
Figure 3-22. 512Kx32 and 256Kx32 Pinout Compatibility
A8/AP Pin 51 A9/AP Intel740™ A9/BS Pin 29 A10/BS Intel740Chip A10 Pin 30 A8 A7 A7 512Kx32 . . SGRAM . . Jedec A0 A0 Standard
Pin 51 Intel740™ A8/AP A8/AP A9/BS Pin 29 A9/BS Intel740Chip A10 Pin 30 NC A7 A7 256Kx32 . . SGRAM . . Jedec A0 A0 Standard
Figure 3-23. 1M X 16 Pinout Compatibility
A11/BS A11 A10/AP A10 A9 A9 A8 A8 Intel740™ 1M X 16 Chip . . SDRAM . . . . A1 A1 A0 A0
Low Power Logic P-38
This page show the logic needed to put the Intel 740 graphics accelerator into a low power state when a video add-in card is installed into the system. In low power mode, the Intel 740 chip is disabled and will not initiate or respond to cycles on the AGP bus.
3-26 Intel740™ Graphics Accelerator Design Guide 3 Device AGP MotherBoard Design
DDC/I2CP-39
This page details the 3.3 volt/5 volt signal conversion as well as the DDC/I2C connections. To perform the voltage translation, quick switches are used.
Voltage Regulator P-40
This page shows the circuitry to convert from 3.3 Volts to 2.7 Volts. The regulator used in the reference design does not need any heatsink for the FET. As shown, the FET will be dissipating slightly over 1 watt. If a different voltage regulator solution will be used, calculations will be needed to determine the need for a heatsink. Core decoupling is shown at the bottom of the page and should be placed close to the Intel740 graphics accelerator.
Revision History P-41
Changes made to the schematics are listed here underneath the revision where they first appeared and by page number.
Intel740™ Graphics Accelerator Design Guide 3-27 3 Device AGP MotherBoard Design
3-28 Intel740™ Graphics Accelerator Design Guide A B C D E 3 Device AGP Refrence Schematics Revision 1.0
4 ** Please note that these schematics are subject to change. 4 TITLE PAGE TITLE PAGE COVER SHEET 1 Low Power Logic 38 BLOCK DIAG RAM 2 DDC 39 SLOT 1 CONNEC TOR 3,4 Graphics Volt Reg 40 CLOCK SYNTHESIZER 5 REVISION HISTORY 41 82443B X 6,7,8 DIMM SOC KETS 9,10,11 THIS SCHEMATIC IS P ROVIDED "AS IS" WITH NO WARRANTIES PIIX4E 12,13 WHATSOEVER, INCLUDING ANY WARRANTY OF 3 MERCHANTABILITY, FITNE SS FOR ANY PARTICULAR PURPOSE, 3 ULTRA I /O 14 OR ANY WARRANTY OTHERWISE ARI SING OUT OF PROPOSAL, AGP C ONNECTOR 15 SPECIFICATION OR SAMPL E. PCI CONNECTORS 16,17 No license, express or implied, by estoppel or o therwise, ISA CONNEC TORS 18 to any intellectual property rights i s granted herein. IDE CONNECTORS 19 Intel disclaims all li ability, including liability for infringement of USB CONNE CTORS 20 any proprietary rights, relating to use of inform ation in this specification. Intel does not warrant or represent that such FLASH BIOS 21 use will not infringe such rights. PARALLEL 22 2 SERIAL/ FLOPPY 23 I C is a two-wire communications bus/protoco l developed 2 by Philips. SMBus is a subset of the I 2C bus/protocol and 2 KEYBO ARD/MOUSE 24 was developed by Inte l. Implementations of the I 2C VRM 25 bus/protocol or the SMBus bus/prot ocol may require licenses from various entities, including Philips Electronics POWER CONNECTOR 26 N.V. and Nor th American Philips Corporation. GTL+ TERMI NATION 27 PCI/AGP PULLUPS/PULLDO WNS 28 *Third-party brands and names are th e property of their respec tive owners. ISA PULLUPS/PULLDOWNS 29
82443BX DECOUPLING 30 Copyrig ht * Intel Corporation 1998 INTEL CORPORATION BULK DEC OUPLING 31 GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 1 TERMINAT ION DECOUPLING 32 FOLSOM, CA 95630 1
LM79 33 Title 3-Device AGP Schematics Intel740TM Graphics Accelerator 34,35 Size Document Number Rev VGA Connect or 36 A 3 DEVICE AGP 1.0 SGRAM 37 Date: 22:16:57 Sheet 1 of 41 A B C D E 1 2 3 4 5 6 7 8
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT DESCHUTES CK100 BEEN VERIFIED FOR MANUFACTURING AN END USER VRM & PRODUCT. iNTEL IS NOT RESPONSIBLE FOR THE MISUSE VTT GEN. PROCESSOR ITP CON. OF THIS INFORMATION. PG. 25 (SLOT 1) PG. 5 PG. 3,4 ADDR CNTL A SMBus MAX1617 ME DATA A Interface PG. 3 SYSTEM BUS GTL TERM. PG. 27 ADDR CNTL DATA AGP CONN. PG. 15 ADD/DATA SIDEBAND
CNTL CNTL MEMORY 3 SDRAM DIMM ADDR MODULES 443BX PG. 9-11 SIDEBAND ADD/DATA 82443BX CNTL CKBF 492 BGA PG. 6
PG. 6-8 DATA GRAPHICS MEMORY CNTL PG. 37 B VGA INTEL740 ADD/DATA B
CONN. CNTL PG. 36 CHIP DATA PG. 34,35 ADD PCI BUS
PG. 20 ADD/DATA CNT 2 USB CONN. PG. 16-17 L USB USB 2 PCI IDE CONNECTORS CON PC CON PC CONN PCI PG. 19 CNTL I I ID SECONDARY ID PR N. N. CNTL E E . PIIX4E IMARY
82371EB ADDR/DATA 324 BGA PG. 12-13 ADDR/DATA CONTROL AD CNT DATA DR C L C ISA BUS ADDR CNTL DATA ADDR PG 18
ADDR CONN ISA FLASH DATA X-BUS BIOS PG. 21 KEYBOARD ULTRA I/O CNTL PG. 24 PG.14
LM79 PG. 33 DATA MOUSE PG. 24 SER. FLOPPY D PARA. CONN. D CONN. CONN. RESET, POWER CONNECTORS PG. 26 PG. 23 PG. 20 PG .23 INTEL CORPORATION SER. PG. 28-29 CONN. ISA, PCI RESISTORS GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 PG. 30-32 FOLSOM, CA 95630 INTEL SECRET DECOUPLING CAPACITORS Title CONFIDENTIAL INFORMATION 3 Device AGP Block Diagram Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 2 of 41 1 2 3 4 5 6 7 8 A B C D E
VCC2.5 VTT
VCC2.5 * Note: This strong pullup resistor on SLP# is necessary when using an R44 VCCCORE VTT U16A VCC3 LAI. 330 R47 B01 EMI VCC_VTT A01 4.7K VCC3 B02 FLUSH# GND A02 28 FLUSH# B03 SMI# VCC_VTT A03 13,28 PX4_SMI# B04 INIT# IERR# A04 4 13,28 HINIT# 4 B05 VCC_VTT A20M# A05 A20M#25,28 C97 B06 STPCLK# GND A06 R37 13,28 STPCLK# B07 TCK FERR# A07 FERR#13,28 10K 5 TCK B08 SLP# IGNNE# A08 0.01 uF 13 SLP# IGNNE#25,28 B09 VCC_VTT TDI A09 U13 2 5 TMS TDI5 B10 TMS GND A10 5 TRST# B11 TRST# TDO A11 TDO5 15 V+ B12 RESERVED PWRGOOD A12 STBY# PWRGOOD21,26 C106 B13 VCC_CORE TESTHI1 A13 3 B14 RESERVED GND A14 D+ 2200pF SMB SLAVE 4 B15 RESERVED THERMTRIP# A15 D- THERMTRIP#28 6 B16 LINT[1] RESERVED A16 ADDRESS ADD1 10 B17 VCC_CORE LINT[0] A17 = 0011000b ADD0 25,28 LINT1 LINT025,28 B18 PICCLK GND A18 MAX1617 ME 5 PICCLK B19 BP#[2] PICD[0] A19 PICD028 16p QSOP B20 RESERVED PREQ# A20 ITPREQ#5 12 B21 100/66# BP#[3] A21 6,9,10,11,13,28,33 SMBDATA SMBDATA 5,11 100/66# B22 PICD[1] GND A22 28 PICD1 14 B23 PRDY# BPM#[0] A23 6,9,10,11,13,28,33 SMBCLK SMBCLK 5,27 PRDY#0 11 B24 BPM#[1] BINIT# A24 SMB_ALERT# B25 VCC_CORE DEP#[0] A25 B26 DEP#[2] GND A26 1 B27 DEP#[4] DEP#[1] A27 RESV THERM#13,28 5 B28 DEP#[7] DEP#[3] A28 RESV 9 B29 VCC_CORE DEP#[5] A29 RESV 13 HD#62 B30 D#[62] GND A30 RESV 16 HD#58 B31 D#[58] DEP#[6] A31 3 RESV 3 HD#63 B32 D#[63] D#[61] A32 HD#61 B33 VCC_CORE D#[55] A33 HD#55 GND GND HD#56 B34 D#[56] GND A34 HD#50 B35 D#[50] D#[60] A35 HD#60 MAX1617_2 7 8 HD#54 B36 D#[54] D#[53] A36 HD#53 B37 VCC_CORE D#[57] A37 HD#57 HD#59 B38 D#[59] GND A38 HD#48 B39 D#[48] D#[46] A39 HD#46 HD#52 B40 D#[52] D#[49] A40 HD#49 B41 EMI D#[51] A41 HD#51 HD#41 B42 D#[41] GND A42 HD#47 B43 D#[47] D#[42] A43 HD#42 HD#44 B44 D#[44] D#[45] A44 HD#45 B45 VCC_CORE D#[39] A45 HD#39 HD#36 B46 D#[36] GND A46 HD#40 B47 D#[40] RESERVED A47 HD#34 B48 D#[34] D#[43] A48 HD#43 B49 VCC_CORE D#[37] A49 HD#37 HD#38 B50 D#[38] GND A50 HD#32 B51 D#[32] D#[33] A51 HD#33 HD#28 B52 D#[28] D#[35] A52 HD#35 B53 VCC_CORE D#[31] A53 HD#31 HD#29 B54 D#[29] GND A54 HD#26 B55 D#[26] D#[30] A55 HD#30 HD#25 B56 D#[25] D#[27] A56 HD#27 B57 VCC_CORE D#[24] A57 HD#24 2 HD#22 B58 D#[22] GND A58 2 HD#19 B59 D#[19] D#[23] A59 HD#23 HD#18 B60 D#[18] D#[21] A60 HD#21 B61 EMI D#[16] A61 HD#16 HD#20 B62 D#[20] GND A62 HD#17 B63 D#[17] D#[13] A63 HD#13 HD#15 B64 D#[15] D#[11] A64 HD#11 B65 VCC_CORE D#[10] A65 HD#10 HD#12 B66 D#[12] GND A66 HD#7 B67 D#[7] D#[14] A67 HD#14 HD#6 B68 D#[6] D#[9] A68 HD#9 B69 VCC_CORE D#[8] A69 HD#8 HD#4 B70 D#[4] GND A70 HD#2 B71 D#[2] D#[5] A71 HD#5 HD#0 B72 D#[0] D#[3] A72 HD#3 B73 VCC_CORE D#[1] A73 HD#1
SLOT1_0.8 SLOT 1a
8,27 HD#[63:0]
R49 R51 R52 1 1 0 0 0 INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 * Please place as close to the connector as possible Title SLOT 1 (PART I)
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 3 of 41 A B C D E A B C D E
VCCCORE
VCC VCC3 U16B
5,6,27 HRESET# B74 RESET# GND A74 B75 BREQ1# BCLK A75 CPUHCLK5 B76 FRCERR# BREQ0# A76 BREQ0#6,27 4 B77 VCC_CORE BERR# A77 4 B78 A#[35] GND A78 B79 A#[32] A#[33] A79 HA#29 B80 A#[29] A#[34] A80 B81 EMI A#[30] A81 HA#30 HA#26 B82 A#[26] GND A82 HA#24 B83 A#[24] A#[31] A83 HA#31 HA#28 B84 A#[28] A#[27] A84 HA#27 B85 VCC_CORE A#[22] A85 HA#22 HA#20 B86 A#[20] GND A86 HA#21 B87 A#[21] A#[23] A87 HA#23 HA#25 B88 A#[25] RESERVED A88 B89 VCC_CORE A#[19] A89 HA#19 HA#15 B90 A#[15] GND A90 HA#17 B91 A#[17] A#[18] A91 HA#18 HA#11 B92 A#[11] A#[16] A92 HA#16 B93 VCC_CORE A#[13] A93 HA#13 HA#12 B94 A#[12] GND A94 HA#8 B95 A#[8] A#[14] A95 HA#14 HA#7 B96 A#[7] A#[10] A96 HA#10 B97 VCC_CORE A#[5] A97 HA#5 HA#3 B98 A#[3] GND A98 HA#6 B99 A#[6] A#[9] A99 HA#9 B100 EMI A#[4] A100 HA#4 B101 SLOTOCC# BNR# A101 BNR#6,27 HREQ#0 B102 REQ#[0] GND A102 HREQ#1 B103 REQ#[1] BPRI# A103 HREQ#4 BPRI#6,27 3 B104 REQ#[4] TRDY# A104 HTRDY#6,27 3 B105 VCC_CORE DEFER# A105 DEFER#6,27 B106 LOCK# GND A106 6,27 HLOCK# B107 DRDY# REQ#[2] A107 HREQ#2 6,27 DRDY# B108 RS#[0] REQ#[3] A108 HREQ#3 6,27 RS#0 B109 VCC_5 HITM# A109 HITM#6,27 B110 HIT# GND A110 6,27 HIT# B111 RS#[2] DBSY# A111 6,27 RS#2 DBSY#6,27 B112 RESERVED RS#[1] A112 RS#16,27 B113 VCC_3 RESERVED A113 B114 RP# GND A114 B115 RSP# ADS# A115 ADS#6,27 B116 AP#[1] RESERVED A116 B117 VCC_3 AP#[0] A117 B118 AERR# GND A118 VID3 R73 0 B119 VID[3] VID[2] A119 R79 0 VID2 VID0 R72 0 B120 VID[0] VID[1] A120 R74 0 VID1 B121 VCC_3 VID[4] A121 R78 0 VID4
SLOT1_0.8 SLOT 1b
6,27 HA#[31:3] 6,27 HREQ#[4:0] 2 2 25,33 VID[4:0]
RP20A VCC J16 1 SEL_VID0 1 8 VRM optional override VID0 2 10K jumpers & resistors 3 * Please place as close to R53 R54 Jumper position 1-2 is the connector as stuffed as the default. To 0 0 J19 1 SEL_VID1 3 RP20C 6 possible VID1 2 10K override, R219-223 must 3 be removed. RP19D J21 1 SEL_VID2 4 5 VID2 2 10K 3 RP20B J18 1 SEL_VID3 2 7 VID3 2 10K 3
J20 1 SEL_VID4 4 RP20D 5 1 VID4 2 10K 1 3 INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title SLOT 1 (PART II)
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 4 of 41 A B C D E A B C D E
C369 C330 C322 C321 + CLOCK SYNTHESIZER C290 C291 +
0.01uF 470pF 22uF 0.01uF 470pF 22uF 16V 16V 16V 16V VCC3 L13 VCC2.5 2 1 1 L14 2 FBHS01L FBHS01L VCC3
4 C300 C333 C331 C294 C334 C332 C301 4 R182 + C299 C297 C298 C296 C293 C292 200 0.01 uF 0.01 uF 0.01uF 100pF 100pF 100pF + Do Not Stuff *NOTE: Override to 16V 16V 16V 16V 16V 16V 22uF 100pF 100pF 0.01uF 0.01uF 0.01uF C264 16V 16V 16V 16V 16V 22uF R12833 66MHz only. 10pF
U27 9 15 19 21 33 48 46 41 37 ITPCLK
J33 40 CPUCLK0 C268 * Note * This is a stuffing option: 10 pF 39 R143 22 CPUCLK1 VCC3 36 R144 22 10pF caps to ground may be desirable to VDDPCI1 VDDPCI0 VDDAPIC CPUCLK2 BXHCLK6 VDDCPU0 VDDCPU1 VDDQREF 35 R145 22 reduce the effects of EMI. VDD48MHZ VDDCORE0 VDDCORE1 CPUCLK3 CPUHCLK4 C320 XTLI1 4 7 R173 22 2 4 1 XTALIN PCICLK_F PXPCLK13 10pF 8 R174 22 PCICLK_1 PCLK116 * Note * For power managed systems, the PIIX4 must be Y2 10 R175 22 PCICLK_2 PCLK216 connected to PCICLK_F of the CK100 which is a free 11 R176 22 C295 14.318MHz PCICLK_3 PCLK317,38 running PCLK not affected by the assertion of 8.2K 8.2K 8.2K XTLO1 5 CK100 13 R177 22
RP108B RP108A PCLK4
RP108D XTALOUT PCICLK_4 10pF 14 R178 22 PCICLK_5 BXPCLK7 PCISTOP#. 7 5 8 42 16 R221 33 RESV PCICLK_6 28 17 33 RESV PCICLK_7 R222 27 22 R179 22 C381 SEL0 48MHZ_0 48Mhz_013 26 23 33 SEL1 48MHZ_1 25 R223 10pF Do Not Stuff 3 3,11 100/66# SEL_100/66# 3 45 R142 22 C382 APICCLK_0 PICCLK3 44 R127 33 APICCLK_1 31 10pF 13 PCI_STP# PCI_STP# 30 1 R171 22 CPU_STP# REF0 OSC118 * Note * This is a stuffing option: 10 pF 29 2 R172 22 PWRDWN# REF1 OSC213 47 R141 22 caps to ground may be desirable to 13 CPU_STP# REF2 OSC314 reduce the effects of EMI.
VCC3 13 SUSA# R131 VSSREF R188 R189 VSSPCI0 VSSPCI1 VSSPCI2 VSSCORE0 VSS48MHZ VSSCORE1 VSSCPU0 VSSCPU1 VSSAPIC 10K 10K 10K
CK100_05 3 6 12 18 20 24 32 38 34 43 C346C270C269
C349C348C347 10pF10pF10pF
10pF10pF10pF R180 C380C351C350 0 10pF10pF10pF VCC2.5 VTT C263C370
10pF10pF VCC2.5
R55 R60 R83 7
1K OPTIONAL ITP 4 2 Stuffing option to enable Spread# 1K 1K RP46B R56 2 5% RP46D function for possible EMI TEST 330 330 reduction. R59 240 4,6,27 HRESET# CONNECTOR 150 J11 2
ITP_RST 5 1 2 26 DBRESET# 3 4 R57 5 6 3 TCK ITP_PON 7 8 TDI3 47 9 10 TDO3 11 12 TRST#3 R58 13 14 ITPREQ#3 3 TMS 15 16 PRDY0_R# 47 17 18 PRDY#03,27 19 20 R22 240 21 22 R24 23 24 25 26 680 ITPCLK 27 28 29 30 ITP CONN
1 1 INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title CLOCK SYNTHESIZER
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 5 of 41 A B C D E A B C D E
VCC3
4,27 HA#[31:3]
U18-1 V21 Y21 F7 F9 F18 F20 G6 G21 J6 J21 AA7 AA9 AA18 AA20 MAA[13:0]9,10 HA#3 G25 AF17 MAA0 HA3# MAA0 HA#4 H22 AB16 MAA1
HA4# VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD MAA1 HA#5 G23 AE17 MAA2 HA5# MAA2 HA#6 H23 AC17 MAA3 HA6# MAA3 HA#7 G24 AF18 MAA4 HA7# MAA4 HA#8 F26 AE19 MAA5 HA8# MAA5 HA#9 G26 AF19 MAA6 4 HA9# MAA6 4 HA#10 G22 AC18 MAA7 HA10# MAA7 HA#11 F22 AC19 MAA8 HA11# MAA8 HA#12 F23 AE20 MAA9 HA12# MAA9 HA#13 F24 AD20 MAA10 HA13# MAA10 HA#14 F25 AF21 MAA11 HA14# MAA11 HA#15 E23 AC21 MAA12 HA15# MAA12 HA#16 E26 AF25 MAA13 C339 HA16# MAA13 MAB#[13:0]11 HA#17 E25 + HA17# HA#18 D25 AD16 MAB#0 C338 C337 HA18# MAB0# HA#19 D26 82443BX AC16 MAB#1 22uF HA19# MAB1# HA#20 B25 AD17 MAB#2 0.01uF 470pF HA20# MAB2# HA#21 C26 AB17 MAB#3 HA21# 492 BGA MAB3# HA#22 A25 AE18 MAB#4 HA22# MAB4# HA#23 C25 AD19 MAB#5 HA23# MAB5# HA#24 A24 AB18 MAB#6 L15 VCC3 HA#25 HA24# MAB6# D24 SYSTEM INTER AB19 MAB#7 2 1 HA25# MAB7# HA#26 C23 AF20 MAB#8 HA26# MAB8# HA#27 B24 AC20 MAB#9 HA27# MAB9# FBHS01L HA#28 C24 AB20 MAB10 HA28# MAB10 HA#29 A23 AE21 MAB#11 HA29# MAB11# 100pF HA#30 E22 AD21 MAB#12 C362 HA30# MAB12# HA#31 D23 AF22 MAB#13 HA31# MAB13# CS_A#[1:0]9 .01uF C304 B23 AB14 CS_A#0 4,5,27 HRESET# CPURST# CSA0# CS_A#[3:2]10 100pF K21 AF15 CS_A#1 C307 4,27 ADS# ADS# CSA1#
H24 FACE AE15 CS_A#2 4,27 BNR# BNR# CSA2# CS_A#[5:4]11 .01uF H26 AC15 CS_A#3 355 3 4,27 BPRI# BPRI# CSA3# 3 INTERFACE AD15 CS_A#4 CSA4# CKE[3:2]10 100pF L23 AE16 CS_A#5 C313 4,27 DBSY# DBSY# CSA5# J26 AE24 CKE2 4,27 DEFER# DEFER# CKE2/CSA6# .01uF K23 AD23 CKE3 C361 4,27 DRDY# DRDY# CKE3/CSA7# CS_B#[1:0]9
L24 DRAM 4,27 HIT# HIT# 100pF L22 AE25 CS_B#0 C358 4,27 HITM# HITM# CSB0# CS_B#[3:2]10 K22 AD24 CS_B#1 4,27 HLOCK# HLOCK# CSB1# .01uF H25 AD26 CS_B#2 C314 4,27 HTRDY# HTRDY# CSB2# CS_B#[5:4]11 B26 AC24 CS_B#3 4,27 BREQ0# BREQ0# CSB3# 100pF AC26 CS_B#4 C310 CSB4# CKE[5:4]11 RS#0 K26 AB23 CS_B#5 RS#0 CSB5# .01uF RS#1 L26 AC23 CKE4 C364 RS#1 CKE4/CSB6# RS#2 L25 AF24 CKE5 RS#2 CKE5/CSB7# DQMA[7:0]9,10,11 .01uF C352 HREQ#0 J22 AD13 DQMA0 4,27 RS#[2:0] HREQ#0 DQMA0 22uF C315 HREQ#1 J23 AC13 DQMA1 + HREQ#1 DQMA1 HREQ#2 K24 AC25 DQMA2 VCC3 HREQ#2 DQMA2 HREQ#3 K25 AB26 DQMA3 HREQ#3 DQMA3 HREQ#4 J25 AE14 DQMA4 HREQ#4 DQMA4 AC14 DQMA5 R154 DQMA5 U28 23 3 7 12 16 20 29 33 37 42 46 AA22 DQMA6 DQMA6 4.7k AA24 DQMA7 DCLK[11:0]9,10,11 4,27 HREQ#[4:0] DQMA7 VDD VDD VDD VDD VDD VDD VDD VDD VDD AE13 DQMB1 VDD 4 R192 0 DCLK9
DQMB1 DQMB111 VDDIIC SDRAM0 N23 AD14 DQMB5 5 R193 0 DCLK8 5 BXHCLK HCLKIN DQMB5 DQMB511 SDRAM1 8 R194 0 DCLK5 SDRAM2 M25 AC22 CKE0 9 R195 0 DCLK4 2 TESTIN# CKE0/FENA CKE09 SDRAM3 2 CRESET# M26 AF23 CKE1 38 CKBF 13 R197 0 DCLK0 25 CRESET# CRESET# CKE1/GCKE CKE19 OE SDRAM4 14 R198 0 DCLK1 SDRAM5 A3 R196 11 17 C357 C360 All Caps are 10pF and 12,15,16,17,38 PCIRST# PCIRST# BUF_IN SDRAM6 AF16 18 C354 SRAS_A# SRAS_A#9,10 47 SDRAM7 are a Stuffing Option VCC3 AA17 25 31 C353 C359 SRAS_B# SRAS_B#11 SCLOCK SDRAM8 for EMI Reductions AF12 24 32 C356 SCAS_A# SCAS_A#9,10 SDATA SDRAM9 AB13 35 R156 0 DCLK11 SCAS_B# SCAS_B#11 SDRAM10 36 R155 0 DCLK10 SDRAM11 AE12 1 40 R153 0 DCLK7 WE_A# WE_A#9,10 RESV SDRAM12 **Please Note ** AE22 AC12 2 41 R152 0 DCLK6 RESVA WE_B# WE_B#11 RESV SDRAM13 R99 R100 AE23 47 44 R151 0 DCLK3 These clock RESVB RESV SDRAM14 P22 AB21 R98 48 45 R150 0 DCLK2 8.2K 10K RESVC DCLKO RESV SDRAM15 assignments may AD25 21 R199 0 DCLKREF DCLKWR 22 SDRAM16 AB22 28 not be optimum. DCLKRD DCLKREF SDRAM17 C308 VSS VSS VSS VSSIIC VSS VSS VSS VSS VSS VSS VSS C311 C305
** TESTIN# pullup may be removed after C363 CKBF 26 6 10 15 19 22 27 30 34 39 43 C312 C306 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 22pF validation has been completed. C309 **Locate R196 close to CKBF and 443BX_10 A1 A14 A26 C5 C9 C18 C22 E3 E12 E15 E24 F6 F8 F19 F21 H6 H21 J3 J24 All Caps are 10pF and slave address = are a Stuffing Option R98 close to 443BX. 1101001b for EMI Reductions **Locate "T" and cap close to BX. 3,9,10,11,13,28,33 SMBCLK 1 1 ** Please make DCLKREF trace length equal to 2.5" more 3,9,10,11,13,28,33 SMBDATA INTEL CORPORATION than the DCLK outputs to the DIMMs. DCLK outputs to GRAPHICS COMPONENTS DIVISION the DIMMs should all be the same recommended length. *The unused SDRAM 1900 PRAIRIE CITY RD. FM5-79 clocks may be disabled FOLSOM, CA 95630 Example: if DCLK[0-11] = 2.5" using the SMBus Title 82443BX SYSTEM AND DRAM INTERFACES then DCLKREF = 2.5" + 2.5". interface. Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 6 of 41 A B C D E A B C D E
VCC3
12,16,17 AD[31:0] U18-2 L11 L13 L14 L16 M12 M15 N11 N16 P11 P16 R12 R15 T11 T13 T14 T16 N26 P1 AE1 V6 Y6 GAD[31:0]15,34 AD0 K6 AB5 GAD0 AD0 GAD0 AD1 K2 AE2 GAD1 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD AD1 VDD GAD1 AD2 K4 AD3 GAD2 4 AD2 GAD2 4 AD3 K3 AD2 GAD3 AD3 GAD3 AD4 K5 AD1 GAD4 AD4 GAD4 AD5 J1 AC3 GAD5 AD5 GAD5 AD6 J2 AC1 GAD6 AD6 GAD6 AD7 H2 AB4 GAD7 AD7 GAD7 AD8 H1 AB1 GAD8 AD8 GAD8 AD9 J5 AA5 GAD9 AD9 GAD9 AD10 H3 AA3 GAD10 AD10 GAD10 AD11 H5 AA4 GAD11 AD11 GAD11 AD12 H4 AA2 GAD12 AD12 GAD12 AD13 G1 AA1 GAD13 AD13 GAD13 AD14 G2 Y5 GAD14 AD14 GAD14 AD15 G4 Y3 GAD15 AD15 GAD15 AD16 D1 W1 GAD16 AD16 GAD16 AD17 D3 82443BX V2 GAD17 AD17 GAD17 AD18 D2 W2 GAD18 AD18 GAD18 AD19 C1 492 BGA U5 GAD19 AD19 GAD19 AD20 A2 V1 GAD20 AD20 GAD20 AD21 C3 U4 GAD21 AD21 GAD21 AD22 B3 U3 GAD22 AD22 GAD22 AD23 D4 U1 GAD23 AD23 GAD23 AD24 E5 T3 GAD24 AD25 AD24 GAD24 GAD25 A4 PCI I T4 AD25 GAD25 AD26 D5 T2 GAD26 AD26 GAD26 AD27 B4 T1 GAD27 AD27 GAD27
AD28 B5 NTERFACE U6 GAD28 AD28 GAD28 AD29 A5 R3 GAD29 3 AD29 GAD29 3 AD30 E6 R4 GAD30 AD30 GAD30 AD31 C6 R2 GAD31 12,16,17 C/BE#[3:0] AD31 GAD31 GC/BE#[3:0]15,34 C/BE#0 J4 AB2 GCBE#0 C/BE0# GC/BE0# C/BE#1 G3 Y4 GCBE#1 VCC3 C/BE1# GC/BE1# C/BE#2 E4 V4 GCBE#2 C/BE2# GC/BE2#
C/BE#3 C4 RFACE U2 GCBE#3 C/BE3# GC/BE3# U19 E2 W3 12,16,17,28 FRAME# FRAME# GFRAME# GFRAME#15,28,34 F3 W5 1 8 12,16,17,28 DEVSEL# DEVSEL# GDEVSEL# GDEVSEL#15,28,34 REF CLKOUT E1 V5 7 GCLKS15 12,16,17,28 IRDY# IRDY# GIRDY# GIRDY#15,28,34 CLK4 F5 W4 6 5 R86 12,16,17,28 TRDY# TRDY# GTRDY# GTRDY#15,28,34 VDD CLK3
F4 AGP INTE Y1 2 12,16,17,28 STOP# STOP# GSTOP# GSTOP#15,28,34 CLK2 0 G5 Y2 4 3 12,16,17,28 PAR PAR GPAR GPAR15,28,34 GND CLK1 VCC3 F1 R85 12,16,17,28 SERR# SERR# F2 L5 16,17,28 PLOCK# PLOCK# GREQ# GREQ#15,28,34 L3 0 GCLK74034 GGNT# GGNT#15,28,34 CY2305 B6 12,28 PHLD# PHOLD# R97 D6 P5 12,28 PHLDA# PHLDA# GCLKOUT R91 10K AE3 N5 VCC3 WSC# PCI ARB & PWR M GCLKIN R69 16,17,28 PREQ#[2:0] 0 PREQ#0 A6 M3 8.2K PREQ0#/IOREQ# PIPE# PIPE#15 PREQ#1 C7 K1 SBA0 PREQ1# SBA0 PREQ#2 F10 M2 SBA1 PREQ2# SBA1 D8 M1 SBA2 PREQ3# SBA2 PREQ#4 D10 N2 SBA3 2 28 PREQ#4 PREQ4# SBA3 2 R94 AD4 P2 SBA4 13 SUSTAT# SUSTAT# SBA4 P4 SBA5 0 16,17,28 PGNT#[2:0] SBA5 PGNT#0 E7 P3 SBA6 VCC3 PGNT0#/IOGNT# SBA6 PGNT#1 D7 R1 SBA7 R70 PGNT1# SBA7
PGNT#2 E10 GT DO NOT STUFF PGNT2# SBA[7:0]15,34 E8 M4 8.2k PGNT3# RBF# RBF#15,34 PGNT#4 E9 Stuffing option to enable and test 28 PGNT#4 PGNT4# AF3 L4 ST0 VCC3 the POS state. 13,26 PWROK BX-PWROK ST0 AC4 L2 ST1 CLKRUN# ST1 C2 L1 ST2 REFVCC5 ST2 13 VREF5V B2 PCLKIN ST[2:0]15,34 5 BXPCLK AC2 R87 GADSTB-A ADSTB-A15,28,34 T5 150 GADSTB-B ADSTB-B15,28,34 1% N3 SBSTB15,28,34 C182 R89 SB-STB .1uF N4 100 AGPREFV
C204 R82 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ** Place as close to 0.001uF 100 1%
443BX_10 N1 M5 L12 L15 M11 M13 M14 M16 M22 N12 N13 N14 N15 P12 P13 P14 P15 P26 T12 T15 R5 R11 R13 R14 R16 R22 V3 V24 W6 W21 443BX as possible.
1 1 INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title 82443BX PCI AND AGP INTERFACES
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 7 of 41 A B C D E A B C D E
VCC3
HD#[63:0]3,27
9,10,11 MD[63:0] U18-3 B1 N22 AF14 AF2 AE26 MD0 AF4 B22 HD#0 MD0 HD0# MD1 AE4 D22 HD#1
MD1 VDD VDD VDD VDD VDD HD1# MD2 AF5 E21 HD#2 MD2 HD2# MD3 AD6 A22 HD#3 MD3 HD3# 4 MD4 AE6 D21 HD#4 4 MD4 HD4# MD5 AB7 C21 HD#5 MD5 HD5# MD6 AC7 A21 HD#6 MD6 HD6# MD7 AF7 C20 HD#7 MD7 HD7# MD8 AB8 B21 HD#8 MD8 HD8# MD9 AB9 E20 HD#9 MD9 HD9# MD10 AC9 A20 HD#10 MD10 HD10# MD11 AE9 E19 HD#11 MD11 HD11# MD12 AB10 B20 HD#12 MD12 HD12# MD13 AC10 E18 HD#13 MD13 HD13# MD14 AF10 D20 HD#14 MD14 HD14# MD15 AD11 D19 HD#15 MD15 HD15# MD16 Y24 D18 HD#16 MD16 HD16# MD17 Y25 C19 HD#17 MD17 HD17# MD18 W23 B19 HD#18 MD18 HD18# MD19 W24 A18 HD#19 VTT MD19 HD19# MD20 W26 82443BX A19 HD#20 MD20 HD20# MD21 W25 B18 HD#21 MD21 492 BGA HD21# MD22 V26 C17 HD#22 MD22 HD22# MD23 U24 E17 HD#23 R76 MD23 HD23# MD24 U23 D17 HD#24 75 MD24 HD24# MD25 T22 B17 HD#25 1% 3 MD25 HD25# 3 MD26 T23 C16 HD#26 MD26 HD26# MD27 T26 A17 HD#27 GTLREF1 MD27 HD27# MD28 R24 C15 HD#28 C149 MD28 MEMORY DATA HD28# MD29 R25 B16 HD#29 MD29 HD29# MD30 P23 D16 HD#30 .1uF R77 C172 C205 MD30 HD30# MD31 N25 A16 HD#31 150 MD31 HD31# MD32 AC5 B15 HD#32 1% 0.001uF 1uF MD32 HD32# MD33 AE5 A15 HD#33 MD33 HD33# MD34 AB6 D14 HD#34 MD34 HD34# MD35 AC6 D15 HD#35 MD35 HD35# MD36 AF6 B13 HD#36 MD36 HD36# MD37 AD7 C14 HD#37 VTT MD37 HD37# MD38 AE7 E14 HD#38 MD38 BUS HD38#
MD39 AC8 T DATA BUS D13 HD#39 MD39 HD39# MD40 AD8 A13 HD#40 MD40 HD40# MD41 AF8 D12 HD#41 R88 MD41 HD41# MD42 AE8 HOS B12 HD#42 75 MD42 HD42# MD43 AF9 B14 HD#43 1% MD43 HD43# MD44 AD10 C13 HD#44 MD44 HD44# MD45 AE10 E13 HD#45 GTLREF2 MD45 HD45# MD46 AB11 D11 HD#46 C206 MD46 HD46# 2 MD47 AC11 A12 HD#47 2 MD47 HD47# MD48 Y23 B11 HD#48 .1uF R92 C217 MD48 HD48# MD49 Y26 A11 HD#49 150 MD49 HD49# MD50 W22 B7 HD#50 1% 0.001uF MD50 HD50# MD51 V22 C12 HD#51 MD51 HD51# MD52 V23 C8 HD#52 MD52 HD52# MD53 V25 B10 HD#53 MD53 HD53# MD54 U22 A10 HD#54 MD54 HD54# MD55 U25 A9 HD#55 MD55 HD55# MD56 U26 A7 HD#56 MD56 HD56# MD57 T24 E11 HD#57 MD57 HD57# MD58 T25 D9 HD#58 MD58 HD58# MD59 U21 C11 HD#59 MD59 HD59# MD60 R23 C10 HD#60 MD60 HD60# MD61 R26 B8 HD#61 MD61 HD61# MD62 P24 A8 HD#62 MD62 HD62# MD63 P25 B9 HD#63 MD63 HD63# GTLREF2 MECC0 AE11 GTLREF1 MECC0 MECC1 AA10 MECC1 INTEL CORPORATION MECC2 AA23 MECC2 MECC3 AA26 M23 1 MECC3 GTLREFA GRAPHICS COMPONENTS DIVISION 1 MECC4 AF11 E16 MECC4 GTLREFB 1900 PRAIRIE CITY RD. FM5-79 MECC5 AD12 M24 MECC5 VTTA VTT FOLSOM, CA 95630 MECC6 AA25 F17 MECC6 VTTB MECC7 Y22 MECC7 Title VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 82443BX MD/HD BUS 9,10,11 MECC[7:0] 443BX_10 Size Document Number Rev AB25 N24 AA6 AA8 AA19 AA21 AB3 AB12 AB15 AB24 AD5 AD9 AD18 AD22 AF1 AF13 AF26 Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 8 of 41 A B C D E A B C D E DIMM SOCKET 0
VCC3 VCC3
8,10,11 MD[63:0]
4 6 18 26 40 41 90 102 110 124 49 59 73 84 133 143 157 168 4 MD0 2 55 MD16 DQ0 DQ16 MD1 3 56 MD17
DQ1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DQ17 MD2 4 57 MD18 DQ2 DQ18 MD3 5 58 MD19 DQ3 DQ19 MD4 7 60 MD20 DQ4 DQ20 MD5 8 65 MD21 DQ5 DQ21 MD6 9 66 MD22 DQ6 DQ22 MD7 10 67 MD23 DQ7 DQ23 MD8 11 69 MD24 DQ8 DQ24 MD9 13 70 MD25 DQ9 DQ25 MD10 14 71 MD26 DQ10 DQ26 MD11 15 72 MD27 DQ11 DQ27 MD12 16 74 MD28 DQ12 DQ28 MD13 17 75 MD29 DQ13 DQ29 MD14 19 76 MD30 DQ14 DQ30 MD15 20 77 MD31 DQ15 DQ31 MD32 86 139 MD48 DQ32 DQ48 MD33 87 140 MD49 DQ33 DQ49 MD34 88 141 MD50 DQ34 DQ50 MD35 89 142 MD51 DQ35 DQ51 MD36 91 144 MD52 DQ36 DQ52 MD37 92 149 MD53 DQ37 DQ53 MD38 93 150 MD54 DQ38 DQ54 MD39 94 151 MD55 DQ39 DQ55 **NOTE ON ALL DIMM SOCKETS** MD40 95 153 MD56 VCC3 DQ40 DQ56 MD41 97 154 MD57 Pin 147 should be pulled to a high state 3 DQ41 DQ57 3 MD42 98 155 MD58 DQ42 DQ58 to accommodate registered DIMMs. MD43 99 156 MD59 DQ43 DQ59 MD44 100 158 MD60 DQ44 DQ60 MD45 101 159 MD61 R102 DQ45 DQ61 MD46 103 160 MD62 DQ46 DQ62 0 ohm MD47 104 161 MD63 6,10 MAA[13:0] DQ47 DQ63 MAA0 33 134 A0 NC MAA1 117 135 A1 NC MAA2 34 146 A2 NC MAA3 118 164 A3 NC MAA4 35 62 A4 NC MAA5 119 A5 CKE[1:0]6 MAA6 36 147 A6 REGE MAA7 120 128 CKE0 A7 CKE0 MAA8 37 63 CKE1 A8 CKE1 MAA9 121 A9 MAA10 38 21 MECC0 A10 (AP) CB0 MAA13 123 22 MECC1 A11 CB1 126 52 MECC2 A12 CB2 132 53 MECC3 6,10,11 DQMA[7:0] A13 CB3 105 MECC4 CB4 DQMA0 28 106 MECC5 DQMB0 CB5 DQMA1 29 136 MECC6 DQMB1 CB6 DQMA2 46 137 MECC7 DQMB2 CB7 DQMA3 47 DQMB3 DQMA4 112 DQMB4 MECC[7:0]8,10,11 DQMA5 113 165 DQMB5 SA0 DQMA6 130 166 DQMB6 SA1 Slave address = 1010000b 2 DQMA7 131 167 2 DQMB7 SA2 SMBDATA3,6,10,11,13,28,33 SMBCLK3,6,10,11,13,28,33 MAA11 122 82 BA0 SDA MAA12 39 83 BA1 SCL CS_A#[1:0]6 24 30 CS_A#0 NC /S0 CS_B#[1:0]6 25 114 CS_A#1 NC /S1 DIMM 0 DIMM 1 DIMM 2 31 45 CS_B#0 NC /S2 44 129 CS_B#1 NC /S3 48 27 NC /WE0 WE_A#6,10 50 111 NC /CAS SCAS_A#6,10 51 115 NC /RAS SRAS_A#6,10 61 NC 80 42 DCLK8 NC CK0 81 125 DCLK9 NC CK1 109 79 DCLK10 NC CK2 CONTROL B 108 163 DCLK11 NC CK3 443BX CONTROL A 145 VSS VSS VSS VSS VSS VSS VSS VSS NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DCLK[11:0]6,10,11 MAB
MAA 1 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 162 U21
STRAPS DIMM REF
1 1
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 Block diagram for 3 DIMM MA and control connection. FOLSOM, CA 95630 Title DIMM SOCKET 0
Size Document Number Rev Custom 3 DEVICE AGP 1.0 Date: 22:16:57 Sheet 9 of 41 A B C D E A B C D E
DIMM SOCKET 1
VCC3 VCC3
4 8,9,11 MD[63:0] 4 6 18 26 40 41 90 102 110 124 49 59 73 84 133 143 157 168
MD0 2 55 MD16 DQ0 DQ16 MD1 3 56 MD17
DQ1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DQ17 MD2 4 57 MD18 DQ2 DQ18 MD3 5 58 MD19 DQ3 DQ19 MD4 7 60 MD20 DQ4 DQ20 MD5 8 65 MD21 DQ5 DQ21 MD6 9 66 MD22 DQ6 DQ22 MD7 10 67 MD23 DQ7 DQ23 MD8 11 69 MD24 DQ8 DQ24 MD9 13 70 MD25 DQ9 DQ25 MD10 14 71 MD26 DQ10 DQ26 MD11 15 72 MD27 DQ11 DQ27 MD12 16 74 MD28 DQ12 DQ28 MD13 17 75 MD29 DQ13 DQ29 MD14 19 76 MD30 DQ14 DQ30 MD15 20 77 MD31 DQ15 DQ31 MD32 86 139 MD48 DQ32 DQ48 MD33 87 140 MD49 DQ33 DQ49 MD34 88 141 MD50 DQ34 DQ50 MD35 89 142 MD51 DQ35 DQ51 MD36 91 144 MD52 DQ36 DQ52 MD37 92 149 MD53 DQ37 DQ53 MD38 93 150 MD54 3 DQ38 DQ54 3 MD39 94 151 MD55 DQ39 DQ55 MD40 95 153 MD56 DQ40 DQ56 MD41 97 154 MD57 VCC3 DQ41 DQ57 MD42 98 155 MD58 DQ42 DQ58 MD43 99 156 MD59 DQ43 DQ59 MD44 100 158 MD60 DQ44 DQ60 MD45 101 159 MD61 DQ45 DQ61 MD46 103 160 MD62 R103 DQ46 DQ62 **NOTE ON ALL DIMM SOCKETS** MD47 104 161 MD63 6,9 MAA[13:0] DQ47 DQ63 0 ohm Pin 147 should be pulled to a high state MAA0 33 134 A0 NC to accommodate registered DIMMs. MAA1 117 135 A1 NC MAA2 34 146 A2 NC MAA3 118 164 A3 NC MAA4 35 62 A4 NC MAA5 119 A5 CKE[3:2]6 MAA6 36 147 A6 REGE MAA7 120 128 CKE2 A7 CKE0 MAA8 37 63 CKE3 A8 CKE1 MECC[7:0]8,9,11 MAA9 121 A9 MAA10 38 21 MECC0 A10 (AP) CB0 MAA13 123 22 MECC1 A11 CB1 126 52 MECC2 A12 CB2 132 53 MECC3 6,9,11 DQMA[7:0] A13 CB3 105 MECC4 CB4 DQMA0 28 106 MECC5 DQMB0 CB5 DQMA1 29 136 MECC6 VCC3 DQMB1 CB6 DQMA2 46 137 MECC7 DQMB2 CB7 2 DQMA3 47 2 DQMB3 Slave address = 1010001b DQMA4 112 DQMB4 R132 DQMA5 113 165 R_SA0 DQMB5 SA0 DQMA6 130 166 DQMB6 SA1 4.7K DQMA7 131 167 DQMB7 SA2 SMBDATA3,6,9,11,13,28,33 SMBCLK3,6,9,11,13,28,33 MAA11 122 82 BA0 SDA MAA12 39 83 BA1 SCL CS_A#[3:2]6 24 30 CS_A#2 NC /S0 CS_B#[3:2]6 25 114 CS_A#3 NC /S1 31 45 CS_B#2 NC /S2 44 129 CS_B#3 NC /S3 48 27 NC /WE0 WE_A#6,9 50 111 NC /CAS SCAS_A#6,9 51 115 NC /RAS SRAS_A#6,9 61 NC 80 42 DCLK4 NC CK0 81 125 DCLK5 NC CK1 109 79 DCLK6 NC CK2 108 163 DCLK7 NC CK3 145 VSS VSS VSS VSS VSS VSS VSS VSS NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DCLK[11:0]6,9,11 U22 DIMM REF 1 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 162
1 1
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title DIMM SOCKET 1
Size Document Number Rev Custom 3 DEVICE AGP 1.0 Date: 22:16:57 Sheet 10 of 41 A B C D E A B C D E DIMM SOCKET 2
VCC3 VCC3
8,9,10 MD[63:0]
4 6 18 26 40 41 90 102 110 124 49 59 73 84 133 143 157 168 4 MD0 2 55 MD16 DQ0 DQ16 MD1 3 56 MD17
DQ1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DQ17 MD2 4 57 MD18 DQ2 DQ18 MD3 5 58 MD19 DQ3 DQ19 MD4 7 60 MD20 DQ4 DQ20 VCC3 MD5 8 65 MD21 DQ5 DQ21 MD6 9 66 MD22 DQ6 DQ22 MD7 10 67 MD23 Do Not Stuff DQ7 DQ23 MD8 11 69 MD24 DQ8 DQ24 MD9 13 70 MD25 DQ9 DQ25 MD10 14 71 MD26 DQ10 DQ26 J30 RP92B 2 7 MAB#9 MD11 15 72 MD27 DQ11 DQ27 10K MD12 16 74 MD28 J34 DQ12 DQ28 RP92D 4 5 MAB#6 MD13 17 75 MD29 DQ13 DQ29 10K MD14 19 76 MD30 DQ14 DQ30 J32 RP92C 3 6 MAB#7 MD15 20 77 MD31 10K DQ15 DQ31 J29 RP92A 1 8 MAB#10 MD32 86 139 MD48 DQ32 DQ48 10K MD33 87 140 MD49 J31 DQ33 DQ49 RP93C 3 6 MAB#11 MD34 88 141 MD50 DQ34 DQ50 10K MD35 89 142 MD51 DQ35 DQ51 MD36 91 144 MD52 DQ36 DQ52 MD37 92 149 MD53 DQ37 DQ53 MD38 93 150 MD54 **NOTE ON ALL DIMM SOCKETS** RP93A MAB#12 MD39 DQ38 DQ54 MD55 3,5 100/66# 1 8 94 151 10K DQ39 DQ55 Pin 147 should be pulled to a high state MD40 95 153 MD56 MAB#6: 100MHz Buffer Select DQ40 DQ56 to accommodate registered DIMMs. MD41 97 154 MD57 3 1 = Mobile Buffer, 0 = Normal Desktop Buffer DQ41 DQ57 3 MD42 98 155 MD58 VCC3 DQ42 DQ58 (Default) MD43 99 156 MD59 DQ43 DQ59 MD44 100 158 MD60 DQ44 DQ60 MD45 101 159 MD61 MAB#7: MMConfig Reg. used with SDRAMPWR Reg. to DQ45 DQ61 MD46 103 160 MD62 config CKE signals of SDRAM DQ46 DQ62 MD47 104 161 MD63 R101 6 MAB#[13:0] DQ47 DQ63 1 = MMCONFIG-1), 0 = MMCONFIG-0 (default) 0 ohm MAB#0 33 134 A0 NC MAB#1 117 135 MAB#9: AGP Interface A1 NC MAB#2 34 146 1 = DISABLE, 0 = A2 NC MAB#3 118 164 A3 NC Enable (default) MAB#4 35 62 A4 NC MAB#5 119 A5 CKE[5:4]6 MAB#6 36 147 MAB#10: Start Mode A6 REGE MAB#7 120 128 CKE4 1 = Quick Start, 0 = A7 CKE0 MAB#8 37 63 CKE5 A8 CKE1 MECC[7:0]8,9,10 Standard Stop MAB#9 121 A9 MAB10 38 21 MECC0 Clock (default) A10 (AP) CB0 MAB#13 123 22 MECC1 A11 CB1 126 52 MECC2 A12 CB2 132 53 MECC3 MAB#11: IOQ Depth 6,9,10 DQMA[7:0] A13 CB3 105 MECC4 1 = 1, 0 = MAX CB4 DQMA0 28 106 MECC5 DQMB0 CB5 (default) 29 136 MECC6 6 DQMB1 DQMB1 CB6 DQMA2 46 137 MECC7 VCC3 DQMB2 CB7 DQMA3 47 DQMB3 DQMA4 112 DQMB4 Slave address = 1010010b 113 165 DQMB5 SA0 R133 DQMA6 130 166 R_SA1 DQMB6 SA1 2 DQMA7 131 167 2 6 DQMB5 DQMB7 SA2 4.7K SMBDATA3,6,9,10,13,28,33 SMBCLK3,6,9,10,13,28,33 MAB#11 122 82 BA0 SDA MAB#12 39 83 BA1 SCL CS_A#[5:4]6 24 30 CS_A#4 NC /S0 CS_B#[5:4]6 25 114 CS_A#5 NC /S1 31 45 CS_B#4 NC /S2 44 129 CS_B#5 NC /S3 48 27 NC /WE0 WE_B#6 50 111 NC /CAS SCAS_B#6 51 115 NC /RAS SRAS_B#6 61 NC 80 42 DCLK0 NC CK0 81 125 DCLK1 NC CK1 109 79 DCLK2 NC CK2 108 163 DCLK3 NC CK3 145 VSS VSS VSS VSS VSS VSS VSS VSS NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DCLK[11:0]6,9,10 U25 DIMM REF 1 12 23 32 43 54 64 68 78 85 96 107 116 127 138 148 152 162
1 1
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title DIMM SOCKET 2
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 11 of 41 A B C D E A B C D E
U24A AD0 B10 E15 SDD0 AD0 SDD0 AD1 A10 B15 SDD1 AD1 SDD1 AD2 D9 D14 SDD2 AD2 SDD2 AD3 C9 C14 SDD3 AD3 SDD3 AD4 B9 A14 SDD4 AD4 SDD4 AD5 A9 C13 SDD5 AD5 SDD5 AD6 D8 A13 SDD6 AD6 SDD6 AD7 E8 C12 SDD7 AD7 SDD7 AD8 B8 D12 SDD8 AD8 SDD8 AD9 A8 B13 SDD9 AD9 SDD9 4 AD10 D7 D13 SDD10 4 AD10 SDD10 AD11 C7 B14 SDD11 AD11 SDD11 AD12 B7 E14 SDD12 AD12 SDD12 AD13 A7 A15 SDD13
AD13 SIGNALS SDD13 AD14 D6 C15 SDD14 AD14 SDD14 AD15 E6 D15 SDD15 AD16 AD15 SDD15 E4 IDE AD16 SDD[15:0]19 AD17 C4 C18 AD17 SCS3# SCS3#19 AD18 B4 PCI BUS H16 AD18 PCS3# PCS3#19 AD19 A4 B18 AD19 SCS1# SCS1#19 AD20 D3 H17 AD20 PCS1# PCS1#19 AD21 E3 AD21 AD22 C3 AD22 AD23 B3 U11 SA0 AD23 SA0 AD24 E2 T11 SA1 AD24 INTERFACE SA1 AD25 C2 W11 SA2 AD25 SA2 AD26 B2 Y11 SA3 AD26 SA3 AD27 A2 T10 SA4 AD27 SA4 AD28 D1 W10 SA5 AD28 SA5 AD29 E1 U9 SA6 AD29 SA6 AD30 C1 V9 SA7 AD30 SA7 AD31 B1 Y9 SA8 AD31 SA8 T8 SA9 SA9 W8 SA10 7,16,17 AD[31:0] SA10 C/BE#0 C8 U7 SA11 C/BE#0 PIIX4E SA11 C/BE#1 C6 V7 SA12 C/BE#1 SA12 C/BE#2 D4 Y7 SA13 C/BE#2 SA13 3 C/BE#3 D2 V6 SA14 3 C/BE#3 82371EB SA14 Y6 SA15 7,16,17 C/BE#[3:0] SA15 C10 T5 SA16 CLOCKRUN# SA16 E5 W5 SA17 7,16,17,28 DEVSEL# DEVSEL# SA17 A5 U4 SA18 7,16,17,28 FRAME# FRAME# SA18 R_AD18 A3 V4 SA19 R138 IDSEL SA19 B5 7,16,17,28 IRDY# IRDY# SA[19:0]14,18,21,29,33 100 B6 7,16,17,28 PAR PAR A1 V3 SD0 6,15,16,17,38 PCIRST# PCIRST# SD0 B12 W3 SD1 7,28 PHLD# PHOLD# SD1 A12 U2 SD2 R125 7,28 PHLDA# PHOLDA# SD2 A6 T2 SD3 7,16,17,28 SERR# SERR# SD3 100 D5 W2 SD4 7,16,17,28 STOP# STOP# SD4 C5 Y2 SD5 7,16,17,28 TRDY# TRDY# SD5 T1 SD6 7,16,17,28 PREQ#[3:0] SD6 AD18 E10 V1 SD7 REQ0# SD7 A11 W16 SD8 REQ1# SD8
B11 S T16 SD9 REQ2# SD9 C11 Y17 SD10 REQ3# SD10 V17 SD11 19 SDA[2:0] SD11 SDA0 C17 Y18 SD12 SDA0 SD12 SDA1 B17 W18 SD13 SDA1 SD13 SDA2 A18 Y19 SD14 SDA2 SD14 G19 W19 SD15 19 PDDACK# PDDACK# SD15 A17 19 SDDACK# SDDACK# SD[15:0]14,18,29 19 PDREQ F18 PDREQ LA17 19 SDREQ A16 Y15 2 SDREQ LA17 LA18 2 19 PDIOR# F17 T14 PDIOR# LA18 LA19 19 PDIOW# F16 W14
PDIOW# ISA/EIO SIGNAL LA19 G20 U13 LA20 19 PIORDY PIORDY LA20 C16 V13 LA21 19 SDIOR# SDIOR# LA21
IDE LA22 19 SDIOW# B16 Y13 SDIOW# LA22 LA23 19 SIORDY D16 T12 PDA0 SIORDY LA23 G16 LA[23:17]18,29
PDA0 SIGNALS PDA1 G18 Y12 PDA1 MEMCS16# MEMCS16#18,29 PDA2 G17 V15 PDA2 MEMR# MEMR#18,21,29 U15 19 PDA[2:0] MEMW# MEMW#18,21,29 W4 SMEMR# SMEMR#18,29 PDD0 F20 PDD0 PDD1 E18 U3 R130 PDD1 SMEMW# SMEMW#18,29 PDD2 E20 T7 PDD2 SYSCLK SYSCLK18,33,38 PDD3 D18 U10 33 PDD3 BALE BALE18,29 PDD4 D20 Y1 PDD4 IOCHK# IOCHK#18,29 PDD5 C20 PDD5 PDD6 B20 W7 PDD6 REFRESH# REFRESH#18,29 PDD7 A20 V12 PDD7 IOCS16# IOCS16#18,29 PDD8 A19 Y3 PDD8 ZEROWS# ZEROWS#18,29 PDD9 B19 PDD10 PDD9 C19 W12 SBHE#18,29 PDD11 PDD10 SBHE# D19 W1 RSTDRV14,26 PDD12 PDD11 RSTDRV D17 Y5 IOR#14,18,29,33 PDD13 PDD12 IOR# E19 T4 IOW#14,18,29,33 PDD14 PDD13 IOW# E17 T3 IOCHRDY14,18,29 PDD15 PDD14 IOCHRDY 1 F19 Y4 AEN14,18 1 PDD15 AEN INTEL CORPORATION 19 PDD[15:0] GRAPHICS COMPONENTS DIVISION PIIX4_15 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title PIIX4E (PART I)
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 12 of 41 A B C D E A B C D E
VCC3 VCC3 3VSB VCC3
U24B F6 E11 F15 R6 R15 E9 E12 E16 F5 F14 G6 R7 P15 T6 R16 N16 K5 14,18 DACK#[3:0] DACK#0 U14 F1 5VSB DACK0# USBP1+ USBP1+20 DACK#1 W6 H2
DACK1# VCC VCC VCC VCC VCC USBP1- USBP1-20
DACK#2 Y10 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP G2 DACK2# USBP0+ USBP0+20 4 DACK#3 V5 H3 4 VCCSUS VCCSUS VCCUSB USBP0-20 18 DACK#[7:5] DACK#5 DACK3# USBP0- T15 USB J1 OC#020 DACK#6 DACK5# OC0 V16 DMA SIGNALS J2 DACK6# OC1 OC#120 DACK#7 W17 3VSB 5VSB R238 DACK7# 100K W15 V20 14,18,29 DRQ0 DREQ0 EXTSMI# EXTSMI#28,33 U6 W20 14 U35F 14 U36B 14,18,29 DRQ1 DREQ1 SUSA# SUSA#5 V2 V19 14,18,29 DRQ2 DREQ2 GPO15/SUSB# U5 U18 SUSC# 13 12 3 4 14,18,29 DRQ3 DREQ3 GPO16/SUSC# Y16 18,29 DRQ5 DREQ5 U16 R1 C373 7 7 18,29 DRQ6 DREQ6 GPO17/CPU_STP# CPU_STP#5 U17 R2 74LVC14 18,29 DRQ7 DREQ7 GPO18/PCI_STP# PCI_STP#5 74F07 K16 0.01 uF GPO19/ZZ M1 J43 28 REQ#A REQA#/GPI2 **External logic shown N2 3 28 REQ#B REQB#/GPI3 is used to handle P3 H19 2 28 REQ#C REQC#/GPI4 GPI8/THERM# THERM#3,28 B_SUSC26 N1 U19 power loss condition. 1 GNTA#/GPO9 GPI9/BATLOW# BATLOW#28 P2 M17 GNTB#/GPO10 RSMRST# RSMRST#26 P4 U20 TP045 GNTC#/GPO11 PWRBT# PWRBT#26 P16 JMP_3P GPI10/LID LID26,28 V10 T20 14,18 TC TC PIIX4 SMBDATA SMBDATA3,6,9,10,11,28,33 R19 VCC3 SMBCLK SMBCLK3,6,9,10,11,28,33 J43 CONFIG. J17 N17 1 APICACK#/GPO12 GPI11/SMBALERT# SMBALERT#28 VCC3 RP94D H18 P18 APICCS#/GPO13 82371AB GPI12/RI#A AGP_PME#15,28 SAVE STATE ON 4 5 K18 1-2 2 1 POWER DOWN. 10K APICREQ#/GPI5 POWER MANAGEMENT D3 PIIX4 POWERS ON SYS. 3 H20 P17 VCC 3 IRQ0/GPO14 SUSCLK 2-3 AT POWER-UP. J20 T17 14,29 IRQ1 IRQ1 GPO20/SUS_STAT1# SUSTAT#7 T9 T18 14,18,29 IRQ3 IRQ3 GPO21/SUS_STAT2# W9 J18 IRQ4 STPCLK# STPCLK#3,28 IRQ 14,18,29 IRQ4 U8 K20 3 R170 IRQ5 SLP# SLP#3 14,18,29 IRQ5 V8 14,18,29 IRQ6 IRQ6 1K Y8 14,18,29 IRQ7 IRQ7 Y20 29 IRQ#8 IRQ8/GPI6 SIGNALS U1 J16 14,18,29 IRQ9 IRQ9 VREF VREF5V7 U12 14,18,29 IRQ10 IRQ10 W13 IRQ11 + 14,18,29 IRQ11 T13 C183 C328 IRQ12 14,18,29 IRQ12 V14 IRQ14 1.0 uF 14,18,19,29 IRQ14 Y14 P19 0.1 uF IRQ15 GPI1 PCI_PME#16,28 14,18,19,29 IRQ15 L2 GPI13 GPI13 J19 J3 GPI14 28 GPI7 SERIRQ/GPI7 GPI14 3 PIRQ#A R3 L5 GPI15 15,16,17,28,34 PIRQ#A PIRQA# GPI15 Q9
PIRQ#B R4 K3 GPI16 5VSB SP3 15,16,17,28 PIRQ#B PIRQB# GPI16 PIRQ#C P5 K4 GPI17 5VSB 2N7002 16,17,28 PIRQ#C PIRQC# GPI17 PIRQ#D G1 H1 GPI18 2 16,17,28 PIRQ#D PIRQD# GPI18 WOLLID26 H4 GPI19 14 U32C GPI19 H5 GPI20 9 GPI20 M19 G3 GPI21 10 8 1
CPURST CPU INTERFACE GPI21 K19 SUSC# 11 3,28 FERR# FERR# GPI[20:13]28 L17 7 25,28 PX4_IGNNE# IGNNE#
L18 /SCAN 3,28 HINIT# INIT GPI2123 74HC10 L19 2 25,28 PX4_INTR INTR 2 P1 14 A20GATE A20GATE L20 25,28 PX4_NMI NMI 3 P20 3,28 PX4_SMI# SMI# Q7 N20 G4 2N7002 14 KBRST# RCIN# GPO0 FAN_LED26 M20 T19 GPO8 RTC_BAT 2 25,28 PX4_A20M# A20M# GPO8 POWER-ON26 M18 G5 7,26 PWROK PWROK GPO27 GPO2738 K17 F2 26 SPKR SPKR GPO28 GPO2838 V18 F3 R219 1 5VSB 28 TEST# TEST# GPO29 CLEAR CMOS GPO/GPI/GPIO F4 R250 10K GPO30 8.2K J44 CONFIG N4 MCCS# 10K 1 -2 NORMAL M4 14 XOE# XOE#/GPO23 X-BUS M3 L4 PGCS#0 1 R205 14 XDIR# XDIR#/GPO22 PGCS0# TP4409 2 - 3 CLEAR CMOS M2 N5 PGCS#1 21 BIOSCS# BIOSCS# PGCS1# PGCS#128,33 4 U33A 10 U33B L1 16 16 RTCALE/GPO25 VCC VCC K2 J4 R236 3 5 11 9 RTC_BAT RTCCS#/GPO24 N/C 26 PS_POK J Q J Q 3 K1 N18 PR PR R248 KBCCS#/GPO26 N/C 1K VB2 3 N3 R235 1 13 Q5 J44 N/C CLK CLK 2 L16 M5 3 VBAT N/C 1.5K 2N7002 1K 1 RTCX2 R20 M16 2 6 12 7 2
RTCX2 N/C K CL Q K CL Q D6 RTCX1 N19 R5 8 8 RTCX1 N/C 3VSB GND GND
C397 R158 15 74HC112 RSMRST# 14 74HC112 1 R17 PX4_CFG128 0.1 uF CMOS_CLR CONFIG1
L3 R18 14 U35E GPO8# JK_CLR 0 5 48Mhz_0 48Mhz CONFIG2 PX4_CFG228 3VSB V11 1 5 OSC2 OSC 1 2 1 D11 11 10 INTEL CORPORATION 5 PXPCLK PCICLK 7 GRAPHICS COMPONENTS DIVISION Y3 74LVC14 1900 PRAIRIE CITY RD. FM5-79 VSS_USB VSS VSS VSS J36 R239 2 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C375 R218 FOLSOM, CA 95630 2 1 4 4 0.01uF 8.2K D10 E7 E13 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 J5 2 1 3 1K 32.768KHz Title 3 3 2 PIIX4E (PART II) 2 BT1 1 C327 C326 RTC_BAT 1 18pF 3 BAT 18pF Size Document Number Rev PIIX4_15 4PIN_JP Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 13 of 41 A B C D E 1 2 3 4 5 6 7 8
VCC
U23 21 60 101 125 139 121 37 VBAT 14CLK01 122 38
XTAL1 VCC VCC VCC VCC VCC 14CLK02 124 39 TP076 1 XTAL2 14CLK03 TP47 22 5 OSC3 14CLOCKI 68 36 TP077 1 12,18,29,33 IOR# IOR# 16CLK TP72 69 35 TP088 1 12,18,29,33 IOW# IOW# 24CLK TP73 70 12,18 AEN AEN 80 14 12,26 RSTDRV RSTDRV INDEX# INDEX#23 90 9 A 12,18,29 IOCHRDY IOCHRDY DIR# DIR#23 A 10 12,18,29 SD[15:0] STEP# STEP#23 SD0 72 11 SD0 WDATA# WDATA#23 SD1 73 12 SD1 WGATE# WGATE#23 Stuff for 93X only SD2 74 15 SD2 TRK0# TRK0#23 SD3 75 16 SD3 WPT# WPT#23 SD4 76 17 R116 SD4 RDATA# RDATA#23 SD5 77 13 SD5 SIDE1# SIDE1#23 R118 SD6 78 18 1K SD6 DSKCHG# DSKCHG#23 SD7 79 4 SD7 MTR0# MOTEA#23 7 1K MTR1# MOTEB#23 89 6 13,18 TC TC DRVSEL0# DRVSA#23 5 13,18,29 DRQ[7:0] DRVSEL1# DRVSB#23 DRQ0 82 2 DRQ0 DRVDEN0 REDWC#23 DRQ1 84 3 DRQ1 DRVDEN1 DRATE023 Stuff for 93XFR DRQ2 86 20 TP090 1 DRQ2 MEDID0 TP4408 R117 DRQ3 88 19 DRQ3 MEDID1 IRR4_MODE26 13,18 DACK#[3:0] DACK#0 81 0 DACK0 PDR[7:0]22 DACK#1 83 138 PDR0 DACK1 PD0 DACK#2 85 137 PDR1 DACK2 PD1 DACK#3 87 136 PDR2 DACK3 PD2 VCC 135 PDR3 13,18,29 IRQ[7:0] PD3 IRQ1 67 134 PDR4 IRQ1 PD4 IRQ3 66 133 PDR5 IRQ3 PD5 IRQ4 65 132 PDR6 IRQ4 FDC37C932FR PD6 R134 IRQ5 64 131 PDR7 IRQ5 PD7 IRQ6 63 B 10k IRQ6 160 PIN QFP B IRQ7 62 140 IRQ7 SLIN# SLIN#R22 CONFIG PORT ADDRESS 61 141 IRQ8# INIT# INIT#R22 IRQ9 59 143 13,18,29 IRQ9 IRQ9 AFD# AFD#R22 IRQ10 58 144 VCC 13,18,29 IRQ10 IRQ10 STB# STB#R22 IRQ11 57 128 13,18,29 IRQ11 IRQ11 BUSY BUSY22 370 I/O decode IRQ12 56 129 13,18,29 IRQ12 IRQ12 ACK# ACK#22 IRQ14 55 127 13,18,19,29 IRQ14 IRQ14 PE PE22 R135 IRQ15 54 126 13,18,19,29 IRQ15 IRQ15 SLCT SLCT22 142 12,18,21,29,33 SA[19:0] ERR# ERR#22 SA0 41 10K SA0 SA1 42 145 SA1 RXD1 RX023 SA2 43 146 SA2 TXD1 TX023 SA3 44 148 SA3 RTS1# RTS0#23 SA4 45 149 SA4 CTS1# CTS0#23 SA5 46 150 SA5 DTR1# DTR0#23 R136 SA6 47 147 SA6 DSR1# DSR0#23 SA7 48 152 SA7 DCD1# RLSD0#23 SA8 49 151 1K SA8 RI1# RI0#23 VCC SA9 50 SA9 SA10 51 155 SA10 RXD2 RX123 3F0 I/O decode(DEFAULT) SA11 52 156 1 SA11 TXD2 TX123 SA12 53 158 SA12/CS RTS2# RTS1#23 RP87A SA13 27 159 SA13/HDCS2# CTS2# CTS1#23 SA14 28 160 10K SA14/HDCS3# DTR2# DTR1#23 SA15 29 157 SA15/IDE2_IRQ DSR2# DSR1#23 154 DCD2# RLSD1#23 8 SIO_PU2 26 153 C IDE1_IRQ RI2# RI1#23 C 1 TP080 23 TP84 IDE1_OE# 1 TP081 24 HDCS0# VCC VCC TP85 1 TP082 25 96 TP092 1 TP86 HDCS1# GP10/IRQIN TP51 1 TP083 30 97 TP091 1 Stuff for 93XFR TP3203 IOROP# GP11/IRQIN TP1130 1 TP084 31 98 TP88 IOWOP# GP12/IRRX IRRX26 RP99C 3 6 4.7K 99 GP13/IRTX IRTX26 RP99D 4 5 4.7K R115 34 100 TP073 1 IDE_A0 GP14/RS TP52 RP99A 1 8 4.7K 1 TP078 33 102 TP072 1 0 TP6 IDE_A1 GP15/WS TP50 RP99B 2 7 4.7K 32 103 TP087 1 C411 C394 IDE_A2 GP16/JOYRS TP76 104 TP075 1 GP17/JSWS TP77 470pF 470pF 92 105 24 KBCLK# KCLK GP20/IDE2_OE KBRST#13 91 106 R_GP21 C410 C409 24 KBDAT# KDAT GP21/EEDIN 94 107 TP071 1 24 MSCLK# MSCLK GP22/EDOUT TP80 93 108 TP070 1 24 MSDAT# MSDAT GP23/EECLK TP79 0.1 uF 0.1 uF 109 TP069 1 GP24/EEEN TP78 XD0 111 110 RD0 GP25/8042_P21 A20GATE13 XD1 112 RD1 XD2 113 VCC RD2 XD3 114 RD3 XD4 115 4 RP100D 5 8.2K RD4 XD5 116 RD5 XD6 117 2 RP100B 7 8.2K RD6 XD7 118 3 6 8.2K RD7 21,33 XD[7:0] RP100C 119 13 XOE# ROMCS# D 13 XDIR# 120 D ROMDIR# VSS VSS VSS VSS VSS VSS VSS INTEL CORPORATION KBLOCK#26
FDC37C932FR_1.3 1 8 40 71 95 123 130 GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 R114 ULTRA I/O FOLSOM, CA 95630 Stuff for 93XFR 1k Title I/O CONTROLLER (ULTRA I/O)
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 14 of 41 1 2 3 4 5 6 7 8 A B C D E AGP CONNECTOR
VCC3 VCC3
7,34 SBA[7:0]
7,34 ST[2:0] VCC3 VCC3 J17 +12V VCC R65 330K 4 4 R68 B1 A1 20 AGP_OC# OVRCNT# 12V 4.7K B2 A2 R67 5V SPARE 4.7K B3 A3 5V RESERVED B4 A4 20 USBAGP+ USB+ USB- USBAGP-20 U15E B5 A5 U15F GND GND PIRQ3#A 13 12 PIRQ#A13,16,17,28,34 10 11 PIRQ3#B B6 A6 13,16,17,28 PIRQ#B INTB# INTA# B7 A7 74F07 7 GCLKS CLK RST# PCIRST#6,12,16,17,38 74F07 B8 A8 7,28,34 GREQ# REQ# GNT# GGNT#7,28,34 B9 A9 VCC3.3 VCC3.3 ST0 B10 A10 ST1 ST0 ST1 ST2 B11 A11 ST2 RESERVED B12 A12 7,34 RBF# RBF# PIPE# PIPE#7 B13 A13 GND GND B14 A14 SPARE SPARE SBA0 B15 A15 SBA1 SBA0 SBA1 B16 A16 VCC3.3 VCC3.3 SBA2 B17 A17 SBA3 SBA2 SBA3 B18 A18 7,28,34 SBSTB SB_STB RESERVED B19 A19 GND GND SBA4 B20 A20 SBA5 SBA4 SBA5 SBA6 B21 A21 SBA7 SBA6 SBA7
3 3
GAD31 B26 A26 GAD30 AD31 AD30 GAD29 B27 A27 GAD28 AD29 AD28 B28 A28 VCC3.3 VCC3.3 GAD27 B29 A29 GAD26 AD27 AD26 GAD25 B30 A30 GAD24 AD25 AD24 B31 A31 GND GND B32 A32 7,28,34 ADSTB-B AD_STB1 RESERVED GAD23 B33 A33 GC/BE#3 AD23 GC/BE3# B34 A34 Vddq3.3 Vddq3.3 GAD21 B35 A35 GAD22 AD21 AD22 GAD19 B36 A36 GAD20 AD19 AD20 B37 A37 GND GND GAD17 B38 A38 GAD18 AD17 AD18 GC/BE#2 B39 A39 GAD16 C/BE2# AD16 B40 A40 Vddq3.3 Vddq3.3 B41 A41 7,28,34 GIRDY# IRDY# FRAME# GFRAME#7,28,34 B42 A42 SPARE SPARE B43 A43 GND GND 2 B44 A44 2 SPARE SPARE B45 A45 VCC3.3 VCC3.3 B46 A46 7,28,34 GDEVSEL# DEVSEL# TRDY# GTRDY#7,28,34
B47 A47 GSTOP#7,28,34 VCC3 Vddq3.3 STOP# B48 A48 AGP_PME#13,28 RP71B PERR# PME# 2 7 2.2K GPERR# B49 A49 GND GND 3 6 2.2K GSERR# B50 A50 SERR# PAR GPAR7,28,34 RP71C GC/BE#1 B51 A51 GAD15 C/BE1# AD15 B52 A52 Vddq3.3 Vddq3.3 GAD14 B53 A53 GAD13 AD14 AD13 GAD12 B54 A54 GAD11 AD12 AD11 B55 A55 GND GND GAD10 B56 A56 GAD9 AD10 AD9 GAD8 B57 A57 GC/BE#0 AD8 C/BE0# B58 A58 Vddq3.3 Vddq3.3 B59 A59 7,28,34 ADSTB-A AD_STB0 RESERVED GAD7 B60 A60 GAD6 AD7 AD6 B61 A61 GND GND GAD5 B62 A62 GAD4 AD5 AD4 GAD3 B63 A63 GAD2 AD3 AD2 B64 A64 Vddq3.3 Vddq3.3 GAD1 B65 A65 GAD0 AD1 AD0 1 B66 A66 1 RESERVED RESERVED
AGP_CONN_1.3
INTEL CORPORATION
7,34 GAD[31:0] GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 34 GC/BE#[3:0] FOLSOM, CA 95630
Title ACCELERATED GRAPHICS PORT (AGP) CONNECTOR
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 15 of 41 A B C D E 1 2 3 4 5 6 7 8
PCI CONNECTORS VCC VCC VCC3 VCC3 VCC3 1 AND 2 VCC3 -12V VCC -12V VCC R30 R28 VCC +12V VCC +12V 5.6K 5.6K
A J13 J14 A B1 A1 B1 A1 PTRST# -12V TRST# PTRST#17 -12V TRST# B2 A2 PTCK B2 A2 17 PTCK TCK +12V TCK +12V B3 A3 B3 A3 PTMS GND TMS PTMS17 GND TMS B4 A4 B4 A4 PTDI TDO TDI PTDI17 TDO TDI B5 A5 B5 A5 +5V +5V +5V +5V B6 A6 R27 B6 A6 PIRQ#B +5V INTA# PIRQ#A13,15,17,28,34 +5V INTA# B7 A7 PIRQ#C B7 A7 PIRQ#D 13,15,17,28 PIRQ#B INTB# INTC# PIRQ#C13,17,28 5.6K INTB# INTC# B8 A8 PIRQ#A B8 A8 R29 13,17,28 PIRQ#D INTD# +5V INTD# +5V PRSNT#11 B9 A9 PRSNT#21 B9 A9 PRSNT1# RSV PRSNT1# RSV 5.6K B10 A10 B10 A10 PRSNT#12 RSV +5V PRSNT#22 RSV +5V B11 PRSNT2# RSV A11 B11 PRSNT2# RSV A11 B12 A12 B12 A12 GND GND GND GND B13 A13 B13 A13 GND GND GND GND B14 A14 B14 A14 RSV RSV RSV RSV B15 A15 B15 A15 PCIRST# GND RESET# PCIRST#6,12,15,17,38 GND RESET# B16 A16 B16 A16 5 PCLK1 CLK +5V 5 PCLK2 CLK +5V B17 A17 B17 A17 GND GNT# PGNT#07,28 GND GNT# PGNT#17,28 B18 A18 B18 A18 7,28 PREQ#0 REQ# GND 7,28 PREQ#1 REQ# GND B19 A19 PCI_PME# B19 A19 PCI_PME# +5V PME# +5V PME# PCI_PME#13,28 AD31 B20 A20 AD30 AD31 B20 A20 AD30 AD(31) AD(30) AD(31) AD(30) AD29 B21 A21 AD29 B21 A21 AD(29) +3.3V AD(29) +3.3V B22 A22 AD28 B22 A22 AD28 GND AD(28) GND AD(28) AD27 B23 A23 AD26 AD27 B23 A23 AD26 AD(27) AD(26) AD(27) AD(26) AD25 B24 A24 A_D25 B24 A24 AD(25) GND AD(25) GND B25 A25 AD24 B25 A25 AD24 +3.3V AD(24) +3.3V AD(24) C/BE#3 B26 A26 R_AD26 C/BE#3 B26 A26 R_AD27 C/BE#3) IDSEL C/BE#3) IDSEL B27 A27 B27 A27 AD(23) +3.3V AD(23) +3.3V AD23 B28 A28 AD22 AD23 B28 A28 AD22 GND AD(22) GND AD(22) AD21 B29 A29 AD20 AD21 B29 A29 AD20 AD(21) AD(20) AD(21) AD(20) AD19 B30 A30 AD19 B30 A30 B AD(19) GND AD(19) GND B B31 A31 AD18 B31 A31 AD18 +3.3V AD(18) +3.3V AD(18) AD17 B32 A32 AD16 AD17 B32 A32 AD16 AD(17) AD(16) AD(17) AD(16) C/BE#2 B33 A33 C/BE#2 B33 A33 C/BE#(2) +3.3V C/BE#(2) +3.3V B34 A34 B34 A34 FRAME# GND FRAME# FRAME#7,12,17,28 GND FRAME# B35 A35 IRDY# B35 A35 7,12,17,28 IRDY# IRDY# GND IRDY# GND B36 A36 B36 A36 TRDY# +3.3V TRDY# TRDY#7,12,17,28 +3.3V TRDY# B37 A37 DEVSEL# B37 A37 7,12,17,28 DEVSEL# DEVSEL# GND DEVSEL# GND B38 A38 B38 A38 STOP# GND STOP# STOP#7,12,17,28 GND STOP# B39 A39 PLOCK# B39 A39 7,17,28 PLOCK# LOCK# +3.3V LOCK# +3.3V B40 A40 SDONEP1 PERR# B40 A40 SDONEP2 17,28 PERR# PERR# SDONE PERR# SDONE B41 A41 SBOP1 B41 A41 SBOP2 +3.3V SBO# +3.3V SBO# B42 A42 SERR# B42 A42 7,12,17,28 SERR# SERR# GND SERR# GND B43 A43 B43 A43 PAR +3.3V PAR PAR7,12,17,28 +3.3V PAR C/BE#1 B44 A44 AD15 C/BE#1 B44 A44 AD15 C/BE#(1) AD(15) C/BE#(1) AD(15) B45 A45 B45 A45 AD(14) +3.3V AD(14) +3.3V AD14 B46 A46 AD13 AD14 B46 A46 AD13 GND AD(13) GND AD(13) AD12 B47 A47 AD11 AD12 B47 A47 AD11 AD(12) AD(11) AD(12) AD(11) AD10 B48 A48 AD10 B48 A48 AD(10) GND AD(10) GND B49 A49 AD9 B49 A49 AD9 GND AD(09) GND AD(09) KEY KEY AD8 B52 A52 C/BE#0 AD8 B52 A52 C/BE#0 AD(8) C/BE#(0) AD(8) C/BE#(0) AD7 B53 A53 AD7 B53 A53 AD(7) +3.3V AD(7) +3.3V B54 A54 AD6 B54 A54 AD6 +3.3V AD(06) +3.3V AD(06) AD5 B55 A55 AD4 AD5 B55 A55 AD4 AD(5) AD(04) AD(5) AD(04) AD3 B56 A56 AD3 B56 A56 AD(3) GND AD(3) GND B57 A57 AD2 B57 A57 AD2 GND AD(02) GND AD(02) AD1 B58 A58 AD0 AD1 B58 A58 AD0 AD(1) AD(00) AD(1) AD(00) B59 A59 B59 A59 +5V +5V +5V +5V PU1_REQ64# B60 A60 PU1_ACK64# PU2_REQ64# B60 A60 PU2_ACK64# ACK64# REQ64# ACK64# REQ64# B61 A61 B61 A61 C +5V +5V +5V +5V C B62 A62 B62 A62 +5V +5V +5V +5V
PCI_CONN PCI_CONN
7,12,17 C/BE#[3:0]
7,12,17 AD[31:0]
C77 PRSNT#11 VCC VCC 0.1 uF
C78 RP68B R62 RP48 PRSNT#12 PU1_ACK64# 2 7 AD26 R_AD26 SBOP1 1 8 SDONEP2 2 7 0.1 uF RP68A 2.7K 100 SBOP2 3 6 PU1_REQ64# 1 8 SDONEP1 4 5 C75 R66 PRSNT#21 2.7K RP68C AD27 R_AD27 PU2_ACK64# 5.6K 3 6 0.1 uF 100 RP68D 2.7K D C76 PU2_REQ64# 4 5 D PRSNT#22 2.7K INTEL CORPORATION 0.1 uF GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title PCI CONNECTORS 1 & 2
Size Document Number Rev Custom 3 DEVICE AGP 1.0 Date: 22:16:57 Sheet 16 of 41 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
VCC3 PCI CONNECTOR
VCC3
-12V VCC 3 +12V VCC
J15 B1 A1 A -12V TRST# PTRST#16 A PTCK B2 A2 16 PTCK TCK +12V B3 A3 GND TMS PTMS16 B4 A4 TDO TDI PTDI16 B5 A5 +5V +5V B6 A6 +5V INTA# PIRQ#C13,16,28 B7 A7 13,16,28 PIRQ#D INTB# INTC# PIRQ#A13,15,16,28,34 B8 A8 13,15,16,28 PIRQ#B INTD# +5V PRSNT#31 B9 A9 PRSNT1# RSV B10 A10 PRSNT#32 RSV +5V B11 PRSNT2# RSV A11 B12 A12 GND GND B13 A13 GND GND B14 A14 RSV RSV B15 A15 GND RESET# PCIRST#6,12,15,16,38 B16 A16 5,38 PCLK3 CLK +5V B17 A17 GND GNT# PGNT#27,28 B18 A18 7,28 PREQ#2 REQ# GND B19 A19 PCI_PME# +5V PME# AD31 B20 A20 AD30 AD(31) AD(30) AD29 B21 A21 AD(29) +3.3V B22 A22 AD28 GND AD(28) AD27 B23 A23 AD26 AD(27) AD(26) AD25 B24 A24 AD(25) GND B25 A25 AD24 +3.3V AD(24) C/BE#3 B26 A26 R_AD29 C/BE#3) IDSEL B27 A27 AD(23) +3.3V AD23 B28 A28 AD22 GND AD(22) AD21 B29 A29 AD20 AD(21) AD(20) AD19 B30 A30 AD(19) GND B31 A31 AD18 +3.3V AD(18) AD17 B32 A32 AD16 B AD(17) AD(16) B C/BE#2 B33 A33 C/BE#(2) +3.3V B34 A34 GND FRAME# FRAME#7,12,16,28 B35 A35 7,12,16,28 IRDY# IRDY# GND B36 A36 +3.3V TRDY# TRDY#7,12,16,28 B37 A37 7,12,16,28 DEVSEL# DEVSEL# GND B38 A38 GND STOP# STOP#7,12,16,28 B39 A39 7,16,28 PLOCK# LOCK# +3.3V B40 A40 SDONEP3 16,28 PERR# PERR# SDONE B41 A41 SBOP3 +3.3V SBO# B42 A42 7,12,16,28 SERR# SERR# GND B43 A43 +3.3V PAR PAR7,12,16,28 C/BE#1 B44 A44 AD15 C/BE#(1) AD(15) B45 A45 AD(14) +3.3V AD14 B46 A46 AD13 GND AD(13) AD12 B47 A47 AD11 AD(12) AD(11) AD10 B48 A48 AD(10) GND B49 A49 AD9 GND AD(09) KEY AD8 B52 A52 C/BE#0 AD(8) C/BE#(0) AD7 B53 A53 AD(7) +3.3V B54 A54 AD6 +3.3V AD(06) AD5 B55 A55 AD4 AD(5) AD(04) AD3 B56 A56 AD(3) GND B57 A57 AD2 GND AD(02) AD1 B58 A58 AD0 AD(1) AD(00) B59 A59 +5V +5V PU3_REQ64# B60 A60 PU3_ACK64# ACK64# REQ64# B61 A61 +5V +5V B62 A62 +5V +5V C C PCI_CONN
7,12,16 C/BE#[3:0]
7,12,16 AD[31:0]
C79 PRSNT#31 VCC 0.1 uF VCC C80 RP69B PRSNT#32 PU3_ACK64# 2 7 R63 RP60 AD29 R_AD29 SDONEP3 1 8 0.1 uF RP69A 2.7K SBOP3 2 7 PU3_REQ64# 1 8 100 3 6 4 5 2.7K
5.6K
D D
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title PCI CONNECTORS 3 & 4
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 17 of 41 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ISA SLOTS A A
VCC J12
B1 GND IOCHK# A1 IOCHK#12,29 26 BRSTDRV B2 A2 SD712,14,29 -5V BRSTDRV SD7 B3 VCC SD6 A3 SD612,14,29 13,14,29 IRQ9 B4 A4 SD512,14,29 -12V IRQ9 SD5 B5 -5V SD4 A5 SD412,14,29 13,14,29 DRQ2 B6 A6 SD312,14,29 +12V DREQ2 SD3 B7 -12V SD2 A7 SD212,14,29 12,29 ZEROWS# B8 ZEROWS# SD1 A8 SD112,14,29 B9 +12V SD0 A9 SD012,14,29 B10 GND IOCHRDY A10 IOCHRDY12,14,29 12,29 SMEMW# B11 SMEMW# AEN A11 AEN12,14 12,29 SMEMR# B12 SMEMR# SA19 A12 SA1912,21,29 12,14,29,33 IOW# B13 IOW# SA18 A13 SA1812,21,29 12,14,29,33 IOR# B14 IOR# SA17 A14 SA1712,21,29 13,14 DACK#3 B15 DACK3# SA16 A15 SA1612,21,29 13,14,29 DRQ3 B16 DREQ3# SA15 A16 SA1512,14,21,29 B17 A17 B 13,14 DACK#1 DACK1# SA14 SA1412,14,21,29 B 13,14,29 DRQ1 B18 DREQ1 SA13 A18 SA1312,14,21,29 12,29 REFRESH# B19 REFRESH# SA12 A19 SA1212,14,21,29 12,33,38 SYSCLK B20 SYSCLK SA11 A20 SA1112,14,21,29 13,14,29 IRQ7 B21 IRQ7 SA10 A21 SA1012,14,21,29 13,14,29 IRQ6 B22 IRQ6 SA9 A22 SA912,14,21,29 13,14,29 IRQ5 B23 IRQ5 SA8 A23 SA812,14,21,29 13,14,29 IRQ4 B24 IRQ4 SA7 A24 SA712,14,21,29 13,14,29 IRQ3 B25 IRQ3 SA6 A25 SA612,14,21,29 13,14 DACK#2 B26 DACK2# SA5 A26 SA512,14,21,29 13,14 TC B27 TC SA4 A27 SA412,14,21,29 12,29 BALE B28 BALE SA3 A28 SA312,14,21,29 B29 VCC SA2 A29 SA212,14,21,29,33 5 OSC1 B30 OSC SA1 A30 SA112,14,21,29,33 B31 GND SA0 A31 SA012,14,21,29,33
12,29 MEMCS16# D1 MEMCS16# SBHE# C1 SBHE#12,29 12,29 IOCS16# D2 IOCS16# LA23 C2 LA2312,29 13,14,29 IRQ10 D3 IRQ10 LA22 C3 LA2212,29 13,14,29 IRQ11 D4 IRQ11 LA21 C4 LA2112,29 13,14,29 IRQ12 D5 IRQ12 LA20 C5 LA2012,29 13,14,19,29 IRQ15 D6 IRQ15 LA19 C6 LA1912,29 13,14,19,29 IRQ14 D7 IRQ14 LA18 C7 LA1812,29 13,14 DACK#0 D8 DACK0# LA17 C8 LA1712,29 C 13,14,29 DRQ0 D9 DREQ0 MEMR# C9 MEMR#12,21,29 C 13 DACK#5 D10 DACK5# MEMW# C10 MEMW#12,21,29 13,29 DRQ5 D11 DREQ5 SD8 C11 SD812,29 13 DACK#6 D12 DACK6# SD9 C12 SD912,29 13,29 DRQ6 D13 DREQ6 SD10 C13 SD1012,29 13 DACK#7 D14 DACK7# SD11 C14 SD1112,29 13,29 DRQ7 D15 DREQ7 SD12 C15 SD1212,29 D16 VCC SD13 C16 SD1312,29 29 RMASTER# D17 MASTER# SD14 C17 SD1412,29 D18 GND SD15 C18 SD1512,29
CON_ISA16C ISA 0
INTEL CORPORATION D D GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title ISA SLOTS
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 18 of 41 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A A IDE CONNECTORS
12 SDD[15:0]
12 PDD[15:0]
J35 J28 R191 R149 R_BRSTDRV#1 BRSTDRV# R_BRSTDRV#2 26 BRSTDRV# 1 2 1 2 RP106 33 RP88 33 DD7#1 3 4 DD8#1 RP107D 4 5 33 PDD8 SDD7#2 3 4 SDD8#2 PDD7 1 8 SDD8 1 8 SDD8#2 PDD9 2 7 DD9#1 DD6#1 5 6 DD9#1 SDD7 2 7 SDD6#25 6 SDD9#2 PDD6 3 6 RP105 SDD6 3 6 RP8933 PDD10 4 5 DD10#1 DD5#1 7 8 DD10#1 DD5#1 8 1 PDD5 SDD9 4 5 SDD9#2 SDD5#2 7 8 SDD10#2 SDD5#2 8 1 SDD5 7 2 PDD11 7 2 SDD10 RP104 RP90 DD4#1 9 10 DD11#1 DD4#1 6 3 PDD4 SDD4#2 9 10 SDD11#2 SDD4#2 6 3 SDD4 PDD3 1 33 8 5 4 PDD12 SDD3 1 33 8 5 4 SDD11 PDD13 DD13#1 DD3#1 DD12#1 SDD12 SDD12#2 SDD3#2 SDD12#2 B 2 7 11 12 2 7 11 12 B PDD2 3 6 33 SDD2 3 6 PDD14 4 5 DD14#1 DD2#1 13 14 DD13#1 SDD13 4 5 SDD13#2 SDD2#213 14 SDD13#2 VCC RP103 RP91 DD1#1 15 16 DD14#1 DD1#1 8 1 PDD1 VCC R148 SDD1#215 16 SDD14#2 SDD1#2 8 1 SDD1 33 R181 7 2 PDD15 33 7 2 SDD14 DD0#1 PDD0 10K R163 10K DD0#1 17 18 DD15#1 6 3 SDD0#2 17 18 SDD15#2 SDD0#2 6 3 SDD0 R_PDDREQ# SDD15 1K 5 4 PDREQ12 R139 5 4 19 20 1K 19 20 RP102 33 RP98 33 12 PDIOW# 1 8 R_PDDREQ# 21 22 R164 12 SDREQ 1 8 R_SDDREQ# 21 22 12 PDIOR# 2 7 5.6K 12 SDIOW# 2 7 R_SDIOW# RPDACK# R_PDIOW# R_SDIOR# 12 PDDACK# 3 6 23 24 12 SDIOR# 3 6 23 24 PDA1 4 5 R_PDA1 12 SDDACK# 4 5 RSDACK# R_PDIOR# 25 26 25 26 R162 R190 R140 R147 33 PRI_PD1 33 SEC_PD1 12 PIORDY 27 28 12 SIORDY 27 28 47 47 470 470 RP96 RPDACK# 29 30 RP97 RSDACK# 29 30 PDA2 1 8 R_PDA2 SDA1 1 8 R_SDA1 PDA0 2 7 R_PDA0 31 32 SDA0 2 7 R_SDA0 31 32 R_PCS3# 12 PCS3# 3 6 3 6 12 PCS1# 4 5 R_PCS1# R_PDA1 33 34 4 5 33 34 SDA2 VCC 33 35 36 R_PDA2 33 35 36 R_SDA2 RP107A 8 1 33 SDA2
R_PCS3# 33 R_SCS1# R_SCS3# RP107C 33 37 38 12 SCS1# 2 7 37 38 6 3 SCS3#12 R244 RP107B 26 IDEACTP# 10K 39 40 26 IDEACTS# 39 40
12 PDA[2:0] 12 SDA[2:0] C C PRIMARY SECONDARY R137 IDE CONN. R129 13,14,18,29 IRQ14 13,14,18,29 IRQ15 IDE CONN. 47 47 R165 R231 5.6K VCC 10K
D D
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title PCI IDE CONNECTORS
Size Document Number Rev Custom 3 DEVICE AGP 1.0 Date: 22:16:57 Sheet 19 of 41 1 2 3 4 5 6 7 8 A B C D E
USB CONNECTORS F3 VCC USB_PWR0 1.5-2.0A R15 4 470K 4
13 OC#0
R12 C41 J5A 560K BLM31A700S 0.001uF 1 L5 2 USBV0 1 VCC 9 UGND0 USBD0- UGND + 2 DATA- C31 10 UGND C13 USBD0+ 3 68 uF DATA+ 0.1 uF (TANTALUM) USBG0 4 GND
2 USB_Conn. Do Not Stuff BLM31A700S F1 C3 L6 VCC USB_PWR1 1 2 .1uF L3 BLM31A700S 1.5-2.0A R14 470K + 3 C32 3
C14 1 R11 J5B 13 OC#1 68 uF 0.1 uF 0 (TANTALUM) USBV1 R13 5 VCC C30 11 UGND 560K USBD1- 6 0.001uF DATA- 12 UGND R10 USBD1+ 7 DATA+
0 2 USBG1 8 GND DO NOT STUFF L1 15 AGP_OC# 2 USB_Conn. BLM31A700S R121 13 USBP0- C12 27 L4 R123 .1uF 13 USBP0+ BLM31A700S 1 27 1 R122 R109 0 13 USBP1- 27 Do Not Stuff R124 R113 0 2 13 USBP1+ 2 27
**NOTE: R106 R110 R107 R111 C247 C249 C248 C250 PLACE R201-204 AND 15K 15K 15K 15K R_USBD1+ R108 0 C158-161 AS CLOSE USBAGP+15 47pF 47pF 47pF 47pF AS POSSIBLE TO THE DO NOT PIIX4. STUFF
R_USBD1- R112 0 USBAGP-15 NOTE: USE PIIX4 APPLICATION NOTE FOR LAYOUT GUIDELINES INTEL CORPORATION
1 GRAPHICS COMPONENTS DIVISION 1 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title USB HEADER
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 20 of 41 A B C D E 1 2 3 4 5 6 7 8
SYSTEM ROM STUFFING OPTION
VCC
A J27 A J40 MODE SA19 2 1 SA16 4 3 SA18 NORMAL SA15 6 5 SA17 2-3 8 7 U30F SA12 SA14 RECOVERY SA7 10 9 SA13 1-2 12 11 13 12 B_SA17 SA6 SA8 14 13 J40 SA5 SA9 16 15 1 SA4 SA11 18 17 74HCT14 2 J_SA17 SA3 MEMW# 20 19 SA17 3 SA2 SA10 SA1 22 21 BIOSCS# SA0 24 23 XD7 FLASH SOCKET XD0 26 25 XD6 XD1 28 27 XD5 12,14,18,29,33 SA[19:0] XD[7:0]14,33 30 29 U26 XD2 XD4 32 31 SA17 40 12 XD3 A17 DU 34 33 SA16 1 A16 SA15 2 A15 Emulator Header SA14 3 A14 SA13 4 A13 MODE J41 J42 SA12 5 A12 SA11 6 Prog Boot Block A11 1-2 2-3 SA10 36 25 XD0 A10 DQ0 +12V SA9 7 26 XD1 * Header provided for BIOS emulation PROG DEV A9 DQ1 (incl. boot block) 1-2 1-2 SA8 8 27 XD2 A8 DQ2 SA7 14 28 XD3 A7 DQ3 PnP 2-3 1-2 SA6 15 32 XD4 A6 DQ4 SA5 16 33 XD5 B Write Protect A5 DQ5 B 2-3 2-3 SA4 17 34 XD6 A4 DQ6 J41 SA3 18 35 XD7 A3 DQ7 1 SA2 19 A2 2 SA1 20 13 +12V A1 NC 3 SA0 21 29 3,26 PWRGOOD A0 NC 37 NC 9 38 J42 12,18,29 MEMW# WE# NC 24 1 12,18,29 MEMR# OE# 22 11 FL_VPP 2 CE# VPP FL2MPU 10 3 FL1MPU RP# E28F002BC-T TSOP SOCKET
C396 0.1 uF C395 0.1 uF
13 BIOSCS#
C C
D D
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title SYSTEM ROM
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 15:23:35 Sheet 21 of 41 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 CP9A 180pF 8
A A 4 CP3D 180pF 3 5 CP3C 180pF 6 VCC 2 CP3B 180pF 1
D1 7 IN4148 CP3A 180pF 8
PAR5VOLTS 4 RP6 CP5D PARALLEL 8 1 180pF
14 PDR[7:0] 3 7 2 5 D-SHELL 6 3 CP5C 5 4 180pF CONNECTOR
6 J7 STB# 1 1 1K PD0 2 2 PD1 3 2 3 PD2 4 B 4 B CP5B PD3 5 5 180pF PD4 6 1 6 7 PD5 7 RP10 7 CP5A PD6 8 8 8 1 180pF PD7 9 9 7 2 8 ACK# 10 10 6 3 BUSY 11 11 5 4 PE 12 12 SLCT 13 4 13 RP84 AFD# 14 14 PDR1 8 1 1K CP6D ERR# 15 15 PDR0 7 2 180pF INIT# 16 3 16 PDR2 6 3 5 SLIN# 17 17 5 4 CP6C 18 PDR3 18 180pF 19 19 6 20 20 33 21 21 22 22 RP11 23 2 23 1 8 24 24 2 7 CP6B 25 25 3 6 180pF 1 4 5 7 CP6A RP83 1K 180pF
PDR4 5 4 8 PDR5 6 3 PDR7 7 2 PDR6 8 1 4
33 CP4D RP9 180pF 3 C 5 4 5 C 6 3 CP4C 7 2 180pF
8 1 6
RP85 1K 5 4 14 STB#R 2 14 AFD#R 6 3 14 SLIN#R 7 2 CP4B 180pF 14 INIT#R 8 1 7 33 RP8 1 8 2 7 3 6 1 4 5 CP4A 180pF
1K 8
14 ACK# 14 BUSY 14 PE 14 SLCT 14 ERR#
D D
INTEL CORPORATION GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title PARALLEL PORT
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 22 of 41 1 2 3 4 5 6 7 8 A B C D E
+12V VCC
U6 1 20 J4 VCC+ VCC SP_DCD0 2 19 RLSD0#14 SP_DCD0 1 RA RY 1 C29 SP_RXD0 3 18 SP_RXD0 2 RA RY RX014 2 .1uF SP_DSR0 4 17 SP_TXD0 3 4 RA RY DSR0#14 3 4 SP_DTR0 5 16 SP_DTR0 4 DY DA DTR0#14 4 COM 0 SP_TXD0 6 15 5 DY DA TX014 5 SP_CTS0 7 14 SP_DSR0 6 RA RY CTS0#14 6 SP_RTS0 8 13 SP_RTS0 7 D-SHELL DY DA RTS0#14 7 SP_RI0 9 12 RI0# SP_CTS0 8 RA RY RI0#14 8 10 11 SP_RI0 9 CONNECTOR VCC- GND 9 GD75232SOP 1 3 1 3 CP7A CP8C CP8A CP7C 100pF 100pF 100pF
-12V 100pF 8 6 8 6 4 2 4 2 CP7D CP7B CP8D CP8B 100pF 100pF 100pF 100pF 5 7 5 7
3 3
+12V VCC COM 1 U3 1 20 HEADER VCC+ VCC SP_DCD1 2 19 J1 RA RY RLSD1#14 C7 SP_RXD1 3 18 SP_DCD1 1 2 SP_DSR1 RA RY RX114 1 2 .1uF SP_DSR1 4 17 SP_RXD1 3 4 SP_RTS1 RA RY DSR1#14 3 4 SP_DTR1 5 16 SP_TXD1 5 6 SP_CTS1 DY DA DTR1#14 5 6 SP_TXD1 6 15 SP_DTR1 7 8 SP_RI1 DY DA TX114 7 8 SP_CTS1 7 14 9 10 RA RY CTS1#14 910 SP_RTS1 8 13 DY DA RTS1#14 SP_RI1 9 12 RI1# RA RY RI1#14 10 11 VCC- GND GD75232SOP 4 3 2 1
CP2D CP2C CP2B CP2A 1 2 3 4 -12V 100pF 100pF 100pF 100pF CP1A CP1B CP1C CP1D
5 6 7 8 100pF 100pF 100pF 100pF 8 7 6 5
2 2
VCC RP111 1 8 2 7 FLOPPY 3 6 INTERFACE 4 5 HEADER
1K R247 1.0K GPI2113 ** Connected to GPI21 of the J37 PIIX4 for BIOS detection of a 14 DSKCHG# 34 33 floppy drive. 14 SIDE1# 32 31 14 RDATA# 30 29 14 WPT# 28 27 14 TRK0# 26 25 14 WGATE# 24 23 14 WDATA# 22 21 14 STEP# 20 19 1 14 DIR# 18 17 1 14 MOTEB# 16 15 INTEL CORPORATION 14 DRVSA# 14 13 14 DRVSB# 12 11 GRAPHICS COMPONENTS DIVISION 14 MOTEA# 10 9 1900 PRAIRIE CITY RD. FM5-79 14 INDEX# 8 7 FOLSOM, CA 95630 14 DRATE0 6 5 1 TP094 TP92 4 3 Title 14 REDWC# 2 1 SERIAL AND FLOPPY
Size Document Number Rev Custom 3 Device AGP 1.0
Date: 15:23:35 Sheet 23 of 41 A B C D E 1 2 3 4 5 6 7 8
VCC
A A
F2 1.25A 2 L10
FBHS04B 1
L12 J6 2 1 KBDAT_FB# 1 14 KBDAT# 1 1 TP095 2 TP096 2 KBSIGND 3 FBHS01K 3 KEYBOARD KB5V_FB 4 B 4 CONNECTOR B KBCLK_FB# 5 L9 5 1 TP096 6 TP095 6 14 KBCLK# 2 1 7 7 8 17 FBHS01K 8 17 9 16 9 16 MOUSE 10 15 10 15 CONNECTOR 11 14 11 14 12 13 L11 12 13 14 MSDAT# 2 1 MSDAT_FB# TP097 TP094 1 FBHS01K MSCLK_FB# L8 TP098 TP093 1 14 MSCLK# 2 1
FBHS01K KBSHGND 1 C44 C35 C43 C34 L2 470pf 470pF 470pF 470pF C33 470pF FBHS01K 2 2 C L7 C
FBHS04B 1
D D
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title KEYBOARD/MOUSE INTERFACE
Size Document Number Rev Custom 3 DEVICE AGP 1.0 Date: 22:16:57 Sheet 24 of 41 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
4,33 VID[4:0]
VCCCORE +12V +12V
VCC VCC J8 VCC3 * ADDITIONAL STRAP CONFIGURATIONS MAY BE A1 B1 A 5Vin 5Vin NECESSARY TO SUPPORT THE DS1P. A A2 B2 5Vin 5Vin RP19B A3 B3 2 7 Frequency Multiplier: LINT[1] LINT[0] IGNNE# A20M# 5Vin 5Vin 10K A4 B4 (System Bus to JP14 JP13 JP12 JP11 12Vin 12VIN ROE1 3 RP19C 6 Processor A5 B5 10K 12Vin RES. Core) 3 L L H L A6 B6 ROE1 ISHARE OUTEN 4 L L L H VID0 A7 B7 VID1 VID0 VID1 VRMPGD26 5 L L H H VID2 VID3 A8 B8 5/2 VID2 VID3 VCCCORE VCC3 L H L L VID4 A9 B9 VID4 PWRGD 7/2 L H H L
A10 B10 9/2 VCCcore Vss R104 L H L H A11 B11 Vss VCCcore 4.7K A12 B12 VCCcore Vss A13 B13 Vss VCCcore J26 A14 B14 1 VCCcore Vss B KL_CFG1 2 U15A B A15 B15 3 Vss VCCcore A20_PB 1 1 2 A20M#3,28 A16 B16 KL_CFG2 2 J23 VCCcore Vss 3 A17 B17 1 Vss VCCcore 74F07 KL_CFG3 2 J24 A18 B18 3 VCCcore Vss U15B 1 A19 B19 KL_CFG4 2 J25 IGNE_PB 3 4 Vss VCCcore IGNNE#3,28 3 A20 B20 VCCcore Vss 74F07
VRM8_2.05 U17 U15D 2 18 LINT0_PB 9 8 1A1 1Y1 LINT03,28 **NOTE** This is the new VRM8_2.05 which has two pin 4 16 1A2 1Y2 changes, pin A5 is now 12Vin and pin B3 is now 5Vin. 6 14 1A3 1Y3 8 12 74F07 1A4 1Y4 11 9 13,28 PX4_INTR 2A1 2Y1 13 7 U15C 13,28 PX4_IGNNE# 2A2 2Y2 15 5 13,28 PX4_A20M# 2A3 2Y3 17 3 LINT1_PB 5 6 13,28 PX4_NMI 2A4 2Y4 LINT13,28 1 6 CRESET# 1G CRESET_BF# 19 74F07 2G C 5VSB C
VCC3 74LVC3244 U31E 11 10 R215
680 74F06
**NOTE** VOLTAGE VTT REGULATORREGULATOR SHOULD VCC3 BE LOCATED NEAR VTT VCC3 THE 440BX U20 +12V U37 2.5V REGULATOR 2 VCC2.5 VOUT V25_G1 1 8 S/D IPOS 4 2 3 VIN + + C221 C208 C197 2 7 C229 C198 VIN INEG Q6 1 100uF 100uF 1 uF 1 uF C378 3 6 V25_R1 R241 V2G 1 GND 1 uF 1.0 uF GND GATE 10 MMFT3055EL CERAMIC 4 5 V25_R2 + LT1585A-1.5 FB COMP X7R C414 3 1.0 uF C220 R95 R246 100uF 10V LT1575_0.1 (Solid Tantalum) 100 100 + + R240 D R96 C230 C379 V25_R3 C376 C365 D 1.0 uF 1.0 uF 0 V2R INTEL CORPORATION 1.30K 22 uF 10V 1 uF CERAMIC 1% X7R R220 GRAPHICS COMPONENTS DIVISION 1.21K C412 C413 1900 PRAIRIE CITY RD. FM5-79 Do Not Stuff 1% 2200pF 0.01 uF FOLSOM, CA 95630 Title DC-DC CONVERTER CONNECTORS
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 25 of 41 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
BRSTDRV#19 +12V +12V
U30E U30A
12,14 RSTDRV 11 10 1 2 BRSTDRV18 5VSB R23 R38
330 1.5K 74HCT14 74HCT14 U31A
1 2 R242 Q2 2 1 VCC P-FET A A 74F06 SI9933DYS 68 5VSB R243 R217 ON-BOARD SPK2 2 1 BUZZ2 DUAL-COLOR LED D2 68 U31F 2 R225
330 1 13 12 3 2 1 SPK1 Q8 13 FAN_LED 2 13 SPKR MMBT3904L C402 0.1uF C372 GREEN 2 D7 1 2.2K
74F06 VCC 2 100pF LED2BHRB10RG 5VSB R39 R230 U34D 14 1.5K 330 1 RED 9 8 +12V J22 C391 1 CPU FAN VCC 7 100pF HEADER SENSE 74F07 3 +12V 2 R84 1 GND VCC VCC C210 640456-3 4.7K OPTIONAL 0.1 uF VCC C200 ATX CPUFAN133 R25 5VSB R233 470 pF J39 CONNECTOR 1 4.7K 14 U34C USE AMP P/N 640456-3 HEADER 1 IRRX14 J10 4.7K 2 2 IRTX14 OR EQUIVALENT. 3 3 4 1394M FanM 1 5 6 PSFAN233 INFRAFED 4 4 IRR4_MODE14 5 1394V FanC 2 5 6 RES Sense 3 7 KEY 5 VCC3 74F07 3VSB 6 6 Molex 39-30-1060 7 C72 ACPI required POWER BUTTON to B KEY 7 C74 B 8 8 be located on the front of the chasis. POWER 9 470 pF 3VSB 14 9 1 5VSB .1uF SW2 U35D ON/OFF 10 10 11 R245 R40 9 8 KEY11 0 PWRBT#13 12 12 VCC 14 13 220 U34F SW PUSHBUTTON 7 74LVC14 KEY13 R234 HD LED 14 14 12 13 IDEACTP#19 15 2 510K C406 15 74F07 KEY16 16 7 0.1 uF 17 17 5VSB KEY18 18 POWER-ON13 POWER 19 19 LED 20 14 KEY20 U34E VCC3 21 21 KBLOCK#14 KEYLOCK 22 22 10 11 IDEACTS#19 23 23 74F07 R232 VCC2.5 KEY24 24 7 SPEAKER 25 C404 240 5VSB 25 BUZZ2 C393 C407 5VSB ON-BOARD 26 26 R46 470 pF 470 pF 470 pF R203 U31D 330 26_PIN_JMP 5 DBRESET# 5VSB 10K 9 8 PWRGOOD3,21 BZ1 1 1 U32A 74F06 2 2 VCC 14 1 3VSB SPEAKER 25 VRMPGD 2 12 PG4 PG5 13 7 14 U35A R187 74HC10 13 B_SUSC C JP_RST C 1 2 PWROK7,13 C69 470pF 100 + 7 +12V 74LVC14 C343 C344 VCC PG3 RESET J46 SW1 VCC3 ATX POWER 4.7NF 22uF CONNECTOR SWITCH VCC HEADER R216 J9 10K 13 WOLLID 5VSB 1 2 U30C U30D 5VSB 3 4 5VSB Wake-On-LAN 5 6 PG1 PG2 7 8 5 6 9 8 PS_POK13 Header + 14 9 10 U34B J45 11 12 C342 74HCT14 74HCT14 4 3 R224 13 14 13,28 LID 3 3VSB 22uF 15 16 74F07 2 17 18 7 1 56.2 19 20 3VSB 3VSB R251 AMP 173981-3 1K (or Foxconn HF58030) 14 U35B 14 U35C -5V 3 BRSM1 + 3 4 5 6 RSMRST#13 D5 -12V C399 C400 7 7 MMBZ5226BL 0.01 uF 22uF R204 74LVC14 74LVC14 SOT-23 R_RSMRST# 1 D 22K D C374 1.0 uF Resume Reset circuitry INTEL CORPORATION using a 22 msec delay GRAPHICS COMPONENTS DIVISION and Schmitt trigger 1900 PRAIRIE CITY RD. FM5-79 logic. FOLSOM, CA 95630 Title Power Connector & Misc
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 26 of 41 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 GTL+ TERMINATION RESISTORS *NOTE: May be removed if route lengths can be restricted to 1.5" MIN to 4.0" MAX.
VTT VTT VTT RP55 RP41 RP39 HA#29 8 1 HD#18 8 1 HD#34 8 1 HD#1 7 2 HD#21 7 2 HD#43 7 2 HD#0 6 3 HD#23 6 3 HD#40 6 3 A HD#3 5 4 HD#19 5 4 HD#36 5 4 A VTT VTT VTT 56 ohm RP42 56 OHM RP53 56 ohm RP28 HD#5 8 1 8 1 HD#39 8 1 HD#2 7 2 HD#22 7 2 HD#44 7 2 HD#4 6 3 6 3 HD#45 6 3 HD#8 5 4 HD#24 5 4 HD#42 5 4 VTT RP54 VTT 56 ohm RP29 VTT 56 OHM RP51 56 ohm HD#12 8 1 HD#25 8 1 HD#47 8 1 HD#10 7 2 HD#27 7 2 HD#41 7 2 HD#15 6 3 HD#30 6 3 HD#51 6 3 HD#11 5 4 HD#26 5 4 HD#49 5 4 VTT VTT VTT 56 ohm RP31 56 OHM RP40 56 ohm RP37 HD#6 8 1 HD#29 8 1 HD#46 8 1 HD#9 7 2 HD#31 7 2 HD#52 7 2 HD#14 6 3 HD#28 6 3 HD#60 6 3 HD#7 5 4 HD#35 5 4 HD#53 5 4 VTT RP30 VTT 56 ohm RP52 VTT 56 OHM RP36 56 ohm HD#13 8 1 HD#33 1 8 HD#50 8 1 HD#17 7 2 HD#32 2 7 HD#56 7 2 HD#20 6 3 HD#38 3 6 HD#55 6 3 HD#16 5 4 HD#37 4 5 3,5 PRDY#0 5 4 56 OHM 56 ohm 56 ohm 3,8 HD#[63:0]
4,6 HA#[31:3]
B B VTT RP38 HD#48 8 1 HD#59 7 2 HD#57 6 3 HD#54 5 4 VTT 56 ohm RP50 HD#63 8 1 HD#61 7 2 HD#58 6 3 HD#62 5 4 VTT RP57 56 ohm HA#3 8 1 HA#5 7 2 HA#7 6 3 HA#10 5 4 VTT 56 ohm RP65 HA#6 1 8 HA#9 2 7 HA#4 3 6 4,6 BNR# 4 5 VTT RP45 56 ohm HA#14 8 1 HA#8 7 2 4,6 BREQ0# 6 3 HA#12 5 4 C C 56 ohm VTT RP72 VTT 1 8 RP63 4,6 DEFER# 2 7 HA#16 1 8 4,6 DRDY# 3 6 4,5,6 HRESET# 2 7 4 5 VTT HA#11 3 6 HA#13 4 5 56 ohm RP64 VTT RP44 HREQ#4 4,6 HTRDY# 8 1 56 ohm HREQ#2 4,6 BPRI# 7 2 HA#18 8 1 HREQ#1 6 3 HA#17 7 2 HREQ#0 5 4 HA#15 6 3 4,6 HREQ#[4:0] VTT HA#19 5 4 RP66 56 ohm VTT RP32 4,6 HIT# 8 1 56 ohm 4,6 HITM# 7 2 HA#25 8 1 RS#0 6 3 HA#21 7 2 HREQ#3 5 4 HA#23 6 3 HA#20 5 4 RP73 VTT 56 ohm VTT RS#2 1 8 56 ohm RP56 4,6 DBSY# 2 7 HA#27 8 1 RS#1 3 6 4,6 HLOCK# 7 2 4,6 ADS# 4 5 HA#22 6 3 HA#28 5 4 56 ohm 4,6 RS#[2:0] 56 ohm
RP43 VTT D HA#31 8 1 D HA#24 7 2 HA#26 6 3 INTEL CORPORATION NOTE : VTT = TERMINATION HA#30 5 4 VOLTAGE 56 ohm GRAPHICS COMPONENTS DIVISION HA#29 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title GTL TERMINATION
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 27 of 41 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 VCC VCC RP49 RP59 7,12,16,17 STOP# 1 8 1 8 7,16,17 PLOCK# 2 7 7,12,16,17 SERR# 2 7 16,17 PERR# 3 6 7,12,16,17 PAR 3 6 4 5 4 5
2.7K 2.7K VCC3 VCC RP34 R75 7,12,16,17 FRAME# 1 8 7 PREQ#4 2 7 7,12,16,17 IRDY# 2.7K 7,12,16,17 TRDY# 3 6 7,12,16,17 DEVSEL# 4 5 VCC VCC RP24 A 2.7K A RP15 1 8 13,15,16,17 PIRQ#B 8 1 7,17 PREQ#2 2 7 13,16,17 PIRQ#C 7 2 7,16 PREQ#1 3 6 13,15,16,17,34 PIRQ#A 6 3 7,16 PREQ#0 4 5 13,16,17 PIRQ#D 5 4 2.7K 2.7K
VCC2.5 VCC3 R50 PICD0 RP23 PCI BUS 150 7,16 PGNT#1 8 1 7,17 PGNT#2 7 2 R48 6 3 PICD1 5 4 7,16 PGNT#0 3 PICD[1:0] 150
R41 8.2K 3 FLUSH# 510 R43 3,13 STPCLK# 430 R42 1 3,13 PX4_SMI# 430
VCC3 B R45 B R119 13,33 PGCS#1 3,13 FERR# 8.2K RP80 RP35 220 RP17 13 REQ#A 8 1 8 1 7 2 7 2 8 1
13 REQ#B SLOT 3,25 LINT1 7,12 PHLD# 13 REQ#C 6 3 6 3 7 2 5 4 7,12 PHLDA# 5 4 6 3 13,33 EXTSMI# 3,25 IGNNE# 3,13 HINIT# 5 4 8.2K 10K RP109 330 1 8 3,13 THERM# RP18 RP16 13 PX4_CFG1 2 7 13 PX4_CFG2 3 6 8 1 1 8 4 5 7 2 2 7 THERMTRIP#3 3,25 A20M# 6 3 3 6 10K 3,25 LINT0 5 4 4 5 RP95 1 8 330 220 13 SMBALERT# 2 7 3 6 4 5 13 BATLOW# VCC3 VCC3 10K RP70 R160 13,16 PCI_PME# 7,15,34 GFRAME# 1 8 8.2K 7,15,34 GIRDY# 2 7 R161 13,26 LID 7,15,34 GDEVSEL# 3 6 8.2K 7,15,34 GTRDY# 4 5 R168 13,15 AGP_PME# 8.2K 8.2K C R159 C 13 TEST# 8.2K RP27 R167 3,6,9,10,11,13,33 SMBDATA 7,15,34 GGNT# 1 8 2.7K 7,15,34 GREQ# 2 7 R169 3,6,9,10,11,13,33 SMBCLK 3 6 IX4 2.7K 7 PGNT#4 4 5 8.2K RP101 RP62 PI 13,25 PX4_IGNNE# 1 8 1 8 13,25 PX4_NMI 2 7 7,15,34 ADSTB-B 2 7 13,25 PX4_INTR 3 6 AGP 3 6 13,25 PX4_A20M# 4 5 4 5 2.7K 10K RP71A 13 GPI[20:13] RP81 7,15,34 GSTOP# 1 8 2.2K GPI18 8 1 GPI19 7 2 GPI20 6 3 GPI15 5 4
2.7K RP86 7,15,34 ADSTB-A R93 GPI14 8 1 8.2K GPI16 7 2 7,15,34 SBSTB R71 GPI17 6 3 8.2K GPI13 R90 5 4 7,15,34 GPAR 100K 2.7K RP110 13 GPI7 1 8 D 2 7 D 3 6 4 5 INTEL CORPORATION
2.7K GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title Pullups; AGP/PCI/PIIX4
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 28 of 41 1 2 3 4 5 6 7 8 A B C D E
UNUSED GATES
3VSB
R157 10K RP67 12,18 SBHE# 1 8 13,14,18 IRQ10 2 7 LA22 3 6 5VSB 5VSB LA23 4 5 14 U32B U30B 4 TP148 TP4402 4 10K 3 12,18 REFRESH# 1 R61 4 6 1 3 4 1 5 10K 7 2 RP87B 18 RMASTER# 1K R126 7 10K 6 3 RP87C 74HCT14 RP79 74HC10 12,18 ZEROWS# 8 1 RP33 7 2 14 U36D TP4407 1 8 12,18 IOCS16# 6 3 SA8 2 7 12,18 MEMCS16# 5 4 9 8 1 3 6 13,14,18 IRQ4 4 5 1K 7 74F07 12,14,18 IOCHRDY R26 1K RP26 10K SA10 1 8 SA9 2 7 RP3 14 U36F 3 6 1 8 TP4400 13,14,18 4 5 2 7 13 12 1 3 6 10K 12,18 IOCHK# 4 5 7 74F07 RP7 4.7K SD7 1 8 U36A SD6 2 7 14 TP4401 13,14,18 IRQ9 3 6 SD5 4 5 1 2 1
RP12 10K 12,14,18 SD[15:0] 7 SD4 3 1 8 74F07 3 SD3 2 7 SD2 3 6 SD1 4 5 5VSB 14 U36E TP141 10K RP78 11 10 1 SD9 1 8 SD10 2 7 14 U34A 7 SD11 TP4403 3 6 74F07 SD12 4 5 1 2 1 U36C 14 RP82 10K 7 TP142 SD13 1 8 74F07 5 6 1 SD14 2 7 SD15 3 6 7 4 5 VCC SD8 74F07 SD7 10K RP58 SD6 SA3 1 8 SD5 SA2 2 7 SD0 SA1 3 6
A BUS SA0 4 5
RP47 10K 10K 1 8 RP94A SA6 1 8 U31B 13,14,18,19 IRQ15 TP151 IS 12,18,21 MEMW 10K 2 7 RP94B SA5 2 12,18,21 MEMR 10K 3 6 RP94C SA4 3 3 4 1 12,18 BALE 4 10K 74F06 RP77 SA8 8 1 U31C 2 13,14,18 DRQ0 TP149 2 13,18 DRQ5 7 2 SA7 13,18 DRQ6 6 3 5 6 1 5 4
5.6K RP14 SA10 74F06 1 8 SA9 2 7 13,14,18 DRQ3 3 6 4 5 13,14,18 DRQ1 RP25 SA13 8 5.6K SA12 7 SA11 6 13,14,18 IRQ7 5 RP22 10K Mounting Holes SA16 1 2 7 SA15 3 6 MH3 MH7 MH6 MH9 MH1 VCC SA14 4 5 1 1 1 1 1 RP74 1 1 1 1 1 RP21 LA23 13,14,18 IRQ11 1 8 M HOLE1 M HOLE1 M HOLE1 M HOLE1 M HOLE1 LA21 2 7 SA18 1 8 LA22 13,14,18 IRQ12 3 6 2 7 LA20 4 5 3 6 12,14,18,33 IOR# MH10 MH4 MH8 MH5 12,14,18,33 IOW# 4 5 1 1 1 1 RP75 10K RP13 10K 1 1 1 1 LA19 1 8 SD0 1 8 M HOLE1 M HOLE1 M HOLE1 M HOLE1 LA18 2 7 12,18 SMEMW# 2 7 1 LA17 3 6 12,18 SMEMR# 3 6 1 SD8 4 5 SA19 4 5
10K INTEL CORPORATION 10K 12,18 LA[23:17] GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title ISA BUS PULLUPS
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: Sheet 29 of 41 A B C D E 1 2 3 4 5 6 7 8
VCC3 VCC3
1 uF 1 uF + C11 C275 16 C154 16 A A 22uF 10V 1 uF + C118 C195 16
22uF 10V 1 uF C236 16 + C23 1 uF 22uF 10V 0.01 uF C252 V 1 uF C40 C317 16 C279 16V 22uF 10V 0.01 uF 1 uF C22 C329 16V C319 16 0.01 uF 1 uF 22uF 16V C219 16V C34 C92 16 0.01 uF
22uF 10V C385 16 C14 0.01 uF
22uF 10V C235 16 C24
22uF 10V B Do Not Stuff C18
22uF 10V
VCC3 VCC VCC3 VT 0.01 uF 0.01 uF VCC VCC VCC C283 16 C126 16 0.01 uF
C261 16 0.01 uF
0.01 uF C C70 16
C265 16 0.01 uF
0.01 uF C39 16
C288 16 0.01 uF
0.01 uF C113 V
C73 16
0.01 uF
C115 16 0.01 uF
C36 16
C99 0.01 uF
C386 16
0.01 uF
C10 16V
D D
0.01 uF
16V INTEL CORPORATION
0.01 uF GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630 C405 16 Titl 0.01 uF 0.01 uF 0.01 uF DRAM, CLOCK AND 440BX DECOUPLING CAPACITORS
S Document Number C401 16 C243 16 16V C 3 DEVICE AGP 1.0
22:16:57 Sheet 30 41 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8
VCC3
0.01 uF 0.01 uF
C152 16V C237 16V
0.01 uF 0.01 uF BULK POWER DECOUPLING VCC
A 0.01 uF C224 16V C251 16V A
VCC 0.01 uF 0.01 uF C53 16V 5VSB VCC C42 0.01 uF C245 16V C153 16V
22 uF 10V 0.01 uF 0.01 uF 0.01 uF C231 C242 16V + C340 0.01 uF C176 16V C138 16V C392 16V 22 uF 10V 22 uF 10V 0.01 uF 0.01 uF 0.01 uF C341 C11 16V C48 0.01 uF C384 16V C137 16V C71 16V 22 uF 10V 22 uF 10V 0.01 uF 0.01 uF 0.01 uF C45 C55 16V C46 0.01 uF C272 16V C136 16V C408 16V 22 uF 10V 22 uF 10V 0.01 uF 0.01 uF C223 C416 16V
0.01 uF C285 16V C303 16V 22 uF 10V 0.01 uF 0.01 uF C21 16V
+12v -5v -12v 0.01 uF C258 16V C276 16V B B 0.01 uF 0.01 uF C54 16V C90 + C1 + C28 + 0.01 uF C169 16V C274 16V
22 uF 16V 22 uF 10V 22 uF 10V 0.01 uF 0.01 uF C222 16V
0.01 uF C241 16V C202 16V 0.01 uF 0.01 uF
C398 16V C168 16V C383 16V 0.01 uF 0.01 uF 0.01 uF
C22 16V C302 16V C38 16V
0.01 uF 0.01 uF
C256 16V C108 16V
0.01 uF 0.01 uF CORE VOLTAGE DECOUPLING C218 16V C109 16V
0.01 uF 0.01 uF
C VCCCORE VCCCORE VCCCORE VCCCORE VCC C C278 16V C107 16V 0.01 uF 0.01 uF
10uF 10uF 100uF 0.01uF C4 16V C377 16V
C85 16V C89 16V C91 16V C68 16V 0.01 uF 0.01 uF
10uF 10uF 100uF C271 16V C371 16V
C83 16V C94 16V C88 16V 0.01 uF 0.01 uF
10uF 10uF 100uF C240 16V C335 16V
C133 16V C127 16V C134 16V 0.01 uF 0.01 uF
10uF 10uF C254 16V C188 16V
C93 16V C87 16V 0.01 uF
10uF C280 16V
C98 16V
D D
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title 3.3 VOLT AND BULK POWER DECOUPLING
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 31 of 41 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
A A TERMINATION VOLTAGE DECOUPLING
VTT VTT VTT
C125 22 pF 22pF
22uF 16V C147 16V C135 16V 0.01 uF 22pF 1 uF
C130 16V C174 16V C124 16V 0.01 uF 22pF 0.01 uF
C170 16V C185 16V C151 16V 0.01 uF 0.01 uF
C207 16V B B C175 16V 0.01 uF
C184 16V
0.01 uF 0.01 uF
C129 16V C150 16V 0.01 uF 0.01 uF
C116 16V C171 16V 0.01 uF 0.01 uF
C148 16V C132 16V 0.01 uF 0.01 uF
C123 16V C173 16V 0.01 uF
C145 16V 0.01 uF
C C128 16V C
0.01 uF 0.01 uF
C199 16V C131 16V 0.01 uF 0.01 uF
C146 16V C196 16V
D D
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title TERMINATION DECOUPLING
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 32 of 41 1 2 3 4 5 6 7 8 A B C D E
VCC
4 U29 12 4 1 12,14,18,29 IOR# IORD# 2 12,14,18,29 IOW# IOWR#
3 VCC5 R201 R202 12,18,38 SYSCLK SYSCLK XD0 11 D0 2.7K 2.7K XD1 10 D1 XD2 9 D2 XD3 8 D3 XD4 7 D4 XD5 6 D5 XD6 5 D6 XD7 4 D7 44 14,21 XD[7:0] CS# 43 40 13,28 PGCS#1 A0 SMI# EXTSMI#13,28 42 LM79 12,14,18,21,29 SA0 A1 12,14,18,21,29 SA1 41 39 VCC A2 NMI/IRQ# 12,14,18,21,29 SA2 VID0 37 HARDWARE VID0 VCCCORE VTT VCC3 VCC +12V -12V -5V VID1 36 VID1 MONITOR VID2 35 16 VID2 PS_BYPASS ** This device is powered by R183 VID3 34 VID3 5V only and requires a VIH of VID4 23 22 VID4/NTEST RESET# R214 R229 R211 R210 R209 R226 R206 14 3.5V on it's SMBus interface. 10K SMI_IN# 15 4,25 VID[4:0] CHASIS_INTRU Q4 Here is a 5V-3V SMBUS 38 1 10K 10K 10K 66.5K 232K 232K 100K BTI# 19 3 specific level translation 26 CPUFAN1 FAN1 18 2 circuit. 3 26 PSFAN2 FAN2 3 17 FAN3 D4 2N3904 21 1 Slave address = SDA SMBDATA3,6,9,10,11,13,28 0 R213 33 20 IN0 0101101b SCL SMBCLK3,6,9,10,11,13,28 0 R212 32 3 IN1 31 2 1 TP3605 IN2 30 IN3 Q3 29 1 IN4 28 3 VCC3 -IN5 27 2 FB5 26 FB6 25 2N3904
-IN6 VSSD VSSA R200
LM79 2.7K 13 24 R228 R227 R208 R207 R185 R184 R186 C388 C387 2.7K 100K 80.6K 66.5K 66.5K 10K 10K 0.1 uF 0.1 uF
2 2
1 1 INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA. 95630
Title LM79 MONITOR
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: Thursday, July 02, 1998 Sheet 33 of 41 A B C D E A B C D E +2_7V VCC3 VCC3 VCC3
U14A
E07 E09 E11 E13 E14 E16 E18 E20 H22 AB07 AB09 AB11 AB13 AB14 AB16 AB18 AB20 F25 G23 G25 G26 GO5 J05 L05 N05 P05 T05 V05 Y05 AC06 AB08 AB10 AB12 AC13 AC14 AB15 AB17 AB19 AC21 Y22 V22 T22 P22 N22 L22 J22 G22 D06 E08 E10 E12 D13 D14 E15 E17 E19 GAD[31:0]7,15 C17 Y04 GAD0 VP0 AD0 A18 Y02 GAD1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VP1 VCC VCC VCC VCC VCC VCC AD1 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCA VCCA GAD2
D17 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ Y03 VP2 AD2 B18 Y01 GAD3 VP3 AD3 4 C18 W05 GAD4 4 VP4 AD4 A19 W03 GAD5 VP5 AD5 D18 VCC3 W04 GAD6 VP6 AD6 B19 W02 GAD7 VP7 AD7 C19 V02 GAD8 VP8 AD8 A20 V03 GAD9 VP9 AD9 D19 V01 GAD10 VP10 AD10 B20 C191 C20 C141 C66 C65 C165 C155 C156 U05 GAD11 VP11 AD11 C20 U03 GAD12 VP12 22UF 10UF .01uF .1UF .01UF .1UF .01UF .1UF AD12 A21 U04 GAD13 VP13 AD13 R31 D20 U02 GAD14 VP14 AD14 3VVP15 B21 T04 GAD15 VCC3 VP15 AD15 2K VIDEO CAPTURE P03 GAD16 AD16 J24 P02 GAD17 VRDY# AD17 K22 P04 GAD18 NOTE: HREF# AD18 L23 P01 GAD19 ----- VREF# VCC3 AD19 L24 N03 GAD20 VCLK AD20 Subsystem ID N01 GAD21 AD21 N04 GAD22 = 1000H AD22 A07 N02 GAD23 ROMA0 AD23 2K 1 8 RP61A ROMA1 B08 C140 M04 GAD24 ROMA1 C162 C163 C63 C164 C158 C57 C61 AD24 ROMA2 A08 M02 GAD25 ROMA2 .1UF .01UF .1UF .01UF .1UF .01UF .1UF .01UF AD25 B09 M05 GAD26 ROMA3 AD26 2K 2 RP61B 7 A09 L01 GAD27 ROMA4 AD27 B10 L03 GAD28 ROMA5 AD28 A10 L02 GAD29 3 ROMA6 AD29 3 2K 3 6 RP61C ROMA7 B11 L04 GAD30 ROMA7 AD30 VCC3 D11 K01 GAD31 ROMA8 AD31 C10 ROMA9 VCC3 D09 ROMA10 D10 V04 ROMA11 C/BE0# GC/BE#015 A11 U01 ROMA12 C/BE1# GC/BE#115 C11 R01 ROMA13 C/BE2# GC/BE#215 D12 M03 ROMA14 C/BE3# GC/BE#315 2K 4 5 RP61D ROMA15 B12 C166 C160 C161 C58 C59 ROMA15 ROMA16 A12 F02 38 ROMA16 ROMA16 10UF .1UF .01UF .1UF .01UF CLK C12 GCLK7407 ROMA17 SBA0 B07 BIOS INTERFACE H01 ROMD0 AGP INTERFACE SBA0 A06 J04 SBA1 ROMD1 SBA1 B06 J02 SBA2 VENDOR ID IS 0X8086 ROMD2 SBA2 C06 J03 SBA3 NOTE: ROMD3 SBA3 D07 K03 SBA4 ----- ROMD4 SBA4 C07 K05 SBA5 ROMD5 SBA5 THIS I.D. NEEDS TO D08 K02 SBA6 ROMD6 USE TANTALUM CAPACITORS FOR 10 AND 22UF SBA6 C08 K04 SBA7 REFLECT BOARD ROMD7 SBA7 VENDOR C09 G03 ROMOE# RESET# RESET#38 SBA[7:0]7,15 C13 G04 ROMWE# INT PIRQ#A13,15,16,17,28 R05 STOP# GSTOP#7,15,28 IREFSET# D21 T03 IREFSET# PAR GPAR7,15,28 R04 TRDY# GTRDY#7,15,28 2 L25 T01 2 38 TESTI TEST IRDY# GIRDY#7,15,28 R32 AA02 R03 VSSA FRAME# GFRAME#7,15,28 R20 T02 1% 511 DEVSEL GDEVSEL#7,15,28 4.7K J23 G02 VDDQ LEFT REQ# GREQ#7,15,28 H05 GNT GGNT#7,15,28 H26 NC H25 H02 NC DBF# RBF#7,15 ST[2:0]7,15 L12 VSS G01 ST0 R81 ST0 B17 H04 ST1 VMIINT# ST1 267 A17 H03 ST2 VMIRDY ST2 1% D16 VMIRD# C16 J01 VMIWR# SBSTB SBSTB7,15,28 B16 VMICS# A16 M01 VMIHA0 ADSTB_1 ADSTB-B7,15,28 D15 W01 R80 VMIHA1 ADSTB_0 ADSTB-A7,15,28 C15 R02 AGPREF C179 VMIHA2 AGPREF 182 B15 A01 VMIHA3 VSS .01UF 1% A15 A02 VMIHA4 VSS A03 VSS VSS VSS VSSA VSS VSS VSSA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
INTEL740 CHIP AF22 AF05 AF04 AF03 AF02 AF01 AE26 AE25 AE24 AE23 L11 H24 G21 G06 F23 F22 F21 F20 F07 F06 F05 F03 E26 E25 E24 E23 E22 E21 E06 E05 E04 E03 E02 E01 D26 D25 D24 D23 D22 D05 D04 D03 D02 D01 C26 C25 C24 C23 C22 C05 C04 C03 C02 C01 B26 B25 B24 B23 B22 B05 B04 B03 B02 B01 A26 A25 A24 A23 A22 A05 A04 INTEL740 (A)
1 INTEL CORPORATION 1
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title TM Intel740 Graphics Accelerator Part A
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 34 of 41 A B C D E A B C D E
VCC3
Y1 C15 C16 66.6667MHZ U14B 1 8 .1UF .01UF 4 5
GFX_OSC LMA[10:0]37 AA23 AD17 LMA0 CKE MA0 4 37 CKE AF16 LMA1 4 MA1 H23 AC17 LMA2 XTAL1 MA2 AE16 LMA3 MA3 AD18 LMA4 MA4 37 LMD[63:0] LMD0 AD06 AF17 LMA5 MD0 MA5 LMD1 AE06 AC18 LMA6 MD1 MA6 LMD2 AC07 AE17 LMA7 MD2 MA7 LMD3 AF06 AD19 LMA8 MD3 MA8 LMD4 AD07 AF18 LMA9 MD4 MA9 LMD5 AF07 AC19 LMA10 MD5 MA10 LMD6 AC08 AE18 LMD7 MD6 MA11 AE07 AE19 WEA#37 LMD8 MD7 WEA# AD08 AF19 WEB#38 LMD9 MD8 WEB# AF08 AF20 SRASA#37 LMD10 MD9 SRASA# AC09 AE20 SRASB#38 LMD11 MD10 SRASB# AE09 AD20 SCASA#37 LMD12 MD11 SCASA# AD09 AC20 SCASB#38 LMD13 MD12 SCASB# AF09 MD13 CSA0# AA25 CSA0#37 LMD14 AC10 FACE AA26 LMD15 MD14 CSA1# AE10 Y23 CS0B#38 DQM[7:0]37 LMD16 MD15 CSB0# AC12 MD16 CSB1# Y24 CS1B#38 LMD17 AF11 AD10 DQM0 MD17 DQM0 LMD18 AD12 AF10 DQM1 MD18 DQM1
LMD19 AE12 DRAM INTER AD11 DQM2 MD19 DQM2 LMD20 AD13 AE11 DQM3 3 MD20 DQM3 3 LMD21 AF12 R22 DQM4 MD21 DQM4 LMD22 AD14 T25 DQM5 MD22 DQM5 LMD23 AE13 R23 DQM6 MD23 DQM6 LMD24 AD15 T26 DQM7 MD24 DQM7 LMD25 AF13 AF21 MD25 TCLKA LMD26 AC15 AE21 RT1 R35 MD26 TCLKB TCLK137 LMD27 AF14 AD21 TDLY 0 MD27 OCLK LMD28 AD16 AC11 RCLK0 R34 MD28 RCLK0 LMD29 AF15 T24 RCLK1 MD29 RCLK1 33 LMD30 AC16 R33 LMD31 MD30 A BUS AE15 MD31 RSVD AA24 33 LMD32 W22 AE08 MD32 RSVD LMD33 Y25 AE14 MD33 RSVD LMD34 W23 V24 MD34 RSVD LMD35 Y26 N25 MD35 MEMORY DAT RSVD LMD36 W24 MD36 LMD37 W25 MD37 LMD38 V23 LMD39 MD38 W26 F24 RED36 LMD40 MD39 RED U22 F26 GREEN36 LMD41 MD40 GREEN V25 G24 BLUE36 LMD42 MD41 BLUE U23 MD42 LMD43 V26 J25 MD43 INT VSYNC VSYNC36 LMD44 U24 J26 MD44 HSYNC HSYNC36 2 LMD45 U25 K26 2 MD45 DDCCLK 3VDDCCL39 LMD46 T23 K25 MD46 DDCDATA 3VDDCDA39 LMD47 U26 MD47 DISPLAY LMD48 R24 K23 MD48 GPIO0 3VSDA39 LMD49 R25 K24 MD49 GPIO1 3VSCL39 LMD50 P23 C14 MD50 GPIO4 LMD51 R26 B14 MD51 GPIO5 LMD52 P24 A14 MD52 GPIO6 LMD53 P25 B13 MD53 GPIO7 LMD54 N24 A13 MD54 GPIO8 LMD55 P26 MD55 LMD56 N23 C21 MD56 IWASTE LMD57 N26 VCC3 R64 MD57 LMD58 M24 MD58 20K LMD59 M26 F01 MD59 VCCDP LMD60 M23 F04 MD60 VCCAP LMD61 M25 AA01 MD61 VCCDP LMD62 M22 AA04 MD62 VCCAP LMD63 L26 AF23 MD63 VSS AF24 VSS AF26
VSSVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AE22AF25 L13 VSS VSS AE05 AE04 AE03 AE02 AE01 AD26 AD25 AD24 AD23 AD22 AD05 AD04 AD03 AD02 AD01 AC26 AC25 AC24 AC23 AC22 AC05 AC04 AC03 AC02 AC01 AB26 AB25 AB24 AB23 AB22 AB21 AB06 AB05 AB04 AB03 AB02 AB01 AA22 AA21 AA20 AA07 AA06 AA05 AA03 Y21 Y06 T16 T15 T14 T13 T12 T11 R16 R15 R14 R13 R12 R11 P16 P15 P14 P13 P12 P11 N16 N15 N14 N13 N12 N11 M16 M15 M14 M13 M12 M11 L16 L15 L14 INTEL CORPORATION 1 1
INTEL740 CHIP GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title Intel740TM Graphics Accelerator Part B
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 35 of 41 A B C D E A B C D E
VCC3
4 CR4 4 1
3
2 VCC3
VCC VCC VCC BAV99 CR5 CR2 1 1
3 3 R5 2 R4 THERMISTOR 2 1K t CR1 BAV99 BAV99 1 SOT23S DIO HIDDEN PINS: 3 GND: 16,17 CR3 USED FOR BRD 2 MOUNT 1
3 BAV99 3 3 R1 FB1 2 J3 1K 35 RED 1 2 FUSE_5 FB 6 BAV99 11 R9 L_RED 1 75 C25 C8 7 22PF 22PF 12 L_GREEN 2 MON0PU 8 13 L_BLUE 3 9 FB2 14 MON2PU 5VDDCDA39 35 GREEN 1 2 4 FB 10 15 R18 5 VGA_HSYNC R3 C26 C9 75 0 R2 HSYNC35 22PF 22PF VGA CONN VGA_VSYNC 0 VSYNC35 2 2
FB3 5VDDCCL 35 BLUE 1 2 39 5VDDCCL FB R19 75 C27 C10 22PF 22PF
INTEL CORPORATION 1 1 GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title VGA CONNECTOR
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 36 of 41 A B C D E A B C D E
VCC3 VCC3
4 C49 C67 C6 C62 4 .1UF .01UF .1UF .01UF VCC3 VCC3 VCC3
VCC3 VCC3 VCC3
SGRAM 512Kx32 SGRAM 512Kx32
U1015 35 65 73 67 22 14 8 U815 35 65 73 67 22 14 8 92 89 92 89 NC NC NC NC 93 90 93 90 35 LMD[63:32] NC NC NC NC
94 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 91 94 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 91 NC NC LMD[31:0]35 NC NC 79 2 79 2 VCC3 VCC3 VCC3 VCC3 55 84 LMD31 55 84 LMD63 35 TCLK1 CLK DQ31 CLK DQ31 83 LMD30 83 LMD62 DQ30 DQ30 59 81 LMD29 59 81 LMD61 VDDQ DQ29 VDDQ DQ29 58 80 LMD28 58 80 LMD60 VREF/MCH DQ28 VREF/MCH DQ28 95 78 LMD27 95 78 LMD59 3 NC/DRDY DQ27 NC/DRDY DQ27 3 54 77 LMD26 54 77 LMD58 35 CKE CKE DQ26 35 CKE CKE DQ26 96 75 LMD25 96 75 LMD57 VCC3 DQ25 VCC3 DQ25 28 74 LMD24 28 74 LMD56 35 CSA0# CS* DQ24 35 CSA0# CS* DQ24 21 LMD23 21 LMD55 DQ23 DQ23 27 20 LMD22 27 20 LMD54 35 SRASA# RAS* DQ22 35 SRASA# RAS* DQ22 18 LMD21 18 LMD53 DQ21 DQ21 26 17 LMD20 26 17 LMD52 35 SCASA# CAS* DQ20 35 SCASA# CAS* DQ20 13 LMD19 13 LMD51 DQ19 DQ19 25 12 LMD18 25 12 LMD50 35 WEA# WE* DQ18 35 WEA# WE* DQ18 10 LMD17 10 LMD49 DQ17 DQ17 53 9 LMD16 53 9 LMD48 DSF DQ16 35 DQM[7:4] DSF DQ16 72 LMD15 72 LMD47 DQ15 DQ15 35 DQM[3:0] DQM3 57 71 LMD14 DQM7 57 71 LMD46 DQM3 DQ14 DQM3 DQ14 DQM2 24 69 LMD13 DQM6 24 69 LMD45 DQM2 DQ13 DQM2 DQ13 DQM1 56 68 LMD12 DQM5 56 68 LMD44 DQM1 DQ12 DQM1 DQ12 DQM0 23 64 LMD11 DQM4 23 64 LMD43 DQM0 DQ11 DQM0 DQ11 101 63 LMD10 101 63 LMD42 NC DQ10 NC DQ10 LMA9 29 61 LMD9 LMA9 29 61 LMD41 A10(BA) DQ9 A10(BA) DQ9 LMA8 51 60 LMD8 LMA8 51 60 LMD40 A9(AP) DQ8 A9(AP) DQ8 LMA10 30 7 LMD7 LMA10 30 7 LMD39 A8 DQ7 A8 DQ7 LMA7 50 6 LMD6 LMA7 50 6 LMD38 A7 DQ6 A7 DQ6 LMA6 49 4 LMD5 LMA6 49 4 LMD37 A6 DQ5 A6 DQ5 LMA5 48 3 LMD4 LMA5 48 3 LMD36 A5 DQ4 A5 DQ4 LMA4 47 1 LMD3 LMA4 47 1 LMD35 2 A4 DQ3 A4 DQ3 2 LMA3 34 100 LMD2 LMA3 34 100 LMD34 A3 DQ2 A3 DQ2 LMA2 33 98 LMD1 LMA2 33 98 LMD33 A2 DQ1 A2 DQ1 LMA1 32 97 LMD0 LMA1 32 97 LMD32 A1 DQ0 A1 DQ0 LMA0 31 40 LMA0 31 40 A0 NC A0 NC 5 41 5 41 GND NC GND NC 11 42 11 42 35 LMA[10:0] GND NC 35 LMA[10:0] GND NC 19 43 19 43 GND NC GND NC 62 44 62 44 GND NC GND NC 70 45 70 45 GND NC GND NC 76 52 76 52 GND NC GND NC 82 87 82 87 GND NC GND NC 99 88 99 88
GNDGND GND GND GND NC NC NCNC NC GNDGND GND GND GND NC NC NCNC NC
SGRAM 512Kx32 16 46 66 85 36 37 38 39 16 46 66 85 36 37 38 39
SGRAM 512Kx32
INTEL CORPORATION 1 1 GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title SGRAMS
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 37 of 41 A B C D E A B C D E
VCC3 VCC3 VCC3 U1 RP2C 14 10 14 VCC U5A 3 6 1 4.7K A_0 2 BO D0 3 ROMA1634 12 9 PRE 6,12,15,16,17 PCIRST# D VCC Q 4 A_1 5 B1 D1 6 4 4 11 8 13 5,17 PCLK3 CLK NQ A_2 12 B2 D2 11 GND VCC3 CLR 10 A_3 9 B3 D3 8 13 7 7 VCC3 GND VCC3 N74LVX125 4 RP2D U4B 14 U4A 4.7K 4 1 6 RESET#34 3 5
5 2 13 GPO27 Q_NAND Q_NAND 7
3 3
VCC3 4
VCC3 RP1D 5
U2 20 U5B 10 14 1 OE_1 OE_2 19 2 2 2 5 2 VCC 18 PRE D VCC Q I0 D0 TESTI34 4 I1 D1 16 WEB#35 6 I2 D2 14 SCASB#35 8 I3 D3 12 SRASB#35 3 6 17 3 12,18,33 SYSCLK CLK NQ I4 D4 15 I5 D5 5 13 7
CLR GND I6 D6 CS0B#35 11 9
GND CS1B#35 VCC3 I7 D7
1 7 74LVT244_1 10
U4C 9 8 10 13 GPO28 Q_NAND
INTEL CORPORATION
1 GRAPHICS COMPONENTS DIVISION 1 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title LOW POWER MODE LOGIC
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 38 of 41 A B C D E A B C D E
4 4
VCC
QSV
R6 1.62K
C19 C18 QSV .1UF .01UF VCC R7 10K 2 RP4B 3 3 10K 1 RP4A
7 10K 1
8 RP5A 2.2K 2 RP5B
8 2.2K QS3861 U7
7 2 22 5VSCL A0 B0 3VSCL35 3 21 5VSDA A1 B1 3VSDA35 4 20 36 5VDDCDA A2 B2 3VDDCDA35 5 19 36 5VDDCCL A3 B3 3VDDCCL35 6 18 A4 B4 7 17 A5 B5 8 16 A6 B6 9 15 A7 B7 10 14 A8 B8 11 13 A9 B9 2 2 23 24 QSV BE* QSV 1 12 NC GND
QS3861
INTEL CORPORATION 1 1 GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title DDC
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 39 of 41 A B C D E A B C D E
4 4 +12V
VCC3
C23 1UF U9 LT1575 C52 C103 1 SHDN IPOS 8 2 VIN INEG 7 1UF 100UF 3 6 L_GATE R17 GND GATE COMP1 4 FB COMP 5 4.7
NOTE: +2_7V
---- FB1575 THE NET CONNECTING C60 TO C61 R16 VCC_REGULATED SHOULD BE CONNECTED DIRECTLY 3 TO PIN 3 OF THE LT1575 DUE TO 150 3 THE GROUND BOUNCE SENSIVITITY OF THE LT1575 COMPENSATION PIN R21
7.5K R_GA R8 C51 120 10PF TE Q1
2 DRN 1 GATE RECOMMENDED HEXFET: 3 SRC ------MOTOROLA PART# MTD3055VLT4 M_COM HEXFET SAMSUNG CORNING CO. LTD PART# SSR3055-TM
P1 C50 1000PF
2 2
+2_7V
C112 C101 C24 C82 C102 C81 C139 C111 C120 C100 C122 C121 22UF 10UF .1UF .1UF .01UF .01UF .1UF .1UF .01UF .01UF .1UF .01UF
INTEL CORPORATION
1 GRAPHICS COMPONENTS DIVISION 1 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title VOLTAGE REGULATOR
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 40 of 41 A B C D E A B C D E
REVISION1.0 8/98 -First release of 3 Device AGP schematics.
4 4
3 3
2 2
1 1
INTEL CORPORATION
GRAPHICS COMPONENTS DIVISION 1900 PRAIRIE CITY RD. FM5-79 FOLSOM, CA 95630
Title REVISION HISTORY
Size Document Number Rev Custom 3 DEVICE AGP 1.0
Date: 22:16:57 Sheet 41 of 41 A B C D E 4 Thermal Considerations
Thermal Considerations
Thermal Considerations 4
Thermal design is an important step in the total design process which must not be overlooked. Systems or cards designed without considering the thermal environment may experience failures. Depending on the usage of the Intel740™ graphics accelerator, the thermal solution may change. The following table lists the design considerations which must be made.
Table 4-1. Thermal Design Considerations Chart
Intel740 Graphics Accelerator Usage Design Considerations
Designing for Retail Add-In Card Must design for worst case (no Airflow, 55o C) Designing for Use With OEM System Work with the OEM, determining Chassis & Airflow
For a comprehensive guide to thermal design, please refer to Application Note 653, Thermal Design Considerations.This application note is provided in Appendix B of this document.
Intel740™ Graphics Accelerator Design Guide 4-1 Thermal Considerations
4-2 Intel740™ Graphics Accelerator Design Guide 5 Mechanical Information
Mechanical Information
Mechanical Information 5
5.1 Board Dimensions
Board Dimensions should be obtained from the AGP 1.0 Specifications and the associated Engineering Change Requests (ECRs).
5.2 Fan/Heatsink Hole Pattern
Note: This solution is only need for those designs in which it has been determined there is a need for additional thermal cooling through the use of a fansink.
The Intel740™ graphics accelerator reference board has the capability of attaching a fansink. If a design requires a fansink, the following design issues must be observed to be compatible with the fan attach mechanism Intel has enabled. The mounting holes must be nonplated but each must have a grounded annular ring on the solder side of the board surrounding the hole. This annular ring should have an inner diameter of 150 mils and an outer diameter of 300 mils. This ring should contain at least eight ground connections. The solder mask opening for these holes should have a radius of 300 mils. The position of these mounting holes in relation to the MBGA is shown in Figure 5-1. Figure 5-1. Mounting Hole Locations (Fan/Heatsink Assembly)
Intel740™ Graphics Accelerator Design Guide 5-1 Mechanical Information
5.3 VMI Header Placement
The VMI header allows the connection of a DVD daughter Card. The reference card places the header at the bottom of the card. For other designs, these headers may be placed at the top of the board. The latter is recommended for an NLX card. Figure 5-2. VMI Header Placement
26-pin conn Z1
0.300” 40-pin conn Z1
0.200” min Board Edge
Figure 5-3. DVD Daughter Card Dimensions (ATX and NLX)—Top Side
.200” min
0.200” min
Z1 0.300”
Z1
2.05” max
0.825” max
0.355” max 1.945” max
Note: Z1 Connectors in Figure 5-3 are on the backside of the card.
5-2 Intel740™ Graphics Accelerator Design Guide Mechanical Information
The dimensions shown in Figure 5-3 should be kept in mind when placing the VMI Headers. The reference DVD daughter cards will be designed for a maximum graphics board component height of 0.2”. If the component height exceeds these dimensions underneath the daughter card, the daughter card may not fit.
5.4 50 Pin Video Connector
The following diagram is a pinout view of the 50 pin video connector illustrating the different video connections which can exist. Figure 5-4. 50 Pin Video Connector Schematic
1 2 1 GND 3 2 GND 3 CVBS 4 4 NC 5 I2CSCK 5 6 12V 7 I2CSDATA 6 7
Tuner Connector
S-Vidoe In 1 2 1 GND 2 GND 3 3 Y 4 C 4
S-Video Out 1 2 1 GND 2 GND 3 3 Y 4 C 4
Composite Video In
Composite Video Out
Intel740™ Graphics Accelerator Design Guide 5-3 Mechanical Information
5.5 Bracket
Figure 5-5. Recommended Bracket Placement
Figure 5-6. Recommended Bracket Cutout
5-4 Intel740™ Graphics Accelerator Design Guide Mechanical Information
5.6 NLX Considerations
The NLX card has a special bracket design and card cutout to accommodate the NLX chassis. The NLX card can be used in an ATX chassis, but needs to use an ATX bracket. Unless a dual sided board is used, the full featured reference design will not be feasible on the NLX add-in card. This is due to the decreased physical size of the NLX add-in card. The 50 pin video connector will not fit in the NLX chassis. Each board designer must determine the placement of their desired features on the NLX card.
Intel740™ Graphics Accelerator Design Guide 5-5 Mechanical Information
5-6 Intel740™ Graphics Accelerator Design Guide 6 Third Party Vendors
Third Party Vendors
Third Party Vendors 6
This chapter provides a useful list of contacts for a design using the Intel740™ graphics accelerator.
6.1 Voltage Regulator
• Linear Technology* — Todd Jackson (408) 428-2061
6.2 50 Pin Connector
• Foxconn* — P/N QA11253-58
6.3 Fan/Heatsink
• Sanyo Denki* — James Sia (310) 212-7724 — Fan/Heatsink P/N 109P4405H9026 — Clip, prototype XF-8300 — Clip, production 109-688
6.4 Flash Components
• Intel — 28F010 — 28F001
6.5 Video Encoders/Decoders
• Rockwell* Semiconductor — Tim Yates (619) 535-3522 — Video Encoder (Bt868/869) — Video Decoder (Bt829a)
Intel740™ Graphics Accelerator Design Guide 6-1 Third Party Vendors
6.6 DVD Daughter Cards
Intel has worked to enable a variety of hardware DVD solutions. Each of the vendors below will have a functional reference daughter card compatible with the Intel740™ graphics accelerator reference design. These designs can be modified so that the DVD component is down on the card or left as is so that multiple DVD solutions can be implemented.
Depending on the implementation of audio chosen three options exist. One option is to have a software audio solution. This decreases the overall board cost and makes the physical requirements of audio hook-up relatively straight forward. The second option is to have hardware audio and cable this over to the system’s sound solution (sound card or motherboard audio). The third option is to use an SPDIF connector to connect to an external SPDIF decoder outside of the chassis. • C-Cube* Microsystems — Clint Chao (408) 490-8112 • Sigma* Designs — Ron Berti (510) 770-2691 • Toshiba* — Elie Semaan (408) 965-4266 • Zoran* Jack Koplik (408) 919-4237
6.7 TV Tuner
• Hauppauge Computer Works, Inc., 91 Cabot Court, Hauppauge, NY 11788 Phone: (516) 434-1600 Fax: 516-434-3198 Web Site: www.hauppauge.com Contact name: Bob Rosoff ([email protected]) — Model 5901 4.1x4.2" ISA form-factor NTSC (systems M/N) tuner card. The only contacts on the ISA bus are for power supply. Software includes support for Windows* 95 and Windows* NT. — Model 5904 4.1x4.2" ISA form-factor PAL (systems B/G) tuner card. The only contacts on the ISA bus are for power supply. Software includes support for Windows95 and Windlassing. — Model 5905 4.1x4.2" ISA form-factor PAL (system I) tuner card. The only contacts on the ISA bus are for power supply. Software includes support for Windows95 and WindowsNT. — Model 5906 4.1x4.2" ISA form-factor PAL/SECAM (systems B/G and L) tuner card. The only contacts on the ISA bus are for power supply. Software includes support for Windows95 and WindowsNT. — Model 5907 4.1x4.2" ISA form-factor PAL/SECAM (systems D/K) tuner card. The only contacts on the ISA bus are for power supply. Software includes support for Windows95 and WindowsNT.
6-2 Intel740™ Graphics Accelerator Design Guide A Application Notes Intel740™ Graphics Accelerator
Application Note 653: Thermal Design Considerations
April 1998
Order Number: 292211-002 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The Intel740™ graphics accelerator may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Such errata are not covered by Intel’s warranty. Current characterized errata are available on request. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by: calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
Application Note 653: Thermal Design Considerations Contents
1.0 Introduction ...... 1 1.1 Document Goals ...... 1 1.2 Importance of Thermal Management...... 1 1.3 Intel740™ Graphics Accelerator Packaging Terminology ...... 2 2.0 Thermal Specifications...... 3 2.1 Case Temperature ...... 3 2.2 Power...... 4 3.0 Designing for Thermal Performance...... 5 3.1 Airflow Management ...... 5 4.0 Cooling Solutions...... 7 4.1 System Fans ...... 7 4.1.1 Fan Placement...... 7 4.1.2 Fan Direction...... 9 4.1.3 Size and Quantity...... 9 4.1.4 Fan Venting...... 9 4.1.5 Vent Placement...... 9 4.1.5.1 Vent Area/Size ...... 9 4.1.5.2 Vent Shape ...... 10 4.1.6 Ducting...... 10 4.1.6.1 Ducting Placement...... 10 4.2 Thermal Enhancements...... 10 4.2.1 Clearance...... 10 4.2.2 Low Profile Fan Heat Sink ...... 11 4.2.2.1 Low Profile Fan Heat Sink PCB Layout Guidelines ...... 11 4.2.2.2 Low Profile Fan Heat Sink Electrical Requirements ...... 12 4.2.2.3 Low Profile Fan Heat Sink Attach ...... 13 4.2.2.4 Low Profile Fan Heat Sink Reliability ...... 13 4.2.3 Low Profile Passive Heat Sink ...... 14 4.2.3.1 Clip Attach...... 14 4.2.3.2 Epoxy ...... 14 4.2.3.3 Tape Attach...... 15 4.2.3.4 Reliability...... 17 4.3 Thermal Interface Management for Heat Sink Solutions ...... 17 4.3.1 Bond Line Management...... 18 4.3.2 Interface Material Performance...... 18 5.0 Measurements for Thermal Specifications...... 19 5.1 Case Temperature Measurements ...... 19 5.2 Power Simulation Software...... 20 6.0 Conclusion ...... 22
A Sources...... 23 A.1 Low Profile Fan Heat Sink Sales Locations ...... 23 A.2 Low Profile Passive Heat Sink Sales Locations...... 23 A.3 Attach Sales Locations ...... 23
Application Note 653: Thermal Design Considerations iii Figures
1 Example of air exchange through a PC chassis ...... 6 2 Fan Placement and Layout of an ATX Form Factor Chassis - Top View ...... 8 3 Fan Placement and Layout of an NLX Form Factor Chassis - Top View ...... 8 4 Low Profile Fan Heat Sink Drawing ...... 11 5 PCB Layout Guidelines for Mounting Holes ...... 12 6 Fan Heat Sink Connector Design ...... 13 7 Tape Layers...... 15 8 Attaching the Tape to the Package and Heat Sink ...... 15 9 Completing the Attach Process ...... 16 10 Technique for Measuring Tcase with 0° Angle Attachment ...... 20 11 Technique for Measuring Tcase with 90° Angle Attachment ...... 20 12 Thermal Enhancement Decision Flowchart ...... 21
Tables
1 Intel740 Graphics Accelerator Preliminary Thermal Absolute Maximum Rating 3 2 Default Thermal Solution Reliability Validation ...... 13 3 Tape Attach Application Temperature/Pressure Option ...... 17 4 Reliability Validation...... 17
iv Application Note 653: Thermal Design Considerations 1.0 Introduction
In a system environment, the chipset temperature is a function of both the system and component thermal characteristics. The system level thermal constraints consist of the local ambient temperature at the component, the airflow over the component and surrounding board as well as the physical constraints at, above, and surrounding the component. The component’s case temperature depends on the component power dissipation, size, packaging materials (effective thermal conductivity), the type of interconnection to the substrate and motherboard, the presence of a thermal cooling solution, the thermal conductivity and the power density of the substrate, nearby components, and motherboard.
All of these parameters are pushed by the continued trend of technology to increase performance levels (higher operating speeds, MHz) and packaging density (more transistors). As operating frequencies increase and packaging size decreases, the power density increases and the thermal cooling solution space and airflow become more constrained. The result is an increased emphasis on system design to ensure that thermal design requirements are met for each component in the system.
1.1 Document Goals
The Intel740™ graphics accelerator is the newest addition to the growing market of fast, 3D graphics accelerators. Previous generations of graphics accelerators generated insufficient heat to require an enhanced cooling solution in order to meet the case temperature specifications in system designs. As the market transition to higher-speeds with enhanced features, the heat generated by these advanced graphics accelerators will introduce new thermal challenges for system designers. Depending on the type of system and the chassis characteristics, new designs may be required to provide better cooling solutions for these graphics accelerators. The goal of this document is to provide an understanding of the thermal characteristics of the Intel740 graphics accelerator and discuss guidelines for meeting the thermal requirements imposed on systems.
1.2 Importance of Thermal Management
The objective of thermal management is to ensure that the temperature of all components in a system are maintained within functional limits. The functional temperature limit is the range within which the electrical circuits can be expected to meet specified performance requirements. Operation outside the functional limit can degrade system performance, cause logic errors or cause component and/or system damage. Temperatures exceeding the maximum operating limits may result in irreversible changes in the operating characteristics of the component.
Application Note 653 1 Intel740™ Graphics Accelerator Thermal Design Considerations
1.3 Intel740™ Graphics Accelerator Packaging Terminology
BGA Ball Grid Array. A package type defined by a resin-fiber substrate on which a die is mounted, bonded and encapsulated in molding compound. The primary electrical interface is an array of solder balls attached to the substrate opposite the die and molding compound. Lands Pads on the PCB where BGA Balls are soldered. Mold-Cap The black encapsulating molding compound. The top of this is where maximum case temperatures are taken and where heat sinks are attached. PCB Printed Circuit Board. STBGA Super Thermal BGA. A Ball Grid Array Package enhanced to improve its thermal characteristics. The Intel740 graphics accelerator uses this type of BGA packaging. Thermal Balls Typically, this refers to an array of balls in the center of the larger array of balls which serve to channel heat into the PCB as well as ground connections.
2 Application Note 653 Intel740™ Graphics Accelerator Thermal Design Considerations
2.0 Thermal Specifications
The Intel740™ graphics accelerator power dissipation can be found in the Intel740™ Graphics Accelerator Datasheet and Intel740™ Graphics Accelerator Specification Updates. Please refer to these documents to verify the actual thermal specifications for the Intel740 graphics accelerator. In general, systems should be designed to dissipate the highest possible thermal power.
To ensure proper operation and reliability of the Intel740 graphics accelerator, the thermal solution must maintain the case temperature at or below its specified value (Table 1). Considering the power dissipation levels and typical system ambient environments of 45°C to 55°C, if the Intel740 graphics accelerator case temperature exceeds the maximum case temperature listed in Table 1, system or component level thermal enhancements will be required to dissipate the heat generated.
The thermal characterization data described in later sections illustrates that good system airflow is critical. In typical systems the thermal solution is limited by board layout, spacing and component placement. Airflow is determined by the size and number of fans and vents along with their placement in relation to the components and the airflow channels within the system. In addition, acoustic noise constraints may limit the size and/or types of fans and vents that can be used in a particular design.
To develop a reliable, cost-effective thermal solution, all of the above variables must be considered. Thermal characterization and simulation should be carried out at the entire system level accounting for the thermal requirements of each component.
Table 1. Intel740 Graphics Accelerator Preliminary Thermal Absolute Maximum Rating
Parameter Maximum
Tcase-nhs1 109°C Tcase-hs2 96°C
NOTES: 1. Tcase-nhs is defined as the maximum case temperature without a Heat Sink attached. 2. Tcase-hs is defined as the maximum case temperature with a Heat Sink attached (see Section 4.2, “Thermal Enhancements” on page 10).
2.1 Case Temperature
The case temperature is a function of the local ambient temperature and the internal temperature of the Intel740graphics accelerator. As a local ambient temperature is not specified for the Intel740, the only restriction is that the maximum case temperature (Tcase) is not exceeded. Section 5.1, “Case Temperature Measurements” on page 19 discusses proper guidelines for measuring the case temperature.
Note: Increasing the heat flow through the case increases the difference in temperature between the junction and case, reducing the maximum allowable case temperature.
Application Note 653 3 Intel740™ Graphics Accelerator Thermal Design Considerations
2.2 Power
In previous generations of graphics accelerators where Quad Flat Pack (QFP) packages have been the primary package type, the majority of power dissipation has been through the plastic case of the package into the surrounding air. With the advent of Ball Grid Array (BGA) packaging for graphics accelerators, the majority of the thermal power dissipated by the chipset typically flows into the motherboard where it is mounted. The remaining thermal power is dissipated by the package itself. The STBGA used for the Intel740 graphics accelerator continues this trend by further enhancing the package’s ability to channel heat into the motherboard.
The amount of thermal power dissipated, either into the board or by the package, varies depending on how well the motherboard conducts heat away from the package and whether the package uses thermal enhancements. While package thermal enhancements typically serve to improve heat flow through the case via a heat sink, how well the motherboard conducts heat away from the package is strictly a function of motherboard design. The following should be taken into account by system designers when developing new systems: • How well the thermal balls are connected to the inner planes of the motherboard. It is recommended that: — One via per ground ball be used. — Minimum width of the trace connecting the motherboard ground pad to the via be 10 mil. — Plated Via Size for ground balls be 14 to 16 mil in diameter on a 24 to 27 mil pad. A larger via is more efficient in channeling heat. — Do not use Thermal Relief Patterns on the inner plane connections of the thermal balls. • How well the inner planes conduct heat away from the package. Good ground paths to other areas of the board will distribute heat more efficiently. • The size of the motherboard, number of copper layers and the thickness of those layers.
4 Application Note 653 Intel740™ Graphics Accelerator Thermal Design Considerations
3.0 Designing for Thermal Performance
In designing for thermal performance, the goal is to keep the component within the operational thermal specifications. The heat generated by the components within the chassis must be removed to provide an adequate operating environment for all of the system components. To do so requires moving air through the chassis to transport the heat generated out of the chassis.
3.1 Airflow Management
It is important to manage the air flow path and amount of air that flows through the system to maximize the amount of air that will flow over the Intel740 graphics accelerator and AGP Card. System air flow can be increased by adding one or more fans to the system, by vents and fans in combination, by increasing the output (faster speed) or size of an existing system’s fan(s). Local air flow can also be increased by managing the local flow direction using baffles or ducts. An important consideration in airflow management is the temperature of the air flowing over the graphics processor. Heating effects from add-in boards, memory, other accelerators and disk drives greatly reduce the cooling efficiency of this air, as does re-circulation of warm interior air. Care must be taken to minimize the heating effects of other system components and to eliminate excessive warm air re-circulation.
For example, a clear air path from the external system vents to the system fan(s) will enable the warm air from the Intel740 graphics accelerator and AGP Card to be efficiently removed from the system. If no air path exists across the them, the warm air ambient to the Intel740 graphics accelerator and AGP Card will not be removed from the system, resulting in localized heating (“hot spots”) at and around the graphics processor requiring the addition of a thermal cooling device. Figure 1 shows two examples of air exchange through a PC-ATX style chassis. The system on the left is an example of good air exchange incorporating both the power supply fan, an additional system fan and good venting. The system on the right shows a system with only a power supply fan (blowing into the box) and minimal venting resulting in poor air flow past the AGP card.
Re-circulation of internal warm air is most common between the system fan and chassis, between the system fan intake and the drive bays behind the front bezel and in the card area. These paths may be eliminated by mounting the fan flush to the chassis, thereby obstructing the flow between the drive bays and fan inlet, and by providing generous intake vents in both the chassis and the front bezel.
Note: Note that these are recommendations. With careful engineering, modeling and testing, other solutions may work equally well in cooling the system.
Application Note 653 5 Intel740™ Graphics Accelerator Thermal Design Considerations
Figure 1. Example of air exchange through a PC chassis
Fan (exhaust) Fan (intake)
Cards Cards Little Power Airflow or Power Supply Recirculated Supply CPU Vent CPU
Drive Drive Bay Bay
Vent Fan (intake) Good Air Exchange Poor Air Exchange
6 Application Note 653 Intel740™ Graphics Accelerator Thermal Design Considerations
4.0 Cooling Solutions
Numerous alternatives for cooling solutions exist for the Intel740 graphics accelerator. This section will explore system cooling solutions as well as package heat-sinks. Due to their varying attributes, each of these solutions may be appropriate for a particular system implementation.
4.1 System Fans
Fans are needed to move the air through the chassis. The airflow rate of a fan is a function of the system’s impedance to airflow and the capability of the fan itself. Maximum acceptable noise levels may limit the fan output or the number of fans selected for a system. It is appropriate at this time to reiterate Section 2.2, “Power” on page 4. The majority of the thermal power dissipated by the Intel740 graphics accelerator typically flows into the motherboard to which it is mounted. Cooling the motherboard will cool the component by increasing the efficiency of heat transfer from the device to the motherboard.
4.1.1 Fan Placement
Proper placement of the fans can ensure that the Intel740 graphics accelerator is properly cooled. Because of the difficulty in building, measuring and modifying a mechanical assembly, models are typically developed and used to simulate a proposed prototype for thermal effectiveness to determine the optimum location for fans and vents within a chassis. Prototype assemblies can also be built and tested to verify if thermal specifications for the system components are met.
An air fan is typically in the power supply exhausting air through the power supply vents. A second system fan is added to improve airflow to the chipset and other system components. The second fan can improve component cooling up to 15% depending on airflow management within the system, obstructions and thermal enhancements. Figure 2 and Figure 3 show recommended fan placements for an ATX form factor layout and a NLX form factor, respectively. Again, note that these are recommendations, with careful engineering, modeling and testing, other solutions may work equally well in cooling the graphics processor.
Application Note 653 7 Intel740™ Graphics Accelerator Thermal Design Considerations
. Figure 2. Fan Placement and Layout of an ATX Form Factor Chassis - Top View
Fan
Passive SECC PS AGP Exhaust Slot Fan
PCI Slot Power Supply
ISA Slot Motherboard
Peripherals
Fan Vent
Required Fan > Power Supply Fan
Figure 3. Fan Placement and Layout of an NLX Form Factor Chassis - Top View
Vent Fan
Power Supply AGP Vent Slot Backplane
Required Vent
Mother
Passive SECC Passive board
Fan Peripherals Vent Vent
Required Fan
8 Application Note 653 Intel740™ Graphics Accelerator Thermal Design Considerations
4.1.2 Fan Direction
If the fan(s) are not moving air across the graphics processor and the card then little cooling can occur. Hence, the Intel740 graphics accelerator may exceed it’s absolute maximum thermal ratings. Note the recommended fan airflow directions in Figure 2 and Figure 3.
The direction of the air flow can also be modified with baffles or ducts to direct the air flow over the graphics processor. This will increase the local flow over the device and card and may eliminate the need for a larger or higher speed fan.
4.1.3 Size and Quantity
A larger fan does not always increase cooling efficiency. A small blower using ducting might direct more air over the graphics card than a larger fan blowing non-directed air. The following provides some recommendations for the size and quantity of the fans in AGP systems. • The fan should be a minimum of 80 mm (3.150”) square, with a minimum airflow of approximately 40 CFM (cubic feet per minute), or approximately 400 LFM (linear feet per minute). As shown in Figure 2 and Figure 3, two fans are used. The intake air fan blows cooler external air into the chassis, while the second fan (most likely in the power supply) exhausts the air out of the system. • As an example, in a lab test system, graphics card ambient temperatures were reduced by an average of roughly 10% in an ATX design and 15% in an NLX design by simply adding a front system fan. In general, the use of two fans benefits the entire system by reducing internal ambient temperatures. However, as system configurations vary, testing the target configuration to verify the benefit is recommended.
4.1.4 Fan Venting
As shown in Figure 2 and Figure 3, intake venting should be placed at the front (user side) of the system. Location should take into consideration cooling of the microprocessor and peripherals as well as the Intel740 graphics accelerator. A good starting point would be the lower 50% of the Front Panel (Bezel). Intake venting directly in front of the intake fan is the most optimal location.
4.1.5 Vent Placement
In most cases, exhaust venting in conjunction with an exhaust fan in the power supply is sufficient. However, depending on the number, location and types of add-in cards, intake or exhaust venting may be necessary near the cards as well. This is particularly important for the graphics card in NLX designs as it aids in eliminating dead air space near the AGP Slot (see Figure 3).
Vent placements should be modeled or prototyped for the optimum thermal potential. Hence, a system should be modeled for the worst case (i.e., all expansion slots should be occupied with typical add-in options).
4.1.5.1 Vent Area/Size
The area and/or size of the intake vents should consider the size and shape of the fan(s). Adequate air volume must be obtained and this will require appropriately sized vents. Intake vents should be located in front of the intake fan(s) and adjacent to the drive bays. Venting should be approximately 50% to 60% open in the EMI containment area due to EMI constraints. Outside the EMI containment area, the open percentage can be greater if needed for aesthetic appeal (i.e., bezel/cosmetics). For more information concerning EMI constraints and Pentium II processor based system design, see the Pentium II Processor EMI Design Guidelines Application Note.
Application Note 653 9 Intel740™ Graphics Accelerator Thermal Design Considerations
4.1.5.2 Vent Shape
Round, staggered pattern openings are best for EMI containment, acoustics and airflow balance. For material related to EMI considerations please see the Pentium II Processor EMI Design Guidelines Application Note.
4.1.6 Ducting
Ducts can be designed to isolate components from the effects of system heating and to maximize the thermal budget. Air provided by a fan or blower could be channeled directly over the Intel740 graphics accelerator and card or split into multiple paths to cool multiple components.
4.1.6.1 Ducting Placement
When ducting is to be used, it should direct the airflow evenly from the fan across the entire component and surrounding motherboard. The ducting should be accomplished, if possible, with smooth, gradual turns as this will enhance the airflow characteristics. Sharp turns in ducting should be avoided. Sharp turns increase friction and drag and will greatly reduce the volume of air reaching the Intel740 graphics accelerator and card.
4.2 Thermal Enhancements
One method used to improve thermal performance is to increase the surface area of the device by attaching a metallic heat sink to the mold cap. To maximize the heat transfer, the thermal resistance from the heat sink to the air can be reduced by maximizing the surface area of the heat sink itself.
For users whose ambient environments exceed 55°C, a Fan Heat Sink is strongly recommended to effectively cool the Intel740 graphics accelerator (discussed in Section 4.2.2, “Low Profile Fan Heat Sink” on page 11).
Note: Increasing the heat flow through the case increases the difference in temperature between the junction and case, reducing the maximum allowable case temperature.
4.2.1 Clearance
Though each design may have unique mechanical volume and height restrictions or implementation requirements, the constraints typically placed on the Intel740 graphics accelerator by an adjacent PCI Card is 0.450” clearance between the Intel740 graphics accelerator mold cap and the back of the adjacent PCI Card.
Note: If the heat sink selected is larger than 35 mm x 35 mm, the maximum component height under the portion of the heat sink overhaning the board is 0.09 inches.
10 Application Note 653 Intel740™ Graphics Accelerator Thermal Design Considerations
4.2.2 Low Profile Fan Heat Sink
A generic drawing for this Fan Heat Sink is shown in Figure 4. Recommended sources for the Low Profile Fan Heat Sink are discussed in Appendix A, “Sources”.
The thermal performance of the Fan Heat Sink and Thermal Interface Material (combined) must be sufficient to maintain a case temperature at or below Tcase-hs (See Table 1) in a worst case system environment (defined as: zero airflow, 55°C ambient temperature).
Note: The weight of the Fan Heat Sink must not exceed 55 gm.
Figure 4. Low Profile Fan Heat Sink Drawing
4.2.2.1 Low Profile Fan Heat Sink PCB Layout Guidelines
As the Low Profile Fan Heat Sink uses a mechanical attach, mounting holes must be provided in the PCB to accommodate the clips necessary in attaching the Fan Heat Sink. PCB Guidelines for the Fan Heat Sink mounting hole layout are provided in Figure 5. The mounting holes must be non- plated, but each must have a grounding pad on the solder side of the board surrounding the hole. It must be designed in such a way to ensure that the mechanical attachment clip is in solid contact with this pad. The mechanical assembly should only contact the PCB within the four 0.300 inch diameter component keep-out zones as shown in Figure 5. The outline of the Fan Heat Sink should be silk-screened onto the PCB to facilitate placement of the Fan Heat Sink on to the package.
Application Note 653 11 Intel740™ Graphics Accelerator Thermal Design Considerations
Figure 5. PCB Layout Guidelines for Mounting Holes
4.2.2.2 Low Profile Fan Heat Sink Electrical Requirements
The Fan Heat Sink’s total maximum power usage should not exceed 1 Watt and should start and operate within ±10% of rated voltage.
The Fan Heat Sink may use a connector which incorporates 2 separate connections: 12 Volt power, ground and signal (tachometer function). The fan connector may mate with a receptacle attached to a power cable that will be installed by the graphics card manufacturer. See Figure 5.
The Fan Heat Sink assembly, when installed in at least one typical host application, should not cause an increase in emissions above that measured from the host application before the assembly was installed.
The signal pin on fan header may supply an open collector rotor lock output signal: • Operating: Output is asserted by pulling the output low • Locked Rotor: Output is de-asserted, allowing output to float high using a pull up resistor on the graphics card.
12 Application Note 653 Intel740™ Graphics Accelerator Thermal Design Considerations
Figure 6. Fan Heat Sink Connector Design
Pwr Gnd Sig
4.2.2.3 Low Profile Fan Heat Sink Attach
The Low Profile Fan Heat Sink uses a mechanical attach to the card in conjunction with a thermal interface material. The recommended process flow for attaching the Low Profile Fan Heat Sink is shown as follows: 1. Ensure that the surface of the component and heat sink are free from contamination. Use a clean, lint-free wipe, proper safety precautions and Isopropyl Alcohol to ensure cleanliness. 2. Apply the Thermal Interface Material to the moldcap. 3. Place the Fan Heat Sink onto the moldcap within the confines of the silkscreened markings on the board. 4. Apply the mechanical attachment clip.
To repeat, the Thermal Performance of the Fan Heat Sink and Attach (combined) must be a maximum of 4.0°C per Watt at 80% of nominal fan RPM in a worst case system environment (defined as: zero airflow, 55°C internal ambient temperature).
4.2.2.4 Low Profile Fan Heat Sink Reliability
As every motherboard, system, heat sink and attach-process combination may introduce variance in attach strength and the use of a fan heat sink adds the need for fan-lifetime evaluation, it is generally recommended that the user carefully evaluate the reliability of the completed assembly prior to use in high volume. Some Test recommendations can be seen in Table 2.
Table 2. Default Thermal Solution Reliability Validation
Test1 Requirement Pass/Fail Criteria
50G Visual Check 3 Mechanical Shock 11 msec, 3 shocks/direction RPM Check 4 7.3 G Visual Check Random Vibration 45 minutes/axis, 50 to 2000 Hz RPM Check
85 °C, 2000 hours total, checkpoints occur at 168, 500, 1000 Visual Check Temperature Life and 2000 hours RPM Check -5 °C to +70 °C Visual Check Thermal Cycling 500 Cycles RPM Check
Application Note 653 13 Intel740™ Graphics Accelerator Thermal Design Considerations
Table 2. Default Thermal Solution Reliability Validation
85% relative humidity Visual Check Humidity 55 °C, 1000 hours RPM Check
7,500 on/off cycles with each cycle specified as 3 minutes Visual Check Power Cycling on, 2 minutes off 70 °C RPM Check
NOTES: 1. The above tests should be performed on a sample size of at least 12 Fan Heat Sink units from 3 assembly lots. 2. Visual Check: Labels, housing and connections all intact. 3. RPM Check: No fan RPM changes before and after test of greater than 20%. 4. The Fan Heat Sink’s thermal performance should meet the minimum specified requirements at an altitude of 1 to 10,000 feet. 5. Additional Pass/Fail Criteria may be added at the discretion of the user.
4.2.3 Low Profile Passive Heat Sink
A Passive, Extruded Heat Sink may be attached using Clips and Thermal Interface (tape, grease, etc.), Epoxy or Tape Adhesives. Suggested suppliers and part numbers for a passive heat sink are listed in Section A, “Sources” on page 23.
4.2.3.1 Clip Attach
A well designed clip in conjunction with a thermal interface material (tape, grease, etc.) solution may offer the best combination of mechanical stability and reworkability. Use of a clip requires significant advance planning as mounting holes are required in the PCB. The mounting holes should be non-plated, but each must have a grounded annular ring on the solder side of the board surrounding the hole. For a typical low-cost clip, this annular ring should have an inner diameter of 150 mils and an outer diameter of 300 mils. This ring should contain at least 8 ground connections. The solder mask opening for these holes should have a radius of 300 mils.
As clip designs are generally unique to a specific system and board layout, no procedural comments are provided.
4.2.3.2 Epoxy
Some users may prefer to implement Epoxy attaches for their thermal solution. For these users, products known to be compatible with the mold cap material are listed in Appendix A. Epoxy users should plan their process carefully as once attached, the heat sink may be difficult or impossible to remove without damaging the component.
For the Epoxies described in Section A, “Sources” on page 23, the manufacturer’s recommended attach procedure is as follows: 1. Ensure that the surface of the component and heat sink are free from contamination. Use a clean, lint-free wipe, proper safety precautions and Isopropyl Alcohol to ensure cleanliness. 2. Use the applicator provided by the epoxy manufacturer to apply the epoxy-activator to the mold-cap. 3. After the activator-solvent evaporates, the active ingredients will appear “wet” and will remain active for a maximum of two hours after application. Contamination of the surface during this time prior to bonding must be avoided. 4. Apply the adhesive to the heat sink. The amount of adhesive applied to the heat sink should be limited to the amount necessary to fill the bond and provide a small fillet (see Section 4.3.1, “Bond Line Management” on page 18).
14 Application Note 653 Intel740™ Graphics Accelerator Thermal Design Considerations
5. Join and secure the assembly centering the heat sink on the component. Wait for the adhesive to fixture (approximately 5 minutes) before any further handling. Full cure occurs in 4-24 hours.
Note: The successful application of this product depends on accurate dispensing on to the parts being bonded. The manufacturer (Section A, “Sources” on page 23) offers equipment engineers to assist customers in selecting and implementing the appropriate dispensing equipment for various applications.
To remove the heat sink after the epoxy has set, the manufacturer recommends applying heat (70°C - 93°C) to the assembly. When in this temperature range the heat sink can safely be removed from the component without damaging it.
4.2.3.3 Tape Attach
For users who prefer to attach via Tape, please refer to Section A, “Sources” on page 23 for the suggested manufacturer and part number. To maximize the bond line contact area and improve adhesion we recommend using two pieces of tape, one attached to the heat sink and one attached to the moldcap as shown in Figure 7, Figure 8, and Figure 9. The recommended attach procedure is at the end of this section.
Figure 7. Tape Layers
Clear Liner Actual Appearance: Acrylic Adhesive Acrylic side appears white, Foil Silicone side appears silver (foil) Silicone Adhesive when liners are removed.
Non-transparent Liner
Figure 8. Attaching the Tape to the Package and Heat Sink
Moldcap Heat Tape: Sink Tape: May be ~ 1"x1” Sq. larger than applied to moldcap or pre- applied by manufacturer
Application Note 653 15 Intel740™ Graphics Accelerator Thermal Design Considerations
Figure 9. Completing the Attach Process
Note: Silicone Adhesive always joins to either the heat sink or the moldcap, the Acrylic Adhesive sides must join to each other (Figure 9).
Note: As every motherboard, system and heat sink combination may introduce variance in attach strength, it is generally recommended that the user carefully evaluate the reliability of tape attaches prior to using in high volume.
For the Tape described in Appendix A, “Sources,” the recommended two-piece attach procedure is as follows: 1. Ensure that the surface of the component and heat sink are free from contamination. Use a clean, lint-free wipe, proper safety precautions and Isopropyl Alcohol to ensure cleanliness. 2. Cut tape to size. Suggestions for the appropriate size can be seen in Figure 8. 3. Heat Sink Side: Remove the non-transparent liner. You will see foil underneath (Figure 7). Apply the tape to the center of the heat sink and smooth over the entire surface using moderate pressure. There should be no air bubbles under the tape. 4. Component Side: Remove the non-transparent liner. You will see foil underneath (Figure 7). Apply the tape to the center of the mold cap and smooth over the entire surface using moderate pressure. There should be no air bubbles under the tape. 5. Both Sides: Remove the clear liners from each side, center the heat sink over the component and apply using any one of the manufacturer’s recommended temperature/pressure options shown in Table 3.
16 Application Note 653 Intel740™ Graphics Accelerator Thermal Design Considerations
Table 3. Tape Attach Application Temperature/Pressure Option
Pressure Temperature Time
10 psi (0.069 mPa) 22°C 15 seconds 30 psi (0.207 mPa) 22°C 5 seconds 10 psi (0.069 mPa) 50-65°C 5 seconds 30 psi (0.207 mPa) 50-65°C 3 seconds
NOTE: Approximately 70% of the ultimate adhesion bond strength is achieved with initial application, 80-90% of the ultimate adhesion bond is achieved within 15 minutes and ultimate adhesion strength is achieved within 36 hours.
4.2.3.4 Reliability
As every motherboard, system, heat sink and attach-process combination may introduce variance in attach strength, it is generally recommended that the user carefully evaluate the reliability of the completed assembly prior to use in high volume. Some Test recommendations can be shown in Table 4.
Table 4. Reliability Validation
Test1 Requirement Pass/Fail Criteria2
50G, board level Mechanical Shock Visual Check 11 msec, 3 shocks/direction 7.3 G, board level Random Vibration Visual Check 45 minutes/axis, 50 to 2000 Hz 85°C, 2000 hours total, checkpoints occur at 168, 500, Temperature Life Visual Check 1000 and 2000 hours -5°C to +70°C Thermal Cycling Visual Check 500 Cycles 85% relative humidity Humidity Visual Check 55°C, 1000 hours
NOTES: 1. The above tests should be performed on a sample size of at least 12 assemblies from 3 lots of material. 2. Additional Pass/Fail Criteria may be added at the discretion of the user.
4.3 Thermal Interface Management for Heat Sink Solutions
For solutions where a heat sink is preferred, to optimize the heat sink design for Intel740 graphics accelerator, it is important to understand the impact of factors related to the interface between the mold-cap and the heat sink base. Specifically, the bond line thickness, interface material area and interface material thermal conductivity should be managed to realize the most effective heat-sink solution.
Application Note 653 17 Intel740™ Graphics Accelerator Thermal Design Considerations
4.3.1 Bond Line Management
The gap between the mold-cap and the heat sink base will impact heat-sink solution performance. The larger the gap between the two surfaces, the greater the thermal resistance. The thickness of the gap is determined by the flatness of both the heat sink base and the mold-cap, plus the thickness of the thermal interface material (e.g., PSA, thermal grease, epoxy) used between these two surfaces.
The Intel740 graphics accelerator mold cap planarity is specified as 0.006 inches maximum (see the Intel740™ Graphics Accelerator Datasheet, order number 290618, for package drawing).
4.3.2 Interface Material Performance
Two factors impact the performance of the interface material between the thermal plate and the heat sink base: • Thermal resistance of the material • Wetting/filling characteristics of the material
Thermal resistance is a description of the ability of the thermal interface material to transfer heat from one surface to another. The higher the thermal resistance, the less efficient an interface is at transferring heat. The thermal resistance of the interface material has a significant impact on the thermal performance of the overall thermal solution. The higher the thermal resistance, the higher the temperature drop across the interface and the more efficient the thermal solution must be.
The wetting/filling of the thermal interface material is its ability to fill the gap between the case and the heat-sink. Since air is an extremely poor thermal conductor, the more completely the interface material fills the gaps, the lower the temperature drop across the interface.
18 Application Note 653 Intel740™ Graphics Accelerator Thermal Design Considerations
5.0 Measurements for Thermal Specifications
To appropriately determine the thermal properties of the system, measurements must be made. Guidelines have been established for the proper techniques to be used when measuring the Intel740 graphics accelerator case temperatures. Section 5.1, “Case Temperature Measurements” on page 19 provides guidelines on how to accurately measure the case temperature of the Intel740 graphics accelerator. Section 5.2, “Power Simulation Software” on page 20 contains information on running an application program which will emulate anticipated thermal design power. The flowchart in Figure 12 as well as Section 4.2, “Thermal Enhancements” on page 10 offer useful guidelines for performance and evaluation.
5.1 Case Temperature Measurements
To ensure functionality and reliability, the Intel740 graphics accelerator is specified for proper operation when Tcase (case temperature) is maintained at or below the maximum case temperatures listed in Table 1. The surface temperature of the case in the geometric center of the mold cap is measured. Special care is required when measuring the Tcase temperature to ensure an accurate temperature measurement.
Thermocouples are often used to measure Tcase. Before any temperature measurements are made, the thermocouples must be calibrated.
When measuring the temperature of a surface which is at a different temperature from the surrounding local ambient air, errors could be introduced in the measurements. The measurement errors could be due to having a poor thermal contact between the thermocouple junction and the surface of the package, heat loss by radiation, convection, by conduction through thermocouple leads, or by contact between the thermocouple cement and the heat-sink base for those solutions which implement a heat-sink. To minimize these measurement errors, the following approach is recommended:
Attaching the Thermocouple • Use 36 gauge or smaller diameter K type thermocouples. • Ensure that the thermocouple has been properly calibrated. • Attach the thermocouple bead or junction to the top surface of the package (case) in the center of the mold-cap using high thermal conductivity cements. An alternative for tape attach users is to use the tape itself to mount the thermocouple. It is Critical that the thermocouple be intimately attached across the entire moldcap. • The thermocouple should be attached at a 0° angle if there is no interference with the thermocouple attach location or leads (refer to Figure 10). This is the preferred method and is recommended for use with both unenhanced packages as well as packages employing Thermal Enhancements. • For solutions where a heat-sink is preferred, the thermocouple should be attached at a 90° angle if a heat sink is attached to the case and the heat sink covers the location specified for Tcase measurement (refer to Figure 11). • The hole size through the heat sink base to route the thermocouple wires out should be smaller than 0.150” in diameter. • Make sure there is no contact between the thermocouple cement and heat sink base. This contact will affect the thermocouple reading.
Application Note 653 19 Intel740™ Graphics Accelerator Thermal Design Considerations
Figure 10. Technique for Measuring Tcase with 0° Angle Attachment
Figure 11. Technique for Measuring Tcase with 90° Angle Attachment
5.2 Power Simulation Software
The power simulation software for the Intel740 graphics accelerator is a utility designed to stress the thermal design power for an Intel740 graphics accelerator when used in conjunction with a Pentium II processor. The combination of the Pentium II processor along with the high bandwidth capability of the new enables new levels of graphics performance which are not utilized in most current software applications. However, it is conceivable that new applications and drivers will be written which take advantage of this increased bandwidth. To ensure the thermal performance of the Intel740 graphics accelerator while running future applications, Intel has developed a software utility which emulates this anticipated power dissipation.
The power simulation software has been developed only for testing Thermal Design Power. Real future applications may exceed the Thermal Design Power limit for transient time periods. For power supply current requirements under these transient conditions, please refer to the Intel740 Graphics Accelerator Datasheet for ICC-740, the Power Supply Current (Max) specification.
Note: Please contact your local Intel representative for more information about the Intel740™ Graphics Accelerator Power Simulation Software.
20 Application Note 653 Intel740™ Graphics Accelerator Thermal Design Considerations
Figure 12.Thermal Enhancement Decision Flowchart
Start
Select Heat Sink. Attach Intel740 graphics (See Section 4.2) accelerator to the motherboard using your normal reflow process
Attach Thermocouples as Attach Thermocouples as described in Section 5.1. described in Section 5.1. Setup system in desired Setup system in desired worst-case configuration worst-case configuration (drives, cards, memory, etc.) (drives, cards, memory, etc.)
Run the Power Software Run the Power Software while monitoring the while monitoring the Intel740 graphics accelerator Intel740 graphics accelerator case temperature. case temperature.
Yes Yes Heat Sink Required Tcase>Y°C? Tcase>X°C? (See Section 4.2)
No No End Heat Sink Not Required
Note: For the latest values of "X°C" and "Y°C", refer to the Power Simulation Software User Guide.
Application Note 653 21 Intel740™ Graphics Accelerator Thermal Design Considerations
6.0 Conclusion
As the complexity of today’s graphics accelerators continues to increase, so do the power dissipation requirements. Care must be taken to ensure that the additional power is properly dissipated. Heat can be dissipated using improved system cooling, selective use of ducting and/or passive heat sinks.
The simplest and most cost effective method is to improve the inherent system cooling characteristics through careful design and placement of fans and ducts. When additional cooling is required, thermal enhancements in conjunction with enhanced system cooling. The size of the fan or heat sink can be varied to balance size and space constraints with acoustic noise. This document has presented the conditions and requirements for properly designing a cooling solution a system implementing the Intel740 graphics accelerator. Properly designed solutions provide adequate cooling to maintain the Intel740 graphics accelerator case temperature at or below those listed in Table 1. This is accomplished by providing a low local ambient temperature and creating a minimal thermal resistance to that local ambient temperature. By maintaining the Intel740 graphics accelerator case temperature at or below those recommended in this document, a system will function properly and reliably.
22 Application Note 653 Appendix A Sources
A.1 Low Profile Fan Heat Sink Sales Locations
Sanyo Denki Please visit WEB at http://www.sanyodenki.co.jp/profile_e17.html
Future Second Source Panasonic
Part Numbers
Sanyo Denki 109P4405H9026
A.2 Low Profile Passive Heat Sink Sales Locations
Thermalloy please visit WEB at: http://www.thermalloy.com
JME please visit WEB at: http://www.jme.com
Part Numbers
Thermalloy 2522B
JME: HAA740BBXXB-001 (with 1-layer Chomerics T410)
HAA740BBXXX-001 (without attach)
A.3 Attach Sales Locations
For Epoxy please visit WEB: http://www.loctite.com Select the country of your choice and Select Products for the Electronics Industry.
For Tape please visit WEB: http://www.chomerics.com/locate
Part Numbers
Loctite Epoxy Part Numbers 383 or 384
Chomerics Tape T-410 Intel740™ Graphics Accelerator Thermal Design Considerations
24 Application Note 653 UNITED STATES AND CANADA Intel Corporation 2200 Mission College Boulevard P.O. Box 58119 Santa Clara, CA 95052-8119 USA Tel: 408-765-8080
EUROPE Intel Corporation (U.K.) Ltd. Pipers Way Swindon Wiltshire SN3 1RJ UK Tel: +44 (0) 1793 403000
ASIA PACIFIC Intel Semiconductor Ltd. 32/F Two Pacific Place 88 Queensway, Central Hong Kong Tel: (852) 844-4555
JAPAN Intel Japan K.K. 5-6 Tokodai, Tsukuba-shi Ibaraki, 300-26 Japan Tel: +81-298-47-8511
SOUTH AMERICA Intel Semicondutores do Brazil LTDA Rua Florida 1703-2 and CJ 22 04565-001-Sao Paulo, SP Brazil Tel: 55-11-5505-2296
FOR MORE INFORMATION To learn more about Intel Corporation visit our site on the World Wide Web at http://www.intel.com/
* Other brands and names are the property of their respective owners.
Printed in USA/0498/PSA
Intel740™ Graphics Accelerator
Application Note: 3 Device AGP System BIOS Design Guidelines
August 1998
Order Number: 290628-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The Intel740 graphics accelerator may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Such errata are not covered by Intel’s warranty. Current characterized errata are available on request. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by: calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
Application Note: 3 Device AGP System BIOS Design Guidelines Contents
1.0 Introduction ...... 1
2.0 Low Power Mode Overview ...... 1 2.1 State Diagrams ...... 2 2.2 Supported Single Monitor and Mulitmonitor Configurations...... 4 2.3 Software Sequence...... 4
Figures
1 Schematic Diagram for GPO27 ...... 2 2 Schematic Diagram for GPO28 ...... 2 3 Intel740™ Graphics Controller (On-board Device) Remains in Low Power Mode ...... 3 4 Intel740™ Graphics Controller (On-board Device) State Diagram ...... 3
Tables
1 Signal Duration of the GPO Signals from PIIX4...... 2 2 Monitor and Mulitmonitor Configurations ...... 4
Application Note: 3 Device AGP System BIOS Design Guidelines iii
1.0 Introduction
For the 3 Device AGP down motherboard design discussed in the Intel740™ Graphics Accelerator Design Guide, Rev 3 (order number 290619), both the video BIOS and support for the 3 Device AGP low power logic must be integrated into the system BIOS. This document details the needed changes to system BIOS to implement the low power logic. Details to incorporate the video BIOS in the system BIOS is beyond the scope of this document.
The on-board AGP device and the AGP add-in card will not be active simultaneously. If an add-in card is present in the AGP slot, the on-board AGP graphics device remains disabled. The system BIOS will provide support for single monitor or multimonitor configurations with or without an AGP graphic device active. The latter is achieved through a CMOS option that will allow the end user, system integrator, or OEM to manually disable the on board Intel740 chip and bypass any enabling events.
2.0 Low Power Mode Overview
Two signals, GPO27# and GPO28#, from the PIIX4E are used in this design. These GPOx signals must be asserted by the system BIOS.
GPO28# is needed to put the Intel740 chip in low power mode. This signal must be asserted sometime after the trailing edge of system RESET (See Figure 2).
GPO27# serves as the hardware reset for the Intel740 chip. A hardware reset to the Intel740 chip takes the device out of the low power state. Since the PCIRST# signal is used to disable the device, it can not be used for this purpose. At the trailing edge of GPO27# the Intel740 chip will be functional (See Figure 1).
The duration of GPO28# and GPO27# are listed in Table 1.
Table 1. Signal Duration of the GPO Signals from PIIX4
Minimum Signal Active Actual Duration* Duration
GP027# from PIIX4 Low (0) 1ms 1ms GP028# from PIIX4 Low (0) =SUM 1ms
NOTE: 1. 1 ms is the smallest system BIOS increment of time 2. SUM = The sum of the propagation delaly for the logic depicted in Figure 2.
Application Note 1 Intel740™ Graphics Accelerator 3 Device AGP System BIOS Design Guidelines
Figure 1. Schematic Diagram for GPO27#
Vcc3 4.7 KΩ PIIX4E GPO27# RESET Intel740™ PCIRST# Vcc3 Chip 4.7 KΩ ROMA16 D Q OE#
PCICLK3 Q# IN1 OUT1
Figure 2. Schematic Diagram for GPO28#
Vcc3 Vcc3 2.2 KΩ TEST OE# OUT1 WEB# D Q IN1 OUT2 IN2 OUT3 SCASB# Intel740™ SRASB# Chip SYSCLK CLR# IN3 OUT4 IN4 OUT5 CS0B# IN5 OUT6 CS1B# IN6 PIIX4E GPO28#
2.1 State Diagrams
At system RESET, the Intel740™ graphics controller on the motherboard is always put into the low power state. The following are examples in which the on-board device shall remain in low power state: 1. AGP add-in card is present 2. PCI or ISA graphics device is the primary and only graphics device desired 3. Multimonitor configurations not utilizing the on-board graphics device
For example 2 and 3 above, an option should be provided in system BIOS or CMOS setup to keep the Intel740™ chip in low power mode.
Note: When not in use, both GPO27# and GPO28# should be driven high (1).
2 Application Note Intel740™ Graphics Accelerator 3 Device AGP System BIOS Design Guidelines
Figure 3. Intel740™ Graphics Controller (On-board Device) Remains in Low Power Mode
System Reset
Low Power Mode
Figure 4. Intel740™ Graphics Controller (On-board Device) State Diagram
System Reset
Low Power Mode
Functional Mode
The Intel740 graphics controller down on the motherboard enters the low power mode at system reset. If an enabling event occurs, the device enters the functional mode from the low power mode (see Figure 4).
The following are examples in which functional mode would be invoked: 1. Intel740™ graphics accelerator as the primary and only graphics device 2. Multimonitor configurations utilizing the Intel740™ graphics controller
Application Note 3 Intel740™ Graphics Accelerator 3 Device AGP System BIOS Design Guidelines
2.2 Supported Single Monitor and Mulitmonitor Configurations
Table 2. Monitor and Mulitmonitor Configurations
Configuration Single Monitor Multimonitor
On-Board Primary Graphics AGP Add-in Non AGP Non AGP Non AGP Non AGP Intel740™ Device Card (PCI or ISA) (PCI or ISA) (PCI or ISA) (PCI or ISA) Device Secondary On-Board AGP Add-in Non AGP None None None Graphics Device Intel740 Card (PCI or ISA)
Flow
System RESET (GP028# Yes Yes Yes Yes Yes Yes Asserted to Enter Low Power Mode) GP027# Asserted to PCI or ISA PCI or ISA PCI or ISA Primary Video AGP Add- PCI or ISA card enable the card card card Initialization in initialized initialized Intel740 initialized initialized initialized Chip GP027# asserted to PCI or ISA Secondary Video Does not Does Not Does Not AGP Add-in enable the card(s) Initialization Apply Apply Apply initialized Intel740 initialized Chip
2.3 Software Sequence
The system BIOS has to follow sequence below for enabling the Intel740™ graphics controller (on-board device). The instructions below should be executed early in POST so that the Intel740™ graphics controller (on-board device) is placed in a low power state. 1. Assert GPO28# low for a minimum of 149 ns. 2. Assert GPO28# high. The Intel740™ graphics controller (on-board device) is placed in a low power state after executing this instruction. 3. Enable the 82443BX Device #1 (AGP Bridge) to access the devices behind the bridge. 4. Check whether any devices are present behind the 82443BX Device #1 (AGP Bridge). The check can be performed by checking the Vendor ID and Device ID register for a non 0FFFFh value. 5. If there are any devices present behind the 82443BX Device #1 (AGP Bridge), go to step #8. 6. Assert GP028# low for at least 1us. 7. Assert GP028# high, the Intel740™ Graphics Controller (on-board device) is in a normal operating state after executing this instruction. 8. Re-program the 82443BX Device #1 (AGP Bridge) to disable the access to devices behind the bridge. 9. Continue with rest of POST in BIOS.
4 Application Note
Intel around the world
United States and Canada Intel Corporation Robert Noyce Building 2200 Mission College Boulevard P.O. Box 58119 Santa Clara, CA 95052-8119 USA Phone: (800) 628-8686
Europe Intel Corporation (U.K.) Ltd. Pipers Way Swindon Wiltshire SN3 1RJ UK
Phone: England (44) 1793 403 000 Germany (49) 89 99143 0 France (33) 1 4571 7171 Italy (39) 2 575 441 Israel (972) 2 589 7111 Netherlands (31) 10 286 6111 Sweden (46) 8 705 5600
Asia Pacific Intel Semiconductor Ltd. 32/F Two Pacific Place 88 Queensway, Central Hong Kong, SAR Phone: (852) 2844 4555
Japan Intel Kabushiki Kaisha P.O. Box 115 Tsukuba-gakuen 5-6 Tokodai, Tsukuba-shi Ibaraki-ken 305 Japan Phone: (81) 298 47 8522
South America Intel Semicondutores do Brazil Rua Florida 1703-2 and CJ22 CEP 04565-001 Sao Paulo-SP Brazil Phone: (55) 11 5505 2296
For More Information To learn more about Intel Corporation, visit our site on the World Wide Web at www.intel.com B Reference Information
PC SGRAM Specification
Revision 0.9
February 1998
Order Number: Not Applicable THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
Copyright © Intel Corporation 1996, 1997.
*Third-party brands and names are the property of their respective owners.
Revision 0.9 Contents
1.0 Introduction ...... 1 1.1 Objective ...... 1 1.2 Scope of This Document...... 1 1.3 Convention Used ...... 1 2.0 Pinout...... 2 2.1 Pin Functional Descriptions (Simplified) ...... 4 3.0 Control Registers ...... 5 3.1 Mode Register and Modes Required to be Supported...... 5 3.2 Special Mode Register...... 5 3.3 Color Register...... 6 4.0 Command Truth Table...... 7
5.0 Operative Command Table...... 8
6.0 Row/Column Addressing Per Memory Size/# Banks...... 13
7.0 Functional Description ...... 14 7.1 Power Up Sequence ...... 14 7.2 Precharge Selected Bank ...... 15 7.3 Precharge All ...... 15 7.4 NOP and Device Deselect ...... 15 7.5 Row activate ...... 15 7.6 Read Bank ...... 15 7.7 Write Bank ...... 15 7.8 Block Write...... 16 7.9 Mode Register Set ...... 16 7.10 Power Down Mode...... 17 8.0 Essential Functionality for the “PC SGRAM” device ...... 18 8.1 Burst Read and Burst Write ...... 18 8.2 Multi- bank ping pong access ...... 18 8.3 Read and Write with autoprecharge ...... 18 8.3.1 Precharge Command After a Burst Read ...... 18 8.3.1.1 Precharge Termination of a Burst Read ...... 19 8.3.1.2 Precharge Command After a Burst Write ...... 19 8.3.1.3 Precharge Termination of a Burst Write...... 19 8.3.2 Read Terminated By Read ...... 19 8.3.3 Write Terminated By Write...... 19 8.3.4 Read Terminated By Write...... 19 8.3.5 Write Terminated By Read...... 19 8.4 Back to Back Command Support...... 20 8.5 Auto Refresh (CBR) Command ...... 20
Revision 0.9 iii 9.0 SGRAM AC/DC Parameters...... 21 9.1 DC Specifications for 100-166 MHz...... 21 9.2 A.C. Specifications for 100-166 MHz...... 21 9.3 A.C. Timing Parameters for 100-166 MHz...... 22 9.4 DC Specifications for 166-250 MHz...... 23 9.5 A.C. Specifications for 166-250 MHz...... 23 9.6 A.C. Timing Parameters for 166-250 MHz...... 23 9.7 IBIS: I/V Characteristics for Input and Output Buffers ...... 24 9.8 IBIS Reference ...... 25 Figures
1 256kx32 SGRAM Pinout...... 2 2 512kx32 SGRAM Pinout...... 3 3 Power Up Initialization Sequence ...... 14 4 Mode Register Set Command ...... 16 5 Timing for Power Down Mode ...... 17 6 A.C Timing Parameters ...... 24 Tables
1 Pin Functional Description ...... 4 2 Mode Register Description ...... 5 3 Special Mode Register...... 5 4 Color Register...... 6 5 Command Truth Table...... 7 6 DQM Truth Table ...... 7 7 Operative Command Table...... 8 8 Row, Column and Bank addressing ...... 13 9 Absolute Maximum D.C. Rating...... 21 10 D.C Operating Requirements ...... 21 11 Maximum AC Operating Requirements ...... 21 12 Refresh Rate...... 22 13 100, 125, 143MHz & 166MHz AC Timing Parameters ...... 22 14 166, 200, 250 MHz & 166 MHz AC Timing Parameters ...... 23
iv Revision 0.9 1.0 Introduction
1.1 Objective
The objective of this document is to define a SGRAM specification (“PC SGRAM”). It should be easy to design and manufacture and highly cost optimized for the main stream volume desktop Graphics architecture PCs.
1.2 Scope of This Document
The scope of this document is limited to identify and define all the essential functionality that is needed to be implemented for “PC SGRAM”. Implementation details are left to the designers of the device.
1.3 Convention Used
• # sign after signals are used after the signal names for active low signals (e.g., CS#, RAS#, etc.)
Revision 0.9 1 PC SGRAM Specification
2.0 Pinout
The pinout for 8Mb and 16Mb SGRAM configurations are shown below.
Figure 1. 256kx32 SGRAM Pinout NC DQ26 VssQ VssQ DQ13 VssQ DQ28 DQ27 DQ25 DQ24 DQ15 DQ14 DQ12 DQ11 DQ10 VddQ VddQ VddQ VddQ VREF DM3 DM1 A8(AP) Vss Vdd CLK CKE DQ9 DQ8 DSF 80 79 78 77 76 75 74 73 72 71 70 69 68 67 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQ29 81 66 65 50 A7 VssQ 82 49 A6 DQ30 83 48 A5 DQ31 84 47 A4 Vss 85 46 Vss NC 86 100 pin PQFP package 45 NC NC 87 44 NC NC 88 43 NC NC 89 42 NC NC 90 Dimension: 41 NC NC 91 40 NC NC 92 14mm x 20mm x 1.4mm 39 NC NC 93 38 NC NC 94 37 NC NC 95 36 NC Vdd 96 35 Vdd DQ0 97 34 A3 DQ1 98 33 A2 VssQ 99 32 A1 10 DQ2 100 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A0 2 5 8 9 1 3 4 6 7 NC Vss Vdd VssQ A9/BS DQ3 VssQ DQ16 DQ17 VssQ DQ18 DQ19 DQ20 DQ21 DQ4 DQ5 DQ6 DQ7 DQ22 DQ23 VddQ VddQ VddQ VddQ WE DM0 DM2 CAS RAS CS
2 Revision 0.9 PC SGRAM Specification
Figure 2. 512kx32 SGRAM Pinout NC VssQ DQ26 VssQ VssQ DQ13 DQ11 DQ10 DQ28 DQ27 DQ25 DQ24 DQ15 DQ14 DQ12 VddQ VddQ VREF VddQ VddQ DM3 DM1 A9(AP) Vss Vdd CLK CKE DQ9 DQ8 DSF 76 75 69 68 63 62 56 55 80 79 78 77 74 73 72 71 70 67 64 61 60 59 58 57 54 53 52 51 DQ29 81 66 65 50 A7 VssQ 82 49 A6 DQ30 83 48 A5 DQ31 84 47 A4 Vss 85 46 Vss NC 86 100 pin TQFP package 45 NC NC 87 44 NC NC 88 43 NC NC 89 42 NC NC 90 Dimension: 41 NC NC 91 40 NC NC 92 14mm x 20mm x 1.4mm 39 NC NC 93 38 NC NC 94 37 NC NC 95 36 NC Vdd 96 35 Vdd DQ0 97 34 A3 DQ1 98 33 A2 VssQ 99 32 A1 10 DQ2 100 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A0 2 5 8 9 1 3 4 6 7 Vss Vdd VssQ DQ3 VssQ DQ16 DQ17 VssQ DQ18 DQ19 DQ20 DQ21 DQ4 DQ5 DQ6 DQ7 DQ22 DQ23 VddQ VddQ VddQ VddQ WE DM2 DM0 CAS RAS CS A10/BS A9/A8
Revision 0.9 3 PC SGRAM Specification
2.1 Pin Functional Descriptions (Simplified)
Table 1. Pin Functional Description
Symbol Type Descriptiona
A[9:0] Input - Synchronous Address. Multiplexed Row and Column Address. BA Input - Synchronous Bank Address. BA0 and BA1 specify the selected Bank during AP Input - Synchronous Auto Precharge (Multiplexed with Row Address). CLK Input - Clock Clock Input Activates the CLK signal when high and deactivates when low. By CKE Input - Clock Enable deactivating the clock, CLKE low initiates the Power Down mode. Chip Select. Disables or enables the device operation by masking or CS# Input - Synchronous enabling all inputs except CLK, CLK#, CKE, DQS, DQ and DM. RAS# Input - Synchronous Row address strobe. CAS# Input - Synchronous Column address strobe. WE# Input - Synchronous Write Enable. DQ Mask. Write data byte mask, Read output byte enables Active high. Read latency is two cycle from DQM and zero cycle for write. In write mode it masks the data from being written to the memory array. DM DQM[3:0] Input masking occurs in the same cycle during write operation. Write data byte mask, Read output byte enables. DQM is synchronous to the clock; thus, the masking occurs for the whole clock. DQ[31:0] Input/Output Data IO pins. DFS: Enables the write per bit and Block write function. This pin has an DSF Input - Synchronus internal pull-down resistor. Vcc, Vss Power pins Supply Pins for the core VccQ, Power pins Supply Pins for the output buffers VssQ
a. See the Truth Table and functional description for detailed information about the functionality
4 Revision 0.9 PC SGRAM Specification
3.0 Control Registers
3.1 Mode Register and Modes Required to be Supported
PC SGRAM’s mode register is accessed through the Mode Register Write command. The Mode Register is used to load the value of CAS Latency, Burst Type, & Burst Length
Table 2. Mode Register Description
Bit Attribute Description
BA Reserved Reserved: For normal operation, BA[1:0] should be “0” A[9:7] Reserved Reserved: For normal operation, A[9:7] should be “000” CAS Latency: 000 Reserved 001 Reserved 010 2 A[6:4] WO 011 3 100 Reserved 101 Reserved 110 Reserved 111 Reserved Burst Type: A[3:0] WO 0 = Sequential 1 = Interleave Burst Length: BT=0 BT=1 000 1 1 001 2 2 010 4 4 A[2:0} WO 011 8 8 100 Reserved Reserved 101 Reserved Reserved 110 Reserved Reserved 111 Full Page Reserved
3.2 Special Mode Register
SGRAM’s Special Mode Register is accessed through the Mode Register Write command. The Special Mode Register is used to load data into the Color Register or the Mask register. During the execution of the Special Mode Register Command, Bits A[6:5] determine if a new value is to be loaded into the Color and Mask registers.
Table 3. Special Mode Register
Bit Attribute Description
Color Register: A[6] WO 0 = Leave data unchanged for Color Register 1 = Load new data into Color Register A[5:0] Reserved Reserved: For normal operation, these bits should always be “00000”
Revision 0.9 5 PC SGRAM Specification
3.3 Color Register
Data is loaded into the Color Register through the Special Mode Register Write command. During the execution of the Special Mode Register Command, bit A[6] is used to determine if a new value is to be loaded into the Mask registers. If A[6] =1 during the special mode register command, then the value on DQ[31:0] is loaded into the Color Register. The color register supplies data for the block write command.
Table 4. Color Register
Bit Default Attribute Description
Color Register Data: Data from these bits is used for Block 31:0 00000000h WO Write Command.
6 Revision 0.9 PC SGRAM Specification
4.0 Command Truth Table
Table 5. Command Truth Table
Function Symbol Command & Address
A8/ BA0, CS# RAS# CAS# WE# DSF DQM A[7:0] A9 BA1
Data for Mode Register MRSLL LLLxxMode x Write Register. Special Mode Data for SMRWR L L L L H x x x Register Write SMR CBR Refresh CBR L L L H L x x x x Activate (Single Row Bank ACT L L H H L x v Bank) Address Address Column Bank Block Write BLKWR L H L L H x v Address Address Column Bank Write WRITELHLLLxv Address Address Write with Auto- Column Bank WRITEAP L H L L L H v precharge Address Address Column Bank Read READ L H L H L L x Address Address Read with Auto- Column Bank READAPLHLHLHx precharge Address Address Burst Stop BST L H H L L x x x x Precharge select Bank PRELL HLLLx x Bank Address Precharge All PA L L L L H L L H x x x Banks No Operation NOP L H H H L x x x x Device DeselectDSELHx xxxxx x x
Table 6. DQM Truth Table
CKE CKE Function DQMx n-1 n
Data write/output enable H X L Data mask/output disable H X H Byte x write mask H X H
NOTE: H: High Level, L: Low Level, X: don’t care, V: Valid data input
Revision 0.9 7 PC SGRAM Specification
5.0 Operative Command Table
Table 7. Operative Command Table
Current CS# RAS# CAS# WE# DSF Address Command Action Notes state Nop or Power Idle H X X X L X DSEL 3 Down Nop or Power LHHHL X NOP 3 Down BA,CA, READ/ LH L H L ILLEGAL 4 A8/A9 READAP BA,CA, WRITE/ LH L L L ILLEGAL 4 A8/A9 WRITEAP L H L L H BA,CA BLKWR ILLEGAL 4 L L H H L BA,RA ACT Row Active BA, LL H L L PRE/PALL NOP A8/A9 Refresh or Self L L L H L X CBR/SELF 5 refresh Mode Register L L L L L Op-code MRS access Special Mode L L L L H Op-code SMRWR Register Write Row active H X X X X X DSEL NOP LHHHL X NOPNOP BA,CA, READ/ Begin read: LH L H L 6 A8/A9 READAP Optional AP BA,CA, WRITE/ Begin write: LH L L L 6 A8/A9 WRITEAP Optional AP Begin Block L H L L H BA,CA BLKWR 6 write: L L H H L BA,RA ACT ILLEGAL 4 BA, LL H L L PRE/PALL Precharge 7 A8/A9 L L L H L X CBR/SELF ILLEGAL 14 L L L L L OP-code MRS ILLEGAL 14 L L L L H OP-code SMRWR ILLEGAL 14 Continue burst READHXXXXX DSEL to end -> Row active Continue burst LHHHL X NOP to end -> Row active Term burst, BA,CA, READ/ LH L H L new read: 8 A8/A9 READAP Optional AP Term burst, BA,CA, WRITE/ LH L L L new wrtie: 8,9 A8/A9 WRITEAP Optional AP L H L L H BA,CA BLKWR ILLEGAL 8,9 L L H H L BA,RA ACT ILLEGAL 4
8 Revision 0.9 PC SGRAM Specification
Table 7. Operative Command Table
Current CS# RAS# CAS# WE# DSF Address Command Action Notes state Te r m bu r st, L L H L L BA,A8 PRE/PALL precharge L H H L L X BST Term burst L L L H L X CBR/SELF ILLEGAL 14 L L L L L Opcode MRS ILLEGAL 14 L L L L H Opcode SMRWR ILLEGAL 14 Continue burst WRITE H x x x x X DSEL to end ->Write recovering Continue burst LHHHL X NOP to end -> Write recovering Te r m bu r st, BA,CA,A READ/ LH L H L start read: 8,9 8/A9 READAP optional AP Te r m bu r st, BA,CA,A WRIT/ LH L L L new write: 8 8/A9 WRITEAP optional AP LHHLLX BSTILLEGAL L H L L H BA,CA BLKWR ILLEGAL 8 L L H H L BA,RA ACT ILLEGAL 4 BA, Te r m bu r st LL H L L PRE/PALL 10 A8/A9 precharging L L L H L X CBR/SELF ILLEGAL 14 L L L L L Op Code MRS ILLEGAL 14 L L L L H Op Code SMRWR ILLEGAL 14 Read with Continue burst auto HXXXXX DSEL to end -> precharge precharging Continue burst LHHHL X NOP to end -> precharging BA,CA, READ/ LH L H L ILLEGAL 13 A8/A9 READAP BA,CA, WRIT/ LH L L L ILLEGAL 13 A8/A9 WRITEAP L H L L H BA,CA BLKWR ILLEGAL 13 L L H H L BA,RA ACT ILLEGAL 4,13 Current CS# RAS# CAS# WE# DSF Address Command Action Notes state LHHLLX BSTILLEGAL BA, LL H L L PRE/PALL ILLEGAL 4,13 A8/A9 L L L H L X CBR/SELF ILLEGAL 14 L L L L L Opcode MRS ILLEGAL 14 L L L L H Opcode SMRWR ILLEGAL 14 Continue burst Write with to end ->Write auto HXXXXX DSEL recovering precharge with auto precharge
Revision 0.9 9 PC SGRAM Specification
Table 7. Operative Command Table
Current CS# RAS# CAS# WE# DSF Address Command Action Notes state Continue bust to end-> Write LHHHL X NOP recovering with auto precharge BA,CA, READ/ LH L H L ILLEGAL 13 A8/A9 READAP BA,CA, WRIT/ LH L L L ILLEGAL 13 A8/A9 WRITEAP L H L L H BA,CA BLKWR ILLEGAL 13 L L H H L BA,RA ACT ILLEGAL 4,13 L L H L L BA,A8 PRE/PALL ILLEGAL 4,13 L L L H L X CBR/SELF ILLEGAL 14 L L L L L Opcode MRS ILLEGAL 14 L L L L H Opcode SMRWR ILLEGAL 14 NOP- Enter Precharging H X X X X X DSEL Idle after Trp NOP-Enter LHHHL X NOP Idle after Trp BA,CA, READ/ LH L H L ILLEGAL 4,13 A8/A9 READAP BA,CA, WRIT/ LH L L L ILLEGAL 4,13 A8/A9 WRITEAP L H L L H BA,CA BLKWR ILLEGAL 4,13 L L H H L BA,RA ACT ILLEGAL 4,13 LHHLLX BSTILLEGAL BA,A8/ NOP- Enter LL H L L PRE/PALL A9 Idle after Trp L L L H L X CBR/SELF ILLEGAL 14 L L L L L Op Code MRS ILLEGAL 14 L L L L H Op Code SMRWR ILLEGAL 14 NOP- Enter Row HXXXXX DSEL row active activating after Trcd NOP- Enter LHHHL X NOP row active after Trcd BA,CA, READ/ LH L H L ILLEGAL 4,13 A8/A9 READAP BA,CA, WRIT/ LH L L L ILLEGAL 4,13 A8/A9 WRITEAP L H L L H BA,CA BLKWR ILLEGAL 4,13 4,11,1 L L H H L BA,RA ACT ILLEGAL 3 LHHLLX BSTILLEGAL BA, LL H L L PRE/PALL ILLEGAL 4,13 A8/A9 L L L H L X CBR/SELF ILLEGAL 14 L L L L L Opcode MRS ILLEGAL 14 L L L L H Opcode SMRWR ILLEGAL 14
10 Revision 0.9 PC SGRAM Specification
Table 7. Operative Command Table
Current CS# RAS# CAS# WE# DSF Address Command Action Notes state NOP - Enter Write HXXXXX DSEL row active Recovering after Tdpl NOP - Enter LHHHL X NOP row active after Tdpl BA,CA, READ/ Start Read, LH L H L 9 A8/A9 READAP optional AP BA,CA, WRIT/ New Write, LH L L L A8/A9 WRITEAP optional AP L H L L L BA,CA BLKWR Block Write L L H H L BA,RA ACT ILLEGAL 4,13 LHHLLX BSTILLEGAL BA, LL H L L PRE/PALL ILLEGAL 4,14 A8/A9 L L L H L X CBR/SELF ILLEGAL 14 L L L L L Opcode MRS ILLEGAL 14 L L L L H Opcode SMRWR ILLEGAL 14 Write NOP - Enter recovering HXXXXX DSEL precharge with auto after Tdpl precharge NOP - Enter LHHHL X NOP precharge after Tdpl BA,CA, READ/ LH L H L ILLEGAL 4,9,13 A8/A9 READAP Current CS# RAS# CAS# WE# DSF Address Command Action Notes state BA,CA, WRIT/ LH L L L ILLEGAL 4,13 A8/A9 WRITEAP L H L L H BA,CA BLKWR ILLEGAL 4,13 L L H H L BA,RA ACT ILLEGAL 4,13 LHHLLX BSTILLEGAL BA, LL H L L PRE/PALL ILLEGAL 4,14 A8/A9 L L L H L X CBR/SELF ILLEGAL 14 L L L L L Op Code MRS ILLEGAL 14 L L L L H Op Code SMRWR ILLEGAL 14 NOP - Enter Refreshing H X X X X X DSEL idle after trc NOP- Enter LHHHL X NOP idle after trc READ/ LHLXXX ILLEGAL 14 READAP LHHLLX BSTILLEGAL L L H X X X ACT/PRE/PALL ILLEGAL 14 CBR/SELF/ LLLXXX ILLEGAL 14 MRS
Revision 0.9 11 PC SGRAM Specification
Table 7. Operative Command Table
Current CS# RAS# CAS# WE# DSF Address Command Action Notes state Mode NOP - Enter Register HXXXXX DSEL idle after tmrd accessing NOP - Enter LHHHL X NOP idle after tmrd READ/ WRITE/ READAP/ LHLXXX ILLEGAL 14 WRITEAP/ BLKWR LHHLLX BSTILLEGAL ACT/PRE/ PALL/ CBR/ LLXXXX ILLEGAL 14 SELF/MRS/ SMRWR
NOTES: 1. H: High Level, L: Low Level, X: don’t care, V: Valid data input, BA: Bank Address, AP: (Auto Precharge), CA: (Column Address), RA: (Row Address) 2. All entries assume that CKE was active (high level) during the preceding clock cycle. 3. If both banks are idle and CKE is inactive (low level), then in power down mode. 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 5. If both banks are idle and CKE is inactive (low level), then Self refresh mode. 6. Illegal if trcd is not satisfied. 7. Illegal if tras is not satisfied. 8. Must satisfy burst interupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10.Must mask preceding data which don’t satisfy tdpl. 11.Illegal if trrd is not satisfied. 12.Burst Stop command is disabled. 13.Ilegal for single bank, but legal for other banks in multi-bank devices. 14.Illegal for all banks.
12 Revision 0.9 PC SGRAM Specification
6.0 Row/Column Addressing Per Memory Size/# Banks
Table 8. Row, Column and Bank addressing
Parameter 2x128kx32 (8Mb) 2x256kx32 (16Mb)
Bank Address BA BA Row Address A[8:0] A[9:0] Column Address A[7:0] A[7:0] Auto-Precharge A8 A9 Page Size 256x32 256x32
Revision 0.9 13 PC SGRAM Specification
7.0 Functional Description
7.1 Power Up Sequence
The SGRAM should be initialized by the following sequence of operations: • Clock will be applied at power up along with power (clock frequency will be unknown). • The clock will be stabilized within 100usec after power stabilizes. • All the control inputs, RAS#, CAS#, WE#, CS# will be held in an undefined state during reset. After reset is complete RAS#, CAS#, WE#, and CS# will be held inactive before the first access to SGRAM is attempted. • The levels on all the address inputs should be ignored. (All the addresses inputs can be indeterminate.) Initialization Sequence
The initialization sequence can be issued at anytime. Following the initialization sequence, the device must be ready for full functionality. SGRAM devices are initialized by the following sequence: • At least one NOP cycle will be issued after the 1msec device deselect. • A minimum pause of 200usec will be provided after the NOP. • A precharge all (PALL) will be issued to the SGRAM. • 8 Auto refresh (CBR) refresh cycles will be provided. • A mode register set (MRS) cycle will be issued to program the SGRAM parameters (e.g., Burst length, CAS# latency, etc.).
• After MRS, the device should be ready for full functionality within 3 clocks after Tmrd is met. Figure 3. Power Up Initialization Sequence
CKE
Trp Trc Tmrd CLK
A(7:0)
A8/A9
BA
CS#
RAS#
CAS#
WE#
DQM Inputs Stable Precharge 1st. Auto Refresh 8th. Auto Refresh MRS Command Legal Command for 200 usec All Banks (CBR) (CBR)
14 Revision 0.9 PC SGRAM Specification
7.2 Precharge Selected Bank
The precharge operation should be performed on the active bank when precharge selected bank command is issued. When the precharge command is issued with address A8/A9 low, BA selects the bank to be precharged. At the end of the precharge selected bank command the selected bank should be in idle state after the minimum TRP is met.
7.3 Precharge All
All the banks should be precharged at the same time when this command is issued. When the precharge command is issued with address A8/A9 high, then all the banks will be precharged. At the end of the precharge all command all the banks should be in idle state after the minimum TRP is met.
7.4 NOP and Device Deselect
The device should be deselected by deactivating the CS# signal. In this mode SGRAM should ignore all the control inputs. The SGRAM is put in NOP mode when CS# is active and by deactivating RAS#, CAS# and WE#. For both Deselect and NOP the device should finish the current operation when this command is issued.
7.5 Row activate
This command is used to select a row in a specified bank of the device. Read and write operations can only be initiated on this activated bank after the minimum TRCD time is elapsed from the activate command.
7.6 Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS#, CAS# and de-asserting WE# at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
7.7 Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS#, CAS# and WE# at the same clock sampling (rising) edge as described in the command truth table. The length of the burst will be determined by the values programmed during the MRS command.
Revision 0.9 15 PC SGRAM Specification
7.8 Block Write
The Block Write command is used to write a block of data to an active row and bank within the device. The Block Write command is issued by driving CS# low, RAS# high, CAS# low, WE# low and DSF high. A Block Write command is a non-burst write command that writes data to 8 columns simultaneously. The data value contained in the Color Register (CR) is written to eight consecutive column locations addressed by A[7:3].
A Block Write access requires a minimum time of TBWC to execute. No new commands can be executed until TWBC is met except for Activate and Precharge command to the other banks.
7.9 Mode Register Set
This command is used to program the SGRAM for the desired operating mode. This command should be used after power up as defined in the power up sequence before the actual operation of the SGRAM is initiated. The functionality of the SGRAM device can be altered by re- programming the mode register through the execution of Mode Register Set command. All the banks should be precharged (i.e., in idle state) before the MRS command can be issued.
Figure 4. Mode Register Set Command
tRP 2 CLK CLK
CLK#
CMD Pre MSR Wr Act
Addr MSR Data Row
CS#
Mode Register Write (msrwr.td)
16 Revision 0.9 PC SGRAM Specification
7.10 Power Down Mode
The Power down mode for PC SGRAM can be entered when both banks are in idle state (precharged) and CKE is asserted low. When in power down mode all input and output buffers are de-activated (except for CKE). If the device stays in the power down mode for more than 15.6 usec (refresh interval), then the PC SGRAM will loose data.
The power down mode can be exited by driving CKE high again. CKE assertion and de-assertion should meet the CKE setup and hold time (tCKS and tCKH).
Figure 5. Timing for Power Down Mode
Input Buffers Gated
tCKH
tCKS tCKS CLK
CKE
CMD NOP NOP
Revision 0.9 17 PC SGRAM Specification
8.0 Essential Functionality for the “PC SGRAM” device
The functionality that are essential for the “PC SGRAM” device are described below: • Burst Read • Burst Write • Multi bank access • Burst Read with Autoprecharge • Burst Write with Autoprecharge • Burst Read terminated with precharge • Burst Write terminated with precharge • Burst Read terminated with another Burst Read/Write • Burst Write terminated with another Burst Write/Read • DQM masking • Fastest command to command delay of 1 clock • Precharge All command • Auto Refresh • CL=2,3 • Burst Length 1,2, 4 & 8
8.1 Burst Read and Burst Write
Burst read and write commands are initiated as shown in the diagram below. The bank first needs to be activated (if not already activated) through the activate bank command and then the read or write command should be initiated. Read and write is distinguished by the WE# signal state as shown. TRCD (RAS to CAS delay) must be met to initiate a command after the activate command.
8.2 Multi- bank ping pong access
Two bank ping pong access is described in the following diagram. Another bank can be activated while the first bank is being accessed as shown. RAS to RAS delay TRRD must be met while activating another bank.
8.3 Read and Write with autoprecharge
Burst reads and writes with auto precharge commands are initiated with autoprecharge if A8/A9 is to high while the read or write commands are issued.
8.3.1 Precharge Command After a Burst Read
The earliest a precharge command can be issued after a Read command without the loss of data is CL + BL - 2 clocks. The precharge command can be issued as soon as the tras time is met. The earliest time that precharge can be issued is shown for the CAS Latency = 3 devices.
18 Revision 0.9 PC SGRAM Specification
8.3.1.1 Precharge Termination of a Burst Read
Burst Read (with no autoprecharge) can be terminated earlier using a precharge command along with the DQM. This terminates reads when the remaining data elements are not needed. It allows starting the precharge early. The remaining data is undefined. DQM should be used to mask.
8.3.1.2 Precharge Command After a Burst Write
The earliest time that precharge can be issued is TDPL clocks after the last data.
8.3.1.3 Precharge Termination of a Burst Write
To terminate Burst Write early with precharge command DQM signal should be used as shown. Data sampled TDPL clocks before precharge command will be written correctly. Data sampled after and before the precharge command is undefined. DQM should be used to prevent the location from being corrupted.
8.3.2 Read Terminated By Read
A Read Command should terminate the previous read command and the data should be available after CAS Latency for the new command. Fastest command to command delay is determined by TCCD
8.3.3 Write Terminated By Write
A Write Command should terminate the previous write command and the new burst write command should start with the new command as shown. Fastest command to command delay is determined by TCCD .
8.3.4 Read Terminated By Write
A Write Command should terminate the previous read command and the new burst write should start. The DQM must be held active to keep the output buffer in HiZ as shown to prevent the internal IO buffer conflict between the read data (in pipe) and the write data driven on the input pins.
8.3.5 Write Terminated By Read
A Read Command should terminate the previous write command and the new burst read should start as shown. In case of with TCCD =1, CL=3 and tdqz=2, there is no loss of data bandwidth even if DQM is activated to mask the write data.
In the case of CL=2 and tdqz=2, the activation of DQM signal causes the first read data to be lost, if read command is issued (TCCD =1). To preserve the first read data the issue of READ command has to be delayed (TCCD=2). This implementation reduces the command bus utilization. If a Precharge-All command is detected by SGRAM component in CLK(n), then there will be no commands presented to this component until CLK(n+tRP).
bank command.
Revision 0.9 19 PC SGRAM Specification
8.4 Back to Back Command Support
Minimum command to command delay of 1 Clock should be supported.
8.5 Auto Refresh (CBR) Command
An auto refresh (CBR) should be used to refresh the SGRAM array explicitly. Refresh addresses should be generated internally by the SGRAM device and incremented after each auto refresh automatically. No commands (including another auto refresh) should be issued until a minimum TRC is satisfied.
20 Revision 0.9 PC SGRAM Specification
9.0 SGRAM AC/DC Parameters
9.1 DC Specifications for 100-166 MHz
Table 9. Absolute Maximum D.C. Rating
Symbol Parameter Min Max Units Notes
Vin, Vout Voltage on any pin w.r.t VSS -0.5 VDD + 0.5 V VDD, VDDQ Voltage Supply pins pin w.r.t VSS -0.5 4.5 V Ts Storage Temperature -55 125 °C
Table 10. D.C Operating Requirements
Symbol Parameter Condition Min Max Units Notes
VDD Supply Voltage 3.135 3.6 V VDDQ I/O Supply Voltage 3. 135 3.6 V Iil Input Leakage Current 0 < Vin < VDDQ -10 +10 µA1,2 Target Cin Input Pin Capacitance @1MHz 2.5 5.0 pF 3.75pf Target CI/O I/O Pin Capacitance @1MHz 4.0 6.5 pF 5.25pf Target Cclk Pin Capacitance @1MHz 2.5 4.0 pF 3.25pf Lpin Pin Inductance 10 nH 2 Ta Ambient Temperature No Airflow 0 65 °C
NOTES: 1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. 2. This is a recommendation, not an absolute requirement. The actual value should be provided with the component data sheet.
9.2 A.C. Specifications for 100-166 MHz
Table 11. Maximum AC Operating Requirements
Symbol Parameter Min Max Units Notes
Vih Input High Voltage 2.0 VDDQ+2.0 V 1,2 Vil Input Low Voltage VSSQ − 2.0 0.8 V 1,2
NOTES: 1. The overshoot and undershoot voltage duration is <=3ns with no input clamp diodes 2. The VDDQ and VSSQ are the operating parameters (not absolute max. parameters) The refresh rate for all devices is assumed at a maximum of 15.6us per row per the table below.
Revision 0.9 21 PC SGRAM Specification
Table 12. Refresh Rate
Symbol Parameter Min Max Units Notes
Tref Refresh rate / row 15.6 usec 1
NOTE: 1. The overall array refresh is determined by multiplying the specified row refresh rate by the number of rows in the total array.
9.3 A.C. Timing Parameters for 100-166 MHz
Table 13. 100, 125, 143MHz & 166MHz AC Timing Parameters
100 125 143 166
Parameter Symbol Min Max Min Max Min Max Min Max Units
Clock Period tCK 10 8 7 6 ns CAS Latency CL 2 3 2 3 2 3 2 3 CLK T CLK to valid output delay (max) AC 7665.5ns (max)
Output data hold time TOH 2.5 2.5 2.5 2.5 ns Address & Command Input setup T 2.5 2.5 2 1 ns time AS Address & Command Input hold T 11 11 ns time AH
Data Input setup time TDS 2.5 2 1.5 1 ns
Data Input hold time TDH 11 11 ns Activate to Activate Delay (Different T 22 22 CLK bank) RRD Read to Read Command Delay,Write to Write Command TCCD 11 11 CLK Delay Activate to Read, Write or Block T 23 33 CLK Write Delay RCD Precharge to Activate Delay (single T 23 33 CLK bank precharge) RP
Activate to Precharge Delay TRAS 56 77 CLK Activat to Activate Delay (Same T 7 9 10 11 CLK Bank), Refresh Cycle time RC
Block Write to Precharge Delay TBPL 22 22 CLK
Block Write Cycle Time TBWC 22 22 CLK
Last write data in to precharge TDPL 11 11 CLK
NOTE: 1. Output I/O Timings measured with a 30pf load
22 Revision 0.9 PC SGRAM Specification
9.4 DC Specifications for 166-250 MHz
Absolute Maximum D.C. Rating (TBD)
D.C Operating Requirements (TBD)
9.5 A.C. Specifications for 166-250 MHz
Maximum AC Operating Requirements (TBD)
Refresh Rate (TBD)
9.6 A.C. Timing Parameters for 166-250 MHz
Table 14. 166, 200, 250 MHz & 166 MHz AC Timing Parameters
166 200 250
Parameter Symbol Min Max Min Max Min Max Units
Clock Period tCK 65 4 ns CAS Latency CL 2 3 2 3 2 3 CLK T CLK to valid output delay (max) AC 5.5 TBD TBD ns (max)
Output data hold time TOH 2.5 TBD TBD ns
Address & Command Input setup time TAS 1TBDTBDns
Address & Command Input hold time TAH 1TBDTBDns
Data Input setup time TDS 1TBDTBDns
Data Input hold time TDH 1TBDTBDns
Activate to Activate Delay (Different bank) TRRD 2 TBD TBD CLK Read to Read Command Delay,Write to Write T 2 TBD TBD CLK Command Delay CCD
Activate to Read, Write or Block Write Delay TRCD 3 TBD TBD CLK Precharge to Activate Delay (single bank T 3 TBD TBD CLK precharge) RP
Activate to Precharge Delay TRAS 7 TBD TBD CLK Activat to Activate Delay (Same Bank), T 11 TBD TBD CLK Refresh Cycle time RC
Block Write to Precharge Delay TBPL 2 TBD TBD CLK
Block Write Cycle Time TBWC 2 TBD TBD CLK
Last write data in to precharge TDPL 2 TBD TBD CLK
Revision 0.9 23 PC SGRAM Specification
9.7 IBIS: I/V Characteristics for Input and Output Buffers
(TBD)
Figure 6. A.C Timing Parameters
<------tcyc ------> <-----tch------><------tcl------> CLK
|<----tsi---><---thi--->| Inputs
<------tohz------>| <---toh--> <------tac ------>| <----toh--->| outputs
ac_tim.td A.C Timing Parameters
NOTE: 1. Reference level is set at 1.5V, AC measurements are specified into 50pf load. 2. input edge rates are specified as 1.0v/ns minimum (0.8v to 2.0v)
24 Revision 0.9 PC SGRAM Specification
9.8 IBIS Reference
The IBIS Open Forum is an industry-wide forum that controls the official IBIS specification. Minutes of IBIS meetings, email correspondence, proposals for specification changes, etc. are on- line at "vhdl.org". To join in the email discussions, send a message to "[email protected]" and request that your name be added to the IBIS mail reflector. Be sure to include your email address.
To download a copy of the specification, the golden parser, various public-domain models, the IBIS Overview in PostScript, and other information, either phone in by modem or use FTP.
FTP: (IP address 198.31.14.3) login as "anonymous" password is your email address
Modem: (408)945-4170 login as "guest" password is your email address
IBIS-related files are in the directory "/pub/ibis" and its sub-directories.
To get documents by email, send an email message to "[email protected]" with the following commands in the message body:
path
For direct modem access, dial-up to the vhdl.org system at (408) 945-4170. You can use any baud rate up to 14,400, any parity, start and stop bits, and any v.* settings. Log in using the "guest" account. Simple UNIX commands such as "cd", "ls", and "cat" are available and you can download files using "kermit", "zmodem", or "sz" (another zmodem application).
For Internet access, use "ftp vhdl.org" (or "ftp 198.31.14.3") and log in as user "anonymous". The gopher utility is available and highly recommended. Gopher to "vhdl.org". Set "binary" mode for transferring binary files (*.doc, *.fm, *.xls).
The IBIS home page can be found at http://www.eia.org/eig/ibis/ibis.htm
Revision 0.9 25 PC SGRAM Specification
26 Revision 0.9 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics
64-bit (Non-ECC/Parity) 144-pin Module Revision 0.91
February 1998
Order Number: Not Applicable THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
Copyright © Intel Corporation 1996, 1997.
*Third-party brands and names are the property of their respective owners.
Revision 0.91 Contents
1.0 Unbuffered Graphics SO-DIMM Module...... 1 1.1 General Features ...... 1 1.2 Labeling ...... 1 2.0 Mechanical Outline ...... 2 3.0 Environmental Requirements...... 3
4.0 Pin Assignments ...... 4
5.0 Graphics SO-DIMM Block Diagram ...... 5 6.0 Address Translation ...... 9 6.1 Configuration...... 9 6.2 Default Parameters...... 10 6.3 Resistor Strapping Options...... 11 6.3.1 Clock Frequency and Memory Timing ...... 11 6.3.2 CAS Latency ...... 11 6.4 Serial Presence Detect EEPROM...... 11 7.0 Electrical Characteristics...... 12 7.1 15 nS Timing...... 12 7.2 12 nS Timing...... 12 7.3 10 nS Timing...... 13 7.4 8 nS Timing...... 13 7.5 A.C Timing Diagrams...... 14 8.0 PCB Layout Considerations...... 16 8.1 Clock Routing and Chip Selects ...... 17 8.2 Address/Control Routing...... 18 8.3 Data Routing ...... 19 9.0 Electrical Specifications ...... 21 9.1 SDRAM/SGRAM Component Absolute Maximum D.C. Ratings ...... 21 9.2 SDRAM/SGRAM Components D.C. Operating Requirements ...... 21 9.3 SDRAM/SGRAM Components Absolute Maximum A.C. Operating Require- ments21 9.4 Memory Timing ...... 22 A PCB Layout...... 23
Revision 0.91 iii Figures
1 SDRAM SO-DIMM Module ...... 2 2 256K/512 x 64 SGRAM SO-DIMM Block Diagram (1 bank of two 256K/512K x 32) ...... 5 3 512K/1M x 64 SGRAM SO-DIMM Block Diagram (2 banks of two 256K/512K x 32)...... 6 4 256K/512K x 32 SGRAM SO-DIMM Block Diagram (1 bank of one 256K/512K x 32) ...... 7 5 512K/1M x 32 SGRAM SO-DIMM Block Diagram (2 banks of one 256K/512K x 32) ...... 8 6 Address/Control A.C. Timing Parameters...... 14 7 Data Write A.C. Timing Parameters ...... 14 8 Data Read A.C. Timing Paramters ...... 15 9 T-Topology Clock Routing ...... 17 10 Address and Control Routing...... 18 11 Data Routing...... 19 12 Silk Screen - Primary Side...... 23 13 Silk Screen - Secondary Side ...... 23 14 Primary Side (layer 1) ...... 24 15 VCC Plane (layer 2)...... 24 16 Inner-Signal (layer 3) ...... 25 17 Inner-Signal (layer 4) ...... 25 18 Ground Plane (layer 5) ...... 26 19 Secondary Side (layer 6) ...... 26 Tables
1 Environmental Requirements ...... 3 2 SO-DIMM Module Pin Assignments ...... 4 3 Address Translation...... 9 4 Module Baseline Component Requirements ...... 10 5 Signal Loading ...... 16 6 Stub Lengths (Clock and Chip Select Routing) ...... 17 7 Stub Lengths (Address/Control Routing) ...... 18 8 Byte Ordering...... 19 9 Stub Lengths (Data Line Routing) ...... 20 10 Absolute Maximum Ratings ...... 21 11 D.C. Operating Requirements ...... 21 12 Absolute Maximum A.C. Operating Requirements ...... 21
iv Revision 0.91 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics
1.0 Unbuffered Graphics SO-DIMM Module
1.1 General Features
• 144-pin, small-outline, dual-in-line memory module (SO-DIMM). • 64-bit data bus (non-ECC/Parity) • Maximum of 8MB per module with extensions to 32MB • SDRAM/SGRAM • Single, 3.3V ±10% power supply • LVTTL-compatible inputs and outputs • Specification currently defines four module frequencies (speeds); 66 MHz (15 nS), 83 MHz (12 nS), 100 MHz (10 nS), and 125 MHz (8 nS).
1.2 Labeling
Four module frequencies are currently defined; they are: • 66 MHz (15 nS). • 83 MHz (12 nS). • 100 MHz (10 nS). • 125 MHz (8 nS).
For consistency, modules should be clearly marked indicating their rated frequency in MHz. The speed, in nano-seconds, is optional. This label should be consistent with the module speed setting used in the resistor strapping option.
To be compliant, a module must meet at least one complete table in the Memory Timing section of the “PC SGRAM” specification.
Revision 0.91 1 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics
2.0 Mechanical Outline
• Dimensions: 67.6 mm (length) X 25.4-50.8 mm (height) X 1.0 mm (thickness) • 144-pin (0.8 mm pitch zig-zag)
For mechanical specifications of SO-DIMM modules, refer to the JEDEC Committee Ballot
JC-42.5-95-171 144-pin SDRAM SO-DIMM Item 708.4 (herein referred to as the JEDEC SO-DIMM specification).
The key position has been shifted to prevent this module from being inserted into a typical main- memory SDRAM socket.
Figure 1. SDRAM SO-DIMM Module
100-pin 100-pin PQFP PQFP or or S TQFP TQFP P D
Pin 50 A000.vsd
2 Revision 0.91 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics
3.0 Environmental Requirements
Table 1. Environmental Requirements
Operating Temperature 0oC to +65oC Operating Humidity 10% to 90% relative humidity, noncondensing Operating Pressure 10.106 PSI (up to 10,000 ft.) Storage Temperature -40oC to +70oC Storage Humidity 5% to 95% without condensation Storage Pressure 1.682 PSI (up to 50,000 ft.) at 50oC
Revision 0.91 3 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics
4.0 Pin Assignments
Table 2. SO-DIMM Module Pin Assignments
PIN # Front PIN # Back PIN # Front PIN # Back
1 Vss 2 Vss 73 CLK1 74 CLK0 3 DQ63 4 DQ62 75 Vcc 76 Vcc 5 DQ61 6 DQ60 77 RSVD 78 RSVD 7 DQ59 8 DQ58 79 RSVD (A11) 801 A10 9 DQ57 10 DQ56 811 A9 821 A8 11 Vcc 12 Vcc 83 A7 84 A6 13 DQ55 14 DQ54 85 Vss 86 Vss 15 DQ53 16 DQ52 87 A5 88 A4 17 DQ51 18 DQ50 89 A3 90 A2 19 DQ49 20 DQ48 91 A1 92 A0 21 Vss 22 Vss 93 Vcc 94 Vcc 23 DQMB7 24 DQMB6 95 DQ31 96 DQ30 25 DQMB5 26 DQMB4 97 DQ29 98 DQ28 27 Vcc 28 Vcc 99 DQ27 100 DQ26 29 DQ47 30 DQ46 101 DQ25 102 DQ24 31 DQ45 32 DQ44 103 Vss 104 Vss 33 DQ43 34 DQ42 105 DQ23 106 DQ22 35 DQ41 36 DQ40 107 DQ21 108 DQ20 37 Vss 38 Vss 109 DQ19 110 DQ18 39 DQ39 40 DQ38 111 DQ17 112 DQ16 41 DQ37 42 DQ36 113 Vcc 114 Vcc 43 DQ35 44 DQ34 115 DQMB3 116 DQMB2 45 DQ33 46 DQ32 117 DQMB1 118 DQMB0 47 Vcc 48 Vcc 119 Vss 120 Vss 49 RSVD 50 RSVD 121 DQ15 122 DQ14 51 RSVD 52 RSVD 123 DQ13 124 DQ12 53 RSVD 54 RSVD 125 DQ11 126 DQ10 55 Vss 56 Vss 127 DQ9 128 DQ8 57 DSF 58 RFU 129 Vcc 130 Vcc 59 RFU 60 RFU 131 DQ7 132 DQ6 61 RFU 62 SBA 133 DQ5 134 DQ4 63 Vcc 64 Vcc 135 DQ3 136 DQ2 65 CS1 66 CS0 137 DQ1 138 DQ0 67 /RAS 68 /CAS 139 Vss 140 Vss 69 /WE 70 CKE 141 SDA 142 SCL 71 Vss 72 Vss 143 Vcc 144 Vcc
NOTE: 1. Refer to Table 3 “Address Translation” on page 9 for determining SO-DIMM to SGRAM device (256Kx32 or 512Kx32) connections for pins 80, 81 and 82.
4 Revision 0.91 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics
5.0 Graphics SO-DIMM Block Diagram
Figure 2 through Figure 5 illustrate the electrical connectivity of several SO-DIMM configurations. The series termination resistors on CLK0 and CLK1 are not currently used and should be set to 0 ohms. Table 3 “Address Translation” on page 9 should be followed for connecting 256Kx32 and 512Kx32 devices.
Figure 2. 256K/512 x 64 SGRAM SO-DIMM Block Diagram (1 bank of two 256K/512K x 32)
CS0
CS CS DQM0 DQM4 DQ[7:0] DQ[39:32]
DQM1 DQM5 D0 D1 DQ[15:8] DQ[47:40]
512Kx32 512Kx32 DQM2 Or DQM6 Or DQ[23:16] 256Kx32 DQ[55:48] 256Kx32 SGRAM SGRAM
DQM3 DQM7
DQ[31:24] DQ[63:56]
CKE D0 to D1 SCL Serial /RAS D0 to D1 PD (optional) /CAS D0 to D1 VSS A2 SDA /WE D0 to D1 A1 DSF D0 to D1
SBA A0 A[10:0] D0 to D1
VCC D0 to D1 Three bypass capacitors per CLK0 D0, D1 SGRAM device (refer to component section).
VSS D0 to D1
A001.vsd
Revision 0.91 5 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics
Figure 3. 512K/1M x 64 SGRAM SO-DIMM Block Diagram (2 banks of two 256K/512K x 32)
CS1 CS0
CS CS CS CS DQM0 DQM4 DQ[7:0] DQ[39:32]
DQM1 DQM5 D0 D2 D1 D3 DQ[15:8] DQ[47:40]
512Kx32 512Kx32 512Kx32 512Kx32 DQM2 Or Or DQM6 Or Or DQ[23:16] 256Kx32 256Kx32 DQ[55:48] 256Kx32 256Kx32 SGRAM SGRAM SGRAM SGRAM
DQM3 DQM7 DQ[31:24] DQ[63:56]
CKE D0 to D3 SCL Serial /RAS D0 to D3 PD (optional) /CAS D0 to D3 VSS A2 SDA /WE D0 to D3 A1 DSF D0 to D3 SBA A0 A[10:0] D0 to D3
VCC D0 to D3 Three bypass capacitors per CLK0 D0, D1 SGRAM device (refer to component section). CLK1 D2, D3 VSS D0 to D3
A002.vsd
6 Revision 0.91 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics
Figure 4. 256K/512K x 32 SGRAM SO-DIMM Block Diagram (1 bank of one 256K/512K x 32)
CS0
CS DQM0
DQ[7:0]
DQM1 D0 DQ[15:8]
512Kx32 DQM2 Or DQ[23:16] 256Kx32 SGRAM
DQM3
DQ[31:24]
CKE D0
SCL Serial /RAS D0 PD (optional) /CAS D0 VSS A2 SDA /WE D0
A1 DSF D0
SBA A0 A[10:0] D0
VCC D0 Three bypass capacitors per CLK0 D0 SGRAM device (refer to component section).
VSS D0
A003.vsd
Revision 0.91 7 SO-DIMM Module — Unbuffered SDRAM/SGRAM Graphics
Figure 5. 512K/1M x 32 SGRAM SO-DIMM Block Diagram (2 banks of one 256K/512K x 32)
CS1 CS0
CS CS DQM0 DQ[7:0]
DQM1 D0 D1 DQ[15:8]
512Kx32 512Kx32 DQM2 Or Or DQ[23:16] 256Kx32 256Kx32 SGRAM SGRAM
DQM3 DQ[31:24]
CKE D0 to D1 SCL Serial /RAS D0 to D1 PD (optional) /CAS D0 to D1 VSS A2 SDA /WE D0 to D1 A1 DSF D0 to D1 SBA A0 A[10:0] D0 to D1
VCC D0 to D1 Three bypass capacitors per CLK0 D0, D1 SGRAM device (refer to component section).
VSS D0 to D1
A004.vsd
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6.0 Address Translation
Table 3 should be followed for 256Kx32 and 512Kx32 SGRAM devices. This table specifies the SGRAM device to SO-DIMM connector connections for a 256Kx32 and 512Kx32 devices.
Table 3. Address Translation
SODIMM 256Kx32 512Kx32
Pin # Functionality Pin # Functionality Pin # Functionality
92 A0 31 A0 31 A0 91 A1 32 A1 32 A1 90 A2 33 A2 33 A2 89 A3 34 A3 34 A3 88 A4 47 A4 47 A4 87 A5 48 A5 48 A5 84 A6 49 A6 49 A6 83 A7 50 A7 50 A7 82 A8 51 A8/AP 51 A9/AP 81 A9 29 A9/BA 29 A10/BA 80 A10 No Connect No Connect 30 A8 79 A11/Reserved No Connect No Connect No Connect No Connect
NOTES: 1. The names for pin 80, 81 and 82 are different for 256Kx32 and 512Kx32 device connection. 2. SO-DIMM’s pin 80 (which is labeled as A10) is a no connect for 256Kx32 device and is connected to pin 30 (labeled as A8) of 512Kx32 device. 3. SO-DIMM’s pin 81 (which is labeled as A9) is connected to pin 29 (labeled as A9/BA) of 256Kx32 device and is connected to pin 29 (labeled as A10/BA) of 512Kx32 device 4. SO-DIMM’s pin 82 (which is labeled as A8) is connected to pin 51 (labeled as A8/BA) of 256Kx32 device and is connected to pin 51 (labeled as A9/AP) of 512Kx32 device.
6.1 Configuration
Graphic controllers can determine the module capabilities one of three ways; they are: • Using the default parameters with power-up testing • Using resistor strapping options on the data lines • Using an optional Serial Presence Detect EEPROM
Modules are required to include resistor support (3 resistors); the Serial Presence Detect EEPROM is optional.
6.2 Default Parameters
All memory modules must meets these baseline component requirements.
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Table 4. Module Baseline Component Requirements
Parameter Min. Max. Unit Notes
Clock Period 15.0 nS Clock High Time 5.0 nS Rated @ 1.4V Clock Low Time 5.0 nS DQM#/CS# Input Setup Time 3.0 nS Other Input Setup Time 3.0 nS DQM#/CS# Input Hold Time 1.0 nS Other Input Hold Time 1.0 nS Output Valid from Clock 11.0 nS Rated @ 30pf Output Hold from Clock 2.5 nS Rated @ 30pf CAS Latency 2 2 Tclk CAS to CAS Delay 1 Tclk CAS Bank Delay 1 Tclk CKE to Clock Disable 1 1 Tclk RAS Precharge Time 3 Tclk RAS Active Time 4 Tclk Activate to Command Delay (RAS to CAS Delay) 2 Tclk RAS to RAS Bank Activate Delay 2 Tclk RAS Cycle Time 7 Tclk DQM to Input Data Delay 0 0 Tclk Write Cmd. to Input Data Delay 0 0 Tclk Mode Register set to Active delay 3 Tclk Precharge to O/P in High-Z 2 Tclk DQM to Data in HiZ for read 2 2 Tclk Data in to Precharge 2 Tclk Data in to Activate/Refresh 5 Tclk DQM to Data mask for write 0 0 Tclk Number of Banks per SDRAM/SGRAM device 2 2 Banks
Module should follow the AC timings specified in the “PC SGRAM” specification.
The graphic controller must assume that the memory is SDRAM unless it can determine that SGRAM functions (block write and write-per-bit) are available. This can be done at power-up using the DSF pin. Modules which do not support SGRAM special functions must disable the DSF pin.
The graphic device must determine the data width of the module, number of row addresses, and number of column addresses.
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6.3 Resistor Strapping Options
Three resistor straps are used to indicate the synchronous clock frequency (period) and memory timing. Timing information for each clock frequency is indicated in the section titled Memory Timing. Memory modules must meet all timing requirements within the specified operating environment.
6.3.1 Clock Frequency and Memory Timing
Cycle Time DQ30 DQ29
15 nS 0 0 12 nS 0 1 10 nS 1 0 8 nS 1 1
6.3.2 CAS Latency
CAS Latency DQ31
30 2 and 3 1
A logic low (0) indicates that the resistor strapping is tied to ground (Vss). A logic high (1) indicates that the resistor strapping is tied to Vcc. Resistors should be a 4.7 Kohm resistor on the DQ lines.
6.4 Serial Presence Detect EEPROM
This EEPROM is optional on the module. For additional information, refer to the Intel document 66 MHz Unbuffered SDRAM SO-DIMM Specification.
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7.0 Electrical Characteristics
The module electrical characteristics are carefully controlled to allow system configurations with two separate memory arrays. This allows one module to be present, plus memory soldered directly to the motherboard or add-in card PCB. Currently, two modules are not being supported. Routing on the main board will generally be done as a T-topology. The module’s electrical characteristics (as well as the main board’s characteristics) must be carefully implemented to insure a balanced T-topology.
The board must have a characteristic impedance between 50 and 85 ohms.
The following table lists the suggested flight time budgets for a typical graphic system using an early/late memory clock.
7.1 15 nS Timing
Parameter Symbol Min. Max. Unit
Clock Cycle Time Tcyc 15.0 nS Early/Late Clock Tcsk 0.35 1.6 nS Output Valid from Clock Tac 11.0 nS Output Hold from Clock Toh 2.5 nS Input Setup Time Tsi 3.0 nS Input Hold Time Thi 1.0 nS Motherboard Clock Flight Time Tcfm 0 0.3 nS Motherboard Addr/Data/Cntrl Flight Time Txfm 0 0.3 nS Module Clock Flight Time Tcfs 0.1 0.365 nS Module Flight Addr/Data/Cntrl Flight Time Txfs 0 0.375 nS
7.2 12 nS Timing
Parameter Symbol Min. Max. Unit
Clock Cycle Time Tcyc 12.0 nS Early/Late Clock Tcsk 1.3 1.8 nS Output Valid from Clock Tac 9.0 nS Output Hold from Clock Toh 2.5 nS Input Setup Time Tsi 3.0 nS Input Hold Time Thi 1.0 nS Motherboard Clock Flight Time Tcfm 0.2 0.3 nS Motherboard Addr/Data/Cntrl Flight Time Txfm 0 0.3 nS Module Clock Flight Time Tcfs 0.175 0.325 nS Module Flight Addr/Data/Cntrl Flight Time Txfs 0 0.375 nS
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7.3 10 nS Timing
Parameter Symbol Min. Max. Unit
Clock Cycle Time Tcyc 10.0 nS Early/Late Clock Tcsk 1.3 1.8 nS Output Valid from Clock Tac 7.0 nS Output Hold from Clock Toh 2.5 nS Input Setup Time Tsi 2.5 nS Input Hold Time Thi 1.0 nS Motherboard Clock Flight Time Tcfm 0.2 0.3 nS Motherboard Addr/Data/Cntrl Flight Time Txfm 0 0.3 nS Module Clock Flight Time Tcfs 0.175 0.325 nS Module Flight Addr/Data/Cntrl Flight Time Txfs 0 0.375 nS
7.4 8 nS Timing
Parameter Symbol Min. Max. Unit
Clock Cycle Time Tcyc 8.0 nS Early/Late Clock Tcsk 1.3 1.8 nS Output Valid from Clock Tac 6.0 nS Output Hold from Clock Toh 2.5 nS Input Setup Time Tsi 2.0 nS Input Hold Time Thi 1.0 nS Motherboard Clock Flight Time Tcfm 0.2 0.3 nS Motherboard Addr/Data/Cntrl Flight Time Txfm 0 0.3 nS Module Clock Flight Time Tcfs 0.175 0.325 nS Module Flight Addr/Data/Cntrl Flight Time Txfs 0 0.375 nS
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7.5 A.C Timing Diagrams
Figure 6. Address/Control A.C. Timing Parameters
tcyc tcsk
CLK to Memory
CLK to Gfx Ctrl Addr/Ctrl
tac toh Addr/Ctrl Output txfm Addr/Ctrl at SO-DIMM Interface thi txfs tsi
Addr/Ctrl Input
A005.vsd
Figure 7. Data Write A.C. Timing Parameters
tcyc tcsk
CLK to Memory
CLK to Gfx Ctrl Data
tac toh Data Output
txfm Data at SO-DIMM Interface thi txfs tsi Data Input
A006.vsd
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Figure 8. Data Read A.C. Timing Paramters
tcyc tcsk
CLK to Memory
CLK to Gfx Ctrl Data
tac toh Data Output
txfm Data at SO-DIMM Interface thi txfs tsi Data Input
A007.vsd
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8.0 PCB Layout Considerations
To insure proper signal integrity, the module routing must be taken under careful considerations. This section outlines PCB layout considerations for the SO-DIMM module.
Each section looks at three separate topologies; one for clocks, one for control/address, and one for data. The assumed loading for this configuration is:
Table 5. Signal Loading
Signal 32-bit 64-bit
Single-sided Double-sided Single-sided Double-sided
clocks 1 load 1 load 2 loads 2 loads address/control 1 load 2 loads 2 loads 4 loads data 1 load 2 loads 1 load 2 loads
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8.1 Clock Routing and Chip Selects
Clock and chip select loading is two loads per line, maximum. Routing should be performed using a T-topology, as shown below:
Figure 9. T-Topology Clock Routing
o b c
o
a A008.vsd
The following table lists the allowable stub lengths for the clock and chip select routing.
Table 6. Stub Lengths (Clock and Chip Select Routing)
SDRAM/SGRAM Clock Frequency
Parameters 15 nS 12 nS 10 nS 8 nS Units
Min. Max Min. Max Min. Max Min. Max
a 75 150 75 150 75 150 75 150 pS b 0 115 0 115 0 115 0 115 pS c 0 115 0 115 0 115 0 115 pS b+c 0 225 0 225 0 225 0 225 pS Total Length 100 365 175 325 175 325 175 325 pS (clock) Total Length 0 365 0 365 0 365 0 365 pS (chip select)
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8.2 Address/Control Routing
The following table lists the allowable stub lengths for the address/control routing.
Figure 10.Address and Control Routing
Bank 1 o
f o
h cd
g Bank 0 o
e
b o
10 ohm
a A009.vsd
Table 7. Stub Lengths (Address/Control Routing)
SDRAM/SGRAM Clock Frequency
Parameters 15 nS 12 nS 10 nS 8 nS Units
Min. Max Min. Max Min. Max Min. Max
a 0 37 0 37 0 37 0 37 pS b 0 190 0 190 0 190 0 190 pS c 0 115 0 115 0 115 0 115 pS d 0 115 0 115 0 115 0 115 pS e 0 115 0 115 0 115 0 115 pS f 0 115 0 115 0 115 0 115 pS g 0 115 0 115 0 115 0 115 pS h 0 115 0 115 0 115 0 115 pS b-c -75 75 -75 75 -75 75 -75 75 pS b-d -75 75 -75 75 -75 75 -75 75 pS c+e 0 190 0 190 0 190 0 190 pS c+f 0 190 0 190 0 190 0 190 pS d+g 0 190 0 190 0 190 0 190 pS d+h 0 190 0 190 0 190 0 190 pS total length 0 375 0 375 0 375 0 375 pS
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8.3 Data Routing
Data lodading is two loads per line, maximum. Routing should be performed using a T-topology, as shown below.
Figure 11.Data Routing
CD
Bank 1
A B b S o
d c
o Bank 0
a
A010.vsd
Byte-ordering (along with the respective Data Mask, DQM) within the SDRAM/SGRAM should be swapped to optimize routing.
Table 8. Byte Ordering
Module Byte Front-Side Memory Byte Back-Side Memory Byte n value
BYTE 0 Memory B; BYTE 0 Memory D; BYTE 3 n = 115 pS BYTE 1 Memory B; BYTE 3 Memory D; BYTE 0 n = 35 pS BYTE 2 Memory B; BYTE 1 Memory D; BYTE 2 n = 35 pS BYTE 3 Memory B; BYTE 2 Memory D; BYTE 1 n = 115 pS BYTE 4 Memory A; BYTE 1 Memory C; BYTE 2 n = 115 pS BYTE 5 Memory A; BYTE 2 Memory C; BYTE 1 n = 35 pS BYTE 6 Memory A; BYTE 0 Memory C; BYTE 3 n = 35 pS BYTE 7 Memory A; BYTE 3 Memory C; BYTE 0 n = 115 pS
The following table lists the allowable stub lengths for the data line routing.
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Table 9. Stub Lengths (Data Line Routing)
SDRAM/SGRAM Clock Frequency
Parameters 15 nS 12 nS 10 nS 8 nS Units
Min. Max Min. Max Min. Max Min. Max
a nn+75nn+75nn+75nn+75pS b 075075075075pS c 075075075075pS d 0 125 0 125 0 125 0 125 pS total length 0 n+150 0 n+150 0 n+150 0 n+150 pS
Stub d is used for the strapping resistors on DQ29-DQ31, and is optional.
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9.0 Electrical Specifications
The following information is from the Intel PC SDRAM Specification, version 1.1, April 1996. It is provided here for convenience
9.1 SDRAM/SGRAM Component Absolute Maximum D.C. Ratings
Table 10. Absolute Maximum Ratings
Symbol Parameter Min. Max. Units
Vin, Vout Voltage on any pin w.r.t VSS -0.5 VCC + 0.5 V VCC, VCCQ Voltage Supply pins w.r.t VSS -0.5 4.5 V Ts Storage Temperature -55 125 °C PD Power Dissipation 1 W
9.2 SDRAM/SGRAM Components D.C. Operating Requirements
Table 11. D.C. Operating Requirements
Symbol Parameter Condition Min. Max. Units Notes
VCC Supply Voltage 3.0 3.6 V VCCQ I/O Supply Voltage 3. 0 3.6 V Iil Input Leakage Current 0 < Vin < VCCQ -5 +5 µA1,2 Voh Output High Voltage Ioh = -4 mA 2.4 V Vol Output Low Voltage Iol = 4 mA 0.4 V Cin Input/Clock Pin Capacitance 5 pF CI/O I/O Pin Capacitance 7 pF Lpin Pin Inductance 10 nH 2 Ta Ambient Temperature No Airflow 0 65 °C
NOTES: 1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs. 2. This is a recommendation, not an absolute requirement. The actual value should be provided with the component data sheet.
9.3 SDRAM/SGRAM Components Absolute Maximum A.C. Operating Requirements
Table 12. Absolute Maximum A.C. Operating Requirements
Symbol Parameter Min. Max. Units Notes
Vih Input High Voltage 2.0 VCCQ + 1.5 V 1 Vil Input Low Voltage VSSQ − 1.5 0.8 V 1
NOTE: The overshoot and undershoot voltage duration is ≤5ns with no input clamp diodes.
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9.4 Memory Timing
Individual DRAM component devices are required to follow the AC timings specified in the Intel “PC SGRAM” specification. Devices which can not meet the minimum timing set forth. must program a lower clock speed.
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Appendix A PCB Layout
This section show an example of a PQFP/TQFP SO-DIMM module routed as a six-layer PCB.
Figure 12.Silk Screen - Primary Side
Figure 13.Silk Screen - Secondary Side
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Figure 14.Primary Side (layer 1)
Figure 15.VCC Plane (layer 2)
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Figure 16.Inner-Signal (layer 3)
Figure 17.Inner-Signal (layer 4)
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Figure 18.Ground Plane (layer 5)
Figure 19.Secondary Side (layer 6)
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