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An Introduction to Microprocessors, Vol. 2 ~ N.B. FAULTY BINDING CHAPTER 3 DUPLICATED, HALF CHAPTER 4 NOT PRINTED. 1%70 PRESTON POLYTECHNIC LIBRARY & LEARNING RESOURCES SERVICE This book must be returned on or before the date lest stamped isation by any he prim act: L. PI n lll II 31 0 07 AN INTRODUCTION TO MICROCOMPUTERS VOLUME II SOME REAL PRODUCTS •. ht a 1976, 1977 by Adam Osborne and Associates. Incorporated. :4 Congress Catalogue Card Number 76-374891 pants eserved. Printed in the United States of America. No part of this publication ninroduced. stored in a retrieval system. or transmitted in any form or by any e electronic, mechanical. photocopying. recording, or otherwise. without the prior *ter. pal mission of the publishers. Published by Adam Osbo and Associates. Incorporated P.O. Box 2036. Berkeley. California 94702 nation oa translations. pricing end ordering outsets the USA, please contact Osborne & Associates, Inc. P.O. Box 2036 Berkeley, California 94702 United States of America (415) 54&2805 Data Sheets in this book have been copied from vender literature. The manufacture are credited as follows'. CHAPTER 1 TEXAS INSTRUMENTS. INC. P.O. Box 1443 Houston. Texas 77001 2 FAIRCHILD SEMICONDUCTOR 464 Ellis Street Mountain View. CA 75006 3 NATIONAL SEMICONDUCTOR CORPORATION 2900 Semiconductor Drive Santa Clara. CA 95050 4 INTEL CORPORATION 3065 Bowers Avenue Santa Clara. CA 95051 NEC MICROCOMPUTERS. INC. 5 Militia Drive Lexington. MA 02173 5 INTEL CORPORATION 3065 Bowers Avenue Santa Clara. CA 95051 6 INTEL CORPORATION 3065 Bowers Avenue Santa Clara, CA 95051 J ZILOG. INC. 10460 Bubb Road Cupertino. CA 95014 8 MOTOROLA. INC. Semiconductor Products Division 3501 Ed Bluestein Boulevard Austin. Texas 78721 9 MOS TECHNOLOGY. INC. 950 Rittenhouse Road Norristown. PA 19401 10 SIGNETICS 811 East Argues Avenue Sunnyvale. CA 94043 11 RCA SOLID STATE DIVISION P.O. Box 3200 Somerville. N.J. 08876 12 INTERSIL. INC. 10900 North Tantau Avenue Cupertino. CA 95014 13 SCIENTIFIC MICRO SYSTEMS. INC. 520 Clyde Avenue Mountain View. CA 94043 14 NATIONAL SEMICONDUCTOR. INC. 2900 Semiconductor Drive Santa Clara. CA 95050 15 GENERAL INSTRUMENT CORPORATION MICROELECTRONICS 600 West John Street Hicksville. N.Y 11802 16 TEXAS INSTRUMENTS. INC. P.O. Box 1443 Houston. Texas 77001 17 DATA GENERAL CORPORATION Mail Stop 6-58 Southborough. MA 01772 18 ADVANCED MICRO DEVICES 901 Thompson Place Sunnyvale. CA 94086 19 MOTOROLA SEMICONDUCTOR Box 20912 Phoenix. Arizona 85036 20 HEWLETT PACKARD Data Systems Division 11000 Wolte Road Cupertino. CA 95014 We would like to acknowledge the diligent work of our production staff George M. Vrana Art and Design Karen deRobinson Art V. Mitchell Typesetting Penny Lawrence Typesetting Marcia P. McCuen Typing Sally Kusch Proofreading Mary Borchers Coordinator ni TABLE OF CONTENTS CHAPTER PAGE 1 4-BIT MICROPROCESSORS AND THE TMS1000 SERIES MICROCOMPUTERS 1-1 TMS1000 PROGRAMMABLE REGISTERS 1-4 TMS1000 MEMORY ADDRESSING MODE 1-5 TMS1000 STATUS FLAGS 1-6 TMS1000 INPUT AND OUTPUT LOGIC 1-6 TMS1000 SERIES MICROCOMPUTER PINS AND SIGNALS 1-7 TMS1000 SERIES MICROCOMPUTER INSTRUCTION EXECUTION 1-11 TMS1000 SERIES MICROCOMPUTER INSTRUCTION SET 1-11 THE BENCHMARK PROGRAM 1-11 DATA SHEETS 1-18 2 THE FAIRCHILD F8 2-1 THE 3850 CPU 2-1 F8 PROGRAMMABLE REGISTERS 2-4 F8 MEMORY ADDRESSING MODES 2-6 FAIRCHILD F8 STATUS FLAGS 2-8 F8 CPU PINS AND SIGNALS 2-8 F8 TIMING AND INSTRUCTION EXECUTION 2-12 A SUMMARY OF F8 INTERRUPT PROCESSING 2-12 THE F8 INSTRUCTION SET 2-12 THE BENCHMARK PROGRAM 2-22 THE 3851 PROGRAM STORAGE UNIT (PSU) 2-27 THE 3856 AND 3857 16K PROGRAMMABLE STORAGE UNITS (16K PSU) 2-30 THE 3852 DYNAMIC MEMORY INTERFACE (DMI) 2-30 THE 3854 DIRECT MEMORY ACCESS (DMA) DEVICE 2-36 THE 3853 STATIC MEMORY INTERFACE (SMI) 2-37 THE 3859 F8 MICROCOMPUTER 2-39 DATA SHEETS 2-42 3 THE NATIONAL SEMICONDUCTOR SC/MP 3-1 SC/MP PROGRAMMABLE REGISTERS 3-3 ADDRESSING MODES 3-4 SC/MP STATUS REGISTER 3-5 SC/MP CPU PINS AND SIGNAL ASSIGNMENTS 3-6 SC/MP TIMING AND INSTRUCTION EXECUTION 3-8 SC/MP BUS ACCESS LOGIC 3-9 SC/MP INPUT/OUTPUT OPERATIONS 3-12 THE SC/MP HALT STATE 3-15 SC/MP INTERRUPT PROCESSING 3-16 SC/MP DMA AND MULTIPROCESSOR OPERATIONS 3-21 THE SC/MP RESET OPERATION 3-26 SC/MP SERIAL INPUT/OUTPUT OPERATIONS 3-26 THE SC/MP INSTRUCTION SET 3-27 THE BENCHMARK PROGRAM 3-35 SUPPORT DEVICES FOR THE SC/MP CPU 3-36 USING OTHER MICROCOMPUTER SUPPORT DEVICES v TABLE OF CONTENTS (Continued) CHAPTER PAGE WITH THE SC/MP CPU 3-39 DATA SHEETS 3-42 4 THE 8080A 4-1 THE 8080A CPU 4-3 8080A PROGRAMMABLE REGISTERS • • 4-5 8080A ADDRESSING MODES 4-5 8080A STATUS 4-6 8080A CPU PINS AND SIGNALS 4-6 8080A TIMING AND INSTRUCTION EXECUTION 4-7 CLOCK SIGNALS 4-8 INSTRUCTION FETCH SEQUENCE 4-12 A MEMORY READ OR WRITE OPERATION 4-13 SEPARATE STACK MEMORY MODULES 4-13 THE WAIT STATE 4-14 THE WAIT, HOLD AND HALT STATES 4-17 THE HOLD STATE 4-18 THE HALT STATE AND INSTRUCTION 4-20 THE RESET OPERATION 4-21 EXTERNAL INTERRUPTS 4-23 EXTERNAL INTERRUPTS DURING THE HALT STATE 4-26 WAIT AND HOLD CONDITIONS FOLLOWING AN INTERRUPT 4-26 THE 8080A INSTRUCTION SET 4-27 THE BENCHMARK PROGRAM 4-28 INSTRUCTION EXECUTION TIMES AND CODES 4-41 SUPPORT DEVICES THAT MAY BE USED WITH THE 8080A 4-41 THE 8224 CLOCK GENERATOR AND DRIVER 4-60 8224 CLOCK GENERATOR PINS AND SIGNALS 4-60 THE 8228 SYSTEM CONTROLLER AND BUS DRIVER 4-62 BUS DRIVER LOGIC 4-62 CONTROL SIGNAL LOGIC 4-63 8228 SYSTEM CONTROLLER PINS AND SIGNALS 4-63 THE 8251 PROGRAMMABLE COMMUNICATION INTERFACE 4-65 8251 USART PINS AND SIGNALS 4-68 8251 DATA TRANSFER AND CONTROL 4-72 TRANSMITTING SERIAL DATA -SERIAL TRANSMIT CONTROL SIGNALS 4-76 RECEIVING SERIAL DATA 4-79 8251 USART CONTROL CODES AND STATUS 4-80 THE NEC µPD379 SYNCHRONOUS RECEIVER/TRANSMITTER 4-85 A µPD379 DEVICE OVERVIEW 4-86 CLOSED MODE 4-88 DATA BUFFERING 4-92 TRANSMITTING AND RECEIVING SERIAL DATA UNDER STANDARD SYNCHRONOUS PROTOCOL 4-94 SERIAL DATA 4-99 TRANSMITTING AND RECEIVING DATA UNDER SDLC PROTOCOL 4-99 vi TABLE OF CONTENTS (Continued) CHAPTER PAGE THE µPD369 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER 4-106 µPD369 DEVICE-PINS AND SIGNALS 4-106 THE 8255 PROGRAMMABLE PERIPHERAL INTERFACE (PPI) 4-113 8255 PPI PINS AND SIGNALS 4-113 8255 PPI OPERATING MODES 4-116 THE 8212 8-BIT INPUT/OUTFIT PORT 4-122 8212 I/O PORT PINS AND SIGNALS 4-122 8212 I/O PORT UTILIZATION OPTIONS 4-127 THE 8257 DIRECT MEMORY ACCESS CONTROLLER 4-133 8257 DMA CONTROLLER PINS AND SIGNALS 4-133 PROGRAMMING THE 8257 DMA CONTROLLER 4-133 DMA TRANSFER RATES 4-147 THE 8253 PROGRAMMABLE CQUNTER/TIMER 4-147 8253 COUNTER/TIMER PINS AND SIGNALS 4-148 8253 COUNTER/TIMER PROGRAMMABLE OPTIONS" 4-149 GATE AND OUTPUT SIGNAL SUMMARY 4-155 MONITORING 8253 COUNTEJR7TIMER°=OPERAT1ON 4-155 THE 8259 PRIORITY INTERRUPTCONTROL UNIT (PICU) 4-157 8259 PICU PINS AND SIGNALS 4-158 THE 8259 PICU INTERRUPT ACKNOWLEDGE VECTOR 4-159 8259 PICU PRIORITY ARBITRATION OPTIONS 4-163 HOW INTERRUPT REQUESTS AND PRIORITY STATUS ARE RECORDED 4-167 PROGRAMMING THE 8259 PICU 4-168 THE 8214 PRIORITY INTERRUPT CONTROL UNIT (PICU) 4-174 8214 PRIORITY INTERRUPT CONTROL UNIT PINS AND SIGNALS 4-175 A TYPICAL 8214 PRIORITY INTERRUPT CONTROL CONFIGURATION 4-177 THE TMS5501 MULTIFUNCTION INPUT/OUTPUT CONTROLLER 4-178 TMS5501 DEVICE PINS AND SIGNALS 4-178 TMS5501 DEVICE ACCESS 4-182 TMS5501 INTERRUPT HANDLING 4-187 TMS5501 PARALLEL I/O OPERATIONS 4-188 TMS5501 SERIAL I/O OPERATION 4-189 TMS5501 INTERVAL TIMERS 4-189 MISCELLANEOUS 8080A SUPPORT DEVICES 4-190 THE 8205 1-OF-8- DECODER 4-190 BIDIRECTIONAL BUS DRIVERS 4-190 DATA SHEETS 4-191 5 THE 8085 5-1 THE 8085 CPU 5-4 8085 ADDRESSING MODES 5-4 8085 STATUS 5-4 8085 CPU PINS AND SIGNALS 5-5 A COMPARISON OF 8085 AND 8080A SIGALS 5-9 vii TABLE OF CONTENTS (Continued) CHAPTER PAGE 8085 TIMING AND INSTRUCTION EXECUTION 5-10 MEMORY ACCESS SEQUENCES 5-12 BUS IDLE MACHINE CYCLES 5-21 THE WAIT STATE 5-23 THE SID AND SOD SIGNALS 5-25 THE HOLD STATE 5-27 THE HALT STATE AND INSTRUCTION 5-29 EXTERNAL INTERRUPTS 5-31 THE RESET OPERATION 5-35 THE 8085 INSTRUCTION SET 5-38 8085 MICROPROCESSOR SUPPORT. DEVICES 5-39 THE 8155/8156 STATIC READ/WRITE MEMORY WITH I/O PORTS AND TIMER 5-39 8155 DEVICE PINS AND SIGNALS 5-39 8155 PARALLEL INPUT/OUTPUT 5-43 8155 DEVICE ADDRESSING 5-44 THE 8155 COUNTER/TIMER 5-48 8155 CONTROL AND STATUS REGISTERS 5-49 8155 DEVICE PROGRAMMING 5-50 THE 8355 READ ONLY MEMORY WITH I/O 5-52 8355 DEVICE PINS AND SIGNALS 5-52 8355 READY LOGIC 5-57 8355 I/O LOGIC 5-60 THE 8755 ERASABLE PROGRAMMABLE READ ONLY MEMORY WITH I/O 5-60 DATA SHEETS 5-63 6 THE 8048. 8748 AND 8035 6-1 THE 8048. 8748 AND 8035 MICROCOMPUTERS 6-3 AN 8048 FUNCTIONAL OVERVIEW 6-4 8048, 8748 AND 8035 MICROCOMPUTER PROGRAMMABLE REGISTERS 6-6 8048, 8748 AND 8035 ADDRESSING MODES 6-7 8048, 8748 AND. 8035 STATUS 6-12 8048 SERIES MICROCOMPUTER OPERATING MODES 6-14 8048, 8748 AND 8035 CPU PINS AND SIGNALS 6-15 8048 SERIES TIMING AND INSTRUCTION EXECUTION 6-18 INTERNAL EXECUTION MODE 6-19 EXTERNAL MEMORY ACCESS MODE 6-20 DEBUG MODE 6-23 SINGLE STEPPING 6-24 PROGRAMMING MODE 6-25 VERIFICATION MODE 6-26 INPUT/OUTPUT PROGRAMMING 6-27 COUNTER/TIMER OPERATIONS 6-28 INTERNAL AND EXTERNAL INTERRUPTS 6-29 THE 8048 MICROCOMPUTER SERIES INSTRUCTION SET 6-34 THE 8243 INPUT/OUTPUT EXPANDER 6-47 8243 INPUT/OUTPUT EXPANDER OPERATIONS 6-51 DATA SHEETS 6-54 viii TABLE OF CONTENTS (Continued) CHAPTER PAGE 7 ZILOG Z80 7-1 THE Z80 CPU 7-1 A SUMMARY OF Z80/8080A,DIFFERENCES 7-3 Z80 PROGRAMMABLE REGISTERS 7-6 Z80 ADDRESSING MODES 7-8 Z80 STATUS 7-9 Z80 CPU PINS AND SIGNALS 7-9 Z80-8080A SIGNAL COMPATIBILITY 7-11 Z80 TIMING AND INSTRUCTION EXECUTION 7-14 INSTRUCTION FETCH EXECUTION SEQUENCES
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