Chapter 34
The engineering design of the Stretch computer 1
Erich Block
The Stretch is an advanced scientific with This Summary computer computer paper reviews the engineering design of the Stretch System variable facilities for and floating-point, fixed-point, variable-field-length with primary concentration on the central computer as the main arithmetic and data-handling facilities. contributor to performance. In it, these new techniques, devices, The of 100 704 is achieved performance goal x speed by high-speed and instructions have been pushed to the limit set by the present circuits, multiplexing, and simultaneous-operation technique of instruction technology and, therefore, its analysis will convey best the prob- and data-fetching, as well as overlap within the execution units. This lems encountered and the solutions employed. massive overlap and multiplexing results in complicated recovery routines between the look-ahead and instruction units. These units are described in as are the detail, arithmetic units and significant algorithms used in the floating-point arithmetic. The Stretch system A flexible set of circuits using a current-switching technique with Early in the system design, it appeared evident that a six-fold overriding-level facility is described, as well as the packaging of circuits improvement in memory performance and a ten-fold on printed cards. The frame and gate concept is also shown. Performance improvement in basic circuit over the 704 was the best one could achieve. figures and hardware count illustrate the size, complexity, and performance speed To meet the of the system. proposed performance criteria, the system had to be in such a that it organized way took advantage of every possible of overlap systems function, multiplexing of the major portion of Introduction the of system, processing operations simultaneously, and anticipa- tion of wherever The Stretch computer [Dunwell, 1956] project was started in order occurrences, possible. The system had to be of based on the to achieve two orders of magnitude of improvement in perform- capable making assumptions probability that certain events and means had to be ance over the then existing 704. Although this computer, like the might occur, provided to is retrace the when the to be 704, aimed at scientific problems such as reactor design, hydro- steps assumption proved wrong. This and of dynamics problems, partial differential equation etc., its instruc- simultaneity multiplexing operations reflects itself in the Stretch at all tion set and organization are such that it can handle with ease System levels, from overall systems organiza- tion to the of data-processing problems normally associated with commercial cycle specific instructions. In the following descrip- tion, this will be discussed in more detail. applications, such as processing of alphanumeric fields, sorting, and If one considers the decimal arithmetic. Stretch System (Fig. 1) from an overall of view it becomes In order to achieve the stated goal of performance, all factors point apparent that the major parts of the can that go into the computer design must contribute towards the system operate simultaneously: performance goal; this includes the instruction set [Buchholz, the internal the data and instruction 1958], system organization, a The 2-jnsec, 16,384-word core memories are self-contained, word and features such as length, auxiliary status-monitoring with their own clocks, addressing circuits, data registers and devices, the circuits, packaging, and component technology. No checking circuits. The memories themselves are interleaved so that the first two memories have their addresses distrib- one of them by itself can give this hundred-fold increase in speed; the uted modulo 2 and the other four are interleaved modulo only by combining and interacting of these contributing 4. The modufo-2-interleaved memories are used factors can this performance be obtained. primarily for instruction storage; since, for high-performance instruc- tions, halfword formats are used, the average rate of ob- l Proc. EJCC, 1959. is pp. 48-59, taining instructions one per % ^isec. Similarly, a 0.5-jusec
421 422 Part 5 The PMS level Section 2 Computers with one central processor and multiple input/output processors
INSTRUCTION MEMORIES OPERAND MEMORIES (MOD 2 INTERLEAVED) (MOD 4 INTERLEAVED) 7=T SEC CORE SEC CORE 2/i SEC CORE 2/i SEC CORE 2/i SEC CORE 2/x SEC CORE 2/i 2/i MEMORY MEMORY MEMORY MEMORY MEMORY MEMORY (16K) (16K) (16K) 06K) (16K) (16K)
MEMORY IN BUS
MEMORY OUT BUS
DISK SYNCH MEMORY CENTRAL UNIT I/O EXCHANGE BUS COMPUTER
DISK CONSOLE READER PRINTER PUNCH TAPE TAPE CONTROL ADAPTER ADAPTER ADAPTER ADAPTER ADAPTER ADAPTER
(CONSOLE)9 £IREADER tPUNCH 4xl0 6 WORDS
Fig. 1. The Stretch system.
data-word rate is achieved by the use of four modulo-4 Before discussing the computer organization, a few general organized memories. The addressing of the memories and features must be mentioned for completeness: the transfer of information from and to the memories by or both for checks and a memory bus permits new addresses, information, o Word length: 64 bits plus eight bits parity to pass through the bus every 200 mjusec. error-correction codes. words The simultaneously-operating Input/Output units are b Memory capacity and addressing: A possible 256,000 linked with the memories and the computer through the can be randomly addressed. These storage positions are all Exchange, which, after initial instruction by the computer, in external memory, except for the 32 first addresses. These time coordinates the starting of the I/O equipment, the checking positions consist of the internal registers (accumulators, and error-correction of the information, the arrangement clocks, index registers). of the information into memory words, and the fetching and c The instructions are single-address instructions with the storing of the information from and to memory. All these exception of a number of special codes that imply the functions are executed without the use of the computer, second address explicitly. so it can in the meantime continue its data and processing a The instruction set (Fig. 2) is generalized and contains computation. full set for single- and double-precision floating-point arith- The central computer processes and executes the stored metic, and a full set for variable-field-length integer arith- program. Here, now, the simultaneity and multiplexing of metic (binary and decimal). It also has a generalized set for functions has reached its ultimate. index modification and a branching set, as well as a set of Chapter 34 The engineering design of the Stretch computer 423 |
instructions. All 765 of instructions I/O told, different types (accumulator). Both halves of the word are independently are used in the system. indexable.
d The instruction format 3) makes use of both half and (Fig. A general monitoring device used for important status full words; half words accommodate indexing and floating- triggers is called the Interrupt [Brooks, 1957] System. This point instructions (for optimum performance these two sets system monitors the flip-flops which reflect internal mal- of instructions use a rigid format), and full-word formats functions, result significance (exponent range, mantissa zero, are used by the variable-field-length instructions. Notice overflow, underflow), program errors (illegal instruction, that the latter specifies the field the address of operand by protected memory area), and conditions (unit 1 input/output its left-most bit, the length of the field, and the byte size, not status ready, etc.). The of these flip-flops can cause a as well as the of the starting point (offset) implied operand break in the normal progression of the stored program for l Byte: a generic term to denote the number of bits to be operated on as fix-up purposes. Their status is automatically interrogated a unit by a variable-field-length instruction. at all times.
INSTRUCTION CATEGORY 424 Part 5 The PMS level Section 2 Computers with one central processor and multiple input/output processors
DATA FORMATS
1 1 1 1 1 1 1 ECC INTEGER BYTE 8 BYTE 7 BYTE 6 BYTE 5 BYTE 4 BYTE 3 BYTE 2 BYTE 1 PTY BITS 15 23 31 39 47 55 63 71
FLAG FLOATING ^ ECC EXPONENT MANTISSA (FRACTION) POINT PARITY 101112 59 63 71
INDEX 1+ WORD VALUE
I/O CONTROL WORD Chapter 34 The engineering design of the Stretch computer 425 |
time-sharing of the major computer organs is no longer possible. Data flow All in all, the computer has 3,000 register positions and about 450 adder positions. The data flow through the computer is shown in Fig. 5 and is Despite the multiplexing and simultaneous operation of suc- comparable to a pipeline which in a steady state (namely, once the if cessive instructions, result appears as sequential step-by-step filled) has a large output rate no matter what its length. The same internal operation were utilized. This has made the design of the is true here; after start-up the execution of the instructions is fast interlocks quite complex. and bears no relation at all to the stages it must progress through.
DATA WORD
INSTRUCTION
INSTRUCTION FETCH 4 INSTRUCTIONS 4 DATA WORDS
1 1 J )L , INSTRUCTION INSTRUCTION UPDATING FETCH DATA WORD FETCH
DATA WORD INSTRUCTION INSTRUCTION FETCH UPDATING EXECUTION
INSTRUCTION EXECUTION
704 STRETCH
Fig. 4. Comparison of Stretch and 704 organization. 426 Part 5 The PMS level Section 2 Computers with one central processor and multiple input/output processors
INSTR FETCH ADR MEMORY BUS MEMORY IN BUS «=? FR EXCHANGE ADDRESS DATA OPERAND FETCH ADR "TZ RESULT STORE ADDRESS MEMORY OUT BUS TO EXCHANGE LI CHECKER OUT BUS 1 INSTR WORD BUFFER OPERAND BUFFER INSTR WORD BUFFER ERROR OPERAND BUFFER INSTRUCTION 8 CORRECTOR OPERAND BUFFER CHECKER INDEXING UNIT OPERAND BUFFER LOOK-AHEAD CHECKER IN BUS 3" LA TRANSFER BUS L_E I ARITH CHECKER OUT BUS 2 WORD 2 WORD ACCUMULATOR OPERAND A,B REGISTER INTERRUPT C,D ARITHMETIC SYSTEM CHECK ARITH CHECKER IN BUS I 71 SERIAL PARALLEL ARITH UNIT ARITH UNIT Fig. 5. Stretch computer—units and data flow. The Memory Bus is the communication link between the mem- rogated on data fetches. The return address is remembered and ories on one side and the exchanges and the computer on the other. the requesting unit receives the information when it becomes It monitors the requests for storage to, or fetches from, memory, available. To accomplish this, from the time information is re- and sets up a priority scheme. Since I/O units cannot hold up quested the receiving data register is in a reserved status. their requests, the exchange will get highest priority, followed by Requests for stores and fetches can be processed at a 200 mjtisec the computer. In the computer the instruction-fetch mechanism rate and the time, if no busy or priority conditions exist, to return has priority over the operand-fetch mechanism. All told, the the word to the requesting unit is 1.6 ;usec, a direct function of memory bus gets requests from and assigns priority to eight differ- the memory read-out time. ent channels. The Instruction Unit [Blaauw, 1959] is a computer of its own. Since memory can be accessed from multiple sources, and once It has its own instruction set, its own small memory for index word accessed it is on its own to complete its cycle, a busy condition storage, and its own arithmetic unit. During its operation as many can exist. Here again, the memory bus tests for busy conditions as six instructions can be at various stages of execution. and delays the requesting unit until memory is ready to be inter- The Instruction Unit fetches the instruction words from mem- Chapter 34 The engineering design of the Stretch computer 427 | it the instruction and the of ory, steps counter, performs indexing as the instruction unit starts processing an instruction, it is re- instructions and the initiation of data fetches. After a preliminary moved from the buffer, thus making room for the next memory- of the class of it its instruc- decoding instruction, recognizes own word access (Fig. 6). Incidentally, half-word instructions and tions and executes indexing instructions. On branches, conditional full-word instructions can be intermixed within the same word, or the instruction unconditional, unit executes these. In the case and therefore the latter can cross a word boundary. This permits of conditional branches, it makes the assumption that the branch maximum packing of instructions in memory and also serves as will not be successful. a facility for automatic program assemblers and compilers. This and the of assumption availability two full-word buffer The adder path, index registers, and transfer bus to look-ahead the flow of instruction to the continuous. the registers keep computer complete instruction unit system (Fig. 6). It should be noted the rate of instructions the instruction unit that the index are Therefore, entering registers part of the instruction-unit data path, is for all of the therefore practical purposes independent memory cycle. permitting fast access (no long transmission lines) to an Since, for high speed instructions, half-word formats are used, index word. There are 16 index words available to the programmer. four of these at one time can be in buffer soon The index any storage. As registers, consisting of multi-aperture cores, are oper- MEMORY OUT BUS 428 Part 5 The PMS level Section 2 Computers with one central processor and multiple input/output processors ated in a non-destructive fashion, since in a representative pro- gram, the index word is used nine out of ten times without modi- fying it. This permits fast operation under these conditions, and additional time is only applied where modification is involved. After processing through the instruction unit, the updated (in- dexed) instruction enters a level of the Look-ahead (Fig. 5). Besides the instruction, all necessary information, its associated instruction counter value, and certain tag information are also stored in the same level. The operand, already requested by the instruction unit, will enter this level directly and will be checked and error- corrected while awaiting transfer to the arithmetic units for execu- tion. An interlocked counter mechanism in the look-ahead keeps its four levels in step, preventing out-of-sequence execution of in- structions, even if all information for a succeeding one is available, before the previous instruction has been started. The pre-accessing of operands by the look-ahead and of instruc- tions by the instruction unit leads sometimes to embarrassing positions, for which a fix-up routine must be provided. Consider the program w Chapter 34 The engineering design of the Stretch computer 429 430 Part 5 The PMS level Section 2 Computers with one central processor and multiple input/output processors A,B C.D MPCD MPCD MPCD MPCD 3 BITS 3 BITS 3 BITS 3 BITS TRUE COMPLEMENT II PARALLEL t t ;i UNIT REGISTER CARRY SAVE CSA 2 ADDER 1 CARRY PROPAGATE ADDER SHIFTER 100 BITS J ]J CSA 3 .s 3 CSA 4 S 4 C4 SUM REG CARRY REG T~~[ Fig. 8. Floating-point arithmetic unit. of the multiplier are handled within one cycle. This is accom- Octal value plished by breaking the 12 bits into groups of three bits each. The action is from right to left and consists of decoding each group If two additions of multiples were permitted of three bits. By observing the lowest-order bit of the next higher 4 X MCD 6 x MCD 6 X MCD 2 X MCD a decision is made as to what of the group, multiple multiplicand - 1 x MCD - 1 X MCD one must add to the partial product. Since only even multiples Instead of subtracting 1 X MCD in n + 1, subtract 8 X MCD in n. of the multiplicand are available, subtraction and addition of the 4 X MCD 6 X MCD 6 X MCD 2 X MCD can result. The will elaborate this multiples following example -8 X MCD -8 X MCD point: (MCD means multiplicand) Resulting decoding Groups 4 x MCD -2 X MCD 6 x MCD n + 4 n + 3 n + 2 n + 1 12 bit Multiplier, group The four multiple multiplicand groups and the partial product of xxO Oil 110 101 010 the are now fed into adders of previous cycle carry-save the form, Chapter 34 The engineering design of the Stretch computer 431 Sum S=AYBVC Cycle 1 01 Carry C = AB + AC + BC Cycle 2 10 Cycle 3 0111 There are four of these adders, two in parallel followed by two — more in series (Fig. 8). The output of Carry-Save Adder 4 then (b) The same problem with both skip over 1/0 and 3/4 3/2 results in a double-rank partial product, the product sum and the complement: product carry. For each cycle this is fed into Carry-Save Adder 101000000000000 2, and, during the last cycle, into the carry-propagate adder, for Step 1: 0011101 accumulation of the carries. Since no of carries is propagation 11011010000 required in the four cycles, where multiple multiplicands are this is fast and is the main contributor to the Same as = ^1 added, operation before, Q l Q 2 fast multiply-time of Stretch. 100101001 Add DR 2: 3/4 The divide scheme [Robertson, 1958] has a similarity to the Step 111111001 multiply scheme. Multiples of the divisor are used, namely, 3/2 X divisor, 3/4 X divisor and 1 X divisor. This, plus shifting This (by table look-up) indicates Q3Q4Q5Q6Q7Q8 100111 over strings of ones and zeros, results in the generation of the Quotient bits generated required 48 quotient bits within thirteen machine cycles. Most per cycle: machines a divide method 48 using nonrestoring require cycles Cycle 1: 01 = 2 for 48 bits. The this quotient following example explains technique. Cycle 2: 100111 = 6 This scheme depends on the use of normalized divisors: In general, this method results in the generation of 3.7 quotient DIVIDEND (DD) = 101000000000000 bits per subtraction. While the mantissa operations of multiply DIVISOR (DR) = 1100011 and divide are performed by the parallel unit, the serial arithmetic 2's COMP DR (DR) = 0011101 unit executes the exponent arithmetic. Here again is a case where 3/4 DR = 100101001 overlap and simultaneity of operation is used to special advantage. (a) Using over 1/0 skip only: Checking. The operation of the computer is checked in its entirety and correction codes are where data transfers from 101000000000000 DIVIDEND employed memory and input-output units are involved. In particular, all Step 1: 0011101 ADD DR information sent to has a correction code associated with 1101101 memory it, which is checked for accuracy on its way from memory. If a single error is indicated, then correction is made and the error Remainder negative, 1st quotient bit = 0; shift one position. is recorded via a maintenance device. Within the 1 indicates that next bit output machine, Leading quotient must be 1; QiQ2 = 01 all arithmetic operations are checked, either by parity, duplica- tion, or a "casting out three" process. These checks are overlapped 011010000 REMAINDER with the execution of the next instruction. Step 2: 1100011 ADD DR 10010111 Hardware count. Figure 9 shows the percentage of transistors used in the various sections of the machine. It becomes obvious that Overflow: Remainder and = zero indicates positive 3 1, leading the parallel unit and the instruction unit use the highest percent- age of transistors. In case of the parallel unit this is due to the extensive circuits for multiply and to the additional hardware to 1011100 REMAINDER achieve speed up of the divide scheme. In the instruction unit, Step 3: 0011101 ADD DR the controls consume the majority of the transistors, because of 1111001 the high multiplexed operation encountered. = l's indicate Negative remainder; Os 0; leading Q6Q 7QS =111 Performance. The performance comparisons in Fig. 10 show the Number of quotient bits per cycle: increase in speed achieved, especially in floating-point operations, 432 Part 5 The PMS level Section 2 Computers with one central processor and multiple input/output processors UNIT Chapter 34 The engineering design of the Stretch computer 433 | Circuits for high-speed operation must be kept out of saturation at all times. This then explains why both the PNP and NPN version are used: Having reviewed the systems organization of Stretch, it is now mainly to avoid the problem of level translation, which would be of interest to discuss briefly the components, circuits, and packag- required due to the potential difference of the base and the col- used ing techniques to implement the design. lector. This difference is 6 volts, an optimum point for this device. basic in is drift 11 The component used Stretch the high-speed Figure shows the basic circuit configuration. It consists of transistor which exists in both an and a version. This a NPN PNP current source, represented by the —30 volt supply and resistor transistor has a cut-off of 100 mc and R. The functional frequency approximately operation of the circuits consists of two possible 434 Part 5 The PMS level Section 2 Computers with one central processor and multiple input/output processors oS A-B SYMBOL + A„ diA- B A N A TRUTH TABLE CIRCUIT DIAGRAM An MIN-MAX SIGNAL VOLTAGES CIRCUIT RESPONSE Chapter 34 The engineering design of the Stretch computer 435 A B 436 Part 5 The PMS level Section 2 Computers with one central processor and multiple Input/output processors A — A- CIRCUIT >AB >A+B B B- A TRUTH TABLES Chapter 34 The engineering design of the Stretch computer 437 | transistor A or C. Which is chosen be and If or of the bases paths represented by path by 4> positive transistor C to the load is or from through positive respect Fig. 14. The circuit package. 438 Part 5 The PMS level Section 2 Computers with one central processor and multiple input/output processors | If transistor X were eliminated, then transistors A and B in A circuit package using the smaller of the two printed circuit conjunction with the reference transistor C would work normally boards shown in Fig. 14, called a single card, contains AND or as a current switching circuit, in this case a +AND circuit. If OR circuits. It should be mentioned that the printed wiring is transistor X is added with the stipulation that the down level of one-sided and that besides the components and transistors, a rail X is more negative than the lowest possible level of A or B, it is added which permits the shorting or addition of certain loads becomes apparent that when X is negative, the current will flow depending on the use of the circuits. This rail then has the effect that branch of the circuit in to branch or of the different of circuit boards in the machine. through preference is to of shifters the inverse of input X. If, however, X positive, then the status Due the large number registers, adders, and used of will the function and This in the it seems reasonable that functional A and B determine function of if is and in a at of inputs allowable per circuit is eight. The number of driven circuits is three. Additional circuits are needed to drive more than three bases and where current switching circuits communicate over long lines, termination networks must be added to avoid reflections. To improve the performance of the computer in certain critical places, emitter-follower logic is used as shown in Fig. 13. These circuits, having a gain less than one, after a number of stages require the use of current switching circuits as level setters and gain devices. Both AND and OR circuits are available for both — — a ground-level and a 6-level input. Change from a 6-level circuit to a ground-level circuit is obtained by applying the ap- propriate power supply levels. Due to the variations in inputs and driven loads, the circuits must be designed so that the load can vary over a wide range. This resulted in instability which had to be offset by the feedback capacitor C shown in the circuit. All functions needed in the computer can be implemented by the use of the aforementioned circuits, including flip-flop opera- tion, which is obtained by tying a PNP current switch block and an NPN current switch block together' with proper feedback. Packaging The circuits described in the last paragraph are packaged in two ways: The back panel. Chapter 34 The engineering design of the Stretch computer 439 | a Double Card, which has 4 times the capacity of a single card and which has wiring on both sides of the board. Furthermore, components are double-stacked; and again, the rail is used to effect circuit variations due to different applications. Eighteen double card types are used in the system. Approximately 4,000 double cards are used, housing 60% of the transistors. The rest of the transistors are on approximately 18,000 single cards. The cards, both single and double, are assembled in gates, and two gates are assembled into a frame. Figure 15 shows the gate back-panel wiring, using wire-wraps; and Figs. 16 and 17 the frame construction, both in a closed and open version. To achieve high performance, special emphasis must be placed on keeping noise to a low level. This required the use of a plane Fig. 17. The frame (extended). which overlies the whole back panel, against which the intercircuit wiring is laid. In addition, the power-supply distribution system must be of such a low impedance that extraneous noise cannot induce circuit malfunction. For this reason, a bus system, consist- ing of laminated copper sheets, is used to distribute the power to each row of card sockets. The wiring rules are such that single- conductor wire is used up to a maximum of 24", twisted pair to a maximum of 36", unterminated coax to a maximum of 60", and terminated coax to a maximum of 100 feet. The whole back-panel construction and the application of single wire, twisted pair, or coax are calculated by a computer program to minimize the noise on each circuit node. of The two gates a frame are a sliding- pair with the power supply mounted on the sliding portion. All connecting wires between frames are coax and arrayed in layers which are formed into a drape. References BlaaG59; BrooF57a, 59; BuchW58; DunwS56; BobeJ58; BlosR60; Fig. 16. The frame (closed). BuchW57, 62; BrooF60; CockJ59; CoddE59, 62.