DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
Updated for Intel® Quartus® Prime Design Suite: 21.1
IP Version: 19.4.0
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Contents
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide...... 3 1.1. Directory Structure...... 3 1.2. Hardware and Software Requirements...... 6 1.3. Generating the Design...... 7 1.4. Simulating the Design...... 8 1.5. Compiling and Testing the Design ...... 9 1.5.1. Regenerating ELF File...... 11 1.6. DisplayPort Intel FPGA IP Design Example Parameters...... 12 2. Parallel Loopback Design Examples...... 14 2.1. Intel Stratix 10 DisplayPort SST Parallel Loopback Design Features...... 14 2.1.1. Enabling Adaptive Sync Support...... 17 2.2. Creating RX-Only or TX-Only Designs...... 17 2.3. Design Components...... 19 2.4. Clocking Scheme...... 21 2.5. Interface Signals and Parameters...... 23 2.6. Hardware Setup...... 35 2.7. Simulation Testbench...... 36 2.8. DisplayPort Transceiver Reconfiguration Flow...... 40 2.9. Transceiver Lane Configurations...... 41 3. HDCP Over DisplayPort Design Example for Intel Stratix 10 Devices...... 44 3.1. High-bandwidth Digital Content Protection (HDCP)...... 44 3.2. HDCP Over DisplayPort Design Example Architecture...... 46 3.3. Nios II Processor Software Flow...... 50 3.4. Design Walkthrough...... 52 3.4.1. Set Up the Hardware...... 52 3.4.2. Generate the Design...... 53 3.4.3. Include HDCP Production Keys...... 53 3.4.4. Compile the Design...... 61 3.4.5. View the Results...... 61 3.5. Protection of Encryption Key Embedded in FPGA Design...... 62 3.6. Security Considerations...... 63 3.7. Debug Guidelines...... 64 3.7.1. HDCP Status Signals...... 64 3.7.2. Modifying HDCP Software Parameters...... 64 3.7.3. HDCP Key Mapping from DCP Key Files...... 65 3.7.4. Frequently Asked Questions (FAQ)...... 71 4. DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide Archives...... 73
5. Revision History for the DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide...... 74
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1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
The DisplayPort Intel® FPGA IP design examples for Intel Stratix® 10 devices feature a simulating testbench and a hardware design that supports compilation and hardware testing.
The DisplayPort Intel FPGA IP offers the following design examples: • DisplayPort SST parallel loopback with a Pixel Clock Recovery (PCR) module • DisplayPort SST parallel loopback without a PCR module • High-bandwidth Digital Content Protection (HDCP) over DisplayPort Note: The HDCP feature is not included in the Intel Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https:// www.intel.com/content/www/us/en/broadcast/products/programmable/ applications/connectivity-solutions.html.
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Steps
Compilation Functional (Simulator) Simulation
Design Example Compilation Hardware Generation (Quartus Prime) Testing
Related Information • DisplayPort Intel FPGA IP User Guide • DisplayPort Intel FPGA IP Release Notes Describes changes to the IP in a particular release.
1.1. Directory Structure
The directories contain the generated files for the DisplayPort design example.
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, eASIC, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide UG-20193 | 2021.05.11
Figure 2. Directory Structure for the Design Example
db s10_dp_demo.v s10_dp_demo.v build_ip.tcl dp_demo xcvr_dp_reconfig_arbiter.sv xcvr_dp_reconfig_arbiter.sv build_sw.sh s10_dp_demo.qpf config.h bitec_reconfig_alt_s10.v bitec_reconfig_alt_s10.v build_sw_hcdp.sh s10_dp_demo.qsf main.c example.sdc dp_analog.mappings.v rx_utils.c reset_gen.sv aldec tx_utils.c reset_sync.sv cadence tx_utils.h clkrec mentor core xcelium rx_phy core tx_phy rx_phy
tx_phy
Table 1. Other Generated Files in RTL Folder
Folders Files
clkrec /altera_pll_reconfig_core.v
/altera_pll_reconfig_mif_reader.v
/altera_pll_reconfig_top.v
/bitec_clkrec.qip
/bitec_clkrec.sdc
/bitec_clkrec.v
/bitec_dp_add.v
/bitec_dp_cdc.v
/bitec_dp_cdc_fifo.v
/bitec_dp_cdc_pulse.v
/bitec_dp_cnt.v
/bitec_dp_dcfifo.v
/bitec_dp_dd.v
/bitec_dp_div.v
/bitec_dp_mult.v
/bitec_fpll_calc.v
/bitec_fpll_cntrl.v
/bitec_fpll_reconf.v continued...
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Folders Files
/bitec_loop_cntrl.v
/bitec_vsyngen.v
/clkrec_pll135_s10.ip
/clkrec_pll_s10.ip
/clkrec_reset_s10.ip
core /dp_core.qsys
/dp_rx.qsys
/dp_tx.qsys
rx_phy /gxb_rx.ip
/gxb_rx_reset.ip
/rx_phy_top.v
tx_phy /gxb_tx.ip
/gxb_tx_reset.ip
/gxb_tx_fpll.ip
/tx_phy_top.v
Table 2. Other Generated Files in Simulation Folder
Folders Files
aldec /aldec.do
/rivierapro_setup.tcl
cadence /cds.lib
/hdl.var
/ncsim.sh
/ncsim_setup.sh
core /dp_core.ip
/dp_rx.ip
/dp_tx.ip
mentor /mentor.do
/msim_setup.tcl continued...
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Folders Files
rx_phy /gxb_rx.ip
/rx_phy_top.v
/gxb_rx_reset.ip
synopsys /vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/synopsys_sim_setup
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
testbench /a10_dp_harness.sv
/clk_gen.v
/freq_check.v
/rx_freq_check.v
/tx_freq_check.v
/vga_driver.v
tx_phy /gxb_tx.ip
/gxb_tx_fpll.ip
/gxb_tx_reset.ip
/tx_phy_top.v
xcelium /cds.lib
/hdl.var
/xcelium_sim.sh
/xcelium_setup.sh
1.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example.
Hardware
• Intel Stratix 10 GX FPGA L-tile or H-tile Development Kit • DisplayPort Source (Graphics Processing Unit (GPU)) • DisplayPort Sink (Monitor) • Bitec DisplayPort FMC daughter card (Revisions 8.0 to 11.0) • DisplayPort cables
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Software
• Intel Quartus Prime Pro Edition (for hardware testing) • ModelSim* - Intel FPGA Edition, ModelSim - Intel FPGA Starter Edition, NCSim (Verilog only), Riviera-PRO*, Xcelium*or VCS* (Verilog only)/VCS MX simulator
1.3. Generating the Design
Use the DisplayPort Intel FPGA IP parameter editor in the Intel Quartus Prime Pro Edition software to generate the design example.
Figure 3. Generating the Design Flow
Start Parameter Specify IP Variation Select Specify Initiate Editor and Select Device Design Parameters Example Design Design Generation
1. Click Tools ➤ IP Catalog, and select Intel Stratix 10 as the target device family. Note: The design example only support Intel Stratix 10 devices. 2. In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP . The New IP Variation window appears. 3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named
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Table 3. Default Device for Intel Stratix 10 GX FPGA Development Kit
DisplayPort Intel FPGA IP Version Default Device
1SG280LU2F50E2VG (L-tile) Version 19.3.0 1SG280HU2F50E2VG (H-tile)
10. Click Generate Example Design.
1.4. Simulating the Design
The DisplayPort Intel FPGA IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench.
Figure 4. Design Simulation Flow
Change to Run Analyze
1. Navigate to the simulation folder of your choice. 2. Run the simulation script for the supported simulator. The script compiles and runs the testbench in the simulator. 3. Analyze the results.
Table 4. Steps to Run Simulation
Simulator Working Directory Instructions
In the command line, type Riviera-PRO /simulation/aldec vsim -c -do aldec.do
In the command line, type ModelSim /simulation/mentor vsim -c -do mentor.do
In the command line, type NCSim /simulation/cadence source ncsim.sh
In the command line, type Xcelium /simulation/xcelium source xcelium.sh
In the command line, type VCS /simulation/synopsys/vcs source vcs_sim.sh
In the command line, type /simulation/synopsys/ VCS MX vcsmx source vcsmx_sim.sh
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A successful simulation ends with the following message:
# SINK CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c, # SOURCE CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c, # Pass: Test Completed
1.5. Compiling and Testing the Design
Compile Design Test Design in Quartus Prime Set Up Hardware Program Device in Hardware Software
To compile and run a demonstration test on the hardware example design, follow these steps: 1. Ensure hardware example design generation is complete. 2. Launch the Intel Quartus Prime Pro Edition software and open
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Note: The latest Bitec DisplayPort FMC daughter card has different schematics compared to the earlier revisions.
Table 5. RX Transceiver Channel Mapping
Parameter Revisions 8 Revision 10 Revision 11 Description and Earlier
Polarity Not inverted Inverted Inverted • When RX polarity is inverted, each lane at the rx_polinv port of the Native PHY is driven to 1 in the rx_phy_top.v file. • When RX polarity is not inverted, each lane at the rx_polinv port of the Native PHY is driven to 0 in the rx_phy_top.v file.
Order Not reversed Not reversed Reversed The rx_parallel_data port of the Native PHY is directly mapped to the rx_parallel_data port of the DisplayPort IP.
Table 6. TX Transceiver Channel Mapping
Parameter Revisions 8 Revision 10 Revision 11 Description and Earlier
Polarity Inverted Not inverted Not inverted • When TX polarity is inverted, each lane at the tx_polinv port of the Native PHY is driven to 1 in the tx_phy_top.v file. • When TX polarity is not inverted, each lane at the tx_polinv port of the Native PHY is driven to 0 in the tx_phy_top.v file.
Order Reversed Not reversed Not reversed • When the lane order is reversed, the data input at the tx_parallel_data port of the Native PHY is swapped in the tx_phy_top.v file based on the lane count configuration. • When the lane order is not reversed, tx_parallel_data port of the Native PHY is directly mapped to the tx_parallel_data port of the DisplayPort IP.
To support all revisions, the design example top level RTL file at
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DisplayPort Intel FPGA IP version 19.3.0:
localparam BITEC_DP_CARD_REV = 2;
// 0 = Bitec FMC DP card rev.4 - 8,
// 1 = rev.10
// 2 = rev.11
in
#define BITEC_DP_CARD_REV 2
// set to 0 = Bitec FMC DP card rev.4 - 8
// set to 1 = Bitec FMC DP card rev.10
// set to 2 = Bitec FMC DP card rev.11 The default value is 2. If the config.h file is updated, you must run build_sw.sh in the script folder before compiling the Intel Quartus Prime Pro Edition project to ensure the software is effective. 3. Click Processing ➤ Start Compilation. 4. After successful compilation, the Intel Quartus Prime Pro Edition software generates a .sof file in your specified directory. 5. Connect the DisplayPort RX connector on the Bitec daughter card to an external DisplayPort source, such as the graphics card on a PC. 6. Connect the DisplayPort TX connector on the Bitec daughter card to a DisplayPort sink device, such as a video analyzer or a PC monitor. 7. Ensure all switches on the development board are in default position. 8. Configure the selected Intel Stratix 10 device on the development board using the generated .sof file (Tools ➤ Programmer ). 9. The DisplayPort sink device displays the video generated from the video source.
Related Information Intel Stratix 10 GX FPGA Development Kit User Guide
1.5.1. Regenerating ELF File
By default, the ELF file is generated when you generate the dynamic design example. However, in some cases, you need to regenerate the ELF file if you modify the software file or regenerate the dp_core.qsys file. Regenerating the dp_core.qsys file updates the .sopcinfo file, which requires you to regenerate the ELF file. 1. Go to
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Note: To execute build script on Windows 10, your system requires Windows Subsystems for Linux (WSL). For more information about WSL installation steps, refer to the Nios II Software Developer Handbook. • On Linux, launch the Platform Designer, and open Tools ➤ Nios II Command Shell. In the Nios II Command Shell, go to
Related Information Nios II Software Developer Handbook Provides information about how to install Windows Subsystem for Linux (WSL) on Windows.
1.6. DisplayPort Intel FPGA IP Design Example Parameters
Table 7. DisplayPort Intel FPGA IP Design Example Parameters for Intel Stratix 10 Devices
Parameter Value Description
Available Design Example
Select Design • None Select the design example to be generated. • DisplayPort SST • None: No design example is available for the current parameter Parallel Loopback selection with PCR • DisplayPort SST Parallel Loopback with PCR: This design example • DisplayPort SST demonstrates parallel loopback from DisplayPort sink to DisplayPort Parallel Loopback source through a Pixel Clock Recovery (PCR) module when you turn without PCR off the Enable Video Input Image Port parameter. • DisplayPort SST Parallel Loopback without PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source without a Pixel Clock Recovery (PCR) module when you turn on the Enable Video Input Image Port parameter.
Design Example Files
Simulation On, Off Turn on this option to generate the necessary files for the simulation testbench.
Synthesis On, Off Turn on this option to generate the necessary files for Intel Quartus Prime compilation and hardware demonstration.
Generated HDL Format
Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset. Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
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Target Development Kit
Select Board • No Development Select the board for the targeted design example. Kit • No Development Kit: This option excludes all hardware aspects for • Intel Stratix 10 the design example. The IP core sets all pin assignments to virtual FPGA H-tile pins. Development Kit • Intel Stratix 10 H-tile FPGA Development Kit: This option • Intel Stratix 10 automatically selects the project's target device to match the device FPGA L-tile on this development kit. You may change the target device using the Development Kit Change Target Device parameter if your board revision has a • Custom different device variant. The IP core sets all pin assignments Development Kit according to the development kit. • Intel Stratix 10 FPGA L-tile Development Kit: This option automatically selects the project's target device to match the device on this development kit. You may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit. • Custom Development Kit: This option allows the design example to be tested on a third-party development kit with an Intel FPGA. You may need to set the pin assignments on your own.
Target Device
Change Target Device On, Off Turn on this option and select the preferred device variant for the development kit.
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2. Parallel Loopback Design Examples
The DisplayPort Intel FPGA IP design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module.
Table 8. DisplayPort Intel FPGA IP Design Example for Intel Stratix 10 Devices
Design Example Designation Data Rate Channel Mode Loopback Type
DisplayPort SST parallel DisplayPort SST HBR3, HBR2, HBR, Simplex Parallel with PCR loopback with PCR and RBR
DisplayPort SST parallel DisplayPort SST HBR3, HBR2, HBR, Simplex Parallel without PCR loopback without PCR and RBR
2.1. Intel Stratix 10 DisplayPort SST Parallel Loopback Design Features
The SST parallel loopback design examples demonstrate the transmission of a single video stream from DisplayPort sink to DisplayPort source with or without Pixel Clock Recovery (PCR).
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, eASIC, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 2. Parallel Loopback Design Examples UG-20193 | 2021.05.11
Figure 5. Intel Stratix 10 DisplayPort SST Parallel Loopback with PCR Top Core System (Platform Designer) RX Sub-System TX Sub-System
PIO Avalon-MM Avalon-MM PIO Interconnect Interconnect CPU Sub-System Debug FIFO DisplayPort DisplayPort Debug FIFO RX Core TX Core EDID RAM
Audio Data
Video Data Video Data Pixel Clock Recovery (PCR)
RX PHY Top TX PHY Top IOPLL TX PLL
Transceiver PHY Transceiver Transceiver Transceiver Transceiver PHY Reset Controller Native PHY Arbiter Native PHY Reset Controller
RX Reconfiguration TX Reconfiguration Management Management
Control/Status Parallel Data Serial Data Avalon-MM • In this variant, the DisplayPort source’s parameter, TX_SUPPORT_IM_ENABLE, is turned off and the standard VSYNC/HSYNC/DE video interface is used. • The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface. • The IOPLL drives the video clock at a fixed frequency (in this case, 160 MHz). • If DisplayPort sink’s MAX_LINK_RATE is configured to HBR2 and PIXELS_PER_CLOCK is configured to Dual, the video clock runs at 300 MHz to support 4Kp60 pixel rate (594/2 = 297 MHz). Otherwise, the video clock runs at 160 MHz. • The design uses the pixel recovery clock (PCR) to recover the pixel clock according to the received MSA information from the sink and converts the RX parallel video interface to the standard VSYNC/HSYNC/DE interface. • The PCR output drives the source video interface and encodes to the DisplayPort main link before transmitting to the monitor. • The recovered clock drives the TX video clock.
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Figure 6. Intel Stratix 10 DisplayPort SST Parallel Loopback without PCR Top Core System (Platform Designer) RX Sub-System TX Sub-System
PIO Avalon-MM Avalon-MM PIO Interconnect Interconnect CPU Sub-System Debug FIFO DisplayPort DisplayPort Debug FIFO RX Core TX Core EDID RAM
Audio Data
Video Data
RX PHY Top TX PHY Top IOPLL TX PLL
Transceiver PHY Transceiver Transceiver Transceiver Transceiver PHY Reset Controller Native PHY Arbiter Native PHY Reset Controller
RX Reconfiguration TX Reconfiguration Management Management
Control/Status Parallel Data Serial Data Avalon-MM • In this variant, the DisplayPort source’s parameter, TX_SUPPORT_IM_ENABLE, is turned on (“1”) and the video image interface is used. • The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface. • The DisplayPort sink video output directly drives the DisplayPort source video interface and encodes to the DisplayPort main link before transmitting to the monitor. • The IOPLL drives both the DisplayPort sink and source video clocks at a fixed frequency. • If DisplayPort sink and source's MAX_LINK_RATE parameter is configured to HBR2 and PIXELS_PER_CLOCK is configured to Dual, the video clock runs at 300 MHz to support 4Kp60 pixel rate (594/2 = 297 MHz). Otherwise, the video clock runs at 160 MHz.
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Table 9. Design Example Variant Comparison
Design Example PCR Module Enable Video Image Adaptive Sync Video Interface Interface
DisplayPort SST Required No Not supported Standard VSYNC/ parallel loopback with HSYNC/DE interface PCR (txN_video_in)
DisplayPort SST Not required Yes Supported Video Image Interface parallel loopback (txN_video_in_im) without PCR
2.1.1. Enabling Adaptive Sync Support
To enable support for the Adaptive Sync feature in the design examples without PCR, you need to edit the MSA_TIMING_PAR_IGNORED bit of the DPCD 00007h register and the MSA_TIMING_PAR_IGNORE_EN bit of the DPCD 00107h register in the rx_utils.c file in the software folder.
Note: The Adaptive Sync feature is applicable only when you turn on the Enable GPU control parameter.
To edit the bits: 1. Locate data[7] = 0x80; // DPCD_ADDR_DOWN_STREAM_PORT_COUNT. 2. Change 0x80 to 0xC0. 3. Locate data[7] = 0x00; // DPCD_ADDR_DOWNSPREAD_CTRL 4. Change 0x00 to 0x80. 5. Regenerate the ELF file, refer to Regenerating ELF File on page 11. 6. After programming the SOF file into the FPGA, program the updated ELF file into the FPGA.
2.2. Creating RX-Only or TX-Only Designs
For advanced users, you can use the DisplayPort design to create a TX- or RX-only design.
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Figure 7. Components Required for RX-Only or TX-Only Design Top Core System (Platform Designer) RX Sub-System TX Sub-System
PIO Avalon-MM Avalon-MM PIO Interconnect Interconnect CPU Sub-System Debug FIFO DisplayPort DisplayPort Debug FIFO RX Core TX Core EDID RAM
Audio Data
Video Data Video Data Pixel Clock Recovery (PCR)
RX PHY Top Video Pattern TX PHY Top IOPLL TX PLL Generator Transceiver PHY Transceiver Transceiver Transceiver Transceiver PHY Reset Controller Native PHY Arbiter Native PHY Reset Controller
RX Reconfiguration TX Reconfiguration Management Management
Control/Status Parallel Data RX Only Component Removed Component Serial Data Avalon-MM TX Only Component Required Component
To use RX- or TX-only components: • Remove the irrelevant blocks from the design. • Edit the config.h file in the software folder to specify if DP_SUPPORT_RX and DP_SUPPORT_TX is 1 or 0. The default setting for both parameters is 1. — For TX-only design, set DP_SUPPORT_RX and BITEC_RX_GPUMODE to 0. — For RX-only design, set DP_SUPPORT_TX to 0.
Table 10. RX-Only and TX-Only Design Requirements
User Requirement Preserve Remove Add
DisplayPort RX Only RX PHY Top; • TX Top Video Processing IP Core System consists of: • PCR (if not needed) • RX sub-system • Transceiver Arbiter • CPU sub-system
DisplayPort TX Only TX PHY Top; • RX Top Video Pattern Generator Core System consists of: • PCR • TX sub-system • Transceiver Arbiter • CPU sub-system
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2.3. Design Components
The DisplayPort Intel FPGA IP design example requires these components.
Table 11. Core System Components
Module Description
Core System (Platform Designer) The core system consists of the Nios II Processor and its necessary components, DisplayPort RX and TX core sub-systems. This system provides the infrastructure to interconnect the Nios II processor with the DisplayPort Intel FPGA IP (RX and TX instances) through Avalon memory- mapped (Avalon-MM) interface within a single Platform Designer system to ease the software build flow. This system consists of: • CPU Sub-System • RX Sub-System • TX Sub-System
RX Sub-System (Platform Designer) The RX sub-system consists of: • Clock Source—The clock source to the DisplayPort RX core. This sub-system has two clock sources integrated: 100 MHz and 16 MHz. • Reset Bridge—The bridge that connects the external signal to the sub-system. This bridge synchronizes to the respective clock source before it is used. • DisplayPort RX Core—DisplayPort Sink IP core, VESA DisplayPort Standard version 1.4. • Debug FIFO—This FIFO captures all DisplayPort RX auxiliary cycles, and prints out in the Nios II Debug terminal. • PIO—The parallel IO that triggers the MSA capture, and prints out when the on-board push button (PB) is pressed. • Avalon-MM Pipeline Bridge—This Avalon-MM bridge interconnects the Avalon- MM interface between components within the RX sub-system to the Nios II processor in the Core sub-system. • EDID—The EDID RAM is only used to store the desired EDID value in the RAM and connect to the DisplayPort Sink IP core. This component is only used when you disable the Enable GPU Control option in the RX core.
TX Sub-System (Platform Designer) The TX sub-system consists of: • Clock Source—The clock source to the DisplayPort TX core. This sub-system has two clock sources integrated: 100 MHz and 16 MHz. • Reset Bridge—The bridge that connects the external signal to the sub-system. This bridge synchronizes to the respective clock source before it is used. • DisplayPort TX Core—DisplayPort Source IP core, VESA DisplayPort Standard version 1.4. • Debug FIFO—This FIFO captures all DisplayPort TX auxiliary cycles, and prints out in the Nios II Debug terminal. This component is only used when the TX_AUX_DEBUG parameter is turned on. • PIO—The parallel IO that triggers the DPTX register update in software (tx_utils.c). • Avalon-MM Pipeline Bridge—This Avalon-MM bridge interconnects the Avalon- MM interface between components within the TX sub-system to the Nios II processor in the Core sub-system.
Table 12. DisplayPort RX PHY Top and TX PHY Top Components
Module Description
RX PHY Top The RX PHY top level consists of the components related to the receiver PHY layer. continued...
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Module Description
• Transceiver Native PHY (RX)—The transceiver block that receives the serial data from an external video source and deserializes it to 20-bit or 40-bit parallel data to the DisplayPort sink IP core. This block supports up to 8.1 Gbps (HBR3) data rate with 4 channels. • Transceiver PHY Reset Controller—The RX Reconfiguration Management module triggers the reset input of this controller to generate the corresponding analog and digital reset signals to the Transceiver Native PHY block according to the reset sequencing. • RX Reconfiguration Management—This block reconfigures and recalibrates the Transceiver Native PHY block to receive serial data in the supported data rates (RBR, HBR, HBR2, and HBR3).
TX PHY Top The TX PHY top level consists of the components related to the transmitter PHY layer. • Transceiver Native PHY (TX)—The transceiver block that receives 20-bit or 40-bit parallel data from the DisplayPort Intel FPGA IP and serializes the data before transmitting it. This block supports up to 8.1 Gbps (HBR3) data rate with 4 channels. Note: You must set the TX channel bonding mode to PMA and PCS bonding and the PCS TX Channel bonding master parameter to 0 (default is auto). • Transceiver PHY Reset Controller—The TX Reconfiguration Management module triggers the reset input of this controller to generate the corresponding analog and digital reset signals to the Transceiver Native PHY block according to the reset sequencing. • TX Reconfiguration Management—This block reconfigures and recalibrates the Transceiver Native PHY and TX PLL blocks to transmit serial data in the required data rates (RBR, HBR, HBR2, and HBR3). • TX PLL—The transmitter PLL block provides a fast serial fast clock to the Transceiver Native PHY block. For the DisplayPort Intel FPGA IP design example, Intel uses transmitter fractional PLL (FPLL).
Table 13. Loopback Top Component
Module Description
Pixel Clock Recovery (PCR) This module recovers pixel clock (derived from the DisplayPort Sink MSA information). PCR dynamically detects the received video format and recovers the corresponding pixel clock. This module also integrates a DCFIFO as video data buffer from the receiver and transmitter clock domains. This module supports resolutions up to 8Kp30 only. Note: Your design may not require PCR if you use your own recovery logic or any of the Video and Image Processing (VIP) IP cores.
Table 14. Top-Level Common Blocks
Module Description
Transceiver Arbiter This generic functional block prevents transceivers from recalibrating simultaneously when either RX or TX transceivers within the same physical channel require reconfiguration. The simultaneous recalibration impacts applications where RX and TX transceivers within the same channel are assigned to independent IP implementations. This transceiver arbiter is an extension to the resolution recommended for merging simplex TX and simplex RX into the same physical channel. This transceiver arbiter also assists in merging and arbitrating the Avalon-MM RX and TX reconfiguration requests targeting simplex RX and TX transceivers within a channel as the reconfiguration interface port of the transceivers can only be accessed sequentially. The transceiver arbiter is not required when only either RX or TX transceiver is used in a channel. continued...
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Module Description
The transceiver arbiter identifies the requester of a reconfiguration through its Avalon-MM reconfiguration interfaces and ensures that the corresponding tx_reconfig_cal_busy or rx_reconfig_cal_busy is gated accordingly.
IOPLL IOPLL generates common source clock: dp_rx_vid_clkout and clk_16 (16 MHz) for the DisplayPort system. • dp_rx_vid_clkout—used as RX core video clock of the video data stream and PCR video input clock. • clk_16—Used as DisplayPort auxiliary clock and PCR reference clock.
2.4. Clocking Scheme
The clocking scheme illustrates the clock domains in the DisplayPort Intel FPGA IP design example.
Figure 8. DisplayPort Intel FPGA IP Design Example Clocking Scheme Top Core System (Qsys)
RX Sub-System (Qsys) TX Sub-System (Qsys)
PIO Avalon-MM Avalon-MM PIO Interconnect Interconnect
Debug FIFO CPU Sub-System Debug FIFO DisplayPort DisplayPort RX Core TX Core EDID RAM
IOPLL
Pixel Clock RX PHY Top TX PHY Top Recovery (PCR) TX PLL
Transceiver PHY Transceiver Transceiver Transceiver Transceiver PHY Reset Controller Native PHY Arbiter Native PHY Reset Controller
RX Reconfiguration TX Reconfiguration Management Management
TX Transceiver clkout RX Video Clock 16 MHz Clock TX PLL/RX CDR refclock/ RX Transceiver clkout TX Video Clock Calibration Clock PCR refclk (135 MHz) Audio Clock Management Clock
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Table 15. Clocking Scheme Signals
Clock Signal Name in Design Description
TX PLL Refclock tx_pll_refclk 135 MHz TX PLL reference clock, that is divisible by the transceiver for all DisplayPort data rates (1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps). Note: The reference clock source of the TX PLL refclock is located at the HSSI refclk pin.
TX Transceiver Clockout gxb_tx_clkout TX clock recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock.
Data Rate Symbols per Frequency Clock (MHz)
RBR (1.62 Gbps) 2 (dual) 81
4 (quad) 40.5
HBR (2.7 Gbps) 2 (dual) 135
4 (quad) 67.5
HBR2 (5.4 Gbps) 2 (dual) 270
4 (quad) 135
HBR3 (8.1 Gbps) 4 (quad) 202.5
TX PLL Serial Clock gxb_tx_bonding_clocks Serial fast clock generated by TX PLL. The clock frequency is set based on the data rate.
RX Refclock rx_cdr_refclk 135 MHz transceiver clock data recovery (CDR) reference clock, that is divisible by all DisplayPort data rates (1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps). Note: The reference clock source of the RX refclock is located at the HSSI refclk pin.
RX Transceiver Clockout gxb_rx_clkout RX clock recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock.
Data Rate Symbols per Frequency Clock (MHz)
RBR (1.62 Gbps) 2 (dual) 81
4 (quad) 40.5
HBR (2.7 Gbps) 2 (dual) 135
4 (quad) 67.5
HBR2 (5.4 Gbps) 2 (dual) 270
4 (quad) 135
HBR3 (8.1 Gbps) 4 (quad) 202.5
Management Clock rx_rcfg_mgmt_clk A free running 100 MHz clock for both Avalon-MM interfaces tx_rcfg_mgmt_clk for reconfiguration and PHY reset controller for transceiver reset sequence.
Component Required Frequency (MHz)
Avalon-MM reconfiguration 100 – 125
Transceiver PHY reset controller 1 – 500 continued...
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Clock Signal Name in Design Description
Audio Clock dp_audio_clk DisplayPort audio clock.
16 MHz Clock clk_16 160 MHz clock used to encode and decode auxiliary channel in the DisplayPort Intel FPGA IP source and sink IP cores. This clock is also used as a reference clock in the Pixel Clock module for fractional calculation.
Calibration Clock dp_rx_clk_cal A 50 MHz calibration clock input that must be synchronous to dp_tx_clk_cal the Transceiver Reconfiguration module's clock. This clock is used in the DisplayPort Intel FPGA IP core's reconfiguration logic.
RX Video Clock dp_rx_vid_clkout Video clock for DisplayPort sink to clock video data stream. If MAX_LINK_RATE = HBR2 and PIXELS_PER_CLOCK = Dual, video clock uses 300 MHz. Otherwise, fixed to 160 MHz.
TX Video Clock tx_vid_clk Recovered video clock from the PCR module that reflects the actual video clock frequency. Used when DisplayPort source's TX_SUPPORT_IM_ENABLE = 0.
TX IM Clock tx_im_clk Video clock for DisplayPort source to clock video data stream. Must be the same as the RX video clock in this design. Used when DisplayPort source's TX_SUPPORT_IM_ENABLE = 1.
2.5. Interface Signals and Parameters
The tables list the signals and parameter for the DisplayPort Intel FPGA IP design example.
Table 16. Top-Level Signals
Signal Direction Width Description
On-board Oscillator Signal
refclk1_p Input 1 100 MHz clock source used as IOPLL reference clock and Avalon-MM management clock
User Push Buttons and LEDs
user_pb[0] Input 1 Push button to trigger MSA print out during debug
user_pb[2] Input 1 Push button to switch to the next video stream, for the MST parallel loopback with PCR design example.
cpu_resetn Input 1 Global reset
user_led_g Output 4 Red LED display Note: Refer to Hardware Setup on page 35 for the on- board user LED functions.
user_led_r Output 4 Green LED display Note: Refer to Hardware Setup on page 35 for the on- board user LED functions.
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DisplayPort FMC Daughter Card Pins on FMC Port A
fmca_gbtclk_m2c_p Input 1 135 MHz dedicated transceiver reference clock from FMC port A
fmca_dp_m2c_p Input N DisplayPort RX serial data Note: N = RX maximum lane count
fmca_dp_c2m_p Output N DisplayPort TX serial data Note: N = TX maximum lane count
fmca_la_tx_p_10 Input 1 DisplayPort RX cable detect • 1 = Cable detected • 0 = Cable not detected
fmca_la_rx_n_8 Input 1 DisplayPort RX power detect • 1 = Power not detected • 0 = Power detected
fmca_la_tx_n_9 Input 1 DisplayPort RX Aux In
fmca_la_rx_n_6 Output 1 DisplayPort RX Aux Out
fmca_la_tx_p_9 Output 1 DisplayPort RX Aux OE
fmca_la_rx_p_6 Output 1 DisplayPort RX HPD • 1 = HPD asserted • 0 = HPD deasserted
fmca_la_rx_n_9 Input 1 DisplayPort TX HPD • 1 = HPD asserted • 0 = HPD deasserted
fmca_la_tx_p_12 Input 1 DisplayPort TX Aux In
fmca_la_rx_p_10 Output 1 DisplayPort TX Aux Out
fmca_la_rx_n_10 Output 1 DisplayPort TX Aux OE
fmca_la_tx_n_12 Output 1 TX CAD for Bitec FMC Rev. 8
fmca_la_tx_p_14 Output 1 TX CAD for Bitec FMC Rev. 10 and 11
FMC On-board Retimer Reconfiguration Interface
fmca_la_tx_p_0 Inout 1 Bitec FMC Rev. 10: PS8460_SDA Bitec FMC Rev. 11: MCDP6000_SDA
fmca_la_tx_n_0 Inout 1 Bitec FMC Rev. 10: PS8460_SCL Bitec FMC Rev. 11: MCDP6000_SDL
fmca_la_rx_p_0 Output 1 Bitec FMC Rev. 10: PS8460_EQ0 Bitec FMC Rev. 11: Unused
fmca_la_rx_n_0 Output 1 Bitec FMC Rev. 10: PS8460_EQ1 Bitec FMC Rev. 11: Unused
fmca_la_tx_p_1 Output 1 Bitec FMC Rev. 10: PS8460_PDN Bitec FMC Rev. 11: Unused
fmca_la_tx_n_1 Output 1 Bitec FMC Rev. 10: PS8460_CFG0 Bitec FMC Rev. 11: Unused
fmca_la_tx_p_2 Output 1 Bitec FMC Rev. 10: PS8460_CFG1 continued...
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FMC On-board Retimer Reconfiguration Interface
Bitec FMC Rev. 11: Unused
fmca_la_tx_n_2 Output 1 Bitec FMC Rev. 10: PS8460_CFG2 Bitec FMC Rev. 11: Unused
Table 17. DisplayPort Intel FPGA IP Signals (Platform Designer System)
Signal Direction Width Description
Clock and Reset
clk_100_in_clk Input 1 100 MHz clock to CPU sub-system
cpu_reset_bridge_in_ Input 1 Reset to CPU sub-system (active low) reset_n
DisplayPort RX Signals
dp_rx_reset_bridge_i Input 1 Reset to RX sub-system (active low) n_reset_n
dp_rx_clk_16_in_clk Input 1 RX Auxiliary clock (16 MHz)
dp_rx_dp_sink_clk_ca Input 1 RX reconfiguration calibration clock l
dp_rx_pio_0_in_port Input 1 Push button IO for debug purpose
dp_rx_dp_sink_rx_aud Output 1 RX Audio Interface io_valid Note: M = RX audio channel dp_rx_dp_sink_rx_aud Output 1 io_mute
dp_rx_dp_sink_rx_aud Output 40 io_infoframe
dp_rx_dp_sink_rx_aud Output M*32 io_lpcm_data
dp_rx_dp_sink_rx_aux Input 1 RX auxiliary interface _in
dp_rx_dp_sink_rx_aux Output 1 _out
dp_rx_dp_sink_rx_aux Output 1 _oe
dp_rx_dp_sink_rx_hpd Output 1 RX HPD
dp_rx_dp_sink_rx_cab Input 1 RX cable detect (active high) le_detect
dp_rx_dp_sink_rx_pwr Input 1 RX power detect (active high) _detect
dp_rx_dp_sink_rx_msa Output 217 DisplayPort RX MSA
dp_rx_dp_sink_rx_lan Output 5 DisplayPort RX lane count e_count continued...
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DisplayPort RX Signals
dp_rx_dp_sink_rx_lin Output 2 RX Link Rate 2-bit indicator, used in PCR k_rate • RBR: 2‘b00 • HBR: 2‘b01 • HBR2: 2‘b10 • HBR3: 2'b11
dp_rx_dp_sink_rx_lin Output 8 RX Link Rate 8-bit indicator, used in transceiver k_rate_8bits reconfiguration management • RBR: 0x06 • HBR: 0x0A • HBR2: 0x14 • HBR3: 0x1E
dp_rx_dp_sink_rx_ss_ Output 1 DisplayPort RX secondary stream interface valid
dp_rx_dp_sink_rx_ss_ Output 160 data
dp_rx_dp_sink_rx_ss_ Output 1 sop
dp_rx_dp_sink_rx_ss_ Output 1 eop
dp_rx_dp_sink_rx_ss_ Output 1 clk
dp_rx_dp_sink_rx_str Output 1 RX post scrambler stream data. For debug purpose. eam_valid Note: S = RX symbols per clock dp_rx_dp_sink_rx_str Output 1 eam_clk
dp_rx_dp_sink_rx_str Output S*32 eam_data
dp_rx_dp_sink_rx_str Output S*4 eam_ctrl
dp_rx_dp_sink_rx_vid Input 1 DisplayPort RX video stream interface. _clk Note: B = RX bits per color, P = RX pixels per clock dp_rx_dp_sink_rx_vid Output 1 _sol
dp_rx_dp_sink_rx_vid Output 1 _eol
dp_rx_dp_sink_rx_vid Output 1 _sof
dp_rx_dp_sink_rx_vid Output 1 _eof
dp_rx_dp_sink_rx_vid Output 1 _locked
dp_rx_dp_sink_rx_vid Output 1 _interlace
dp_rx_dp_sink_rx_vid Output 1 _field continued...
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DisplayPort RX Signals
dp_rx_dp_sink_rx_vid Output 1 _overflow
dp_rx_dp_sink_rx_vid Output B*P*3 _data
dp_rx_dp_sink_rx_vid Output P _valid
dp_rx_dp_sink_rx_par Input N *S*10 DisplayPort parallel data from RX Native PHY allel_data Note: N = RX maximum lane count, S = RX symbols per clock
dp_rx_dp_sink_rx_std Input N CDR clock out from RX Native PHY _clkout Note: N = RX maximum lane count
dp_rx_dp_sink_rx_res Output 1 Reset signal to RX Native PHY Reset controller when RX tart data loses alignment. Triggered by the DisplayPort RX core.
dp_rx_dp_sink_rx_rec Output 1 Transceiver reconfiguration interface to the RX onfig_req reconfiguration management module Note: N = RX maximum lane count dp_rx_dp_sink_rx_rec Input 1 onfig_ack
dp_rx_dp_sink_rx_rec Input 1 onfig_busy
dp_rx_dp_sink_rx_bit Output N slip
dp_rx_dp_sink_rx_cal input N _busy
dp_rx_dp_sink_rx_ana Output N logreset
dp_rx_dp_sink_rx_dig Output N italreset
dp_rx_dp_sink_rx_is_ Input N lockedtoref
dp_rx_dp_sink_rx_is_ Input N lockedtodata
dp_rx_dp_sink_rx_set Output N _locktoref
dp_rx_dp_sink_rx_set Output N _locktodata
DisplayPort TX Signals
dp_tx_reset_bridge_i Input 1 Reset to TX sub-system n_reset_n
dp_tx_clk_16_in_clk Input 1 TX Auxiliary clock (16 MHz)
dp_tx_dp_source_clk_ Input 1 TX reconfiguration calibration clock cal
dp_tx_dp_source_tx_a Input 1 TX audio channel interface udio_valid Note: M = TX audio channel continued...
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DisplayPort TX Signals
dp_tx_dp_source_tx_a Input 1 udio_mute
dp_tx_dp_source_tx_a Input M*32 udio_lpcm_data
dp_tx_dp_source_tx_a Input 1 udio_clk
dp_tx_dp_source_tx_a Input 1 TX auxiliary interface ux_in
dp_tx_dp_source_tx_a Output 1 ux_out
dp_tx_dp_source_tx_a Output 1 ux_oe
dp_tx_dp_source_tx_h Input 1 TX HPD pd
dp_tx_dp_source_tx_l Output 2 TX Link Rate 2-bit indicator, used in transceiver ink_rate reconfiguration management • RBR: 2‘b00 • HBR: 2‘b01 • HBR2: 2‘b10 • HBR3: 2'b11
dp_tx_dp_source_tx_l Output 8 TX Link Rate 8-bit indicator, used in transceiver ink_rate_8bits reconfiguration management • RBR: 0x06 • HBR: 0x0A • HBR2: 0x14 • HBR3: 0x1E
dp_tx_dp_source_tx_s Output 1 DisplayPort TX secondary stream interface s_ready
dp_tx_dp_source_tx_s Input 1 s_valid
dp_tx_dp_source_tx_s Input 128 s_data
dp_tx_dp_source_tx_s Input 1 s_sop
dp_tx_dp_source_tx_s Input 1 s_eop
dp_tx_dp_source_tx_s Output 1 s_clk
dp_tx_dp_source_tx_v Input 1 DisplayPort TX video stream (VYSNC/HSYNC/DE) id_clk interface (only used when TX_SUPPORT_IM_ENABLE = 0) dp_tx_dp_source_tx_v Input B*P*3 Note: B = TX bits per color, P = TX pixels per clock. id_data
dp_tx_dp_source_tx_v Input P id_v_sync
dp_tx_dp_source_tx_v Input P id_h_sync continued...
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DisplayPort TX Signals
dp_tx_dp_source_tx_v Input P id_de
dp_tx_dp_source_tx_i Input 1 DisplayPort TX video image interface (only used when m_clk TX_SUPPORT_IM_ENABLE = 1) Note: B = TX bits per color, P = TX pixels per clock. dp_tx_dp_source_tx_i Input 1 m_sol
dp_tx_dp_source_tx_i Input 1 m_eol
dp_tx_dp_source_tx_i Input 1 m_sof
dp_tx_dp_source_tx_i Input 1 m_eof
dp_tx_dp_source_tx_i Input B*P*3 m_data
dp_tx_dp_source_tx_i Input 1 m_valid
dp_tx_dp_source_tx_i Input 1 m_locked
dp_tx_dp_source_tx_i Input 1 m_interlace
dp_tx_dp_source_tx_i Input 1 m_field
dp_tx_dp_source_tx_p Output N*S*10 DisplayPort parallel data to TX Native PHY arallel_data Note: N = TX maximum lane count, S = TX symbols per clock
dp_tx_dp_source_tx_s Input N TX Native PHY clock out td_clkout Note: N = TX maximum lane count
dp_tx_dp_source_tx_p Input 1 TX PLL locked indicator ll_locked
dp_tx_dp_source_tx_r Output 1 Transceiver Reconfiguration interface to TX econfig_req reconfiguration management module Note: N = TX maximum lane count dp_tx_dp_source_tx_r Input 1 econfig_ack
dp_tx_dp_source_tx_r Input 1 econfig_busy
dp_tx_dp_source_tx_p Output 1 ll_powerdown
dp_tx_dp_source_tx_a Output 1 nalog_reconfig_req
dp_tx_dp_source_tx_a Input 1 nalog_reconfig_ack
dp_tx_dp_source_tx_a Input 1 nalog_reconfig_busy continued...
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DisplayPort TX Signals
dp_tx_dp_source_tx_v Output N*2 od
dp_tx_dp_source_tx_e Output N*2 mp
dp_tx_dp_source_tx_a Output N nalogreset
dp_tx_dp_source_tx_d Output N igitalreset
dp_tx_dp_source_tx_c Input N al_busy
Table 18. RX PHY Top-Level Signals
Signal Direction Width Description
rx_cdr_refclk Input 1 RX Native PHY CDR reference clock. This design example uses 135 MHz.
dp_rx_clk_cal Output 1 50 MHz DisplayPort RX reconfiguration calibration clock. This clock must be synchronous to rcfg_mgmt_clk.
rx_cdr_resetn Input 1 RX Native PHY reset (active low)
video_pll_locked Input 1 This signal indicates that the video PLL (video clock and clk16) is stable and locked. Use as reset to the DisplayPort Intel FPGA IP and the transceiver.
dp_rx_link_rate_8bit Input 8 RX link rate indicator, used in transceiver reconfiguration s management
rx_rcfg_mgmt_reset Input 1 RX reconfiguration reset
rx_rcfg_mgmt_clk Input 1 RX reconfiguration management clock (100 MHz)
rx_rcfg_en Output 1 RX reconfiguration enable signal
rx_rcfg_write Output 1 Reconfiguration Avalon® memory-mapped interfaces that interact with Transceiver Arbiter rx_rcfg_read Output 1 Note: N = RX maximum lane count (1, 2, or 4) rx_rcfg_address Output 12
rx_rcfg_writedata Output 32
rx_rcfg_readdata Input 32
rx_rcfg_waitrequest Input 1
rx_rcfg_cal_busy Input N
gxb_rx_rcfg_write Input N Reconfiguration Avalon memory-mapped interfaces from Transceiver Arbiter gxb_rx_rcfg_read Input N Note: N = RX maximum lane count (1, 2, or 4) gxb_rx_rcfg_address Input N*10
gxb_rx_rcfg_writedat Input N*32 a
gxb_rx_rcfg_readdata Output N*32 continued...
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Signal Direction Width Description
gxb_rx_rcfg_waitrequ Output N est
gxb_rx_rcfg_cal_busy Output N
gxb_rx_clkout Output N RX Native PHY CDR clock out Note: N = RX maximum lane count (1, 2, or 4)
gxb_rx_serial_data Input N DisplayPort Serial Data to RX Native PHY Note: N = RX maximum lane count (1, 2, or 4)
dp_rx_parallel_data Output N*S*10 DisplayPort parallel data to DisplayPort RX core Note: N = RX maximum lane count (1, 2, or 4), S = RX symbols per clock (2 or 4)
dp_rx_restart Input 1 Reset signal to the RX Native PHY Reset controller when RX data loses alignment. Triggered by the DisplayPort RX core.
dp_rx_rcfg_req Input 1 Transceiver Reconfiguration interface from the DisplayPort RX core dp_rx_rcfg_ack Output 1 Note: N = RX maximum lane count (1, 2, or 4) dp_rx_rcfg_busy Output 1
dp_rx_is_lockedtoref Output N
dp_rx_is_lockedtodat Output N a
dp_rx_bitslip Input N
dp_rx_cal_busy Output 1
dp_rx_set_locktoref Input N
dp_rx_set_locktodata Input N
Table 19. TX PHY Top-Level Signals
Signal Direction Width Description
tx_pll_refclk Input 1 TX transceiver PLL reference clock. This design example uses 135 MHz.
dp_tx_clk_cal Output 1 50 MHz DisplayPort TX reconfiguration calibration clock. This clock must be synchronous to rcfg_mgmt_clk.
tx_pll_resetn Input 1 TX transceiver PLL reset (active low)
video_pll_locked Input 1 This signal indicates that the video PLL (video clock and clk16) is stable and locked. Use as reset to the DisplayPort Intel FPGA IP and the transceiver.
tx_cad Output 1 Driven to FMC card TX CAD. Tied to 0.
dp_tx_link_rate_8bit Input 8 TX Link Rate indicator, used in transceiver s reconfiguration management. • RBR: 0x06 • HBR: 0x0A • HBR2: 0x14 • HBR3: 0x1E
tx_rcfg_mgmt_reset Input 1 TX reconfiguration reset continued...
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Signal Direction Width Description
tx_rcfg_mgmt_clk Input 1 TX reconfiguration management clock (100 MHz)
tx_rcfg_en Output 1 TX reconfiguration enable signal
tx_rcfg_write Output 1 Reconfiguration Avalon memory-mapped interfaces to Transceiver Arbiter tx_rcfg_read Output 1 Note: N = TX maximum lane count (1, 2, or 4) tx_rcfg_address Output 12
tx_rcfg_writedata Output 32
tx_rcfg_readdata Input 32
tx_rcfg_waitrequest Input 1
tx_rcfg_cal_busy Input N
gxb_tx_rcfg_write Input N Reconfiguration Avalon memory-mapped interfaces from Transceiver Arbiter gxb_tx_rcfg_read Input N Note: N = TX maximum lane count (1, 2, or 4) gxb_tx_rcfg_address Input N*10
gxb_tx_rcfg_writedat Input N*32 a
gxb_tx_rcfg_readdata Output N*32
gxb_tx_rcfg_waitrequ Output N est
gxb_tx_rcfg_cal_busy Output N
gxb_tx_clkout Output N Transceiver clock out Note: N = TX maximum lane count (1, 2, or 4)
gxb_tx_serial_data Output N DisplayPort Serial Data from Transceiver Note: N = TX maximum lane count
dp_tx_parallel_data Input N*S*10 DisplayPort Parallel Data from DisplayPort TX Core Note: N = TX maximum lane count (1, 2, or 4), S = TX symbols per clock (2 or 4)
dp_tx_rcfg_req Input 1 Transceiver Reconfiguration interface from DisplayPort TX Core dp_tx_rcfg_ack Output 1 Note: N = TX maximum lane count (1, 2, or 4) dp_tx_rcfg_vod Input 8
dp_tx_rcfg_emp Input 8
dp_txpll_rcfg_req Input 1
dp_txpll_rcfg_ack Output 1
dp_tx_rcfg_busy Output 1
dp_txpll_powerdown Input 1
dp_tx_cal_busy Output N
dp_txpll_locked Output 1
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Table 20. Transceiver Arbiter Signals
Signal Direction Width Description
clk Input 1 Reconfiguration clock. This clock must share the same clock with the reconfiguration management blocks.
reset Input 1 Reset signal. This reset must share the same reset with the reconfiguration management blocks.
rx_rcfg_en Input 1 RX reconfiguration enable signal
tx_rcfg_en Input 1 TX reconfiguration enable signal
rx_rcfg_ch Input 2 Indicates which channel to be reconfigured on the RX core. This signal must always remain asserted.
tx_rcfg_ch Input 2 Indicates which channel to be reconfigured on the TX core. This signal must always remain asserted.
rx_reconfig_mgmt_wri Input 1 Reconfiguration Avalon memory-mapped interfaces from te the RX reconfiguration management
rx_reconfig_mgmt_rea Input 1 d
rx_reconfig_mgmt_add Input 10 ress
rx_reconfig_mgmt_wri Input 32 tedata
rx_reconfig_mgmt_rea Output 32 ddata
rx_reconfig_mgmt_wai Output 1 trequest
tx_reconfig_mgmt_wri Input 1 Reconfiguration Avalon memory-mapped interfaces from te the TX reconfiguration management
tx_reconfig_mgmt_rea Input 1 d
tx_reconfig_mgmt_add Input 10 ress
tx_reconfig_mgmt_wri Input 32 tedata
tx_reconfig_mgmt_rea Output 32 ddata
tx_reconfig_mgmt_wai Output 1 trequest
reconfig_write Output 1 Reconfiguration Avalon memory-mapped interfaces to the transceiver reconfig_read Output 1
reconfig_address Output 10
reconfig_writedata Output 32
rx_reconfig_readdata Input 32
rx_reconfig_waitrequ Input 1 est continued...
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Signal Direction Width Description
tx_reconfig_readdata Input 1
tx_reconfig_waitrequ Input 1 est
rx_cal_busy Input 1 Calibration status signal from the RX transceiver
tx_cal_busy Input 1 Calibration status signal from the TX transceiver
rx_reconfig_cal_busy Output 1 Calibration status signal to the RX transceiver PHY reset control
tx_reconfig_cal_busy Output 1 Calibration status signal from the TX transceiver PHY reset control
Table 21. Pixel Clock Recovery Signals
The PCR module in the dynamic generation design example is an enhanced version where 2 Fractional PLLs (FPLLs) are used.
Signal Direction Width Description
areset Input 1 PCR reset
clk Input 1 Control loop clock (16 MHz)
clk_135 Input 1 135 MHz clock
rx_link_clk Input 1 RX Native PHY CDR clock out
rx_link_rate Input 2 RX link rate 2-bit indicator
rx_msa Input 217 RX MSA
vidin_clk Input 1 RX video clock. If MAX_LINK_RATE = HBR2 and PIXELS_PER_CLOCK = Dual, uses 300 MHz. Otherwise, fixed to 160 MHz.
vidin_data Input B*P*3 RX video stream interface from RX core Note: B = RX bits per color, P = RX pixels per clock. vidin_valid Input 1
vidin_locked Input 1
vidin_sof Input 1
vidin_eof Input 1
vidin_sol Input 1
vidin_eol Input 1
rec_clk Output 1 Reconstructed/recovered video clock
rec_clk_x2 Output 1 Reconstructed/recovered video clock (2x faster); not used
vidout Output B*P*3 TX video stream interface Note: B = TX bits per color, P = TX pixels per clock. hsync Output 1
vsync Output 1
de Output 1
field2 Output 1
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Table 22. Pixel Clock Recovery Parameters You can use these parameters to configure the clock recovery core.
Parameter Default Value Description
PIXELS_PER_CLOCK 1 Specifies how many pixels in parallel (for each clock cycle) are gathered from the DisplayPort RX core (1, 2 or 4).
BPP 24 Specifies the width (in bits) of a single pixel. 1 bit per pixel is equivalent to 3* bits per color.
CLK_PERIOD_NS 10 Specifies the period (in nanoseconds) of the clock signal connected to the port. In this design example, the value used is 62.
DEVICE_FAMILY Intel Stratix 10 Identifies the family of the device used.
FIXED_NVID 0 Specifies the configuration of the DisplayPort RX received video clocking used. • 1 if GPU NVID is fixed to 'h8000 • 0 if GPU NVID is not fixed Select 0 if you require the PCR to inter-operate with any GPU. Select 1 if you want to optimize resources but take note that this option may not work with certain GPUs.
2.6. Hardware Setup
The DisplayPort Intel FPGA IP design example is 8Kp30 capable and performs a loop- through for a standard DisplayPort video stream.
1. To run the hardware test, connect a DisplayPort-enabled source device to the DisplayPort FMC daughter card sink input. 2. The DisplayPort sink decodes the port into a standard video stream and sends it to the clock recovery core. 3. The clock recovery core synthesizes the original video pixel clock to be transmitted together with the received video data. Note: You require the clock recovery feature to produce video without using a frame buffer. 4. The clock recovery core then sends the video data to the DisplayPort source and the Transceiver Native PHY TX block. 5. Connect the DisplayPort FMC daughter card source port to a monitor to display the image.
Table 23. On-board User LED Functions
LEDs Function
USER_LED_G[0] This LED indicates that the source is successfully lane-trained. At this point, the IP core asserts rx0_vid_locked.
USER_LED_G[2:1] These LEDs indicate the RX link rate. continued...
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LEDs Function
• 2'b00 = RBR • 2'b01 = HBR • 2'b10 = HBR2 • 2'b11 = HBR3
USER_LED_R[3:0] These LEDs illuminate design example lane counts. • 4'b0001 = 1 lane • 4'b0010 = 2 lanes • 4'b0100 = 4 lanes
2.7. Simulation Testbench
The simulation testbench simulates the DisplayPort TX serial loopback to RX.
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Figure 9. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram
a10_dp_harness Clock Generator Testbench Video Pattern 100 MHz, 135 MHz Control Generator
Top Clocked Video Interface Converter
Core System (Platform Designer) RX Sub-System TX Sub-System PIO PIO DisplayPort DisplayPort Debug FIFO Debug FIFO RX Core TX Core EDID RAM
RX PHY Top TX PHY Top IOPLL TX PLL
Transceiver PHY Transceiver Transceiver Transceiver Transceiver PHY Reset Controller Native PHY Arbiter Native PHY Reset Controller
RX Reconfiguration TX Reconfiguration Management Management
RX Link Speed Clock TX Link Speed Clock Frequency Checker Frequency Checker
Control/Status Avalon-MM Serial Data Clock Parallel Data
Table 24. Testbench Components
Component Description
Video Pattern Generator This generator produces color bar patterns that you can configure. You can parameterize the video format timing.
Testbench Control This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX core. The testbench control block also reads the CRC value from both source and sink to make comparisons.
RX Link Speed Clock Frequency This checker verifies if the RX transceiver recovered clock frequency matches the Checker desired data rate.
TX Link Speed Clock Frequency This checker verifies if the TX transceiver recovered clock frequency matches the Checker desired data rate.
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The simulation testbench does the following verifications:
Test Criteria Verification
• Link Training sweep across all data rates from HBR3 to Integrates Frequency Checker to measure the Link Speed HBR2 to HBR and RBR clock's frequency output from the TX and RX transceiver. • Read the DPCD registers to check if the DP Status sets and measures both TX and RX Link Speed frequency.
• Run video pattern from TX to RX. • Connects video pattern generator to the DisplayPort • Verify the CRC for both source and sink to check if they Source to generate the video pattern. match. • Testbench control next reads out both Source and Sink CRC from DPTX and DPRX registers and compares to ensure both CRC values are identical. Note: To ensure CRC is calculated, you must enable the Support CTS test automation parameter.
A successful simulation ends with the following message:
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Table 25. DisplayPort Design Example Supported EDA Simulators
Simulator Supported Platform Supported Language
Riviera-PRO Windows/Linux VHDL and Verilog HDL
ModelSim Windows/Linux VHDL and Verilog HDL
NCSim Linux Verilog HDL
Xcelium Parallel Linux Verilog HDL
VCS/VCS MX Linux VHDL and Verilog HDL
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2.8. DisplayPort Transceiver Reconfiguration Flow
The VESA DisplayPort Standard version 1.4 supports 4 link rates (8.1 Gbps, 5.4 Gbps, 2.7 Gbps, and 1.62 Gbps). You can dynamically switch from 1 data rate to another. Transceiver reconfiguration is required to support dynamic link rate switching.
The DisplayPort Intel FPGA IP design examples require some level of reconfiguration and recalibration but with some modification. In these design examples, the pre- calibration method is implemented to reduce the transceiver reconfiguration duration.
Figure 10. Transceiver Reconfiguration Flowchart Reset/Power Up
Start
Reconfigure Transceiver Start Recalibration DisplayPort New to RBR, HBR, and HBR2 Link Rate Request?
Yes Reconfigure Transceiver to Lane 1, 2, and 4 Recalibration Busy? Reconfigure Transceiver to Requested Link Rate
No No All Lane Counts Done? Reconfigure Transceiver to Store Calibrated Register Requested Lane Count according to Data Rate
Yes Retrieve Calibrated Register Value According to Data Rate No Reconfiguration Busy?
Reconfigure the Calibrated Register
No Yes All Data Rate Done?
Reconfiguration Busy?
No
Done Yes
Pre-calibration DisplayPort Link Training
The following sequences describe the flow. 1. Upon power up or push button reset, the DisplayPort reconfiguration module initiates the transceiver reconfiguration to sweep across all supported link rate and all lane count. a. For TX FPLL, these register offsets are reconfigured:
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• 11’h12B (TXPLL M Counter) • 11’h12C (TXPLL L Counter) b. For RX CDR, these register offsets are reconfigured: • 11’h13a (RX L PFD and PD Counter) • 11’h13b (RX M Counter) 2. After reconfiguration completes, recalibration initiates per data rate. 3. After calibration completes, the pre-defined calibrated registers will be stored according to the respective data rate. a. For TX FPLL, these register offsets are recalibrated: • 11’h10A (PLL VCO Frequency Band 0 fix low bits) • 11’h123 (PLL VCO Frequency Band 1 fix) • 11’h133 • 11’h136 b. For RX CDR, these register offsets are recalibrated: • 11’h132 (CDR VCO Speed fix) • 11’h133 (Charge Pump Vcc register) • 11’h135 (LF PFD and PD Register) • 11’h136 (CDR VCO Speed fix) • 11’h137 (CDR VCO Speed fix) • 11’h139 (Charge Pump current PFD and PD register) 4. Steps 1 through 3 are repeated until all supported data rates are covered. 5. When the pre-calibration steps complete, the reconfiguration module is ready to start DisplayPort link training. 6. Whenever the DisplayPort Intel FPGA IP sends a new link rate request, the reconfiguration module initiates reconfiguration to the transceiver. 7. The reconfiguration flow includes retrieving the calibrated register offset value that corresponds to the link rate and reconfigure it to the transceiver. No recalibration is required. 8. When reconfiguration completes, the transceiver is ready to receive the link rate. 9. The DisplayPort reconfiguration module continues to monitor if a new link rate request is detected. If it detects a new request, the module repeats step 5.
2.9. Transceiver Lane Configurations
If you want to configure your design to use 1, 2 or 4 lanes targeting different versions of Bitec FMC daughter cards, you have to configure the pin assignments accordingly in the Intel Quartus Prime Pro Settings File (QSF).
To configure the DisplayPort Intel FPGA IP design example using 1, 2 or 4 lanes, follow these steps:
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1. In both the DisplayPort Source and Sink parameter editors, set the Maximum lane count parameter to 1, 2 or 4. 2. Generate the design example. 3. Make the following assignments in the Assignment Editor.
Table 26. Pin Assignments for Bitec FMC Revision 8 or Earlier
DisplayPort Pin Location Four Lanes Two Lanes One Lane (Intel Stratix 10 Development Kit)
BJ4 fmca_dp_c2m_p[0] Not applicable Not applicable
BJ5 fmca_dp_c2m_n[0]
BF5 fmca_dp_c2m_p[1]
BF6 fmca_dp_c2m_n[1] Source BG3 fmca_dp_c2m_p[2] fmca_dp_c2m_p[0]
BG4 fmca_dp_c2m_n[2] fmca_dp_c2m_n[0]
BE3 fmca_dp_c2m_p[3] fmca_dp_c2m_p[1] fmca_dp_c2m_p[0]
BE4 fmca_dp_c2m_n[3] fmca_dp_c2m_n[1] fmca_dp_c2m_n[0]
BH9 fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] fmca_dp_m2c_p[0]
BH10 fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] fmca_dp_m2c_n[0]
BJ7 fmca_dp_m2c_p[1] fmca_dp_m2c_p[1] Not applicable
BJ8 fmca_dp_m2c_n[1] fmca_dp_m2c_n[1] Sink BG7 fmca_dp_m2c_p[2] Not applicable
BG8 fmca_dp_m2c_n[2]
BE7 fmca_dp_m2c_p[3]
BE8 fmca_dp_m2c_n[3]
Transceiver Avalon XCVR_RECONFIG_GR Enable Disable Disable Memory-Mapped OUP Interface Group
Table 27. Pin Assignments for Bitec FMC Revision 10
DisplayPort Pin Location (Intel Four Lanes Two Lanes One lane Stratix 10 Development Kit)
Source BJ4 fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] fmca_dp_c2m_p[0]
BJ5 fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] fmca_dp_c2m_n[0]
BF5 fmca_dp_c2m_p[1] fmca_dp_c2m_p[1] Not Applicable
BF6 fmca_dp_c2m_n[1] fmca_dp_c2m_n[1]
BG3 fmca_dp_c2m_p[2] Not Applicable
BG4 fmca_dp_c2m_n[2]
BE3 fmca_dp_c2m_p[3]
BE4 fmca_dp_c2m_n[3] continued...
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DisplayPort Pin Location (Intel Four Lanes Two Lanes One lane Stratix 10 Development Kit)
Sink BH9 fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] fmca_dp_m2c_p[0]
BH10 fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] fmca_dp_m2c_n[0]
BJ7 fmca_dp_m2c_p[1] fmca_dp_m2c_p[1] Not Applicable
BJ8 fmca_dp_m2c_n[1] fmca_dp_m2c_n[1]
BG7 fmca_dp_m2c_p[2] Not Applicable
BG8 fmca_dp_m2c_n[2]
BE7 fmca_dp_m2c_p[3]
BE8 fmca_dp_m2c_n[3]
Merging of XCVR_RECONFIG_GR Enable Enable Enable Reconfiguration OUP 1 Interfaces
Table 28. Pin Assignments for Bitec FMC Revision 11
DisplayPort Pin Location Four Lanes Two Lanes One Lane (Intel Stratix 10 Development Kit)
BJ4 fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] fmca_dp_c2m_p[0]
BJ5 fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] fmca_dp_c2m_n[0]
BF5 fmca_dp_c2m_p[1] fmca_dp_c2m_p[1] Not applicable
BF6 fmca_dp_c2m_n[1] fmca_dp_c2m_n[1] Source BG3 fmca_dp_c2m_p[2] Not applicable
BG4 fmca_dp_c2m_n[2]
BE3 fmca_dp_c2m_p[3]
BE4 fmca_dp_c2m_n[3]
BH9 fmca_dp_m2c_p[0] Not applicable Not applicable
BH10 fmca_dp_m2c_n[0]
BJ7 fmca_dp_m2c_p[1]
BJ8 fmca_dp_m2c_n[1] Sink BG7 fmca_dp_m2c_p[2] fmca_dp_m2c_p[0]
BG8 fmca_dp_m2c_n[2] fmca_dp_m2c_n[0]
BE7 fmca_dp_m2c_p[3] fmca_dp_m2c_p[1] fmca_dp_m2c_p[0]
BE8 fmca_dp_m2c_n[3] fmca_dp_m2c_n[1] fmca_dp_m2c_n[0]
Transceiver Avalon XCVR_RECONFIG_GR Enable Disable Disable Memory-Mapped OUP Interface Group
Note: You can disable the non-applicable pin assignments in the Assignment Editor.
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3. HDCP Over DisplayPort Design Example for Intel Stratix 10 Devices
The HDCP over DisplayPort hardware design example helps you to evaluate the functionality of the HDCP feature and enables you to use the feature in your Intel Stratix 10 designs.
Note: The HDCP feature is not included in the Intel Quartus Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/ broadcast/products/programmable/applications/connectivity-solutions.html.
3.1. High-bandwidth Digital Content Protection (HDCP)
High-bandwidth Digital Content Protection (HDCP) is a form of digital rights protection to create a secure connection between the source to the display.
Intel created the original technology, which is licensed by the Digital Content Protection LLC group. HDCP is a copy protection method where the audio/video stream is encrypted between the transmitter and the receiver, protecting it against illegal copying.
The HDCP features adheres to HDCP Specification version 1.3 and HDCP Specification version 2.3.
The HDCP 1.3 and HDCP 2.3 IPs perform all computation within the hardware core logic with no confidential values (such as private key and session key) being accessible from outside the encrypted IP.
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, eASIC, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 3. HDCP Over DisplayPort Design Example for Intel Stratix 10 Devices UG-20193 | 2021.05.11
Table 29. HDCP IP Functions
HDCP IP Functions
HDCP 1.3 IP • Authentication exchange — Computation of master key (Km) — Generation of random An — Computation of session key (Ks), M0 and R0. • Authentication with repeater — Computation and verification of V and V’ • Link integrity verification — Computation of frame key (Ki), Mi and Ri. • All cipher modes including hdcpBlockCipher, hdcpStreamCipher, hdcpRekeyCipher, and hdcpRngCipher • True random number generator (TRNG) — Hardware based, full digital implementation and non-deterministic random number generator
HDCP 2.3 IP • Master Key (km), Session Key (ks) and nonce (rn, riv) generation — Compliant to NIST.SP800-90A random number generation • Authentication and key exchange — Generation of random numbers for rtx and rrx compliant to NIST.SP800-90A random number generation — Signature verification of receiver certificate (certrx) using DCP public key (kpubdcp) — 3072 bits RSASSA-PKCS#1 v1.5 — RSAES-OAEP (PKCS#1 v2.1) encryption and decryption of Master Key (km) — Derivation of kd (dkey0, dkey1) using AES-CTR mode — Computation and verification of H and H’ — Computation of Ekh(km) and km (pairing) • Authentication with repeater — Computation and verification of V and V’ — Computation and verification of M and M’ • System renewability (SRM) — SRM signature verification using kpubdcp — 3072 bits RSASSA-PKCS#1 v1.5 • Session Key exchange • Generation and computation of Edkey(ks) and riv. • Derivation of dkey2 using AES-CTR mode • Locality Check — Computation and verification of L and L’ — Generation of nonce (rn) continued...
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HDCP IP Functions
• Data stream management — AES-CTR mode based key stream generation • Asymmetric crypto algorithms — RSA with modulus length of 1024 (kpubrx) and 3072 (kpubdcp) bits — RSA-CRT (Chinese Remainder Theorem) with modulus length of 512 (kprivrx) bits and exponent length of 512 (kprivrx) bits • Low-level cryptographic function — Symmetric crypto algorithms • AES-CTR mode with a key length of 128 bits — Hash, MGF and HMAC algorithms • SHA256 • HMAC-SHA256 • MGF1-SHA256 — True random number generator (TRNG) • NIST.SP800-90A compliant • Hardware based, full digital implementation and non-deterministic random number generator
3.2. HDCP Over DisplayPort Design Example Architecture
The HDCP feature protects data as the data is transmitted between devices connected through a DisplayPort or other HDCP-protected digital interfaces.
The HDCP-protected systems include three types of devices: • Sources (TX) • Sinks (RX) • Repeaters
This design example demonstrates the HDCP system in a repeater device where it accepts data, decrypts, then re-encrypts the data, and finally retransmits data. Repeaters have both DisplayPort inputs and outputs. It instantiates the FIFO buffers to perform a direct DisplayPort video stream pass-through between the DisplayPort sink and source. It may perform some signal processing, such as converting videos into a higher resolution format by replacing the FIFO buffers with the Video and Image Processing (VIP) Suite IP cores.
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Figure 11. HDCP Over DisplayPort Design Example Block Diagram
Core System (Platform Designer) RX Subsystem TX Subsystem Intel FPGA DisplayPort RX IP 1 1 Intel FPGA DisplayPort TX IP Debug Debug FIFO HDCP1x RX IP HDCP2x TX IP FIFO 7 5 EDID HDCP2x RX IP CPU Subsystem HDCP1x TX IP RAM 6 4 4 HDCP Messages DisplayPort RX IP DisplayPort TX IP HDCP Messages (DisplayPort (DisplayPort Aux Channel) Aux Channel)
2 HDCP2x RX HDCP1x RX HDCP2x TX HDCP1x TX Key Mem Key Mem Key Mem Key Mem
Pixel Clock Recovery (PCR) & Pass-through Link Unencrypted DP Video TX PLL PHY Reset RX Native PHY 3 Controller IOPLL (Crypto) TX Native PHY PHY Reset Controller Encrypted Encrypted DisplayPort PHY Arbiter DisplayPort Video In RX Reconfig TX Reconfig Video Out
RX PHY Layer TX PHY Layer
Data Path: Block: Video Control & Status HDCP Message HDCP Production Key Required for HDCP
The following descriptions about the architecture of the design example correspond to the HDCP over DisplayPort design example block diagram. When SUPPORT HDCP KEY MANAGEMENT = 1, the design example hierarchy is slightly different from Figure 11 on page 47 but the underlying HDCP functions remain the same. 1. The HDCP1x and HDCP2x are IPs that are available through the DisplayPort Intel FPGA IP parameter editor. When you configure the DisplayPort IP in the parameter editor, you can enable and include either HDCP1x or HDCP2x or both IPs as part of the subsystem. With both HDCP IPs enabled, the DisplayPort IP configures itself in the cascade topology where the HDCP2x and HDCP1x IPs are connected back-to- back. • The HDCP egress interface of the DisplayPort TX sends unencrypted audio video data. • The unencrypted data gets encrypted by the active HDCP block and sent back into the DisplayPort TX over the HDCP Ingress interface for transmission over the link. • The CPU subsystem as the authentication master controller ensures that only one of the HDCP TX IPs is active at any given time and the other one is passive. • Similarly, the HDCP RX also decrypts data received over the link from an external HDCP TX. 2. You need to program the HDCP IPs with Digital Content Protection (DCP) issued production keys. Load the following keys:
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Table 30. DCP-issued Production Keys
HDCP TX/RX Keys
HDCP2x TX 16 bytes: Global Constant (lc128)
RX • 16 bytes (same as TX): Global Constant (lc128) • 320 bytes: RSA Private Key (kprivrx) • 522 bytes: RSA Public Key Certificate (certrx)
HDCP1x TX • 5 bytes: TX Key Selection Vector (Aksv) • 280 bytes: TX Private Device Keys (Akeys)
RX • 5 bytes: RX Key Selection Vector (Bksv) • 280 bytes: RX Private Device Keys (Bkeys)
The design example implements the key memories as simple dual-port, dual-clock synchronous RAM. For small key size like HDCP2x TX, the IP implements the key memory using registers in regular logic. Note: Intel does not provide the HDCP production keys with the design example or Intel FPGA IPs under any circumstances. To use the HDCP IPs or the design example, you must become an HDCP adopter and acquire the production keys directly from the Digital Content Protection LLC (DCP). To run the design example, you either edit the key memory files at compile time to include the production keys or implement logic blocks to securely read the production keys from an external storage device and write them into the key memories at run time. 3. You can clock the cryptographic functions implemented in the HDCP2x IP with any frequency up to 200 MHz. The frequency of this clock determines how quickly the HDCP2x authentication operates. You can opt to share the 100 MHz clock used for Nios® II processor but the authentication latency would be doubled compared to using a 200 MHz clock. 4. The values that must be exchanged between the HDCP TX and the HDCP RX are communicated over the DisplayPort AUX channel. The AUX controller is embedded within the DisplayPort IP. 5. The Nios II processor acts as the master in the authentication protocol and drives the control and status registers (Avalon-MM) of both the HDCP2x and HDCP1x TX IPs. The software drivers implements the authentication protocol state machine including certificate signature verification, master key exchange, locality check, session key exchange, pairing, link integrity check (HDCP1x), and authentication with repeaters, such as topology information propagation and stream management information propagation. The software drivers do not implement any of the cryptographic functions required by the authentication protocol. Instead, the HDCP IP hardware implements all the cryptographic functions ensuring no confidential values can be accessed. 6. In a DisplayPort application, the HDCP TX and HDCP RX IPs communicate the HDCP register values over the AUX channel. For a repeater application, the DisplayPort IP is configured in GPU mode where the HDCP registers in DPCD are defined in the embedded Nios II processor. The Nios II processor acts as an authentication master for the HDCP RX. The Nios II processor processes all HDCP register values received from the AUX controller in the DisplayPort sink before sending the values to the HDCP RX IP and vice versa. 7. In a true repeater demonstration where propagating topology information upstream is required, the Nios II processor drives the Repeater Message Port (Avalon memory-mapped) of both HDCP2x and HDCP1x RX IPs. The Nios II
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processor clears the RX REPEATER bit to 0 when it detects the connected downstream device is not HDCP-capable or when no downstream device is connected. Without downstream connection, the RX system is now an end-point receiver, rather than a repeater. Conversely, the Nios II processor sets the RX REPEATER bit to 1 upon detecting the downstream device is HDCP-capable.
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3.3. Nios II Processor Software Flow
The Nios II software flowchart includes the HDCP authentication controls over DisplayPort application.
Figure 12. Nios II Processor Software Flowchart
1. PHY Pre-calibration
4. HDCP2x Authentication New Link Rate 9. HDCP1x Authentication Request or Hot-plug? No
No Authenticated? Yes Authenticated? No
Yes 2. DisplayPort Link Training Yes
CP_IRQ Received? No No CP_IRQ Received? HDCP2x Yes Yes Authenticated? Yes
5. AUX No 10. AUX Reads RxStatus Reads Bstatus & Ri’ HDCP1x Yes Loss of Authenticated? Reads Ri Yes Synchronization? Compare Ri & Ri’ No No 3. Aux Loss of Reads RxCaps Synchronization? Yes No 6. ReceiverID_List Ready? No Yes Yes HDCP2x Capable? 11. KSV List Ready? No Verify No ReceiverID_List Yes 3. Aux Reads Bcaps No ReceiverID_List Verify KSV List Valid?
Yes HDCP1x Capable? Yes KSV List Valid? No Content Stream No Management Yes
7. Prepare & Write Prepare & Write ReceiverID_List & RxInfo KSV_List & Bstatus to Upstream to Upstream
8. Enable TX Encryption
1. The VESA DisplayPort Standard v1.4 supports four link rates (1.62 Gbps, 2.7 Gbps, 5.4 Gbps and 8.1 Gbps). You can dynamically switch from one data rate to another. Transceiver reconfiguration is required to support dynamic link rate switching. The DisplayPort IP design example implements pre-calibration method to reduce the transceiver reconfiguration duration. Upon power-up or push button
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reset, the DisplayPort reconfiguration block initiates the transceiver reconfiguration to sweep across all supported link rates and all lane counts. After each data rate completes reconfiguration, each data rate recalibrates. After calibration for each data rate completes, the pre-defined calibrated registers will be stored according to the respective date rate. 2. When the precalibration step completes, the reconfiguration block is ready to start DisplayPort link training. Whenever the DisplayPort IP sends a new link rate request or hot-plug event, the reconfiguration block initiates reconfiguration to the transceiver. The reconfiguration flow includes retrieving the calibrated register offset value that corresponds to the link rate and reconfiguring the value to the transceiver. No recalibration is required. When reconfiguration completes, the transceiver is ready to receive the link rate and HDCP authentication can be initiated. 3. The Nios II software starts the HDCP activity by commanding the DisplayPort AUX controller to read RxCaps followed by Bcaps from external RX to detect if the downstream device is HDCP-capable, or otherwise: • If the returned HDCP_CAPABLE bit of RxCaps is 1, the downstream device is HDCP2x-capable. • If the returned HDCP_CAPABLE bit of Bcaps is 1, the downstream device is HDCP1x-capable. • If the returned HDCP_CAPABLE bits of both RxCaps and Bcaps are 0, the downstream device is either not HDCP-capable or inactive. • If the downstream device is previously not HDCP-capable or inactive but is currently HDCP-capable, the software sets the REPEATER bit of the repeater upstream (RX) to 1 to indicate the RX is now a repeater. • If the downstream device is previously HDCP-capable but is currently not HDCP-capable or inactive, the software sets the REPEATER bit of to 0 to indicate the RX is now an endpoint receiver. 4. The software initiates the HDCP2x authentication protocol that includes RX certificate signature verification, master key exchange, locality check, session key exchange, pairing, authentication with repeaters such as topology information propagation. 5. When in authenticated state, the Nios II software processes the CP_IRQ interrupts if there is any, and reads the RxStatus register from external RX. If the software detects the REAUTH_REQ bit is set, it initiates re-authentication and disables TX encryption. 6. When the downstream device is a repeater and the READY bit of the RxStatus register is set to 1, this usually indicates the downstream device topology has changed. So, the Nios II software commands the AUX controller to read the ReceiverID_List from downstream device and verify the list. If the list is valid and no topology error is detected, the software proceeds to the Content Stream Management module. Otherwise, it initiates re-authentication and disables TX encryption. 7. The Nios II software prepares the ReceiverID_List and RxInfo values and then writes to the Avalon-MM Repeater Message port of the repeater upstream (RX). The RX then propagates the list to external TX (upstream). 8. Authentication is complete at this point. The software enables TX encryption.
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9. The software initiates the HDCP1x authentication protocol that includes key exchange and authentication with repeaters. 10. When the Nios II software encounters CP_IRQ interrupts, it performs link integrity check by reading and comparing Ri’ and Ri from external RX (downstream) and HDCP1x TX respectively. If the values do not match, this indicates loss of synchronization and the software initiates re-authentication and disables TX encryption. 11. If the downstream device is a repeater and the READY bit of the Bcaps register is set to 1, this usually indicates that the downstream device topology has changed. So, the Nios II software commands the AUX controller to read the KSV list value from the downstream device and verify the list. If the list is valid and no topology error is detected, the software prepares the KSV list and Bstatus value and writes to the Avalon-MM Repeater Message port of the repeater upstream (RX). The RX then propagates the list to external TX (upstream). Otherwise, it initiates re-authentication and disables TX encryption.
3.4. Design Walkthrough
Setting up and running the HDCP over DisplayPort design example consists of five stages. 1. Set up the hardware. 2. Generate the design. 3. Edit the HDCP key memory files to include your HDCP production keys. a. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) b. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) 4. Compile the design. 5. View the results.
3.4.1. Set Up the Hardware
The first stage of the demonstration is to set up the hardware.
To set up the hardware for the demonstration: 1. Connect the Bitec DisplayPort FMC daughter card (revision 10) to the Intel Stratix 10 development kit at FMC port A. 2. Connect the Intel Stratix 10 development kit to your PC using a USB cable. 3. Connect a DisplayPort cable from the DisplayPort RX connector on the Bitec DisplayPort FMC daughter card to an HDCP-enabled DisplayPort device, such as a graphic card with DisplayPort output. 4. Connect another DisplayPort cable from the DisplayPort TX connector on the Bitec DisplayPort FMC daughter card to an HDCP-enabled DisplayPort device, such as a display monitor with DisplayPort input.
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3.4.2. Generate the Design
Use the DisplayPort Intel FPGA IP parameter editor in the Intel Quartus Prime Pro Edition software to generate the design example.
Before you begin, ensure to install the HDCP feature in the Intel Quartus Prime Pro Edition software.
Note: The HDCP feature is not included in the Intel Quartus Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/ broadcast/products/programmable/applications/connectivity-solutions.html.
1. Click Tools ➤ IP Catalog, and select Intel Stratix 10 as the target device family. Note: The HDCP design example supports only Intel Arria® 10 and Intel Stratix 10 devices. 2. In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP . The New IP variation window appears. 3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named
3.4.3. Include HDCP Production Keys
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0)
After generating the design, you need to edit the HDCP key memory files to include your production keys.
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To include the production keys, follow these steps. 1. Locate the following key memory files in the
Figure 13. Wire Array of Facsimile Key R1 for Receiver Public Certificate
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Figure 14. Wire Array of Facsimile Key R1 for RX Private Key and Global Constant
3. Locate the placeholder for the production keys and replace with your own production keys in their respective wire array in big endian format.
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Figure 15. Wire Array of HDCP Production Keys (Placeholder)
4. Repeat Step 3 for all other key memory files. When you have finished including your production keys in all the key memory files, ensure that the USE_FACSIMILE parameter is set to 0 at the design example top level file (s10_dp_demo.v).
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3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
Figure 16. High Level Overview of HDCP Key Management
HDCP Production Keys (issued by DCPLLC) Intel FPGA Encrypted HDCP 1.x TX IP Aksv (40-bit) Akey (40x56-bit) Onchip Intel Processing Memory Encrypted HDCP KEYDEC Engine Production Keys
Encrypted HDCP 1.x RX IP Bksv (40-bit) Bkey (40x56-bit) Encrypted Encrypted Onchip Intel Processing HDCP HDCP Memory Encrypted HDCP KEYDEC Engine Production Production Production Keys Keys Keys EEPROM I2C Master Arbitration Encrypted HDCP 2.x TX IP Global Constant (128-bit)
Onchip Intel Processing Encrypted HDCP Encrypted Production Keys HDCP Memory Encrypted HDCP KEYDEC Engine Production Production Keys Keys Intel Encrypted HDCP 2.x RX IP Receiver ID (40-bit) KEYENC Receiver Public Key (1048-bit) Onchip Intel Processing DCPLLC Signature (3072-bit) Memory Encrypted HDCP KEYDEC Engine Global Constant (128-bit) Production Keys Receiver Private Key (2560-bit)
You can change the mif of an on-chip memory HDCP HDCP and use the “quartus_cdb --update_mif” assembler Production Protection flow to update the on-chip memory Keys Key with HDCP protection key without re-compiling.
When Support HDCP Key Management parameter is turned on, you hold control of HDCP production key encryption by using the key encryption (KEYENC) design that Intel provides. You must provide the HDCP production keys and a 128 bits HDCP protection key. The HDCP protection key encrypts the HDCP production key and the encrypted key is stored in the external flash memory (ie. EEPROM) on DisplayPort daughter card.
Turn on the Support HDCP Key Management parameter and the key decryption feature (KEYDEC) becomes available in the HDCP IP cores. You must use the same HDCP protection key in the KEYDEC to retrieve the HDCP production keys at run time for processing engines. KEYENC and KEYDEC support Atmel AT24CS32 32-Kbit serial EEPROM, Atmel AT24C16A 16-Kbit serial EEPROM and compatible I2C EEPROM devices with at least 16-Kbit rom size.
To include the HDCP production keys in the KEYENC design and program the encrypted HDCP production keys onto the EEPROM, follow these steps: 1. Copy the hardware demonstration files from the following path to your working directory:
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Figure 17. Data array of Facsimile Key R1 for RX Private Key
Figure 18. Data arrays of HDCP Production Keys (Placeholder)
Figure 19. Data array of HDCP Protection Key (Predefined key)
5. Run ./runall.tcl. This script executes the following commands: • Generate IP catalog files • Generate the Platform Designer system • Create an Intel Quartus Prime project • Create a software workspace and build the software • Perform a full compilation
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6. Download the Software Object File (.sof) to the FPGA to program the encrypted HDCP production keys onto the EEPROM. 7. To generate the EEPROM image file, edit the read_mem.tcl to make sure the hardware_name and device_name are matching to the running hardware. 8. Run "quartus_stp -t read_mem.tcl". The script generates an EEPROM image file in .hex file format under the same directory.
Generate the DisplayPort SST Parallel Loopback With PCR design example with Support HDCP 2.3 and Support HDCP 1.4 parameters turned on, then follow these steps to include the HDCP protection key. 1. Locate the following Memory Initialization Files (.mif) in the
Figure 20. HDCP protection key initialized in hdcp2x_rx_kmem.mif
3. Repeat Step 2 for the other memory initialization files as shown in the examples below.
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Figure 21. HDCP protection key initialized in hdcp2x_tx_kmem.mif
Figure 22. HDCP protection key initialized in hdcp1x_rx_kmem.mif
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Figure 23. HDCP protection key initialized in hdcp1x_tx_kmem.mif
3.4.4. Compile the Design
After you include your own production keys, you can now compile the design.
1. Launch the Intel Quartus Prime Pro Edition software and open
3.4.5. View the Results
At the end of the demonstration, you will be able to view the results on the HDCP- enabled DisplayPort external sink.
To view the results of the demonstration, follow these steps: 1. Power up the Intel FPGA board. 2. Change the directory to
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3.4.5.1. LED Functions
The LEDs on the board indicates the demonstration status.
Table 31. LED Indicators
LED Functions
RX PHY ready status. user_led_g[0] • 0: Not ready • 1: Ready
RX DisplayPort IP video lock status user_led_g[1] • 0: Unlocked • 1: Locked
RX HDCP1x IP decryption status. user_led_g[2] • 0: Inactive • 1: Active
RX HDCP2x IP decryption status. user_led_g[3] • 0: Inactive • 1: Active
TX data rate. • 2'b00: RBR user_led_r[1:0] • 2'b01: HBR • 2'b10: HBR2 • 2'b11: HBR3
TX HDCP1x IP encryption status. user_led_r[2] • 0: Inactive • 1: Active
TX HDCP2x IP encryption status. user_led_r[3] • 0: Inactive • 1: Active
3.5. Protection of Encryption Key Embedded in FPGA Design
Many FPGA designs implement encryption, and there is often the need to embed secret keys in the FPGA bitstream. In newer device families, such as Intel Stratix 10 and Intel Agilex, there is a Secure Device Manager block that can securely provision and manage these secret keys. Where these features do not exist, you can secure the content of the FPGA bitstream, including any embedded secret user keys, with encryption.
You can keep the user keys secure within your design environment, and ideally add to the design using an automated secure process. The following steps show how you can implement such a process with Intel Quartus Prime tools. 1. Develop and optimize the HDL in Intel Quartus Prime in a non-secure environment. 2. Transfer the design to a secure environment and implement an automated process to update the secret key. The on-chip memory embed the key value. When the key is updated, the memory initialization file (.mif) can change and the
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“quartus_cdb --update_mif” assembler flow can change the HDCP protection key without re-compiling. This step is very quick to run and preserves the original timing. 3. The Intel Quartus Prime bitstream would then encrypt with the FPGA key before transferring the encrypted bitstream back to the non-secure environment for final testing and deployment.
It is recommended to disable all debug access that can recover the secret key from the FPGA. You can disable the debug capabilities completely by disabling the JTAG port, or selectively disable and review that no debug features such as in-system memory editor or Signal Tap can recover the key. Refer to AN556 for further information on using FPGA security features including specific steps on how to encrypt the FPGA bitstream and configure security options such as disabling JTAG access.
Note: You can consider the additional step of obfuscation or encryption with another key of the secret key in the MIF storage.
3.6. Security Considerations
When using the HDCP feature, be mindful of the following security considerations.
• When designing a repeater system, you must block the received video from entering the TX IP in the following conditions: — If the received video is HDCP-encrypted (i.e. encryption status rx_hdcp1_enabled or rx_hdcp2_enabled from the RX IP is asserted) and the transmitted video is not HDCP-encrypted (i.e. encryption status tx_hdcp1_enabled or tx_hdcp2_enabled from the TX IP is not asserted). — If the received video is HDCP TYPE 1 (i.e. rx_streamid_type from the RX IP is asserted) and the transmitted video is HDCP 1.3 encrypted (i.e. encryption status tx_hdcp1_enabled from the TX IP is asserted) • You should maintain the confidentiality and integrity of your HDCP production keys, and any user encryption keys. • Intel strongly recommends you to develop any Intel Quartus Prime projects and design source files that contain encryption keys in a secure compute environment to protect the keys. • Intel strongly recommends you to use the design security features in FPGAs to protect the design, including any embedded encryption keys, from unauthorized copying, reverse engineering, and tampering.
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3.7. Debug Guidelines
3.7.1. HDCP Status Signals
There are several signals that are useful to identify the working condition of the HDCP IP cores. These signals are available at the design example top-level and are tied to the onboard LEDs:
Table 32. Signal Name
Signal Name Function
rx_hdcp1_enabled RX HDCP1x IP Decryption Status 0: Inactive 1: Active
rx_hdcp2_enabled RX HDCP2x IP Decryption Status 0: Inactive 1: Active
tx_hdcp1_enabled TX HDCP1x IP Encryption Status 0: Inactive 1: Active
tx_hdcp2_enabled TX HDCP2x IP Encryption Status 0: Inactive 1: Active
Refer to Table 31 on page 62 for their respective LED placements.
The active state of these signals indicates that the HDCP IP is authenticated and receiving/sending encrypted video stream. For each direction, only HDCP1x or HDCP2x encryption/decryption status signals is active. For example, if either rx_hdcp1_enabled or rx_hdcp2_enabled is active, the HDCP on the RX side is enabled and decrypting the encrypted video stream from the upstream video source.
3.7.2. Modifying HDCP Software Parameters
To facilitate the HDCP debugging process, you can modify the parameters in hdcp.c. Table below summarizes the list of configurable parameters and their functions.
Parameter Function
SUPPORT_HDCP1X Enable HDCP 1.3 on TX side
SUPPORT_HDCP2X Enable HDCP 2.3 on TX side
DEBUG_MODE_HDCP Enable debug messages for TX HDCP
REPEATER_MODE Enable repeater mode for HDCP design example
To modify the parameters, change the values to the desired values in hdcp.c. Before starting the compilation, make the following change in the build_sw_hdcp.sh: 1. Locate the following line and comment it out to prevent the modified software file being replaced by the original files from the Intel Quartus Prime Software installation path.
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2. Run “./build_sw_hdcp.sh” to compile the updated software. 3. The generated .elf file can be included into the design through two methods: a. Run “nios2-download -g
3.7.3. HDCP Key Mapping from DCP Key Files
This section describes the mapping of the HDCP production keys stored in DCP key files into the wire array of the HDCP kmem files.
3.7.3.1. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files
For hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files • These two files are sharing the same format • To identify the correct HDCP1 TX DCP key file for hdcp1x_tx_kmem.v, make sure the first 4 bytes of the file are “0x01, 0x00, 0x00, 0x00”. • To identify the correct HDCP1 RX DCP key file for hdcp1x_rx_kmem.v, make sure the first 4 bytes of the file are “0x02, 0x00, 0x00, 0x00”. • The keys in the DCP key files are in little-endian format. To use in kmem files, you must convert them into big-endian.
Figure 24. Byte mapping from HDCP1 TX DCP key file into hdcp1x_tx_kmem.v
This figure shows the exact byte mapping from HDCP1 TX DCP key file into hdcp1x_tx_kmem.v. The same mapping applies to hdcp1x_rx_kmem.v.
Note: The byte number displays in below format: • Key size in bytes * key number + byte number in current row + constant offset + row size in bytes * row number • 308*n indicates that each key set has 308 bytes. • 7*y indicates that each row has 7 bytes.
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Figure 25. HDCP1 TX DCP key file filling with junk values
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Figure 26. Wire Arrays of hdcp1x_tx_kmem.v
Example of hdcp1x_tx_kmem.v and how its wire arrays map to the example of HDCP1 TX DCP key file in Figure 25 on page 66
3.7.3.2. hdcp2x_rx_kmem.v file
For hdcp2x_rx_kmem.v file • To identify the correct HDCP2 RX DCP key file for hdcp2x_rx_kmem.v, make sure the first 4 bytes of the file are “0x00, 0x00, 0x00, 0x02”. • The keys in the DCP key files are in little-endian format
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Figure 27. Byte mapping from HDCP2 RX DCP key file into hdcp2x_rx_kmem.v
Figure below shows the exact byte mapping from HDCP2 RX DCP key file into hdcp2x_rx_kmem.v
Note: The byte number displays in below format: • Key size in bytes * key number + byte number in current row + constant offset + row size in bytes * row number • 862*n indicates that each key set has 862 bytes. • 16*y indicates that each row has 16 bytes. There is an exception in cert_rx_prod where ROW 32 has only 10 bytes.
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Figure 28. HDCP2 RX DCP key file filling with junk values
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Figure 29. Wire Arrays of hdcp2x_rx_kmem.v
This figure shows the wire arrays for hdcp2x_rx_kmem.v (cert_rx_prod, kprivrx_qinv_prod, and lc128_prod) map to the example of HDCP2 RX DCP key file in Figure 28 on page 69
3.7.3.3. hdcp2x_tx_kmem.v file
For hdcp2x_tx_kmem.v file:
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• To identify the correct HDCP2 TX DCP key file for hdcp2x_tx_kmem.v, make sure the first 4 bytes of the file are “0x00, 0x00, 0x00, 0x01”. • The keys in the DCP key files are in little-endian format. • Alternatively, you can apply the lc128_prod from hdcp2x_rx_kmem.v directly into hdcp2x_tx_kmem.v. The keys share the same values.
Figure 30. Wire array of hdcp2x_tx_kmem.v This figure shows the exact byte mapping from HDCP2 TX DCP key file into hdcp2x_tx_kmem.v
3.7.4. Frequently Asked Questions (FAQ)
Table 33. Failure Symptoms and Guidelines
Number Failure Guideline Symptom
1. The RX is This is due to the unsuccessful TX authentication with external sink. A HDCP-capable repeater receiving must not transmit the video in unencrypted format if the incoming video from the upstream is encrypted encrypted. To achieve this, a static video in blue or black colour replaces the outgoing video video, but the when the TX HDCP encryption status signal is inactive while the RX HDCP decryption status TX is sending signal is active. a static video For the exact guidelines, refer to Security Considerations on page 63. However, this behaviour in blue or may deter the debugging process when enabling the HDCP design. Below is the method to black colour. disable the video blocking in the design example: 1. Locate the following port connection at the top level of the design example. This port belongs to the hdmi_tx_top module.
2. Modify the port connection into the following line:
2. TX HDCP This is due to the downstream sink does not decrypt the outgoing encrypted video correctly. encryption Make sure you provide the global constant (LC128) to the TX HDCP IP. The value must be the status signal production value and correct. is active but snow picture is displayed at the downstream sink.
3. TX HDCP This is due to the unsuccessful TX authentication with downstream sink. To facilitate the encryption debugging process, you can enable the DEBUG_MODE_HDCP parameter in hdcp.c. status signal Refer to Modifying HDCP Software Parameters on page 64 on the guidelines. is unstable or The following 3a-3c are the possible causes of unsuccessful TX authentication. always inactive.
3a. The software The message indicates the downstream sink does not support both HDCP 2.3 and HDCP 1.3. debug log Make sure the downstream sink supports HDCP 2.3 or HDCP 1.3. keeps printing this message “HDCP 1.4 is not supported continued...
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Number Failure Guideline Symptom
by the downstream (Rx)”.
3b. TX This is due to any part of the TX authentication such as signature verification, locality check etc authentication can fail. Make sure the downstream sink is using production key but not facsimile key. fails halfway.
3c. The software This message indicates the downstream sink has requested re-authentication because the debug log received video was not decrypted correctly. Make sure you provide the global constant (LC128) keeps printing to the TX HDCP IP. The value must be the production value and the value is correct. “Re- authentication is required” after the HDCP authentication is completed.
4 RX HDCP This indicates that the RX HDCP IP has not achieved the authenticated state. By default, the decryption REPEATER_MODE parameter is enabled in the design example. If the REPEATER_MODE is status signal enabled, make sure the TX HDCP IP is authenticated. is inactive When the REPEATER_MODE parameter is enabled, the RX HDCP IP attempts authentication although the as a repeater if the TX is connected to a HDCP-capable sink. The authentication stops halfway upstream while waiting for the TX HDCP IP to complete the authentication with downstream sink and source has pass the RECEIVERID_LIST to the RX HDCP IP. Timeout as defined in the HDCP Specification is enabled HDCP. 2 seconds. If the TX HDCP IP is unable to complete the authentication in this period, the upstream source treats the authentication as fail and initiates re-authentication as specified in the HDCP Specification. Note: • Refer to Modifying HDCP Software Parameters on page 64 for the method to disable the REPEATER_MODE parameter for debugging purpose. After disabling the REPEATER_MODE parameter, the RX HDCP IP always attempt authentication as an endpoint receiver. The TX HDCP IP does not gate the authentication process. • If the REPEATER_MODE parameter is not enabled, make sure the HDCP key provided to the HDCP IP is the production value and the value is correct.
5 RX HDCP This means the RX HDCP IP has requested re-authentication right after the authenticated state decryption is achieved. This is probably due to the incoming encrypted video is not decrypted correctly by status signal the RX HDCP IP. Make sure the global constant (LC128) provided to the RX HDCP IP core is is unstable. production value and the value is correct.
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4. DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide Archives
IP versions are the same as the Intel Quartus Prime Design Suite software versions up to 19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme. If an IP core version is not listed, the user guide for the previous IP core version applies.
Intel Quartus Prime IP Core Version User Guide Version
20.3 19.4.0 DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide
20.2 19.3.0 DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide
20.1 19.3.0 DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide
19.2 19.1.0 DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide
19.1 19.1 DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide
18.1 18.1 DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, eASIC, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. UG-20193 | 2021.05.11
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5. Revision History for the DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide
Document Version Intel Quartus Intel FPGA IP Changes Prime Version Version
2021.05.11 21.1 19.4.0 • Added SUPPORT HDCP KEY MANAGEMENT = 1 to the description for Figure:HDCP Over DisplayPort Design Example Block Diagram. • Added the steps in HDCP over DisplayPort design example in Design Walkthrough. • Added the step to edit the HDCP key memory files to include HDCP production keys in Design Walkthrough. • Added the step to turn on Support HDCP Key Management parameter in Generate the Design. • Added a new subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1). • Added a new chapter Protection of Encryption Key Embedded in FPGA Design. • Added a new chapter Debug Guidelines and subsection HDCP Status Signals, Modifying HDCP Software Parameter, and Frequently Asked Questions.
2020.09.28 20.3 19.4.0 • Updated and renamed the Configuring Single or Dual Lanes section to Transceiver Lane Configurations. • Added pin assignments for Bitec FMC revision 10 in the Transceiver Lane Configurations section. • Updated the pin assignments for Bitec FMC revision 8 or earlier, and revision 11 with transceiver Avalon memory-mapped interface group information in the Transceiver Lane Configurations section.
2020.06.22 20.2 19.3.0 • Added the build_sw_hdcp.sh script in the Directory Structure section. • Added HDCP over DisplayPort design example to the list of DisplayPort Intel FPGA IP design examples offered for Intel Stratix 10 devices in the DisplayPort Intel FPGA IP Design Example Quick Start Guide section. • Added a new section about the HDCP design example: HDCP Over DisplayPort Design Examples. The HDCP feature is now available for Intel Stratix 10 devices. • Added data link rate support for HBR3 (8.10 Gbps) for both with and without PCR design examples in the Parallel Loopback Design Examples section. • Added HBR3 (8.10 Gbps) information for the DisplayPort RX PHY top and TX PHY top components in the Design Components section. continued...
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Document Version Intel Quartus Intel FPGA IP Changes Prime Version Version
• Added HBR3 (8.10 Gbps) information for the gxb_tx_clkout, rx_cdr_refclk, and gxb_rx_clkout clocks in the Clocking Scheme section. • Added HBR3 (8.10 Gbps) information for the dp_rx_dp_sink_rx_lin k_rate, dp_rx_dp_sink_rx_lin k_rate_8bits, dp_tx_dp_source_tx_l ink_rate, dp_tx_dp_source_tx_l ink_rate_8bits, and dp_tx_link_rate_8bit s signals in the Interface Signals and Parameters section. • Updated the information that the design example is 8Kp30 capable and added HBR3 (8.10 Gbps) information in the Hardware Setup section. • Added clock recovery core information in the Hardware Setup section.
2020.04.13 20.1 19.3.0 • Updated the Bitec DisplayPort card revision and the IP version in the local parameter in the RTL file at
2019.07.30 19.2 19.1.0 • Updated the files and folders in the Directory Structure section. • Added support for the Bitec DisplayPort FMC daughter card revision 11 in the Hardware and Software Requirements section. • Updated the Generating the Design section to include a note to turn on the Enable GPU Control parameter to read or print MSA information. continued...
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75 5. Revision History for the DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide UG-20193 | 2021.05.11
Document Version Intel Quartus Intel FPGA IP Changes Prime Version Version
• Updated the Regenerating ELF File section to include information about WSL and provided a link to the Nios II Software Developer Handbook. • Updated the Compiling and Testing the Design section to include information about the Bitec DisplayPort FMC daughter card revision 11 and channel mapping. • Updated the Configuring Single or Dual Lanes section with information about the Bitec DisplayPort FMC daughter card revision 11.
2019.04.01 19.1 19.1 • Added information about a new design example variant (DisplayPort SST Parallel Loopback with PCR) in the DisplayPort Intel FPGA IP Design Example Parameters section. The new variant was added to the DisplayPort Intel FPGA IP version 18.1 Update 1. • Removed the /altera_avalon_i2c file from the Directory Structure section. It is not added in the core folder. • Moved the .c and .h software files to a new folder in the Directory Structure section. These files are now in the dp_demo subfolder in version 19.1 of the DisplayPort Intel FPGA IP . • Added the default device for the Intel Stratix 10 GX FPGA Development Kit versions 19.1 and 18.1 Update 1 in the Generating the Design section. • Updated the Bitec DisplayPort FMC daughter card local parameter in the Compiling and Testing the Design section. • Added support for Intel Stratix 10 L-tile devices. You can now target your design example to be tested on the Intel Stratix 10 FPGA L-tile development kit in the DisplayPort Intel FPGA IP version 19.1. • Updated block diagrams to include Pixel Clock Recovery (PCR) modules in the Intel Stratix 10 DisplayPort SST Parallel Loopback and Clocking Scheme sections. • Added information about PCR module in the Design Components section. • Added information about PCR signals and parameters in Interface Signals and Parameters section. • Edited the note about CRC calculation in the Simulation Testbench section. To ensure CRC is calculated, you must enable the Support CTS test automation parameter. • Added link to the archived version of the DisplayPort Intel Stratix 10 IP Design Example User Guide.
2018.10.09 18.1 18.1 Initial release.
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