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UTP Cable Connectors Computer Architecture The Von Neumann Model/Architecture • Also called stored program computer Prof. Dr. Nizamettin AYDIN (instructions in memory). • Two key properties: – Stored program [email protected] • Instructions stored in a linear memory array • Memory is unified between instructions and data – The interpretation of a stored value depends on the control http://www.yildiz.edu.tr/~naydin signals • When is a value interpreted as an instruction? – Sequential instruction processing • One instruction processed (fetched, executed, and completed) at a time 1 2 A computing System (Reminder) Structure - Top Level • What is a computer? Peripherals Computer – in terms of what? Central Main • Functional Processing Memory Unit • Structural Computer Systems Functional definition Structural definition Interconnection – Data processing – Central processing unit Input – Data storage – Main memory Output – Data movement – Input/Output Communication lines – Control – System interconnection 3 4 Structure - The CPU Structure - The Control Unit CPU Control Unit Computer Arithmetic CPU Registers and Sequencing I/O Logic Unit ALU Logic Control System CPU Internal Unit Bus Bus Internal CPU Control Unit Memory Interconnection Registers Registers and Decoders Control Unit Control Memory 5 6 Copyright 2000 N. AYDIN. All rights reserved. 1 The Stored Program Computer Von Neumann Model •1943: ENIAC – Presper Eckert and John Mauchly -- first general electronic computer. (or was it John V. Atanasoff in 1939?) – Hard-wired program -- settings of dials and switches. •1944: Beginnings of EDVAC – among other improvements, includes program stored in memory •1945: John von Neumann – wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC •The basic structure proposed in the draft became known as the “von Neumann machine” (or model). – a memory, containing instructions and data – a processing unit, for performing arithmetic and logical operations – a control unit, for interpreting instructions 7 8 ENIAC - details Interface to Memory • Decimal (not binary) • How does processing unit get data to/from memory? • 20 accumulators of 10 • MAR: Memory Address Register digits • MBR (MDR): Memory Buffer (Data) Register • Programmed manually by switches To LOAD a memory location (A): • 18,000 vacuum tubes • 30 tons 1. Write the address (A) into the MAR. • 15,000 square feet 2. Send a “read” signal to the memory. • 140 kW power 3. Read the data from MBR. consumption To STORE a value (X) to a location (A): • 5,000 additions per http://www.seas.upenn.edu/~museum/ 1. Write the data (X) to the MBR. second 2. Write the address (A) into the MAR. 3. Send a “write” signal to the memory. 9 10 Processing Unit Input and Output •Functional Units (Execution unit) •Devices for getting data into and – ALU = Arithmetic and Logic Unit out of computer memory – could have many functional units. some of them special-purpose •Each device has its own interface, (multiply, square root, …) usually a set of registers (I/OAR and •Registers I/OBR) – Small, temporary storage – Operands and results of functional units •Some devices provide both input •Word Size and output – number of bits normally processed by ALU in one instruction – disk, network – also width of registers •Program that controls access to a device is usually called a driver. 11 12 Copyright 2000 N. AYDIN. All rights reserved. 2 Control Unit Program Concept •Orchestrates execution of the program • Hardwired systems •Instruction Register (IR) contains the current are inflexible instruction. •Program Counter (PC) contains the address of • General purpose the next instruction to be executed. hardware can do •Control unit: different tasks, given – reads an instruction from memory correct control • the instruction’s address is in the PC – interprets the instruction, generating signals signals that tell the other components • Instead of re-wiring, what to do • an instruction may take many supply a new set of machine cycles to complete control signals 13 14 What is a program? Instruction Processing • A sequence of steps Fetch instruction from memory • For each step, an arithmetic or logical operation is done Decode instruction • For each operation, a different set of control Evaluate Address signals is needed fetch OPerands from memory EXecute operation Store result 15 16 Instruction Instruction Processing: FETCH •The instruction is the fundamental unit of work. •Load next instruction (at address stored in PC) F •Specifies two things: from memory – opcode: operation to be performed into Instruction Register (IR). D – operands: data/locations to be used for operation – Copy contents of PC into MAR. •An instruction is encoded as a sequence of bits. – Send “read” signal to memory. (Just like data!) EA – Often, but not always, instructions have a fixed length, – Copy contents of MBR into IR. such as 16 or 32 bits. – Control unit interprets instruction: OP generates sequence of control signals to carry out operation. •Then increment PC, so that it points to the next instruction in sequence. – Operation is either executed completely, or not at all. EX – PC becomes PC+1. •A computer’s instructions and their formats is known as its Instruction Set Architecture (ISA). S 17 18 Copyright 2000 N. AYDIN. All rights reserved. 3 Instruction Processing: DECODE Instruction Processing: EVALUATE ADDRESS •For instructions that require memory access, •First identify the opcode. F F compute address used for access. – A n-to-2n decoder asserts a control line corresponding to the desired opcode. D D •Examples: – add offset to base register EA EA •Depending on opcode, identify other operands – add offset to PC from the remaining bits. OP – add offset to zero OP EX EX S S 19 20 Instruction Processing: FETCH OPERANDS Instruction Processing: EXECUTE •Obtain source operands needed to F •Perform the operation, F perform operation. using the source operands. D D •Examples: EA •Examples: EA – load data from memory (LDA) – send operands to ALU and assert ADD signal – read data from register file (ADD) OP – do nothing (e.g., for loads and stores) OP EX EX S S 21 22 Instruction Processing: STORE RESULT Changing the Sequence of Instructions •In the FETCH phase, we increment the Program Counter by 1. •Write results to destination. F (register or memory) •What if we don’t want to always execute the instruction that D follows this one? – examples: loop, if-then, function call •Examples: EA – result of ADD is placed in destination register •Need special instructions that change the contents of the PC. – result of memory load is placed in destination OP •These are called control instructions. register – jumps are unconditional -- they always change the PC EX – branches are conditional -- they change the PC only if – for store instruction, data is stored to memory some condition is true (e.g., the result of an ADD is zero) • write address to MAR, data to MBR S • assert WRITE signal to memory 23 24 Copyright 2000 N. AYDIN. All rights reserved. 4 Instruction Processing Summary Control Unit State Diagram •Instructions look just like data -- it’s all interpretation. •The control unit is a state machine. •Four basic kinds of instructions: •Here is part of a simplified state diagram: – Data processing instructions • Arithmetic and logic instructions (ADD, AND, …) – Data storage instructions • Memory instructions (LDA, STA) – Data movement instructions • I/O instructions (IN, OUT, …) – Program flow control instructions • Test and branch instructions (JMP, BRP, …) •Six basic phases of instruction processing: F D EA OP EX S – not all phases are needed by every instruction – phases may take variable number of machine cycles 25 26 Stopping the Clock •Control unit will repeat instruction processing sequence Dataflow Model of a Computer as long as clock is running. – If not processing instructions from your application, Von Neumann model Dataflow model then it is processing instructions from the Operating System (OS). • An instruction is • An instruction is fetched and executed – The OS is a special program that manages processor in data flow order and other resources. fetched and executed in – i.e., when its operands are ready •To stop the computer: – i.e., there is no instruction pointer control flow order – AND the clock generator signal with ZERO – Instruction ordering specified by data – As specified by flow dependence – When control unit stops seeing the CLOCK signal, it stops the instruction • Each instruction specifies “who” should processing. pointer receive the result • An instruction can “fire” whenever all – Sequential unless operands are received explicit control – Potentially many instructions can flow instructio execute at the same time – Inherently more parallel 27 28 von Neumann vs Dataflow • Consider a von Neumann program (sequential) vs dataflow execution • Which model is more natural to you as a programmer? • All major instruction set architectures today use von Neumann – x86, ARM, MIPS, SPARC, Alpha, POWER PC 29 Copyright 2000 N. AYDIN. All rights reserved. 5.
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