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(12) Patent Application Publication (10) Pub. No.: US 2015/0067389 A1 Galloway (43) Pub

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(12) Patent Application Publication (10) Pub. No.: US 2015/0067389 A1 Galloway (43) Pub US 2015 OO67389A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2015/0067389 A1 Galloway (43) Pub. Date: Mar. 5, 2015 (54) PROGRAMMABLE SUBSTITUTIONS FOR (52) U.S. Cl. MCROCODE CPC .......... G06F 1 1/1405 (2013.01); G06F 9/3016 (2013.01) (71) Applicant: ADVANCED MICRO DEVICES, USPC ............................................................ 71.4/10 INC., Sunnyvale, CA (US) (72) Inventor: Frank C. Galloway, Dripping Springs, TX (US) (57) ABSTRACT (73) Assignee: ADVANCED MICRO DEVICES, INC., Sunnyvale, CA (US) The apparatuses, systems, and methods in accordance with the embodiments disclosed herein may facilitate modifying (21) Appl. No.: 14/014,220 post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an integrated (22) Filed: Aug. 29, 2013 circuit. These registers may be mapped to generic instruc Publication Classification tions, which can modify an operation of the integrated circuit. In some embodiments, these registers may be used to imple (51) Int. C. ment a patch routine to change the behavior of at least a G06F II/4 (2006.01) portion of the integrated circuit. In this manner, the original G06F 9/30 (2006.01) design of the integrated circuit may be altered. Peera Revices Processor Central Processing init (CPU) agrarirrate Comute act Output. {-n}init(s) Dynamic Randon evices) 165 Access Merroy 142 (DRAM) i 2 t South Eridge pi (evices) f Graphics Processing Unit (GP or Floating Point (Graphics Processor) B (EPU) 8 as 8 : Programmate -: agrariate Scrage Storage Paic nit as it 1 65 Patent Application Publication Mar. 5, 2015 Sheet 1 of 7 US 2015/0067389 A1 §6% Patent Application Publication Mar. 5, 2015 Sheet 2 of 7 US 2015/0067389 A1 {{{}}?? us? {{}{} Patent Application Publication Mar. 5, 2015 Sheet 3 of 7 US 2015/0067389 A1 029 9aun64-) jepeo"; Patent Application Publication Mar. 5, 2015 Sheet 4 of 7 US 2015/0067389 A1 §§§§§§§§ Patent Application Publication Mar. 5, 2015 Sheet 5 of 7 US 2015/0067389 A1 Patent Application Publication Mar. 5, 2015 Sheet 6 of 7 US 2015/0067389 A1 ?. 0$9 Patent Application Publication Mar. 5, 2015 Sheet 7 of 7 US 2015/0067389 A1 US 2015/0067389 A1 Mar. 5, 2015 PROGRAMMABLE SUBSTITUTIONS FOR ment data type for the first replacement instruction; and MCROCODE implementing the operational change by executing the first replacement instruction using the first replacement data type. BACKGROUND 0008. Some embodiments provide an a method that include determining if a hardware erroris present in a device; 0001 1. Technical Field determining an execution unit of the device affected by the 0002 Generally, the disclosed embodiments relate to inte hardware error, executing a patch routine in response to deter grated circuits, and, more particularly, modifying processor mining the execution unit affected by the hardware error; operations using programmable Substitutions. determining at least one reserved instruction in response to 0003 2. Description of the Related Art executing the patch routine, the at least one reserved instruc 0004 Conventional processor-based systems from per tion to provide an alternative operation of the execution unit; Sonal computers to mainframes typically include a central determining a value for a data type for the reserved instruc processing unit (CPU) that is configured to access instruc tion; providing the data type to the execution unit for execu tions or data that are stored in a main memory. Processor tion of the reserved data; and executing an alternative opera based systems may also include other types of processors tion of the execution unit based upon the patch routine. Such as graphics processing units (GPUs), digital signal pro 0009. Some embodiments provide an a method that cessors (DSPs), accelerated processing units (APUs), co include determining whether an operational change is processors, or applications processors. Entities within the required for a device; determining an execution unit of the conventional processor-based system communicate by device affected by the operational change; executing a patch exchanging signals over buses or bridges such as a north routine in response to determining the execution unit affected bridge, a Southbridge, a Peripheral Component Interconnect by the operational change, determining at least one reserved (PCI) Bus, a PCI-Express Bus, or an Accelerated Graphics instruction in response to executing the patch routine. The Port (AGP) Bus. reserved instruction is adapted to provide an alternative 0005. Some or all of the processors, buses, or bridges in operation of the execution unit. The method also includes the processor-based system may be fabricated on an inte determining a value for a data type for the reserved instruc grated circuit (IC) using a circuit design created by engineers, tion; providing the data type to the execution unit for execu typically using automated design software. The design of an tion of the reserved data; and executing an alternative opera IC for a system, which may include multiple ICs, is typically tion of the execution unit based upon the patch routine. verified using a suite of tests to ensure that the IC functions 0010 Some embodiments provide an integrated circuit correctly. Testing of the IC during the design, development, that includes an execution unit for performing a computing fabrication, or operational stages is generally referred to as operation; and a programmable patch unit for modifying at debugging the IC. With the evolution of processing technolo least one operation of the execution unit. The programmable gies and reduction of size and increase in complexity of patch unit comprises a programmable instruction and a pro devices, debugging of circuit designs has become more and grammable data type for executing the programmable more difficult to perform using traditional simulation tools instruction. The programmable instruction is capable of being and techniques. Once a device is tested at a post-fabrication programmed to modify the at least one operation of the execu level, engineers may desire a change in operation of the tion unit. device. These changes may be prompted by the discovery of 0011. Some embodiments provide a non-transitory com a bug in the system, or by a desire to modify the capabilities puter-readable medium storing instructions executable by at or operations of the device. Designers generally use Software least one processor to fabricate an integrated circuit device. to override the behavior of the integrated circuit. This solution The integrated circuit device includes an execution unit for can be cumbersome, and requires overriding the behavior of performing a computing operation; and a programmable existing hardware of the integrated circuit. Such as disable one patch unit for modifying at least one operation of the execu or more features of the integrated circuit. tion unit. The programmable patch unit includes a program mable instruction and a programmable data type for execut SUMMARY OF EMBODIMENTS ing the programmable instruction. The programmable 0006. The apparatuses, systems, and methods in accor instruction being capable of being programmed for modify dance with the embodiments disclosed herein may facilitate ing the at least one operation of the execution unit. modifying post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an BRIEF DESCRIPTION OF THE FIGURES integrated circuit. These registers may be mapped to generic instructions, which can modify an operation of the integrated 0012. The disclosed subject matter will hereafter be circuit. In some embodiments, these registers may be used to described with reference to the accompanying drawings, implement a patch routine to change the behavior of at least a wherein like reference numerals denote like elements, and: portion of the integrated circuit. In this manner, the original 0013 FIG. 1 is a schematic diagram of an exemplary design of the integrated circuit may be altered. microcircuit design in accordance with some embodiments. 0007 Some embodiments provide an a method that 0014 FIG. 2 provides a block diagram representation of a include receiving a request to implement a patch mode for a programmable patch unit of FIG. 1, in accordance with some first execution unit; selecting, in response to receiving the embodiments. request, a first patch mode for implementing a patch. The first 0015 FIG. 3 provides a block diagram representation of patch mode comprises information regarding an operational circuitry for loading a programmable data type of FIG. 2, in change relating to at least a portion of the execution unit. The accordance with some embodiments. method also includes selecting a first replacement instruction 0016 FIG. 4 provides a representation of a processor for providing the operational change, selecting a first replace depicted in FIG. 1, in accordance with some embodiments. US 2015/0067389 A1 Mar. 5, 2015 0017 FIG. 5A provides a representation of a silicon die/ tomary meaning as understood by those skilled in the art, is chip that includes one or more circuits as shown in FIG.3, in intended to be implied by consistent usage of the term or accordance with Some embodiments. phrase herein. To the extent that a term or phrase is intended 0018 FIG. 5B provides a representation of a silicon wafer to have a special meaning, i.e., a meaning other than that which includes one or more dies/chips that may be produced understood by skilled artisans, such a special definition is in a fabrication facility, in accordance with some embodi expressly set forthin the specificationina definitional manner mentS. that directly and unequivocally provides the special definition 0019 FIG. 6 is a flowchart of a method relating modifying for the term or phrase. Additionally, the term, “or,” as used post-silicon instruction behavior, in accordance with some herein, refers to a non-exclusive “or, unless otherwise indi embodiments. cated (e.g., "or else' or “or in the alternative”). Also, the 0020 FIG. 7 is a flowchart of a method for activating various embodiments described herein are not necessarily reserve instruction path of FIG.
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