Intrinsic Silicon Properties • Read textbook, section 3.2.1, 3.2.2, 3.2.3
• Intrinsic Semiconductors – undoped (i.e., not n+ or p+) silicon has intrinsic charge carriers – electron-hole pairs are created by thermal energy 10 -3 – intrinsic carrier concentration ≡ ni = 1.45x10 cm , at room temp. – function of temperature: increase or decrease with temp?
– n = p = ni, in intrinsic (undoped) material •n ≡ number of electrons, p ≡ number of holes 2 – mass-action law, np = ni • applies to undoped and doped material
ECE 410, Prof. A. Mason Lecture Notes 6.1 Extrinsic Silicon Properties •doping, adding dopants to modify material properties n-type Donor – n-type = n+, add elements with extra an electron + • (arsenic, As, or phosphorus, P), Group V elements + - P P electron group V free •nn ≡ concentration of electrons in n-type material ion element carrier -3 •nn = Nd cm , Nd ≡ concentration of donor atoms •p ≡ concentration of holes in n-type material n n+/p+ defines region 2 •Nd pn = ni , using mass-action law as heavily doped, – always a lot more n than p in n-type material typically ≈ 1016-1018 cm-3 less highly doped regions – p-type = p+, add elements with an extra hole generally labeled n/p • (boron, B) (without the +)
•pp ≡ concentration of holes in p-type material p-type Acceptor -3 - •pp = Na cm , Na ≡ concentration of acceptor atoms B B + + •np ≡ concentration of electrons in p-type material hole free 2 group III ion •Na np = ni , using mass-action law element carrier – always a lot more p than n in p-type material do example on board 2 20 –if both Nd and Na present, nn = Nd-Na, pp=Na-Nd ni = 2.1x10 ECE 410, Prof. A. Mason Lecture Notes 6.2 Conduction in Semiconductors • doping provides free charge carriers, alters conductivity • conductivity, σ, in semic. w/ carrier densities n and p -19 – σ = q(μnn + μpp), q ≡ electron charge, q = 1.6x10 [Coulombs] 2 • μ≡mobility [cm /V-sec], μn ≅ 1360, μp ≅ 480 (typical values)
• in n-type region, nn >> pn mobility = average velocity per Mobility often assumed constant – σ≈qμnnn unit electric field but is a function of μn > μp • in p-type region, pp >> np Temperature and Doping electrons more mobile than holes Concentration – σ≈qμpnp ⇒conductivity of n+ > p+ • resistivity, ρ = 1/σ t • resistance of an n+ or p+ region –R = ρ l , A = wt w l A
• drift current (flow of charge carriers in presence of an electric field, Ex)
– n/p drift current density: Jxn = σn Ex = qμnnnEx, Jxp = σp Ex = qμpppEx
– total drift current density in x direction Jx = q(μnn + μpp) Ex = σ Ex
ECE 410, Prof. A. Mason Lecture Notes 6.3 pn Junctions: Intro
contact contact • What is a pn Junction? to p-side to n-side depletion region boundaries p+ n+ – interface of p-type and dielectric n “well” pn diode insulator n-type semiconductor junction (oxide) p-type Si wafer – junction of two materials forms a diode p-type n-type p-type + + + + - - - n-type • In the Beginning… - - - - + + + - + - + - + -+ + + - - - - 3 - - – ionization of dopants + + + + 3 N acceptors/cm N donors/cm A D hole diffusion - at material interface hole current + donor ion and electron free carrier electron diffusion + electron current - acceptor ion and hole free carrier • Diffusion -movement of charge to regions of lower concentration electric field – free carries diffuse out depletion region E – leave behind immobile ions p-type - + + n-type – region become depleted of - - + - + free carriers - + 3 - + 3 N acceptors/cm - N donors/cm – ions establish an electric field A - + + D x x immobile acceptor ions p n immobile donor ions • acts against diffusion (negative-charge) (positive-charge) W ECE 410, Prof. A. Mason Lecture Notes 6.4 pn Junctions: Equilibrium Conditions electric field E • Depletion Region depletion region p-type - + + n-type – area at pn interface - - + - + + void of free charges NA - ND 3 - + 3 N acceptors/cm - N donors/cm – charge neutrality A - + + D x x immobile acceptor ions p n immobile donor ions • must have equal charge on both sides (negative-charge) (positive-charge) W •q A xp NA = q A xn ND , A=junction area; xp, xn depth into p/n side
• ⇒ xp NA = xn ND • depletion region will extend further into the more lightly doped side of the junction • Built-in Potential – diffusion of carriers leaves behind immobile charged ions – ions create an electric field which generates a built-in potential ⎛ NN ⎞ =Ψ V ln⎜ DA ⎟ 0 T ⎜ 2 ⎟ ⎝ ni ⎠
•where VT = kT/q = 26mV at room temperature
ECE 410, Prof. A. Mason Lecture Notes 6.5 pn Junctions: Depletion Width electric field E • Depletion Width depletion region use Poisson’s equation & charge neutrality p-type - + + n-type - - + - + + –W = xp + xn NA - ND 3 - + 3 1 N acceptors/cm - N donors/cm 1 A - + + D 2 2 ⎡2ε ()0 +Ψ NV DR ⎤ ⎡2ε()0 +Ψ NV AR ⎤ x x x = xn = ⎢ ⎥ immobile acceptor ions p n immobile donor ions p ⎢ ⎥ ()+ NNqN (negative-charge) (positive-charge) ⎣ ()+ NNqN ADA ⎦ ⎣ ADD ⎦ W ⎛ NN ⎞ •where VR is applied reverse bias ⎜ DA ⎟ is the permittivity of Si 0 =Ψ VT ln 2 1 ε ⎜ n ⎟ 2 ε = 1.04x10-12 F/cm ⎝ i ⎠ ⎡2ε ()0 +Ψ VR + NN AD ⎤ ε = K ε , where ε = 8.85x10-14 F/cm W = ⎢ ⎥ S 0 0 and K = 11.8 is the relative permittivity of silicon ⎣ q NN AD ⎦ S
• One-sided Step Junction 1 ⎡ ⎤ 2 –if N>>N (p+n diode) 2ε()0 +Ψ VR A D xW n =≅ ⎢ ⎥ • most of junction on n-side ⎣ qN D ⎦
1 2 –if ND>>NA (n+p diode) ⎡2ε ()0 +Ψ VR ⎤ • most of junction on p-side xW p =≅ ⎢ ⎥ ⎣ qN A ⎦
ECE 410, Prof. A. Mason Lecture Notes 6.6 pn Junctions - Depletion Capacitance • Free carriers are separated by the depletion layer • Separation of charge creates junction capacitance –Cj = εA/d ⇒ (d = depletion width, W) 1 ⎡ ε NNq ⎤ 2 ⎛ 1 ⎞ ε is the permittivity of Si DA ⎜ ⎟ ε = 11.8⋅ε = 1.04x10-12 F/cm j = AC ⎢ ⎥ 0 2()+ NN ⎜ ⎟ V = applied reverse bias ⎣ DA ⎦ ⎝ 0 +Ψ VR ⎠ R – A is complex to calculate in semiconductor diodes • consists of both bottom of the well and side-wall areas ⎛ ⎞ ⎜ ⎟ – Cj is a strong function of biasing 1 ⎜ C jo ⎟ ⎡ ε NNq ⎤ 2 C j = ⎜ ⎟ DA jo = AC ⎢ ⎥ • must be re-calculated if ⎜ VR ⎟ 2 ()+Ψ NN ⎜ 1+ ⎟ ⎣ 0 DA ⎦ bias conditions change ⎝ Ψ0 ⎠ ⎛ ⎞ – CMOS doping is not linear/constant ⎜ ⎟ ⎜ C jo ⎟ C j = ⎜ ⎟ • graded junction approximation ⎜ VR ⎟ 3 1+ ⎜ Ψ ⎟ • Junction Breakdown ⎝ 0 ⎠ – if reverse bias is too high (typically > 30V) can get strong reverse current flow
ECE 410, Prof. A. Mason Lecture Notes 6.7 Diode Biasing and Current Flow I + V - + V - D D D p n V V I I f D D D
• Forward Bias; VD > Ψ0 – acts against built-in potential – depletion width reduced
– diffusion currents increase with VD • minority carrier diffusion ⎛ 11 ⎞ VV TD ⎜ ⎟ = (eII −1) S AI ⎜ +∝ ⎟ SD ⎝ NN AD ⎠
• Reverse Bias; VR = -VD > 0 – acts to support built-in potential – depletion width increased – electric field increased – small drift current flows • considered leakage
• small until VR is too high and breakdown occurs
ECE 410, Prof. A. Mason Lecture Notes 6.8 MOSFET Capacitor • MOSFETs move charge from drain to source underneath the gate, if a conductive channel exists under the gate • Understanding how and why the conductive channel is produced is important • MOSFET capacitor models the gate/oxide/substrate region G – source and drain are ignored S D gate G – substrate changes with applied gate voltage gate oxide •Consider an nMOS device channel =
– Accumulation, VG < 0, (-)ve charge on gate Si substrate = bulk B • induces (+)ve charge in substrate B • (+)ve charge accumulate from substrate holes (h+)
– Depletion, V > 0 but small V < 0 V > 0 V >> 0 G G G G
• creates depletion region in substrate + + + + + + + + + + + ------+ + + + + + + + + + + + + + + + + • (-)ve charge but no free carriers + + + + + + + ------depletion- - -layer - - - - depletion- - - layer - - – Inversion, VG > 0 but larger • further depletion requires high energy p-type Si substrate p-type Si substrate p-type Si substrate BB B • (-)ve charge pulled from Ground Accumulation Depletion Inversion • electron (e-) free carriers in channel
ECE 410, Prof. A. Mason Lecture Notes 6.9 Capacitance in MOSFET Capacitor • In Accumulation – Gate capacitance = Oxide capacitance 2 – Cox = εox/tox [F/cm ]
• In Depletion – Gate capacitance has 2 components – 1) oxide capacitance Cox – 2) depletion capacitance of the substrate depletion region Cdep •Cdep= εsi/xd, xd = depth of depletion region into substrate – Cgate = Cox (in series with) Cdep = Cox Cdep / (Cox+Cdep) < Cox • C’s in series add like R’s in parallel Cgate • In Inversion Cox – free carries at the surface – Cgate = Cox V accumulation inversion G depletion
ECE 410, Prof. A. Mason Lecture Notes 6.10 Inversion Operation • MOSFET “off” unless in inversion – look more deeply at inversion operation • Define some stuff – Qs = total charge in substrate
–VG = applied gate voltage – Vox = voltage drop across oxide
– φs = potential at silicon/oxide interface (relative to substrate-ground)
–Qs = -Cox VG
–VG = Vox + φs • During Inversion (for nMOS)
–VG > 0 applied to gate – Vox drops across oxide (assume linear)
– φs drops across the silicon substrate, most near the surface
ECE 410, Prof. A. Mason Lecture Notes 6.11 Surface Charge
•QB = bulk charge, ion charge in depletion region under the gate 1 ⎡2εφ ⎤ 2 –Q= - q N x , x = depletion depth s B A d d xd = ⎢ ⎥ 1/2 ⎣ qN A ⎦ –QB = - (2q εSi NA φs) = f(VG) – charge per unit area • Qe = charge due to free electrons at substrate surface
•Qs = QB + Qe < 0 (negative charge for nMOS)
depletion electron region QB, bulk layer, Qe charge
ECE 410, Prof. A. Mason Lecture Notes 6.12 Surface Charge vs. Gate Voltage • Surface Charge vs. Gate Voltage
–VG < Vtn, substrate charge is all bulk charge, Qs = QB
–VG = Vtn, depletion region stops growing
•xd at max., further increase of VG will NOT increase xd
•QB at max.
–VG > Vtn, substrate charge has both components, Qs = QB + Qe
•since QB is maxed, further increases in VG must increase Qe • increasing Qe give more free carriers thus less resistance
• Threshold Voltage – Vtn defined as gate voltage where Qe starts to form
–Qe= -Cox (VG-Vtn) – Vtn is gate voltage required to • overcome material difference between silicon and oxide • establish depletion region in channel to max value/size
ECE 410, Prof. A. Mason Lecture Notes 6.13 Overview of MOSFET Current • Gate current – gate is essentially a capacitor ⇒ no current through gate – gate is a control node
•VG < Vtn, device is off
•VG > Vtn, device is on and performance is a function of VGS and VDS
• Drain Current (current from drain to source), ID – Source = source/supply of electrons (nMOS) or holes (pMOS) – Drain = drain/sink of electrons (nMOS) or holes (pMOS)
–VDS establishes an E-field across (horizontally) the channel • free charge in an E-field will create a drain-source current nMOS •is ID drift or diffusion current? • MOSFET I-V Characteristics
VDS = VGS -Vtn
source @ ground drain @ (+)ve potential
↑ VGS Charge Flow Electron Flow Current Flow Current Flow
ECE 410, Prof. A. Mason Lecture Notes 6.14 Channel Charge and Current • Threshold Voltage = Vtn, Vtp – amount of voltage required on the gate to turn tx on – gate voltage > Vtn/p will induce charge in the channel •nMOS Channel Charge
–Qc = -CG(VG-Vtn), from Q=CV, (-) because channel holds electrons assumes channel charge is •nMOS Channel Current (linear model:) constant from source to drain
–I = |Qc| / tt , where tt = transit time, average time to cross channel
•tt = channel length / (average velocity) = L / v
• average drift velocity in channel due to electric field E Æ v = μn E
• assuming constant field in channel due to VDS Æ E = VDS / L V μ DS • Æ n C = CoxWL ⇒ Qc = −VtnVCoxWL )(|| = QcI L G G L
–I = μnCox (W/L) (VG-Vtn) VDS : linear model, assumes constant charge in channel similar analysis applies for pMOS, see textbook
ECE 410, Prof. A. Mason Lecture Notes 6.15 Transconductance and Channel Resistance
•nMOSChannel Charge: Qc = -CG(VG-Vtn) •nMOSlinear model Channel Current:
–I = μnCox(W/L)(VG-Vtn) VDS
• assumes constant charge in channel, valid only for very small VDS •nMOSProcess Transconductance μ 2 ⇒ –k’n = nCox [A/V ] I = k’n (W/L) (VG-Vtn) VDS similar analysis •nMOSDevice Transconductance applies for pMOS, 2 see textbook – βn = μnCox (W/L) [A/V ] ⇒ I = βn (VG-Vtn) VDS – constant for set transistor size and process
•nMOSChannel Resistance 1 R = – channel current between Drain and Source n W μ Coxn −VV tnGS )( – channel resistance = VDS / IDS L 1 –Rn= 1/( βn (VG-Vtn) ) R = p W μ β μ μ Coxp ()− VV tpSG •pMOS: k’p = pCox, p = pCox (W/L) L
ECE 410, Prof. A. Mason Lecture Notes 6.16 nMOS Current vs.Voltage • Cutoff Region General Integral for expressing ID • channel charge = f(y) –VGS < Vtn • channel voltage = f(y) ⇒ I = 0 • y is direction from drain to source D VD = δαyVyQI )()( •Linear Region D ∫ I 0 –VGS > Vth, VDS > 0 but very small V = V -Vtn • Qe = -Cox (VGS-Vtn) DS GS
•ID = μn Qe (W/L) VDS
⇒ ID = μnCox (W/L) (VGS-Vtn) VDS ↑ VGS • Triode Region
–VGS > Vth, 0 < VDS < VGS-Vth
• surface potential, φs , at drain now f(VGS-VDS=VGD) ⇒ less charge near drain • assume channel charge varies linearly from drain to source
– at source: Qe = -Cox (VGS-Vtn), at drain: Qe = 0 ⇒ μ C W I = OXn [ )(2 −− VVVV 2 ] D 2 L DSDStGS
ECE 410, Prof. A. Mason Lecture Notes 6.17 nMOS Current vs.Voltage
• Saturation Region (Active Region)
–VGS > Vtn, VDS > VGS-Vtn
• surface potential at drain, φsd = VGS-Vtn-VDS
•when VDS = VGS-Vtn, φsd = 0 ⇒ channel not inverted at the drain – channel is said to be pinched off
• during pinch off, further increase in VDS will not increase ID
–define saturation voltage, Vsat, when VDS = VGS-Vtn • current is saturated, no longer increases
• substitute Vsat=VGS-Vtn for VDS into triode equation μ COXn W 2 ⇒ μ C W I D = [ )(2 −− VVVV DSDStGS ] square law OXn 2 2 L I D = −VV tGS )( equation 2 L
ECE 410, Prof. A. Mason Lecture Notes 6.18 Other Stuff • Transconductance
– process transconductance, k’ = μn Cox • constant for a given fabrication process
–device transconductance, βn= k’ W/L • Surface Mobility – mobility at the surface is lower than mobility deep inside silicon 2 – for current, ID, calculation, typical μn = 500-580 cm /V-sec • Effective Channel Length – effective channel length reduced by • lateral diffusion under the gate • depletion spreading from drain-substrate junction L (drawn) S G D = − 2)( − XLdrawnLLeff dD x L d D ⎛ 2ε ()()−− VVV ⎞ ~x ⎜ tGDs ⎟ d X d = ⎜ ⎟ Leff ⎝ qN A ⎠
ECE 410, Prof. A. Mason Lecture Notes 6.19 Second Order Effects • Channel Length Modulation
– Square Law Equation predicts ID is constant with VDS
–However, ID actually increases slightly with VDS •due to effective channel getting shorter as VDS increases • effect called channel length modulation – Channel Length Modulation factor, λ
• models change in channel length with VDS
– Corrected ID equation μ C W I = OXn 2 ( λ −+− VVVV )(1)( ) D 2 L tGS effDS •Veff= VGS -Vtn • Body Effect – so far we have assumed that substrate and source are grounded
– if source not at ground, source-to-bulk voltage exists, VSB > 0
–VSB > 0 will increase the threshold voltage, Vtn = f(VSB) – called Body Effect, or Body-Bias Effect
ECE 410, Prof. A. Mason Lecture Notes 6.20 pMOS Equations • Analysis of nMOS applies to pMOS with following modifications –physical • change all n-tpye regions to p-type • change all p-type regions to n-type – substrate is n-type (nWell) • channel charge is positive (holes) and (+)ve charged ions – equations
•change VGS to VSG (VSG typically = VDD - VG)
•change VDS to VSD (VSD typically = VDD - VD) • change Vtn to |Vtp| – pMOS threshold is negative, nearly same magnitude as nMOS –other factors 2 • lower surface mobility, typical value, μp = 220 cm /V-sec
•body effect, change VSB to VBS
ECE 410, Prof. A. Mason Lecture Notes 6.21 Transistor Sizing •Channel Resistance Rn “ON” resistance of transistors Rp –Rn= 1/(μnCox (W/L) (VGS-Vtn) )
–Rp= 1/(μpCox (W/L) (VSG-|Vtp|) )
2 • Cox = εox/tox [F/cm ], process constant VG Vtn VDD-|Vtp| • Channel Resistance Analysis –R ∝ 1/W (increasing W decreases R & increases Current) – R varies with Gate Voltage, see plot above – If Wn = Wp, then Rn < Rp
•since μn > μp • assuming Vtn ~ |Vtp| – to match resistance, Rn = Rp
• adjust Wn/Wp to balance for μn > μp
ECE 410, Prof. A. Mason Lecture Notes 6.22 Transistor Sizing •Channel Resistances
–Rn= 1/(μnCox (W/L) (VG-Vtn) )
–Rp= 1/(μpCox (W/L) (VG-|Vtp|) )
–Rn/Rp= μn/μp
• if Vtn = |Vtp|, (W/L)n = (W/L)p • Matching Channel Resistance – there are performance advantage to setting Rn = Rp • discussed in Chapter 7 – to set Rn = Rp
• define mobility ratio, r = μn/μp
•(W/L)p = r (W/L)n –pMOSmust be larger than nMOS for same resistance/current
•Negative Impact How does this impact – ⇒ CGp = r CGn larger gate = higher capacitance circuit performance?
ECE 410, Prof. A. Mason Lecture Notes 6.23 MOSFET RC Model •Modeling MOSFET resistance and capacitance is very important for transient characteristics of the device
• RC Model time constant
at drain, τD τD = CD Rn
• Drain-Source (channel) Resistance, Rn
–Rn= VDS / ID • function of bias voltages – point (a), linear region
•Rn= 1/[βn(VGS-Vtn)] – point (b), triode region
•Rn= 2/{βn[2(VGS-Vtn)-VDS]} – point (c), saturation region – general model equation 2 •Rn= 2VDS / [βn (VGS-Vtn) ] •Rn= 1/[βn(VDD-Vtn)]
ECE 410, Prof. A. Mason Lecture Notes 6.24 MOSFET Capacitances -Preview
• Need to find C and C Gate Cgd Drain S D v vd g + id C v ro gs gs gv gv •MOSFET Small - mgs mb sb Cdb i Signal model s vs Source – Model Capacitances Csb • Cgs Cgb Body (Bulk) • Cgd •Cgb • Cdb • Csb •no Csd!
• MOSFET Physical Capacitances – layer overlap – pn junction
ECE 410, Prof. A. Mason Lecture Notes 6.25 RC Model Capacitances • Why do we care? – capacitances determine switching speed • Important Notes – models developed for saturation (active) region – models presented are simplified (not detailed) •RC Model Capacitances – Source Capacitance • models capacitance at the Source node
•CS = CGS + CSB – Drain Capacitance • models capacitance at the Drain node What are C , C , C , and C ? •CD = CGD + CDB GS GD SB DB
ECE 410, Prof. A. Mason Lecture Notes 6.26 MOSFET Parasitic Capacitances • Gate Capacitance – models capacitance due to overlap of Gate and Channel
•CG = Cox W L
– estimate that CG is split 50/50 between Source and Drain
•CGS = ½ CG
•CGD = ½ CG – assume Gate-Bulk capacitance is negligible • models overlap of gate with substrate outside the active tx area
•CGB = 0 • Bulk Capacitance ND –CSB (Source-Bulk) and CDB (Drain-Bulk) • pn junction capacitances 1 2 ⎛ V ⎞ ⎡ ε NNq DA ⎤ = ⎜CC 1+ R ⎟ = AC NA j ⎜ jo ⎟ jo ⎢ ⎥ ⎝ Ψ0 ⎠ ⎣2 0 ()+Ψ NN DA ⎦
What are VR, Ψ0, NA, and ND? ECE 410, Prof. A. Mason Lecture Notes 6.27 MOSFET Junction Capacitances • Capacitance/area for pn Junction 1 m j 2 ⎛ ⎞ ⎡ ⎤ NN DA ⎛ VR ⎞ εNq A V ln⎜ ⎟ CC ⎜1+= ⎟ C = 0 =Ψ T 2 joj ⎜ ⎟ jo ⎢ ⎥ ⎜ n ⎟ ⎝ Ψ0 ⎠ ⎣ 2Ψ0 ⎦ ⎝ i ⎠ mj = grading coefficient (typically 1/3) assuming ND (n+ S/D) >> NA (p subst.) • S/D Junction Capacitance – zero-bias capacitance
• highest value when VR = 0, assume this for worst-case estimate
•Cj = Cjo
–CS/Dj = Cjo AS/D, AS/D = area of Source/Drain
•what is AS/D? • complex 3-dimensional geometry – bottom region and sidewall regions
–CS/Dj = Cbot + Csw • bottom and side wall capacitances ECE 410, Prof. A. Mason Lecture Notes 6.28 Junction Capacitance • Bottom Capacitance
–Cbot = Cj Abot x •Abot = X W j • Sidewall Capacitance
–Csw = Cjsw Psw
•Cjsw = Cj xj [F/cm]
–xj = junction depth
•Psw = sidewall perimeter
–Psw = 2 (W + X) •Accounting Gate Undercut – junction actually under gate also due to lateral diffusion
–X ⇒ X + LD (replace X with X + LD) • Total Junction Cap
–CS/Dj = Cbot + Csw = Cj Abot + Cjsw Psw = CS/Dj
ECE 410, Prof. A. Mason Lecture Notes 6.29 MOSFET Bulk Capacitances • General Junction Capacitance
–CS/Dj = Cbot + Csw •CSB (Source-Bulk)
–CSB = Cj ASbot + Cjsw PSsw •CDB (Drain-Bulk)
–CDB = Cj ADbot + Cjsw PDsw
Gate Cgd Drain v vd g + id C v ro gs gs gv gv - mgs mb sb Cdb
is vs •RC Model Capacitances Source Csb
– Source Capacitance Cgb Body (Bulk)
•CS = CGS + CSB – Drain Capacitance
•CD = CGD + CDB
ECE 410, Prof. A. Mason Lecture Notes 6.30 Junction Areas • Note: calculations assume following design rules –poly size, L = 2λ W = 4λ – poly space to contact, 2λ ⇒ X1 = 5λ, X2= 2λ, X3 = 6λ –contact size, 2λ –active overlap of contact, 1λ X1 • Non-shared Junction with Contact – Area: X1 W = (5)(4) = 20λ2 – Perimeter: 2(X1 + W) = 18λ • Shared Junction without Contact 2 2 – Area: X2 W = (2)(4)λ = 8λ X2 – Perimeter: 2(X2 + W) = 12λ • much smaller! • Shared Junction with Contact X3 – Area: X3 W = (6)(4)λ2 = 24λ2 – Perimeter: 2(X3 + W) = 20λ • largest area!
ECE 410, Prof. A. Mason Lecture Notes 6.31